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Computer Architecture & Organization

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53 views2 pages

Computer Architecture & Organization

Cao

Uploaded by

2022ece.r109
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Code:CS20AOE502 R 20

B.Tech III Year I Semester Supplementary Examinations May - 2024


COMPUTER ARCHITECTURE & ORGANIZATION
(Electronics & Communication Engineering)
Time: 3 hrs. Max Marks: 60
PART-A
(Compulsory Question)
1. Answer the following 05 x 02 = 10 Marks
a) List the various CPU Registers. 2M
b) List any two applications of logical operations. 2M
c) Perform the 2’s complement subtraction of number (101011) from number 2M
(111001).
d) Outline auxiliary memory in a computer. 2M
e) Recall array processing. 2M
PART-B
Answer All five Units 05 x 10 = 50 Marks
UNIT-I
2. a) Explain the functional units of a computer system with neat sketch. 5M
b) Explain common bus constructed using multiplexers. 5M
OR
3. a) Discuss a Composite Arithmetic Circuit with diagram. 5M
b) Explain about instruction cycle with a flowchart. 5M
UNIT-II
4. a) Describe the design of control unit with a suitable diagram. 5M
b) Illustrate arithmetic shift instructions with suitable examples. 5M
OR
5. a) Summarize execution of complete instruction with suitable example. 5M
b) Classify and explain direct and indirect addressing modes instructions with 5M
examples.
UNIT-III
6. a) Outline the addition and subtraction algorithm with suitable diagrams. 5M
b) Summarize the hardware circuit for multiplication operation with diagram. 5M
OR
7. a) Draw and explain the flowchart for floating point subtraction. 5M
b) Explain the block diagram of BCD adder with neat diagram. 5M
UNIT-IV
8. a) Differentiate between Isolated I/O and Memory-Mapped I/O. 5M
b) What is the importance of I/O interface in a computer system? why a PCI bus is 5M
used? Explain PCI bus with a neat sketch.
OR
9. a) Explain about the DMA controller with a block diagram. 5M
b) Describe virtual-memory address-translation method based on the concept of 5M
fixed-length pages with a neat block diagram.

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Code:CS20AOE502 R 20

UNIT-V
10. a) Describe cache coherence. Why is it important in shared memory and 5M
multiprocessor systems? How can the problem be solved with a snoopy cache
controller?
b) Illustrate a processor with multiple functional units with a neat diagram. 5M
OR
11. a) Explain inter processor communication and synchronization in a shared 5M
multiprocessor environment.
b) What is instruction pipelining? What are the conflicts that occurred during 5M
instruction pipelining?
*****

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