QUESTION1. Differentiate computer Organization and Architecture.

Ans. Computer Organization and Computer Architecture are two key

concepts in computer science, and while they are related, they focus on different
aspects of computer systems. Here's a simple differentiation:

1. Computer Architecture

 Definition: Computer architecture refers to the design and structure of a

computer system at a higher level. It focuses on how the system’s
components are structured and how they interact with each other.
 Focus: It deals with the logical design and functional behavior of the
computer system.
 Key Elements:
o Instruction Set Architecture (ISA)
o Memory hierarchy
o Data formats and operations
o Processor design (e.g., RISC or CISC)
 Example: A computer's instruction set (which defines the operations the
CPU can perform) and the addressing modes are part of the architecture.

2. Computer Organization

 Definition: Computer organization refers to the physical implementation

of the architecture. It focuses on the operational and structural
components that make up the computer system.
 Focus: It deals with the hardware aspects of the system, including how
the components are arranged and how data is processed.
 Key Elements:
o CPU components (ALU, registers, control unit)
o Memory organization (RAM, cache)
o Input/Output systems
o Interconnects (buses)
 Example: How memory is physically organized or how data is
transferred between the CPU and memory.

Simple Summary:

 Architecture is about the design and functionality of the system.

 Organization is about the physical structure and how things work
together inside the system.
QUESTION2. Explain Memory Hierarchy.

Ans. Memory Hierarchy (Short Explanation)

Memory hierarchy organizes different types of memory in a computer based on speed, size,
and cost. The goal is to provide fast access to frequently used data while offering large
storage capacity.

1. Registers: Fastest, very small size (inside CPU), holds data being processed.
2. Cache Memory: Faster than RAM, small in size, stores frequently accessed data. (L1,
L2, L3 caches)
3. Main Memory (RAM): Larger than cache, slower, stores active programs and data.
4. Secondary Storage (Hard Disk/SSD): Larger, slower, stores long-term data.
5. Tertiary Storage: Very slow, used for backups or archives (e.g., cloud storage,
tapes).

Why Important: It ensures fast access to data with a balance between speed and
cost by using different types of memory at each level.

QUESTION3. Explain the Multiplexer and De-Multiplexer along with the

Block diagram.

Ans. Multiplexer (MUX)

A Multiplexer (MUX) is a digital device that selects one of many input signals and forwards
it to a single output line. It acts as a data selector that allows multiple data sources to share a
single resource (such as a communication line or data bus).

Block Diagram of Multiplexer (MUX):

+---------+
Input 0 ---->| |
| |----> Output
Input 1 ---->| MUX |
| |
Input 2 ---->| |
| |
Input N ---->| |
+---------+
|
Control Signals

Key Points:

 A multiplexer uses control signals to select which input line (Input 0, Input 1, etc.) is
connected to the output.
 The number of control lines depends on the number of input lines. For example, for 2^n
inputs, you need n control lines.
 Example: A 4-to-1 MUX has 4 input lines, 1 output line, and 2 control lines (since 2^2 = 4).
De-Multiplexer (DEMUX)

A De-Multiplexer (DEMUX) is the opposite of a multiplexer. It takes a single input signal

and channels it to one of many output lines. The selection of the output line is based on the
control signals.

Block Diagram of De-Multiplexer (DEMUX):

+---------+
Input ------->| |----> Output 0
| DEMUX |
| |----> Output 1
| |
| |----> Output N
+---------+
|
Control Signals

Key Points:

 A demultiplexer uses control signals to decide which output line will receive the input signal.
 The number of control lines depends on the number of output lines. For 2^n outputs, you
need n control lines.
 Example: A 1-to-4 DEMUX takes 1 input and has 4 output lines, with 2 control lines (since
2^2 = 4).

Summary:

 Multiplexer (MUX): Selects one input from many and sends it to the output.
 De-Multiplexer (DEMUX): Takes one input and sends it to one of many outputs, based on
control signals.

QUESTION4. Define peripheral devices and classify them into categories.

Provide one example for each category.

Ans. Peripheral Devices

Peripheral devices are hardware that connects to the computer to perform input, output, or
storage functions.
Categories of Peripheral Devices:

1. Input Devices
o Definition: Used to input data into the computer.
o Example: Keyboard (for typing)
2. Output Devices
o Definition: Used to display or output data from the computer.
o Example: Monitor (for displaying images)
3. Storage Devices
o Definition: Used to store data permanently or temporarily.
o Example: Hard Disk Drive (HDD) (for long-term storage)
4. Communication Devices
o Definition: Used for data transfer between computers or networks.
o Example: Modem (for internet connection)

Summary:

 Input: Keyboard
 Output: Monitor
 Storage: HDD
 Communication: Modem

QUESTION5 Differentiate between hardware interrupts and software

interrupts.

Ans. Difference between Hardware Interrupts and Software Interrupts

Aspect Hardware Interrupts Software Interrupts

Generated by hardware devices to gain the Generated by programs or
Definition
CPU's attention. software to trigger an interrupt.
Triggered by external devices like keyboard, Triggered by a program's
Cause
mouse, or timer. instructions (e.g., system calls).
Hardware-based, independent of the running Controlled by software and the
Control
program. operating system.
Usually have higher priority as they are time- Lower priority compared to
Priority
sensitive (e.g., handling hardware failures). hardware interrupts.
Pressing a key on the keyboard (keyboard A system call or a breakpoint in
Example
interrupt). the program.
Handled by the operating system
Handling Handled by the hardware or interrupt controller.
or the program.
Summary:

 Hardware Interrupts: Triggered by external devices, handled by hardware.

 Software Interrupts: Triggered by software (programs), handled by the OS.

QUESTION6 Explain virtual Memory and its need in computer system. A

hierarchical memory system has the following specification, 20 MB main
storage with access time of 300 ns, 256 bytes cache with access time of 150 ns,
word size 8 bytes, page size 4 words. What will be the hit ratio if the page
address trace of a program has the pattern 10, 2, 12, 30, 10, 10, 2, 4 following
LRU page replacement technique?

Ans. Virtual Memory and Its Need

Virtual Memory allows programs to use more memory than the physical RAM
by using secondary storage (like hard drives). It makes programs believe they
have access to a larger memory space than what is physically available.

Need for Virtual Memory:

1. Program Isolation: Prevents one program from interfering with another.

2. Efficient Memory Use: Enables programs to run even if their memory requirements
exceed physical RAM.
3. Multitasking: Allows multiple programs to run by allocating memory as needed.
4. Simpler Programming: Programmers don’t need to worry about memory limitations.

Hit Ratio Calculation (using LRU)

Given:

 Main Storage: 20 MB, Cache: 256 bytes

 Access Time: Main memory (300 ns), Cache (150 ns)
 Page Size: 32 bytes (4 words × 8 bytes)
 Page Address Trace: 10, 2, 12, 30, 10, 10, 2, 4

Steps:

1. Page Mapping:
o Each address maps to page 0 (since all addresses fall within 32-byte page
size).

2. Page Replacement:
 o Cache is large enough to hold all accessed pages, so no replacement needed.

3. Hit Ratio:
o All 8 accesses are to page 0, so all are hits.
o Hit Ratio = 8 hits / 8 accesses = 100%.

Summary:

 Virtual Memory allows for efficient memory use.

 Hit Ratio for the given trace is 100%.

QUESTION7 What is an I/O interface, and why is it essential in computer

systems?

Ans. I/O Interface and Its Importance

I/O Interface (Input/Output Interface) is a hardware component that enables

communication between the CPU and peripheral devices (such as keyboard,
mouse, printer, disk drives, etc.). It acts as a bridge that allows data transfer
between the computer’s internal system (CPU, memory) and external devices.

Functions of I/O Interface:

1. Data Conversion: Converts data from the form used by peripheral

devices (analog or digital) to a format the computer can process and vice
versa.
2. Control and Timing: Manages the timing and control signals required
for data transfer between the CPU and I/O devices.
3. Buffering: Temporarily stores data to match the speed differences
between the CPU and slower I/O devices.
4. Error Checking: Ensures that data transferred between the CPU and
peripheral devices is error-free.

Why It Is Essential:

1. Communication with External Devices: I/O interfaces allow the CPU to

send and receive data from devices like printers, hard drives, and network
adapters.
 2. Device Management: They help manage and control various devices
with different communication protocols, ensuring compatibility.
3. Data Transfer: Without I/O interfaces, the computer wouldn’t be able to
interact with external devices, which are necessary for input (e.g.,
keyboard) and output (e.g., monitor).

In Summary:

The I/O interface is crucial for enabling interaction between the computer and
external devices, ensuring smooth data transfer, compatibility, and efficient
system performance.

QUESTION8. List and briefly describe two types of Read-Only Memory (ROM)
and their uses.

Ans. Types of Read-Only Memory (ROM) and Their Uses

1. PROM (Programmable Read-Only Memory)

o Description: PROM is a type of ROM that can be programmed by the user
once, using a special device called a programmer. After programming, the
data cannot be changed (i.e., it becomes permanent).
o Uses:
 Firmware Storage: Used to store firmware or system-level software
that doesn't need to change after the initial setup, such as in calculators
or embedded systems.
2. EEPROM (Electrically Erasable Programmable Read-Only Memory)
o Description: EEPROM can be electrically erased and reprogrammed,
allowing for multiple write cycles. It is slower compared to other types of
memory but is more flexible as it can be modified in-place.
o Uses:
 Storing Configuration Settings: Often used in devices like BIOS
chips in computers, where settings need to be preserved even when
power is lost, but may need occasional updates (e.g., updating
firmware or settings in electronic devices).

Summary:

 PROM: Programmable once, used for permanent storage (e.g., embedded systems).
 EEPROM: Can be erased and rewritten, used for settings and firmware updates (e.g.,
BIOS in computers).
QUESTION9. Explain Cache Mapping techniques. A computer has a
256 KB, 2-way set associative, write back data cache with block
size of 16 bytes. The processor sends 32 bit addresses to the
cache controller. Each cache tag directory entry contains in
addition to address tag, 2 valid bits, 1 modified bit and
replacement bit.1. Find the number of bits in the tag field. 2. Find
the size of the cache tag directory.

Ans. Cache Mapping Techniques

Cache mapping refers to the method used by the cache to determine how data
from main memory is stored and retrieved. There are three main types of cache
mapping techniques:

1. Direct-Mapped Cache:
In this method, each block in the main memory maps to exactly one cache
line. The address is divided into three parts: Tag, Index, and Block
offset.
2. Fully Associative Cache:
In this method, any block from the main memory can be stored in any
cache line. The cache controller needs to search all cache lines to check if
a block is present.
3. Set-Associative Cache:
This is a combination of direct-mapped and fully associative caches. The
cache is divided into sets, and each set contains multiple lines (blocks). A
block in main memory can be placed in any line of a set, and the cache
controller searches within the set to find the block. The 2-way set
associative cache means each set has 2 lines.

Problem Breakdown

Given:

 Cache size = 256 KB

 Cache type = 2-way set associative
 Block size = 16 bytes
 Address size = 32 bits
 Cache tag directory entry has:
o 2 valid bits
o 1 modified bit
o 1 replacement bit
1. Find the number of bits in the tag field

To calculate the number of bits in the tag field, we need to break down the 32-
bit address into three parts: Block Offset, Index, and Tag.

1. Block Offset:
Since the block size is 16 bytes, we need log⁡216=4\log_2 16 = 4 bits to
represent the byte position within the block.
2. Index:
The cache is 2-way set associative. To determine the number of sets:

Number of sets=Cache sizeBlock size×Number of ways=256 KB16 bytes×2=8192 sets\

text{Number of sets} = \frac{\text{Cache size}}{\text{Block size} \times \text{Number
of ways}} = \frac{256 \text{ KB}}{16 \text{ bytes} \times 2} = 8192 \text{ sets}

The number of sets requires log⁡28192=13\log_2 8192 = 13 bits for the

index.

3. Tag:
The total address length is 32 bits. So, the number of bits in the tag field
is:

Tag bits=32−(Index bits+Block offset bits)=32−(13+4)=15 bits\text{Tag bits} = 32 - (\

text{Index bits} + \text{Block offset bits}) = 32 - (13 + 4) = 15 \text{ bits}

Thus, the tag field will be 15 bits.

2. Find the size of the cache tag directory

The cache tag directory stores the tag for each set, along with the status bits
(valid, modified, replacement). To calculate the size of the cache tag directory,
we need to determine how much storage is needed for each entry.

1. Number of cache entries:

Since there are 8192 sets and each set has 2 lines (2-way set associative),
the total number of entries in the cache tag directory is:

Total entries=Number of sets×Number of lines per set=8192×2=16,384 entries\

text{Total entries} = \text{Number of sets} \times \text{Number of lines per set} =
8192 \times 2 = 16,384 \text{ entries}

2. Size of each entry:

Each entry consists of:
 o Tag: 15 bits
o Valid bit: 2 bits
o Modified bit: 1 bit
o Replacement bit: 1 bit Total size per entry = 15+2+1+1=1915 + 2 + 1 + 1 = 19
bits.

3. Total size of the tag directory:

Multiply the number of entries by the size of each entry:

Size of the cache tag directory=Total entries×Size of each entry=16,384×19 bits\

text{Size of the cache tag directory} = \text{Total entries} \times \text{Size of each
entry} = 16,384 \times 19 \text{ bits}

Convert bits to bytes:

Size in bytes=16,384×198=38,720 bytes=37.5 KB\text{Size in bytes} = \frac{16,384 \

times 19}{8} = 38,720 \text{ bytes} = 37.5 \text{ KB}

Thus, the size of the cache tag directory is 37.5 KB.

Summary:

1. Number of bits in the tag field: 15 bits.

2. Size of the cache tag directory: 37.5 KB.

QUESTION10 Consider a machine with 64 MB physical memory and a 16 bit

virtual address space. If the page size is 4 KB, what is the approximate size of
the page table?

Ans. Calculating the Size of the Page Table

To find the size of the page table, we need to break down the problem into
parts and use the following information:

 Physical memory: 64 MB (megabytes)

 Virtual address space: 16-bit
 Page size: 4 KB (kilobytes)

Steps to Calculate the Page Table Size:

1. Page Size:
o The page size is 4 KB, which is 2122^{12} bytes.
 o Therefore, each page covers 4 KB of memory.

2. Number of Pages in Virtual Memory:

o The virtual address space is 16 bits, meaning it can address 2162^{16}
locations, or 64 KB of virtual memory.
o To find how many pages are needed:
Number of pages=Virtual memory sizePage size=216212=24=16 pages\
text{Number of pages} = \frac{\text{Virtual memory size}}{\text{Page size}}
= \frac{2^{16}}{2^{12}} = 2^4 = 16 \text{ pages}

3. Page Table Entries:

o The physical memory size is 64 MB, which is 2262^{26} bytes.
o With 4 KB page size, the number of frames in physical memory is:
Number of frames=Physical memory sizePage size=226212=214 frames\
text{Number of frames} = \frac{\text{Physical memory size}}{\text{Page size}}
= \frac{2^{26}}{2^{12}} = 2^{14} \text{ frames}
o Each page table entry (PTE) needs to store the frame number, which is 14 bits
(since 2142^{14} frames are possible).

4. Page Table Size:

o There are 16 pages, and each page table entry is 14 bits.
o The total number of bits needed for the page table is:
Page Table Size (in bits)=Number of pages×Bits per page table entry=16×14=2
24 bits\text{Page Table Size (in bits)} = \text{Number of pages} \times \
text{Bits per page table entry} = 16 \times 14 = 224 \text{ bits}
o Convert bits to bytes: Page Table Size (in bytes)=2248=28 bytes\text{Page
Table Size (in bytes)} = \frac{224}{8} = 28 \text{ bytes}

Summary:

The size of the page table is approximately 28 bytes

QUESTION11Write a program to evaluate the arithmetic statement. X-A*B-

C*(D+E) using a general register computer with three address instruction,

Ans. To evaluate the expression:

X−A×B−C×(D+E)X - A \times B - C \times (D + E)

using a general register computer with three-address instructions, let's break it down into
smaller steps for clarity. We'll use three-address instructions, where each instruction
operates on three operands (two source operands and one destination operand).

Steps to Evaluate the Expression:

We can evaluate the expression in the following order based on operator precedence:

1. Calculate D + E.
2. Calculate A * B.
3. Calculate C * (D + E).
4. Calculate X - (A * B).
5. Finally, calculate X - (A * B) - (C * (D + E)).

Three-Address Instructions:
LOAD R1, D ; R1 = D
ADD R1, E ; R1 = D + E
STORE R1, R5 ; Store D + E in R5

LOAD R2, A ; R2 = A
MUL R2, B ; R2 = A * B
STORE R2, R6 ; Store A * B in R6

LOAD R3, C ; R3 = C
MUL R3, R5 ; R3 = C * (D + E), using R5 for (D + E)
STORE R3, R7 ; Store C * (D + E) in R7

LOAD R4, X ; R4 = X
SUB R4, R6 ; R4 = X - (A * B), using R6 for A * B
SUB R4, R7 ; R4 = (X - (A * B)) - (C * (D + E)), using R7 for C *
(D + E)

STORE R4, X ; Store final result back to X

Explanation:

1. Step 1: Load D into register R1 and add E to it. Store the result (D + E) in register R5.
2. Step 2: Load A into register R2 and multiply it by B. Store the result (A * B) in
register R6.
3. Step 3: Load C into register R3 and multiply it by the value stored in R5 (which is D +
E). Store the result (C * (D + E)) in register R7.
4. Step 4: Load X into register R4 and subtract the value in R6 (A * B) from it.
5. Step 5: Subtract the value in R7 (C * (D + E)) from the result in R4, and store the
final result back into X.

Summary:

 Registers used: R1, R2, R3, R4, R5, R6, R7.

 This program evaluates the arithmetic expression using step-by-step calculations and
three-address instructions.

This approach ensures that we respect the order of operations in the expression and efficiently
use the registers for intermediate results.

QUESTION12 Steps involved in basic instruction cycle for the Following

instruction: IR<-M[100]
Ans. Steps Involved in the Basic Instruction Cycle for the Instruction: IR <-
M[100]

The instruction IR <- M[100] means "Load the contents of memory location
100 into the Instruction Register (IR)." This involves a sequence of operations
in the basic instruction cycle. The basic instruction cycle typically involves the
Fetch, Decode, and Execute phases.

Let's break down the steps involved in this cycle:

Basic Instruction Cycle:

1. Fetch the Instruction:

o Program Counter (PC) holds the address of the next instruction
to be fetched. Initially, the PC points to the memory location of the
next instruction.
o Memory Address Register (MAR) is loaded with the address
from the PC.
o Memory Read operation: The content at memory address M[100]
is read.
o The fetched instruction is loaded into the Instruction Register
(IR).

So, for IR <- M[100]:

o The address 100 is placed in the MAR.

o A Memory Read is performed, and the content at memory location
100 is fetched and placed into the IR.

Instruction Fetch Cycle:

oMAR <- PC (load the address of the next instruction into MAR)
o IR <- M[MAR] (fetch instruction from memory and load it into
IR)
o PC <- PC + 1 (increment the program counter to point to the next
instruction)
2. Decode the Instruction:
o The instruction in the IR is decoded. In this case, the instruction is
IR <- M[100], which means it is a Memory Read operation.
o The Control Unit decodes this instruction and generates the
control signals to initiate the memory read operation.

Instruction Decode Cycle:

 o The control unit decodes the instruction from the IR and generates
control signals.
o Based on the decoded instruction, it knows that it needs to perform
a memory read from location 100.
3. Execute the Instruction:
o The MAR is loaded with the address 100 (which is already in the
IR).
o The Memory Read operation is performed.
o The value at memory location 100 is fetched and loaded into the
IR.

Execution Cycle:

o MAR <- 100 (load the address 100 into MAR)

o IR <- M[MAR] (perform memory read and load data from
memory into IR)

After executing the instruction, the value from memory location 100 is
now in the IR.

Summary of the Instruction Cycle for IR <- M[100]:

1. Fetch Phase:
o MAR <- PC
o M[MAR] -> IR (fetch instruction from memory into IR)
o PC <- PC + 1
2. Decode Phase:
o Control Unit decodes the instruction (IR <- M[100]), generating
control signals for a memory read operation.
3. Execute Phase:
o MAR <- 100 (load the address 100 into the MAR)
o M[MAR] -> IR (fetch the data from memory at location 100 and
load it into the IR)

At the end of the cycle, the IR holds the data from memory location 100, and
the PC is incremented to the next instruction location.

In Summary:

The basic instruction cycle for IR <- M[100] consists of:

1. Fetching the instruction from memory (placing it into IR).

2. Decoding the instruction to recognize that it is a memory read.
3. Executing the memory read, placing the content of M[100] into the IR.