8.

Interrupt

A single microcontroller can serve several devices. There are two ways to do that:
interrupts or polling. In the Interrupt method, whenever any device needs its service, the device
notifies the microcontroller by sending an interrupt signal. Once the interrupt is accepted the
microcontroller serves the device by executing an interrupt service routine (ISR). In polling
method the microcontroller continuously monitor the status of a give device, when the condition
is met it performs the service. This polling method is not efficient because it has to monitor all
times the status of devices in round-robin fashion and priority assignment is not possible.

Interrupt Service Routine

For every interrupt, there must be an Interrupt service routine (ISR), Interrupt handler. For every
interrupt, there is a fixed location in memory that holds the address of its ISR. The group of
memory locations set aside to hold the addresses of ISRs is called the interrupt vector table.

Steps in executing an Interrupt

Once an interrupt is activated, microcontroller performs the following steps.

1. It finishes the instruction it is executing and save the address of the next instruction (PC)
on the stack.
2. It also saves the the current status of all the interrupts internally.
3. It jumps to a fixed location in memory called the interrupt vector table that holds the
address of ISR.
4. The microcontroller gets the address of the ISR from the interrupt vector table and jumps
to it. It starts to execute the ISR until it reaches last instruction of subroutine RETI (return
from the interrupt).
5. Upon executing the RETI instruction, the microcontroller returns to the place where it
was interrupted. First it gets PC address from the stack by popping the top two bytes of
the stack into the PC

Six Interrupts of 8051

The six interrupts in the 8051 are allocated as follows

1. Reset- when the reset pin is activated, the 8051 jumps to address location 0000. This is
power-up reset.

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 2. Two interrupts are set aside for the timers: one for timer 0 and one for timer 1. Memory
locations 000BH and 001BH in the interrupt vector table belongs to timer 0 and timer
1.respectively.
3. Two interrupts are set aside for hardware external hardware interrupts, Pin numbers 12
(P3.2) and 13(P3.3) in port 3 are for the external hardware interrupts INT0 and INT1,
respectively. These external interrupts are also referred to as EX1 and EX2. Memory
location 0003H and 0013H in the interrupt vector table are assigned to INT0 and INT1
respectively.
4. Serial communication has a single interrupt that belongs to both receive and transfer. The
interrupt vector table location 0023H belongs to this interrupt.

Interrupt Vector Table for 8051

From the table it has been observed that only three bytes of ROM space is assigned to the reset
pin. They are ROM address locations 0,1 and 2.

Table 4.2 Interrupt vector addresses

Interrupt ROM Pin
Location(Hex)
Reset 0000 9
External hardware interrupt (INT0) 0003 12
Timer 0 interrupt (TF0) 000B 13
External hardware interrupt (INT1) 0013
Timer 1 interrupt (TF1) 001B
Serial COM interrupt ( RI and TI) 0023

Enabling and disabling an interrupt

Upon reset all interrupts are disabled. The interrupts must be enabled by software. There is a
register IE (interrupt enable) that is responsible for enabling and disabling the interrupts.

To enable an interrupt following steps should be followed.

1. Bit D7of IE register (EA) must be set high to allow the rest of register to take effect.
2. If EA=1 , interrupts are enabled and will be responded to if their corresponding bits in IE
are high. If EA=0, no interrupt will be responded to, even if the associated bit in the IE
register is high.

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Fig. 4.21 Interrupt Enable Register

Interrupt Priority in the 8051

When the 8051 is powered up, the priorities are assigned, that are enlisted in table.

Table 4.3 Interrupt priority

Highest to Lowest priority
External Interrupt 0 INT0
Timer Interrupt 0 TF0
External Interrupt 1 INT1
Timer Interrupt 1 TF1
Serial Communication RI-TI

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 TIMERS AND COUNTERS
In a microcontroller, physical time is represented by the count value of a timer. By interpreting the count
Value of a timer properly, many timer applications can be realized. There are many applications that require a
dedicated timer system, including
 Time reference
 Time delay creation
 Pulse width, period and frequency measurement
 Periodic interrupt generation (to remind the processor to perform routine tasks)
 Waveform generation
A basic timer consists of a register that can be read from or written to by the processor and is driven
by some frequency source. The register is usually of 8 or 16 bit. The timer/counter clock source is either
Microcontrollers clock or an external clock.

8051 TIMERS/COUNTERS
The 8051 has two timers, Timer 0 and Timer 1. Both are 16 bit timers/counters. Both timers consist
of two 8 bit registers. Timer 0 consists of two 8 bit registers—TH0 and TL0 and Timer 1 consist of two 8 bit
registers, TH1 and TL1. Both share the timer control (TCON) register and timer mode register (TMOD).
A timer can be used to create time delay, or as a counter to count the external events happening outside
the microcontroller that occurred within a time interval.
The C/T bit in the TMOD register decides the source of the clock for the timer. If C/T = 1, then timer is used
as counter and gets the clock from outside the microcontroller, else if C/T = 0, then timer gets the clock
pulses from the crystal.

When used as a timer, the clock pulse is obtained from the oscillator through divide by 12 d circuit.
When used as counter, pin T0 (P3.4) supplies pulses to counter 0, and pin T1 (P3.5) supplies pulses to
Counter 1. If 12 MHz crystal is connected to the 8051, then the clock period will be equal to 1μs. Registers
are incremented after 1μs. In the counter function, the registers are incremented in response to a transition
from 1 to 0, at external input pin P3.4 for counter 0 and P3.5 for counter 1.

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When the registers overflow from FFFF h to 0000 h, it sets a flag (TF flag) and generates an interrupt. Timer
control register controls the timer/counter operation.

TR0 and TR1 flags turn the timer ON or OFF. The upper 4 bit are used to store the TF and TR bits of
Both Timer 0 and Timer 1. The lower 4 bits are used for controlling the interrupt. TCON is a bit addressable
register. Instructions SETB TCON.6 and CLR TCON.6 can be used to store 1 and 0 in TR1 flag of TCON
register. The lower 4 bits are used for controlling Timer 0 and the upper 4 bit are used for controlling Timer
1. C/T selects timer or counter operation and M1 and M0 select the mode.

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TIMER/COUNTER OPERATION MODES
In addition to the timer or counter selection, both timer 0 and timer 1 have operating modes. Modes
are selected by using Timer Mode Control Register (TMOD). The timers may operate in any one of the four
modes that are determined by mode bits, M1 and M0, in TMOD register.

MODE 0 In this mode, timer register is configured as a 13 bit register. The 13 bit timer register consists of all
8 bit of THx and the lower 5 bit of TLx register. The upper 3 bit of TLx register are ignored. As the counter
changes from all 1’s to 0’s, it sets the timer interrupt flag, TFx. The timer is enabled when TRx = 1, and
either gate = 0 or INTx = 1.13 bit registers can hold values between 0000H to 1FFFH in TH and TL. When
the register reaches its maximum 1FFFH, it rolls over to 0000H i.e. when the register overflows, then it sets
the timer interrupt flag (TF1 for timer 1 and TF0 for timer 0).

Mode 1 is the same as mode 0 except that the timer register uses all 16 bit. In this mode, THx
and TLx are cascaded. For mode 1, loading TLx and THx with values derived from the formula can create a
specifi c time delay.
Time delay = [12 × [65,536 – Init Value]]/ Freq
where Init Value = TLx + [256 × THx]
If the values of THx and TLx are in decimal, the values must be converted to Hexadecimal, then it must be
loaded to THx and TLx registers.

Mode 2 The operation is same for timer 0 and timer 1. In this mode, timer register is configured as TLx.
When TLx overflows from FFh to 00H it, sets the flag TFx and it loads TLx with the contents of THx. The
reload leaves THx unchanged. In this mode, timer 1or timer 0 supports the automatic reload operation. The
timer control logic is same as mode 0 or mode 1 as shown in Fig. 7.9. Example 7.3 gives the program to
initialize timer 0 in mode 2.

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Mode 3 Timer 0 in mode 3 establishes TL0 and TH0 as two separate registers as shown in Fig. 7.10. TL0
uses Gate, TR0, INT0 and TF0 control bits of timer 0 and TH0 uses TR1 and TF1 control bits of timer 1.
When TL0 overflows from FF to 00, then it sets the timer fl ag TF0. If control bit TR1 is set, TH0
Receives the timer clock (oscillator divided by 12). When the counter TH0 overflows from FF to 00, then it
sets the flag TF1.Timer 1 may still be used in mode 0, mode 1 and mode 2, but it neither interrupts the
processor nor sets the flag. When timer 0 is in mode 3, timer 1 can be used for baud rate generation in serial
communication.

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