Scribd
Upload
32 views2 pages

Digital Logic Design

Uploaded by

redragon165
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
32 views2 pages

Digital Logic Design

Uploaded by

redragon165
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

H.T.No.

Code No: CT3510 SRGEC-R20


II B.Tech I Semester Supplementary Examinations, August 2022
DIGITAL LOGIC DESIGN
(Computer Science and Engineering, Artificial Intelligence and Data Science, Information
Technology)
Time: 3 Hours Max. Marks: 70
Note: Answer one question from each unit.
All questions carry equal marks.
5 × 14 = 70M
UNIT-I
1. a) List any two weighted codes, two self-complementing codes, two un-weighted codes and
two alphanumeric codes. Also specify examples for each code. (8M)
b) Convert the following BCD number 11001111 to Excess -3 code and Gray code. (6M)
(OR)
2. a) Perform the following conversions: (8M)
(i) (10011010)EX-3 to BCD (ii) (10110.001)2= ( )10 (iii) (111110101011.0011)2=( )8
b) What is meant by reflective code and sequential code. Give an example for each. (6M)
UNIT-II
3. a) Represent NOT, AND, OR using NAND and NOR with suitable proof. (8M)
b) Simplify the Boolean expressions: (6M)
(i) AB + A (B + C) + B(B + C)
(ii) [AB (C + BD) + A B]C
(iii)A1BC + ABC1 + A B C + A1BC1
(OR)
4. a) Express the following functions as a sum of min terms and as a product of max terms:
F(A,B,C)=B1C+A1C+BC (6M)
b) Reduce the following Boolean expressions to the indicated number of literals: (8M)
(i) A'C'+ABC +AC' to THREE literals
(ii) ABC1D+A1BD+ABCD to TWO literals
(iii) A'B(D'+CD')+B(AD'+D') to ONE literal
UNIT-III
5. a) Design a circuit that has a 3-bit binary input and a single output (Z) specified as follows:
Z = 0, when the input is less than 510
Z = 1, otherwise (6M)
b) Explain design of full adder. (8M)

Page 1 of 2
(OR)
6. Formulate the Sum and Carry expressions of Full Adder in terms of Sum and Carry
expressions of Half Adder and realize Full adder using Half Adder and Gates. (14M)
UNIT-IV
7. a) Design Octal to Binary Encoder . (7M)
b) Interpret the operation of suitable multiplexer to exhibit the functionality of sum output
full adder. (7M)
(OR)
8. a) Design a logic diagram for constructing a 3X8 decoder using a pair of 2 X 4 decoders and
also draw the configuration for the truth table. (8M)
b) What is the purpose of De-Multiplexer? Draw the block diagram for 1X4 De-Multiplexer.
(6M)
UNIT-V
9. a) Explain the operation of JK flip-flop using NAND Gates with the aid of truth table.
(7M)
b) Design Parallel in -Serial out shift register and explain its operation. (7M)
(OR)
10. a) Illustrate the operation of universal shift register, with the help of diagram. (8M)
b) Reproduce the truth tables of D flip flop and JK flip flop and write their characteristic
equations. (6M)

*****

Page 2 of 2

You might also like