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Digital Down Conversion In Software Radio Terminals

Conference Paper · April 2002

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 DIGITAL DOWN CONVERSION IN SOFTWARE RADIO
TERMINALS
Michael Löhning, Tim Hentschel, and Gerhard Fettweis
Dresden University of Technology
Mannesmann Mobilfunk Chair for Mobile Communications Systems
D-01062 Dresden, Germany
e-mail: [email protected]

ABSTRACT nique requires a large look-up table (~ 2n ¥n bit) resulting in

large chip area, high power consumption, lower speed, and
The idea of software radio requires an expansion of digital increased costs.
signal processing towards the antenna. Hence, for convert- An approach to overcome this drawback is the calculation
ing the received signal to baseband, the need of efficient high of the corresponding sine- and cosine-values by means of
speed digital down converters arises. In [1] digital down con- CORDIC [2, 3, 4] with the main advantage of using only
version was identified as one of the ’critical functionalities’ a small look up table (~ n ¥ n bit). The major drawback of
because it has to run at a relative high sample rate, and has the CORDIC approach is the increased circuit complexity.
to provide high resolution. The common approach for digi- However, if used in the context of digital down conversion
tal down conversion (DDC) is the so called ROM table ap- or frequency synchronization, the additional hardware effort
proach where the samples of the input signal are multiplied is partly compensated because there is no need for explicit
with amplitude values of the sine- and cosine-function stored multipliers as will be shown in this paper.
in ROM. To achieve high resolution this technique requires a
large look-up table which means large chip area, high power 2 THE CORDIC-ALGORITHM
consumption, lower speed, and increased costs.
In this paper a CORDIC-based digital down converter is de- The CORDIC (COordinate Rotation Digital Computer) was
scribed. It enables to reduce the size of the look-up table developed by Volder [2] in 1959 as an iterative algorithm to
considerably. Additionally to previous publications, this pa- convert between polar and cartesian coordinates using shift,
per provides an overall worst case quantization error estima- add, and subtract operations only.
tion that facilitates the dimensioning of the CORDIC-DDC. In the circular rotation mode the CORDIC computes the
cartesian coordinates of the target vector vn = [xn yn ]T by
rotating the input vector v0 = [x0 y0 ]T by an arbitrary an-
1 INTRODUCTION
gle f = z0 . This vector rotation is realized by perform-
DDC is conventionally performed by multiplying the digi- ing a sequence of successively decreasing elementary ro-
tized input signal with amplitude values of sine- and cosine- tations with the basic rotation angles fi = ± arctan(2-i ) for
functions stored in a ROM table which could easily be ad- i = 0, . . . , n - 1. The resulting iterative process can be de-
dressed by the output of an overflowing phase accumulator scribed by the following equations
(Figure 1). However, for high resolution (n bit) this tech-
xi+1 = xi - di yi 2-i (1)
-i
yi+1 = yi + di xi 2 (2)
f
I(k) ∼ sBP (k) cos(2π o k )
f s zi+1 = zi - di arctanI2 M -i
(3)
sBP (k)
f where
Q(k) ∼ - sBP (k) sin (2π o k )
fs
Ï
Ô-1 if zi < 0
di = Ì
Ô+1 . (4)
Ó otherwise

f cos ( ) sin ( ) specifies the direction for each elementary rotation. Eq. (3)
φ (k) = 2π fo k
s describes an angle accumulator. After n iterations the
ROM-Table
CORDIC equations result in

Figure 1: Conventional I/Q-DDC using the ROM table ap- xn ª An [x0 cos(z0 ) - y0 sin(z0 )] (5)
proach yn ª An [y0 cos(z0 ) + x0 sin(z0 )] (6)
zn ª 0 (7)
where the sample rate of the signal. However, the CORDIC can
n 0 be implemented by a pipelined architecture [5, 6]. Thus,
An = ‰ 1 + 2-2i (8) the CORDIC-DDC becomes suitable for high speed appli-
i=0 cations. An additional advantage of such an implementation
is that there is no need for a look-up table anymore, since
is the CORDIC scaling factor which depends on the total
the invariant elementary rotation angles can be hard-wired to
number of iterations n. xn and yn contain the coordinates
each stage.
of a scaled version of the z0 -rotated vector [x0 y0 ]T . The ac-
Further it should be noted that the hardware effort of the
curacy is determined by the number of iterations n and the
CORDIC is approximately that of three multipliers with the
word length of the CORDIC processor (s. section 4).
respective word length. This means that the CORDIC-DDC
It should be noted that Eqs. (1–3) converge for rotation
has only one and a half of the hardware complexity of the
angles between - p2 and p2 only. In order to increase the con-
common DDC (two explicit multipliers), while saving a large
vergence range for all rotation angles |z0 | £ p, Volder [2]
amount of chip area because no ROM table is needed. In this
proposes an initial iteration which rotates the input vector by
context it is worth mentioning that without any additional
± p2 :
hardware effort the CORDIC can easily be used as a com-
¢
x = -d y (9) plex image rejection mixer (s. Figure 4) e.g., for frequency
¢ synchronization purposes. Comparing with the conventional
y =dx (10) image rejection mixer of Figure 3 reveals that the CORDIC
¢ p
z =z-d (11) even replaces four multipliers and the look-up table.
2
where f
I’(k) ∼ I(k) cos(2π o k )
fs
Ï
Ô-1 if z < 0 I(k) f
- Q(k) sin (2π fo k )
d=Ì
Ô+1 . (12) s

Ó otherwise
3 THE CORDIC-DDC
After the brief review of the CORDIC algorithm it will be f cos ( ) sin ( )
φ (k) = 2π fo k
shown how it can be used for digital down conversion. Sub- s
ROM-Table
stituting the output signals of the conventional DDC of Fig-
ure 1 into Eqs. (5) and (6) yields the structure of a CORDIC- f
based DDC. It is shown in Figure 2. Q’(k) ∼ Q(k) cos(2π o k )
f s
Q(k) f
+ I(k) sin (2π fo k )
s
Lookup - Table
arctan( 2 -i )
Figure 3: Conventional image rejection mixer
f
0 x0 xn Q(k) ∼ - An sBP (k) sin (2π fo k )
s
CORDIC f
sBP (k) y0 yn I(k) ∼ An sBP (k) cos(2π o k ) Lookup - Table
z0 f s arctan( 2 -i )

f f f
φ (k) = 2π fo k I(k) x0 xn I’(k) ∼ An [ I(k) cos(2π o k ) - Q(k) sin (2π o k )]
fs f s
s CORDIC f f
Q(k) y0 yn Q’(k) ∼ An [ Q(k) cos(2π o k ) + I(k) sin (2π o k )]
z0 fs fs
Figure 2: CORDIC-based I/Q-DDC
f
φ (k) = 2π fo k
s

At each clock interval, y0 is loaded with the current sam-

ple sBP (k) of an IF-input signal, and z0 with the current sam- Figure 4: CORDIC-based image rejection mixer
ple f(k). The latter is supplied by an overflowing phase ac-
cumulator which generates the oscillator frequency f0 . x0 is
set to zero. After n + 1 iterations the CORDIC provides the 4 QUANTIZATION ERROR BOUND
samples I(k) and Q(k) of the down-converted in-phase and
quadrature-phase signal with a resolution of approximately n In order to dimension the CORDIC-DDC it is necessary to
bits. In order to achieve this, only a very small look-up table estimate the achievable accuracy. For that purpose we derive
is needed. It contains the (n + 2) basic rotation angles. a worst case error bound of the overall quantization error of
Still, the main problem of the CORDIC is that n + 1 itera- the CORDIC algorithm. With respect to the high-speed ap-
tions have to be performed for each signal sample, requir- plication as a digital down-converter, only fixed point im-
ing an internal clock rate being (n + 1)-times higher than plementations are considered. An approach to this problem
including CORDIC processors with floating point arithmetic In Figure 5 these results are compared with the minimum
has been presented in [7], still, without considering the quan- SNR values obtained by means of Monte Carlo simulations.
tization error produced in the CORDIC angle accumulator The latter have been made with a parameterizable model
(Eq. (3)). of the CORDIC-DDC considering all quantization effects.
After an initial iteration (Eqs. (9)-(12)), and n further iter- 105 vector rotations with randomly generated rotation an-
ations (Eqs. (1)-(4)), the maximum overall quantization error gles f(k) (uniformly distributed in the interval [-p, p]) were
of a fixed point CORDIC processor can be calculated as fol- performed in MATLAB for each set of parameters (m, b).
lows: The worst result for each set (m, b) has been taken as the
“simulated worst case error” (in contrast to the analytically
|Dvn | = |vn - v* | £ |v* | ◊ I |dn | + |qn | M + | f n | (13) predicted worst case error of Eq. (13)). As the curves in Fig-
ure 5 suggest, Eq. (13) tends to overestimate the worst case
where v* = [x* y* ]T is the ideal output vector (theoreti- quantization error. This means that the analytically predicted
cally produced by a CORDIC processor with infinite preci- minimum SNR is lower than the simulated one. Neverthe-
sion arithmetic after an infinite number of iterations), and less, although a bit pessimistic, the theoretically derived er-
vn = [xn yn ]T is the output vector computed by the finite pre- ror bound can be used for dimensioning a CORDIC-DDC.
cision CORDIC. dn stands for the so-called (angle) approxi- For a given minimum SNR and a given number of iterations,
mation error and f n for the rounding error vector, both de- the difference between the theoretically calculated minimum
rived in [7]: number of fractionally binary digits b and that found by sim-
ulation is only about one.
|dn | £ 2-(n-1) for n ≥ 1 (14)
85
m = 16
È ˘
0 ÍÍÍ n-1 ÊÁ n-1 n-1 ˆ˜˙˙˙
Í
| f n | £ 2 Íe0 ‰ k(i) + e ÁÁ1 + ‚ ‰ k(i)˜˜˙˙˙
Á ˜ 80
Í (15)
ÍÍ Á ˜˙˙
ÍÎ i=0 Ë j=1 i= j ¯˙˚ 75
m = 15
with
minimum SNR in dB

0 70
m = 14
k(i) = 1 + 2-2i . (16)
65
Thereby, e0 considers the maximum absolute input quanti-
zation error in x0 and y0 , while e = 2-b stands for the maxi- 60
mum absolute rounding error in xi and yi due to bit truncation worst case error estimation
with fixed point arithmetic (b fractional binary digits) which Monte Carlo simulation
55
is done in each iteration. (m ... number of CORDIC iterations)
As an extension to the results in [7], qn describes the re-
50
sulting error component in vn due to the rounding errors in zi 14 15 16 17 18 19 20
number of fractional binary digits b
that are caused by the input quantization of z0 and the quan-
tized fixed point representation of the basic rotation angles p2
Figure 5: Minimum SNR predicted and simulated for a
and arctan(2-i ), respectively:
CORDIC-DDC with m = n + 1 iterations, different numbers
Ï of fractional binary digits b, and ideal ADC
Ôs0 + n s for 0 £ n £ b + 1
|qn | £ Ì
Ôs0 + (b + 2) s (17)
Ó for n > b + 1
Beside the overall quantization error power its spectral dis-
s0 represents the maximum absolute phase input quantiza- tribution is an important property, i.e., the spectral purity. A
tion error, and s the maximum absolute rounding error of worst case assumption would be to concentrate the error in
the basic rotation angles. one discete spur. This would give a bound for the spurious-
free dynamic range (SFDR) i.e., the ratio of the power of the
5 SIMULATION RESULTS
desired signal, and the power of the strongest spur.
In this section some simulation results are presented in order Still, simulations have shown that the error is distributed
to verify the quality of the derived maximum quantization er- over frequency. Due to this distribution the strongest result-
ror bound. Therefore, Eqs. (13)-(17) are evaluated for differ- ing spur is significantly lower than the overall error (worst
ent values for n and b. For simplification the input quantiza- case error bound). Figure 6 shows the result of downcon-
tion error e0 is set to zero, which models an ideal analog-to- verting a 20 MHz tone to DC (sample rate fS = 65 MSps).
digital converter (ADC). The input signal is set to constant The SFDR is approximately 98 dB in contrast to the worst
one. With the so computed worst case error estimates the case estimation of 75 dB (analytically predicted) or 79 dB
minimum SNR (signal to [quantization] noise ratio) can be (simulated) in Figure 5.
estimated. The spurs in Figure 6 are a result of cross-mixing the spurs
of the CORDIC with the input signal. If the input signal itself 0

contains spurs, even more spurs will appear at the output of

−20
the CORDIC-DDC. In this case the spurs of the input signal
are mixed with the desired CORDIC frequency, and with all −40

power spectral density in dB

the spurs of the CORDIC. Quantizing the input signal yields
such spurs. If their power is larger than the power of the −60
spurs of the CORDIC the SFDR is mainly determined by the
quantization of the input signal rather than the quantization −80

effects within the CORDIC-DDC. This is shown in Figure 7

−100
where a 12 bit input signal is fed to the CORDIC. The SFDR
is decreased to approximately 70 dB compared to Figure 6. −120
It should be noted that quantized harmonic signals produce
an error spectrum which is much worse conditioned that that −140
of typical signals e.g., in communication applications.
−160
−30 −20 −10 0 10 20 30
freqency in MHz
0

−20 Figure 7: Power spectral density of the complex DDC out-

put signal I(k) + ¸ Q(k) after down conversion of a 20 MHz
−40 harmonic tone using a CORDIC-DDC with 16 iterations, 18
power spectral density in dB

fractional binary digits, and 12 bit ADC

−60

−80
References
−100
[1] T. Hentschel and G. Fettweis, “Software radio receivers,”
−120
in CDMA Techniques for Third Generation Mobile Sys-
tems (F. Swarts, P. van Rooyen, I. Opperman, and M. P.
−140 Lötter, eds.), vol. 487 of The Kluwer International Series
in Engineering and Computer Science, ch. 10, pp. 257–
−160 283, Kluwer Academic Publishers, 1999.
−30 −20 −10 0 10 20 30
freqency in MHz
[2] J. E. Volder, “The CORDIC trigonometric computing
Figure 6: Power spectral density of the complex DDC out- technique,” IRE Transactions on Electronic Computers,
put signal I(k) + ¸Q(k) after down conversion of a 20 MHz vol. EC–8, pp. 330–334, Sept. 1959.
harmonic tone using a CORDIC-DDC with 16 iterations, 18 [3] J. S. Walther, “A unified algorithm for elementary func-
fractional binary digits, and ideal ADC tions,” in Proceedings of the Joint Spring Computer Con-
ference, pp. 379–385, 1971.
[4] J. Vankka, “Methods of mapping from phase to sine am-
plitude in direct digital synthesis,” IEEE Transactions
6 CONCLUSIONS on Ultrasonics, Ferroelectrics, and Frequency Control,
vol. 44, pp. 526–534, Mar. 1997.
In this paper a CORDIC-based method for digital down con-
version was proposed which overcomes the drawback of the [5] R. Andraka, “A survey of CORDIC algorithms for
common DDC of requiring a very large ROM table to achieve FPGA based computers,” in Proceedings of the 1998
high resolution. Therefore, it helps to save chip area, power ACM/SIGDA 6th international symposium on Field pro-
consumption, and costs. Since this CORDIC-DDC can eas- grammable gate arrays, (Monterey, CA), pp. 191–200,
ily be implemented on a pipelined architecture, it is suitable Feb. 1998.
for high speed applications as required for the task of digital
down-conversion in software radio terminals. The CORDIC- [6] S. Wang, V. Piuri, and E. E. Schwartzlander, Jr.,
DDC can realize any oscillator frequency by simply feeding “Granularly-pipelined CORDIC processors for sine and
it with the appropriate saw-tooth input signal. No coefficients cosine generators,” in Proceedings of the 1996 IEEE In-
must be changed. Thus, it empowers the software radio con- ternational Conference on Acoustics, Speech and Signal
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