47.

1 DATA TRANSFER INSTRUCTIONS

The instruction set of the 8051 microcontrollef includes a variety of instructions tor
data transfer between theregisters and thememorv locations. The various
mnemonics used Tor data
transfer instructions are MOV, MOVC. MOVx PUSH POP XCH and XCHD, and they perform
any one of the following operations:
1. Copy the content of an SFR to the internalmemory or vice
versa.
2. Load an immediate operand to the SFR/internal memory.
3. Exchange the content of the SFR/internal memory with the accumulator.
4. Copy the content of the program memory to the accumulator.
5. Copy the content of the data memory to the accumulator or vice versa.
The data transfer instructions of 8051 are listed in Table 4.11 with a brief explanation abo
each instruction.
TABLE 4.11: DATA TRANSFER INSTRUCTIONS 22
4.

S.No. Instruction
Symbolicrepresentation Explanation
MOV A,Rn (A)- (Rn) The content of register Rn is movd to the accUmulator (A-register).
The Rn can be any one of the &régisters of the currently selected bank.
MOV A,direct, direct = 8-bit address of The content of internal RAMISÉR (whose address is specified
internal RAM/SFR directly in the instruction) is rgoved to accumulator (A-register).
(A) (RAM/SFR)
MOV A,@Ri/ (Ri)= Internal RAM address The content of internal RAM memory (whose address is specified by
(A) - (RAM) the Ri-registeris movgd to the accumulator (A-register). The
register Ri can be either R0 or R1or the currently selected register bank.
MOV A,#data (A) data The data given in the instruction is moved to the accumulator (A-register).
5. MOV Rn,A (Rn) (A) The content of the accumulator is moved to register Rn, where Rn is any
one of the 8 registers of the currently selected register bank.
8. MOV Rn,direct direçe = 8-bit address of The content of internal RAM/SFR (whose address is directly specified
intfnal RAM/SFR in the instruction) is moved to register Rn, where Rn is any one of the
(Bh) (RAM/SFR) 8 registers of the currently selected register bank.
t7. MOV Rn,#data Rn)- data The immediate data given in the instruction is moved to register Rn,
where Rn is any one of the 8 registers of the currently selected register
bank.
8 MOV direct,A direct = 8-bit address of internal The content of the accumulator is moved to internal RAM/SFR M1crop
RAM/SFR (RAM/SFR) (A) whose address is directly specified in the instruction.
|MOV direct, Rn direct = 8-bit address of internal The content of register Rn is moved to internal RAM/SFR
RAM/SFR (RAM/SFR) (Rn) whose address is directly specified in the instruction.
10 MOV direct,direct direct = 8-bit address of internal The content of one internal RAM/SFR is moved to another
RAM/SFR internal RAM/SFR. The address of the source and destination
(RAM/SFR)(RAMWSFR) are directly specified in the instruction.
11. MOV direct, @Ri (Ri) = Internal RAM address The content of internal RAM whose address is specified by Ri
of source operand is moved to another internal RAM/SFR whose address is
direct = Internal RAM/SFR directly specified in the instruction. The register Ri can be nrollcrs
address of destination operand either RO or R1.
(RAM/SFR) (RAM)
Table 4.11: continued...
Instruction
Symbolic representation
The immediate data given in the
Explanation
instruction is mnoved to the
thapter
S.No.
MOV direct,#data direct= Address of internal RAM/SF whose address is directly specified in the
4-
12. internal RAM/SFR,

Microcontrol er
(RAM/SFR) data
instruction.
moved to an internal RAM
The content of the accumulator is
(Ri) =Internal RAM address Ri-register. The
13. MOV @Ri,A location whose address is specified by the
(RAM) (A) register Rican be either R0 or R1.
whose address is directly
direct = Internal RAM/SFR address The content of the internal RAM/SFR
14. MOV @Ri,direct specified in the instruction is moved to another internal RAM
of source operand Ri-register. The
location whose address is specified by the
(Ri)= Internal RAM address of
destination operand. register Rican be either RO or R1.
(RAM) (RAM/SFR)
moved to an
The immediate data given in the instruction is
15. MOV @Ri,#data (Ri) =Internal RAM address address is specified by the
(RAM)+ data internal RAM location, whose
Ri-register. The register Ri can be RO or R1.
moved
16. MOV DPTR,#data16|(DPTR) - data16 The 16-bit constant (data16) given in the instruction is
(The content of the DPTR is used as address of
to the DPTR.
external data memory in the subsequent instruction.)
17. MOVC A,@A+DPTR (A) + (DPTR) = Address of program This instruction will copy a byte from the codelprogram memory
memory to the accumulator. The address of the program memory is given
(A) + (program memory) by the sum of the content of the DPTR and accumulator before
the move operation.
18. MOVC A,@A+PC (PC) - (PC)+1 This instruction will copy a byte from the codelprogram memory
(A) + (PC) =Address of program tothe accumulator. The address of the program memory is given
memory by the sum of the PC and the accumulator. Here, the content of
(A)+ (program memory) the PC is incremented before adding to A to get the address of
the code memory.
19. MOVX A,@Ri (Ri) =8-bit address external The content of external data RAM is moved to the accumulator.
data RAM The content of register Riis the 8-bit address of the
(A) - (RAM) external memory. The register Ri can be either RO or R1 of the
currently selected register bank.
20. MOVX A,@DPTR (DPTR)= 16-bit address of external The content of external data RAM is moved to the acCCumulator.
data RAM (A) 4 (RAM) The content of DPTR is the 16-bit address of the external RAM.
 Table 4.11: continued. 24
4.
S.No. Instruction
21.
Symbolic representation Explanation
MOVX @Ri,A (Ri) = 8-bit address of external data RAM
The coritent of the accurnulator is moved to the external
(RAM) (A) data RAM. The content of the Ri is the 8-bit address of
external RAM. The register Rican be either RO or R1
22.
of the currehtly selected register bank.
MOVX @DPTR,A (DPTR) =16-bit address of external data RAM The coniént of the accumulator is moved to the external
(RAM) < (A) data RAM. The content of the DPTRis the 16-bit address
of he external RAM.
23. PUSH direct (SP) (SP) + 1 The stack pointer is incremented by one. The content of
direct = 8-bit address of internal RAM/SFR the internal RAMISFR (whose address is directly specified
((SP)) (RAM/SFR) in the instruction)is moved to the intermal RAM memory
pointed by the SP.
24. POP direct direct = 8-bit address of internal RAM/^FR The content of the internal RAM memory pointed by the
(RAM/SFR}-(SP) SP is moved to the internal RAM/SFR (whose address
(SP) (SP) 1 isdirectly specified in the instruction). Then the stack
pointer is decremented by one.
25. XCH A,Rn (A)Z (Rn) The content of register Rn is exchanged with the
accumulator. The register Rn can be any one of the eight
registers of the currently selected register bank.
26. XCH A,direct direct = 8-bit address of internal RAM/SFR The content of the internal RAM /SFR whose address
(A) (RAMISFR) is directly specified in the instruction is exchanged with
the accumulator.
27. XCH A,@Ri (Ri) =8-bit address of internal RAM The content of the internal RAM whose address is specified
(A) (RAM) by the Ri-register is exchanged with the accumulator.
The register Ri can be either RO or R1 of the currently
selected register bank.
28. XCHD A,@Ri (Ri) =&-bit address of internal RAM The lower nibble of the internal RAM addressed by Ri
(A)a0 (RAM),o register is exchanged with the lower nibble of the
accumulator. The content of the upper nibble of RAM
and accumulator are not altered. The Register Rican
be either RO or R1 of the currently selected register
bank.
 WAP A
(Ao The higher nibble of the accumulator is exchanged with the
lower nibble of the acCumulator.
4.7.4 PROGRAM BRANCHING INSTRUCTIONS

Nomally, aprogram is executed sequentially and the PC(ProgramCounter) keeps track of the address of the instructions and it
is incremented appropriately after each fetch operation. The program branching instructions will modify the content of the PCso that,
the program control branches to a new address. The program branching instructions of 805I includes conditional and unconditional
olers
branching instruction. Inconditional branching instructions, the content of the PC is modified, only ifthe condition

instrucions like
instruction, the PC is always modifcd. The MICrocontroller
hapter-
instruction is true, whereas in unconditional
branching
modifying the PC. The program branching instructions
enecifed in the
previous value of thePC in thestack before
ACALL and LCALL willsave the explanationabout each instruction.
4.14 with a brief
of 805Iare listed in Table
PROGRAM BRANCHING INSTRUCTIONS
TABLE 4.14:
Explanation
S.No. Instruction Symbolic representation unconditionally call a subroutine which resides within
This instruction is used to
ACALL addr11 (PC)(PC) + 2
of the program memory in which the instruction following ACALL
78.
(SP) -(SP)+1 the same 2k block increments the PCby two, to point to the
is stored. This instruction first incremented
(SP) (PCh Next, the content of the SP is
address of the instruction next to ACALL. SP.
(SP) - (SP) +1 saved in the stack memory pointed by
by one and the low byte of PC is saved in
(SP)) -(PC)15-8
content of the SP is incremented by one and then, high byte of PCis
Again,
(PC)pa - addr11 Then, the 11-bit address given in the
the stack memory pointed by the SP. thePC. (The 11- bit address is the
instruction is moved to the lower 11-bit position of opcode.) Now, the controller
of the
second byte of the instruction and upper 3 bits
address.
starts fetching the instructions from this new
instruction is used to unconditionally call a subroutine anywhere in the 64 k
This
79.LCALL addr16 (PC) - (PC) +3 three to point to the next instruction.
(SP) - (SP) +1 space. First, the PC is incremented by the PC is saved in the stack memory
of
Next, the SP is incremented and the content
(SP) + (PCh given in the instruction is moved
(SP) - (SP) +1 pointed by the SP. Then, the 16-bit address address.
fetching the instruction from this new
(SP) (PChs8 to the PC and so the controller
(PC) - addr16 starts
this
terminate a subroutine. On execution of
(PC),., + (SP) This instruction is used to is moved
80. RET the stack memory pointed by the SP
instruction, the content of
(SP) -(SP)-1
high byte of PC and SP is decremented by one. Then, the content of the
(PC),, 4-(SP) tothe
the low byte of PCand again
(SP) - (SP)- 1 stack memory pointed by SP is moved to
the SP is decremented by one.
This
terminate an interrupt service subroutine.
(PC),- (SP) This RETI instruction is used to to that of RET instruction
81.RETI top of the stack to the PC similar tho
Table 4.14: continued.
|s.No Instruction Symbolic representation Explanation
memory iocation wthin
82. AJMP addr11 (PC) (PC) +2 This instruction is used to unconditionally /urno to a
which the instruction
(PC),,n f- addr11 the same 2k block of progran memory in
by two to point to the
following AJMP is stored. First, the PCis incrernented
instruction and then the 11-bit address given in the instrucion
address of next address is the second
11-bit position of the PC.The 11-ot
is moved to the lower
byte of the instruction and upper 3 bits of opcode
to any location in the 64 k
LJMP addr16 (PC) addr16 This instruction is used to unConditionally jump
83. instruction,the 16-bit address given
memory space. Upon execution of this controller starts fetching the
instruction is moved to the PC, and so the
in the
instruction from this new address.

the program control to

SJMP offset (PC) (PC) + 2 This instruction is used to unconditionally transfer
84.
obtained by adding the 8-bit signed offset to the content
(PC)+ (PC) + offset a new address
of the PC. The offset will be in the range of -128,,to +127n:
program control has
JMP @A+DPTR (A) + (DPTR) = Address This instruction computes the address to which the
85. address in the PC. The address is
(PC) Address to be transferred and loads this content
accumulator and the 16-bit
given by the sum of the signed 8-bit in the
of the DPTR.
Next, the content of
JZ offset (PC) (PC) + 2 First, the content of the PC is incremented by two.
accumulator is zero, then the
86. accumulator is checked. If the content of the
If (A) = 0 then added to the PC, so that the
(PC)- (PC) + offset 8-bit signed offset given in the instruction is accumulator is not zero
program control branches to new address. If the
the next instruction of the program is fetche
then PC is not modified, so that
and executed.

Next, the content of

87. JNZ offset (PC) (PC) + 2 First, the content of the PC is incremented by two.accumulator is not zero,
the accumulator is checked. If the content of the
If (A) =0then added to the PC,
(PC) (PC) + offset then the 8-bit signed offset given in the instruction is If the accumula
new address.
So that the program control branches to a
is zero, then PC is not modified so that the next instruction of the progr
is fetched and executed.
 Symolie re

CINEAdiredfset (PC)
diret
(PC) 3 First, trhe PCis irirornerted ty threes tr
Address of internal RAM/SERontent f the accurnulator ard thie internal PAMISFR (whose
f (A) (RAMISFR) then
(PC) 4 (PC)+ offset
If (A) <(RAMISFR) then, CF 1
|If (A) > (RAMISFR) then, CF 4 0
addrgss is dirertty speified in the instrurtion) are ompared. Kthe
contents are not 9qual then the prograrn onrol is transferred to a
new address. The new address is the un of the PC and otset grven
ordMro ntro
irt , thereni n t n . The

in the instruction. Also, if the ontent of the arcurnulator is less than

RAMISFR, then the carry flag is set,otherwise tis cleared.
|(PC) <(PC) +3 This instruction is sarne as CJNE A,direct,offset encept that the
If (A) data then cormparison is perforrned with the imnediate data gven in the
|(PC)4 (PC)+ offset instruction andthe accumulator.
|f (A) < data then, CF 41
f (A) >data then, CF 40
CJNE RnWta,tsst (PC) 4-(PC) +3 This ínstruction is sarne as CJNE A,direct,offset except that the
|H (Rn) z data then cormparison is performedwith the content of the Rnand the immediate
(PC)4- (PC) + offsst data. The Rncan beany one of the eight registers of the currently
|H (Rn)< data then, CF 41 sslected register bank,
(Rn) > datathen, CF 40
CINE Fi #4sta, tset|(PC) (PC) +3 This instructíon is same as CJNE A,direct,ofset except that the
(Ri) =Asdrsssof internal RAM comparison is performed between the RAM (whose address is
|f(RAM) datathen specified by Ri) and the immediate data given in the instruction.
(PC)4 (PC)+ offsst The register Ri can be either RO or R1 of the currently selected
|H (Ri)< data thn, CF 4- 1 rogister bank
|H (Ri) >datathen, CF 4 0
|(PC) 4 (PC) +2 First, the PC is incremented by two to point to the address of the
|(Rn) (Rn)-1 next instruction. Then, the content of register Rn is decremented by one.
AU May'15,2 murkel If (Rn) 0then If the content of Rn (after decrement) is not equal to zero then, the
|(PC)4 (PC) + offsst offset glven In the instruction is added to the PCso that, the program
control branchos to a new address. The register Rncan be any one
of tho olght registers of the currentty selected register bank .33
able 4.14:continued
Instruction Symbolic representation ExpBanatinn
S.No.
DJNZ direct,offset (PC) (PC) + 2 This instruction is sanme as DJNZ Rn, offset xceot hat he content
93
direct = Address of RAMISFR of the RAM/SFR isdecremented and comoarsd The oress of the
(RAM/SFR) (RAM/SFR) -1 RAMISFR is directly specified in the instruction
If (RAM/SFR) 0then
(PC) + (PC) + offset

94 NOP (PC) + (PC) + 1 This instruction will not perform any operation. Sxcet hat he PCis
incremented by one to point to the next instruction. EAecutton of NOP
will produce a delay ofone machine cycle time and so, his instruction
can be used to create smalldelaysin multiplies of machine cycde time.