Scribd
Upload
5 views5 pages

Assignment 5 CG

Uploaded by

atp20.12.2003
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
5 views5 pages

Assignment 5 CG

Uploaded by

atp20.12.2003
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 5

Jadavpur University

Department of Electronics and Tele-Communication Engineering


Faculty of Engineering and Technology

Computer Architecture and System


Software Lab

UG-IV Semester-VII
Submitted By - Adway Paul
Roll - 002110701100
Group - G1
Assignment - 3
Question: Design a 4-bit Arithmetic Logic Unit (ALU) capable of
performing arithmetic and logic operations such
as addition, subtraction, AND, OR, and NOT. Implement the ALU using
suitable logic gates and
components. Verify its functionality by testing it with a range of test inputs and
operations.

Introduction: An Arithmetic Logic Unit (ALU) is a digital circuit that


performs arithmetic (like addition, subtraction) and logic operations (like AND,
OR, NOT). It's a core component of CPUs and is responsible for executing the
majority of mathematical and logical instructions. A typical ALU takes two
input values, uses a control signal (opcode) to select the operation, and outputs
the result along with flags like carry-out and zero. The ALU's efficiency directly
impacts the performance of the processor.

Theory: Designing a 4-bit Arithmetic Logic Unit (ALU) involves creating a


module that can perform basic arithmetic and logic operations, such as
addition, subtraction, AND, OR, and NOT. The ALU will have two 4-bit
inputs, a 3-bit control signal to select the operation, and 4-bit output for the
result, along with an additional carry-out and zero flag. The carry-out flag is set
when there is a carry-out from addition or subtraction. The zero flag is set when
the result is 0. The opcode control signal determines which operation is
performed on A and B. Based on the value of opcode, the ALU will either
perform addition, subtraction, AND, OR, or NOT.

Operations:

● Addition (opcode 000)


● Subtraction (opcode 001)
● AND (opcode 010)
● OR (opcode 011)
● NOT (opcode 100)

Implementation:
Program Code:
Here we used verilog to design our4bit ALU using above specifications .
module ALU_4bit (
input [3:0] A, // 4-bit input A
input [3:0] B, // 4-bit input B
input [2:0] opcode, // 3-bit opcode for operation selection
output reg [3:0] result, // 4-bit output result
output reg carry_out, // Carry out for addition/subtraction
output zero // Zero flag (1 if result is zero)
);
wire [4:0] sum, diff; // Wires for storing sum and difference
wire [3:0] and_res, or_res, not_res; // Wires for logical operations

// Arithmetic operations
assign sum = A + B; // Addition
assign diff = A - B; // Subtraction

// Logical operations
assign and_res = A & B; // AND
assign or_res = A | B; // OR
assign not_res = ~A; // NOT (only applied to A)

// Zero flag logic (set if result is zero)


assign zero = (result == 4'b0000);

always @(*) begin


carry_out = 0; // Default carry out
case (opcode)
3'b000: begin // Addition
result = sum[3:0];
carry_out = sum[4]; // Carry out is the 5th bit of sum
end
3'b001: begin // Subtraction
result = diff[3:0];
carry_out = diff[4]; // Carry out for subtraction
end
3'b010: result = and_res; // AND
3'b011: result = or_res; // OR
3'b100: result = not_res; // NOT (only on A)
default: result = 4'b0000; // Default to zero for invalid opcode
endcase
end
endmodule

Testbench Code:
module test_ALU_4bit_random;
reg [3:0] A, B; // 4-bit inputs
reg [2:0] opcode; // 3-bit opcode
wire [3:0] result; // 4-bit result
wire carry_out, zero; // carry-out and zero flags

// Instantiate the ALU


ALU_4bit uut (
.A(A),
.B(B),
.opcode(opcode),
.result(result),
.carry_out(carry_out),
.zero(zero)
);

integer i; // Loop variable

initial begin
// Randomly generate test cases for a certain number of cycles
for (i = 0; i < 10; i = i + 1) begin
A = $random % 16; // Random 4-bit value for A (0 to 15)
B = $random % 16; // Random 4-bit value for B (0 to 15)
opcode = $random % 5; // Random 3-bit opcode (0 to 4, as we have 5
operations)

// Display the test case details and the ALU output


#10 $display("Test case %d: A = %b, B = %b, Opcode = %b, Result = %b, Carry =
%b, Zero = %b",
i+1, A, B, opcode, result, carry_out, zero);
end

$stop; // Stop the simulation


end
endmodule

Simulation Output:
Output Waveform:

Conclusion: This 4-bit ALU supports basic arithmetic and logic operations,
and its functionality can be verified using the provided testbench. The testbench
will generate 20 random tests, displaying the input values and the ALU outputs
after each cycle.

You might also like