14-01-2023

MAJOR DIFFERENCES BETWEEN 8085 AND 8086

8086 Microprocessor
Block Diagram and Pin Function description

Reference: Understanding 8085/8086 Microprocessors and Peripherals IC’s Through Questions and answers: S. K. Sen
2nd ed., New Age International (P) Limited, Publishers, 2010 . The content in the slides are used for Academic Purpose only

1
 14-01-2023

8086 CPU Block Diagram and Pin Diagram

Source: Intel datasheet

Architecture of 8086
✓ The architecture of 8086 provides a number of improvements over 8085 architecture.
✓ It supports:
✓ A 16-bit ALU, A set of 16-bit registers
✓ Direct segmented memory addressing capability of 1Mbyte
✓ A rich instruction set with 8 and 16-bit signed and unsigned arithmetic in binary or decimal including
multiply and divide, bit, byte, word and block operations
✓ Powerful interrupt structure
✓ 6 byte instruction queue for overlapped fetching and execution.
✓ Clock frequency of 5MHz (8086), 8 MHz (8086-2) and 10 MHz (8086-1)
✓ The complete architecture of 8086 can be logically divided into two units
✓ a) Bus Interface Unit (BIU) and
✓ (b) Execution Unit (EU).
✓ Both units operate asynchronously to provide the 8086 to overlap instruction fetch and execution
operation, which is called as parallel processing.

2
 14-01-2023

Pipelining of 8086

Non-Pipelining Process of 8085

Registers of 8086

3
 14-01-2023

Registers of 8086

✓ The general-purpose registers in 8088/86 microprocessors can be accessed as either 16-bit

or 8-bit registers. All other registers can be accessed only as the full 16 bits.
✓ In the 8088/86, data types are either 8 or 16 bits. To access 12-bit data, for example, a 16-
bit register must be used with the highest 4 bits set to 0.
✓ The first letter of each general register indicates its use. AX is used for the accumulator, BX
as a base addressing register, CX is used as a counter in loop operations, and DX is used
to point to data in I/O operations.

Special Purpose Registers

✓ The special purpose registers are Segment registers, Pointers and index registers
✓ Segment Registers: Unlike 8085, the 8086 addresses a segmented memory of 1 MB, which
the 8086 is able to address.
✓ The 1 MB is divided into 16 logical segments (16 X 64 KB = 1024 KB = 1 MB). Each segment
thus contains 64 Kbytes of memory.
✓ There are four segment registers, viz.
✓ Code Segment Register (CS),
✓ Data Segment Register (DS),
✓ Extra Segment Register (ES)
✓ and Stack Segment Register (SS).

4
 14-01-2023

Special Purpose Registers

Pointers and Index Registers:

✓ The pointers contain offset within the particular segments.
✓ The pointers IP, BP and SP usually contain offsets within the code, data and stack segments
respectively.
✓ The index registers are used as general purpose registers as well as for offset storage in case
of indexed, based indexed and relative based indexed addressing modes.
✓ The register SI is generally used to store the offset of source data DS while the register DI is
used to store the offset of destination in DS or ES.
✓ The index registers are particularly useful for string manipulations.

Special Purpose Registers

Flag Register (status Register):

✓ The FLAG is group of flip-flops which are affected (SET or RESET) immediately after an
arithmetic or logical operation performed by the ALU.
✓ The flags of 8086 can be divided into two types: Conditional Flags and Control Flags
✓ Conditional Flags are affected immediately after an arithmetic or logical operation performed
by the ALU.
✓ The 8086 has 6 conditional flags, out of which 5 (same as 8085) while Overflow flag is the
additional flag.
✓ Control Flags are not affected by arithmetic or logical operation performed by the ALU but
programmer can SET or RESET these Flags to control certain operation/Instructions.

5
 14-01-2023

Special Purpose Registers

Flag Register:

THE 80x86 IBM PC AND COMPATIBLE COMPUTERS VOLUMES I & II Assembly Language, Design, and Interfacing Fourth Edition, Muhammad Ali Mazidi, Janice Gillispie Mazidi , Pearson Education International, 2003

Special Purpose Registers

Conditional Flag:
CF, the Carry Flag. This flag is set whenever there is a carry out, either from D7 after an 8-bit
operation, or from D15 after a 16-bit data operation.
PF, the Parity Flag. After certain operations, the parity of the result's low-order byte is checked. If
the byte has an even number of 1s, the parity flag is set to 1; otherwise, it is cleared.
AF, Auxiliary Carry Flag. If there is a carry from D3 to D4 of an operation, this bit is set; otherwise,
it is cleared (set equal to zero). This flag is used by the instructions that perform BCD arithmetic.
ZF, the Zero Flag. The zero flag is set to 1 if the result of an arithmetic or logical operation is zero;
otherwise, it is cleared.
SF, the Sign Flag. Binary representation of signed numbers uses the most significant bit as the
sign bit. After arithmetic or logic operations, the status of this sign bit is copied into the SF, thereby
indicating the sign of the result.

6
 14-01-2023

Special Purpose Registers

✓ OF, the Overflow Flag. This flag is set whenever the result of a signed number operation is too
large, causing the high-order bit to overflow into the sign bit.
✓ This flag is set under one of the following conditions
✓ i) there is an overflow into the MSB (8th or 16th bit) from the bit of lower significance, but no
carry out from the MSB,
✓ ii) there is a carry out from the MSB, but no carry into the MSB. This flag indicates that the result
of a signed number operation is too large, causing the higher order bit to overflow into the sign
bit, thus changing the sign bit.

Control Flag:
✓ TF, the Trap Flag. When this flag is set it allows the program to single-step, meaning to execute
one instruction at a time. Single-stepping is used for debugging purposes.
✓ IF, Interrupt Enable Flag. This bit is set or cleared to enable or disable only the external
maskable interrupt requests.
✓ OF, the Direction Flag. This bit is used to control the direction of string operations.
✓ In general, the carry flag is used to detect errors in unsigned arithmetic operations. The overflow
flag is only used to detect errors in signed arithmetic operations.

7
 14-01-2023

Example

Example

8
 14-01-2023

INTRODUCTION TO SEGMENTATION

✓ A typical Assembly language program consists of at least three segments:

✓ The code segment contains the Assembly language instructions that perform the tasks that
the program was designed to accomplish.
✓ The data segment is used to store information (data) that needs to be processed by the
instructions in the code segment.
✓ The stack is used to store information temporarily.
✓ The extra segment

Definition of the segment

✓ A segment is an area of memory that includes up to 64K bytes and begins on an address
evenly divisible by 16 (such an address ends in 0H).
✓ The segment size of 64K bytes came about because the 8085 microprocessor could address a
maximum of 64K bytes of physical memory since it had only 16 pins for the address lines (2 16 =
64K).
✓ This limitation was carried into the design of the 8088/86 to ensure compatibility Whereas in the
8085 there was only 64K bytes of memory for all code, data, and stack information, in the
8088/86 there can be up to 64K bytes of memory assigned to each category.
✓ The 8088/86 can only handle a maximum of 64K bytes of code and 64K bytes of data and 64K
bytes of stack at any given time, although it has a range of 1 megabyte of memory because of
its 20 address pins (220 = 1 megabyte).

9
 14-01-2023

Logical address and physical address

✓ In Intel literature concerning the 8086, there are three types of addresses mentioned
frequently: The physical address, the offset address, and the logical address.
✓ The physical address is the 20-bit address that is actually put on the address pins of
the 8086 microprocessor and decoded by the memory interfacing circuitry. This address
can have a range of 00000H to FFFFFH for the 8086. This is an actual physical location
in RAM or ROM within the 1 megabyte memory range.
✓ The offset address is a location within a 64K-byte segment range. Therefore, an offset
address can range from 0000H to FFFFH. Offset is the displacement of the memory
location from the starting location of the segment.
✓ The logical address consists of a segment value (Base address) and an offset address.

10
 14-01-2023

Code segment
✓ To execute a program, the 8086 fetches the instructions (opcodes and operands) from the
code segment. The logical address of an instruction always consists of a CS (code segment)
and an IP (instruction pointer), shown in CS:IP format.
✓ The physical address for the location of the instruction is generated by shifting the CS left one
hex digit and then adding it to the IP. IP contains the offset address.
✓ The resulting 20-bit address is called the physical address since it is put on the external
physical address bus pins to be decoded by the memory decoding circuitry.

THE 80x86 IBM PC AND COMPATIBLE COMPUTERS VOLUMES I & II Assembly Language, Design, and Interfacing Fourth Edition, Muhammad Ali Mazidi, Janice Gillispie Mazidi , Pearson Education International, 2003

80x86 ADDRESSING MODES

✓ The CPU can access operands (data) in various ways, called addressing modes.
✓ The number of addressing modes is determined when the microprocessor is designed and
cannot be changed. The 80x86 provides a total of seven distinct addressing modes:
1. Register
2. Immediate
3. Direct
4. Register indirect
5. Based relative
6. indexed relative
7. Based indexed relative

11
 14-01-2023

Register addressing mode:

✓ The register addressing mode involves the use of registers to hold the data to be manipulated.
Memory is not accessed when this addressing mode is executed; therefore, it is relatively fast.

Immediate addressing mode:

✓ In the immediate addressing mode, the source operand is a constant. Immediate addressing
mode can be used to load information into any of the registers except the segment registers
and flag registers.

✓ To move information to the segment registers, the data must first be moved to a general-purpose register
and then to the segment register.

12
 14-01-2023

Direct addressing mode

✓ In the direct addressing mode the data is in some memory location(s) and the address of the data in
memory comes immediately after the instruction.
✓ Note that in immediate addressing, the operand itself is provided with the instruction, whereas in direct
addressing mode, the address of the operand is provided with the instruction.
✓ This address is the offset address and one can calculate the physical address by shifting left the DS
register and adding it to the offset as follows:

✓ In this case the physical address is calculated by combining the contents of offset location 2400 with DS,
the data segment register.
✓ Notice the bracket around the address. In the absence of this bracket it will give an error since it is
interpreted to move the value 2400 (16-bit data) into register DL, an 8-bit register.

Example

THE 80x86 IBM PC AND COMPATIBLE COMPUTERS VOLUMES I & II Assembly Language, Design, and Interfacing Fourth Edition, Muhammad Ali Mazidi, Janice Gillispie Mazidi , Pearson Education International, 2003

13
 14-01-2023

Register indirect addressing mode

✓ In the register indirect addressing mode, the address of the memory location where the
operand resides is held by a register. The registers used for this purpose are SI, DI, and BX.
✓ If these three registers are used as pointers, that is, if they hold the offset of the memory
location, they must be combined with DS in order to generate the 20-bit physical address.

✓ Notice that BX is in brackets. In the absence of brackets, it is interpreted as an instruction

moving the contents of register BX to AL (which gives an error because source and
destination do not match) instead of the contents of the memory location whose offset
address is in BX.
✓ The physical address is calculated by shifting DS left one hex position and adding BX to it.
The same rules apply when using register SI or DI.

Example

THE 80x86 IBM PC AND COMPATIBLE COMPUTERS VOLUMES I & II Assembly Language, Design, and Interfacing Fourth Edition, Muhammad Ali Mazidi, Janice Gillispie Mazidi , Pearson Education International, 2003

14
 14-01-2023

Based relative addressing mode

✓ In the based relative addressing mode, base registers BX and BP, as well as a displacement
value, are used to calculate what is called the effective address.
✓ The default segments used for the calculation of the physical address (PA) are DS for BX and
SS for BP.

✓ Alternative coding are "MOV CX,[BX+1O]" or "MOV CX,1O[BX]". Again the low address
contents will go into CL and the high address contents into CH.

✓ Again, alternative coding are "MOV AL,[BP+5]" or "MOV AL,5[BP]".

✓ The terminology effective address is used in Intel literature. In "MOV AL,[BP]+5", BP+5 is
called the effective address since the fifth byte from the beginning of the offset BP is moved to
register AL.
✓ Similarly in "MOV CX,[BX]+10", BX+10 is called the effective address.

Indexed relative addressing mode

✓ The indexed relative addressing mode works the same as the based relative addressing
mode, except that registers DI and SI hold the offset address.

THE 80x86 IBM PC AND COMPATIBLE COMPUTERS VOLUMES I & II Assembly Language, Design, and Interfacing Fourth Edition, Muhammad Ali Mazidi, Janice Gillispie Mazidi , Pearson Education International, 2003

15
 14-01-2023

Based indexed addressing mode

✓ By combining based and indexed addressing modes, a new addressing mode is derived
called the based indexed addressing mode. In this mode, one base register and one index
register are used.

THE 80x86 IBM PC AND COMPATIBLE COMPUTERS VOLUMES I & II Assembly Language, Design, and Interfacing Fourth Edition, Muhammad Ali Mazidi, Janice Gillispie Mazidi , Pearson Education International, 2003

16