Part 1: Gate switching control circuit without ground isolation

Pspice Schematic:

Fig: Schematic for PWM gate control without isolation

The circuit given in the labsheet has separate reference points for the source driving the
control circuit and the source driving output – namely because of the position of the
switching MOSFET in the buck converter part. In the above circuit, the MOSFET is gate
driven without ground isolation. Here, a capacitor charge-discharge occurs that can take
the voltage at the MOSFET gate higher than source voltage, driving it in the forward
operating region. In the output terminal, only the voltage without loading has been shown
to simplify simulation complexity (the circuit does not converge otherwise). Here both
the circuits can be driven using the same source voltage, essentially removing the
necessity of two separate sources for two parts of the circuit. One thing to be noted here
is that although the output shown is for the buck converter circuit, this type of gate
driving can be done for buck-boost modules also.
 Fig: Switching output (green) and overall output voltage (red)

In the output, the voltage at the PWM controller output (green signal) and the overall
output voltage of the converter circuit (red signal) has been shown. The control circuit
has been set to generate a pulsewidth of 50%, hence the output voltage shown has a 50%
duty cycle too. The switching signal is supposed to be a pulse wave, but there is a
considerable distortion in the waveform – this is due to the capacitor at the output stage
of the switching circuit – the charging cycle of the capacitor lowers the actual voltage in
this part. As for the output, since this is a buck converter, a constant DC output would be
expected, but the output shown is also a square wave. Again this is because no capacitor-
inductor has been added at the buck output to simplify circuit simulation. Adding filters
would give a constant DC output. In this circuit, the time average output voltage = 6 volts
(12 volts source x 0.5 duty cycle)
Part 2: Buck Boost converter configurations Simulink

Fig: (3-a) Zeta converter (positive output buck-boost converter)

Fig: (3-b) Buck-boost converter with continuous input current

 Fig: (4-a) Cuk converter

Fig: (4-b) Sepic converter

For constructing the circuits, we used generic Simscape electrical circuit blocks and
mostly used the default values unless specified in the original circuit design. The values
of all inductors in the circuits have been set to 27mH.
Part 3: Output voltage-pwm and inductor current-voltage plots
ZETA CONVERTER:

Fig: (a) Switching signal 25% duty cycle (b) VOUT (c) IL (d) VL

Outputs for Zeta converter circuit

Fig: (a) Switching signal 50% duty cycle (b) VOUT (c) IL (d) VL

Outputs for Zeta converter circuit

Fig: (a) Switching signal 75% duty cycle (b) VOUT (c) IL (d) VL

Outputs for Zeta converter circuit

CONTINUOUS INPUT CURRENT BUCK-BOOST CONVERTER:

Fig: (a) Switching signal 25% duty cycle (b) VOUT (c) IL (d) VL

Outputs for buck-boost with constant input current

Fig: (a) Switching signal 50% duty cycle (b) VOUT (c) IL (d) VL

Outputs for buck-boost with constant input current

Fig: (a) Switching signal 75% duty cycle (b) VOUT (c) IL (d) VL

Outputs for buck-boost with constant input current

CUK CONVERTER

Fig: (a) Switching signal 25% duty cycle (b) VOUT (c) IL (d) VL

Outputs for Cuk converter

Fig: (a) Switching signal 50% duty cycle (b) VOUT (c) IL (d) VL

Outputs for Cuk converter

Fig: (a) Switching signal 75% duty cycle (b) VOUT (c) IL (d) VL

Outputs for Cuk converter

CEPIC CONVERTER:

Fig: (a) Switching signal 25% duty cycle (b) VOUT (c) IL (d) VL

Outputs for Cepic converter

Fig: (a) Switching signal 50% duty cycle (b) VOUT (c) IL (d) VL

Outputs for Cuk converter

Fig: (a) Switching signal 75% duty cycle (b) VOUT (c) IL (d) VL

Outputs for Cuk converter

Part 4: Output Analysis
For a buck-boost converter, VOUT = D VIN / (1-D) where D = duty cycle

In all the circuits, the input voltage has been set to 12V dc, so expected outputs should be
(irrespective of voltage inversion at output):

25% duty cycle, VOUT = 0.25 * 12 / (1-0.25) = 4 Volts

50% duty cycle, VOUT = 0.50 * 12 / (1-0.50) = 12 Volts

75% duty cycle, VOUT = 0.75 * 12 / (1-0.75) = 36 Volts

Table: Simulation outputs (average DC values)

Buck-boost circuit 25% Duty 50% Duty 75% Duty

5.5V 12V 36V

Zeta Converter
(No overshoot) (+5.5 overshoot) (+6 overshoot)
-4.5V -11V -38V
CC Converter
(-1 overshoot) (-5 overshoot) (No overshoot)
-6V -13V -38V
Cuk Converter
(No overshoot) (-5 overshoot) (-10 overshoot)
6V 12.5V 35V
Cepic Converter
(No overshoot) (+6 overshoot) (+10 overshoot)

From the simulation output graphs shown in part-3, the outputs have significant output
ripple voltages. However unlike the unfiltered circuit design of part-1, these circuits have
an average DC value in the range of expected output value.

For 25% duty cycle, none of the converters reached the expected value of 4V output. We
can explain this from the inductor current waveforms. It can be seen that at 25% duty
cycle, the inductor current falls to 0 in each cycle. Because of this, the voltage chopping
operation cannot achieve target value. One solution for this would be to use an
inductance of higher value.
For 50% duty cycle, Zeta and Cepic converters achieved expected output values. The
other two are also in close range to expected outputs. In all the circuits, there is a 50%
overshoot in the initial stage. This overshoot occurs due to the transient response of the
circuit, but dies out after reaching steady state.

For 75% duty cycle, all the circuits achieved near expected output levels. Only the
constant current controlled buck-boost converter (ckt-2) achieved zero overshoot, all the
other circuits had around 25% overshoot values.

Part 4: Inductor Tuning

In the zeta converter circuit (3-a), we saw that the output voltage was greater than
expected, and the reason explained was that inductor current was not entirely continuous
(dropping down to zero each cycle). A low inductance value causes this issue, and the
circuit cannot operate at optimal region. Because of this, we changed the series inductor
value from 27mH to 200mH, and the following results were obtained.
Output voltage with 27mH inductance (previously obtained)

Output voltage with 200mH inductance (Newly obtained)

Output voltage with 200mH series inductance and 470uF load capacitance

The last circuit has a longer time to reach steady state (about 10 times the original
circuits) but the output is very smooth – appropriate for DC operations. As can be seen
here - using higher inductance the desired 4V output at 25% duty cycle was obtained.
Inductor current in 27mH series inductance (previously obtained)

Inductor current in 200mH series inductance (newly obtained)

Inductor current in for 200mH inductance and 470uF output capacitor

Here in the first figure, we can see that inductor current has a peak of 0.14A, average
value of 0.07A and drops to 0 (inconsistent current). Since inductors resist sharp change
in current through them, higher inductance means a more stable current. Using a higher
inductance gives current in the range of 0.03A-0.05A (average of 0.04A) – a much more
consistent value than the previous one. Using a higher output capacitance does not
improve the steady state current values, but introduces a higher overshoot in the transient
response of the circuit.