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21 views3 pages

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nivaspenta910
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NAME: GODUGU NAVVYA DATE:

ROLL NO: 21EG504202 PAGE NO:

EXPERIMENT-1
VERIFY HDL CODE TO REALIZE ALL THE LOGIC GATES.
Aim: To realize all logic gates using Xilinx ISE 9.2i with Verilog HDL programming
language.

Tools Required:
Software: ISE Xilinx vivado
Hardware: Personal Computer

Theory:
AND, OR, NOT gates are basic gates. NAND and NOR are Universal gates. Basically, logic
gates are electronic circuit because they are made up of electronic device and components.

AND GATE:
If both the inputs are high the output will be high means 1 otherwise 0.

OR GATE:
If any of the input is high or both the inputs are high the output will be high means 1
otherwise 0.

NOT GATE:
NOT gate is also known as Inverter. It has one input A and one output Y.

NAND GATE:
It is the compliment of AND Gate.

NOR GATE:
It is the compliment of OR Gate.

EX-OR GATE:
The output of an EX-OR Gate is the module sum of its two inputs.

Source code:

Data flow Model:


module logicgates(c,d,e,f,g,h,i,a,b);
input a;
input b;
output c,d,e,f,g,h,i;
assign c=a&b; //and gate
assign d=~(a&b); //nand gate
assign e=a|b; //or gate
assign f=~(a|b); //nor gate
assign g=a^b; //xor gate

ANURAG UNIVERSITY ELECTRONIC CIRCUITS AND ANALYSIS LAB ECE DEPARTMENT


NAME: GODUGU NAVVYA DATE:
ROLL NO: 21EG504202 PAGE NO:

assign h=~(a^b); //xnor gate


assign i=~a; //inverter or not gate
endmodule

Test Bench Model:


module logicgates_tb();
reg a,b;
wire c,d,e,f,g,h,i;
logicgates uut(c,d,e,f,g,h,i,a,b);
initial begin
a=0;b=0;#100;
a=0;b=1;#100;
a=1;b=0;#100;
a=1;b=1;#100;
end
endmodule

Procedure:
1. Open Xilinx Vivado software tool and click on new project.
2. Select Verilog HDL language and proceed to next.
3. Select the Constraints inputs and outputs used for design.
4. Select Zedboard. A file will be selected write the code and save the file.
5. Check for errors, if any correct them.
6. Now add a source file for writing test bench code.
7. Write Test bench code and run synthesis.
8. Now run behavioral simulation for output waveform.

Applications:
1. There are mainly two applications of AND gate as Enable gate and Inhibit gate.
2. Logic gates are used in generation of parity generation and checking units.
3. The CMOS inverters are commonly used to build square wave oscillators which are used
for generating clock signals.

Result: Thus, realized all logic gates using Xilinx vivado with Verilog HDL programming
language.

Output:

ANURAG UNIVERSITY ELECTRONIC CIRCUITS AND ANALYSIS LAB ECE DEPARTMENT


NAME: GODUGU NAVVYA DATE:
ROLL NO: 21EG504202 PAGE NO:

ANURAG UNIVERSITY ELECTRONIC CIRCUITS AND ANALYSIS LAB ECE DEPARTMENT

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