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NAME: P.

VARSHITHA DATE:
ROLL NO: 20EG104249 PAGE NO:

EXPERIMENT-3
VERIFY HDL CODE TO REALIZE 8 TO 1 MULTIPLEXER AND
1 TO 8 DEMULTIPLEXER.
Aim: To realize 8 to 1 Multiplexer and 1 to 8 Demultiplexer using Xilinx ISE 9.2i with Verilog
HDL Programming language.

Apparatus: ISE Xilinx 9.2i.

Theory:
Mux is a device That has 2^n Input Lines. But Only One has Output Line. Where n= number of
input selector line. Mux is A device Which is used to Convert Multiple Input line into one Output
Line. At a time only one Input Line will Connect to the output line. Which Input Line Connected
In Output Line is decided by Input Selector Line.
A Demultiplexer is also called Demux or data distributor and its operation
is quite opposite to a multiplexer because it is an inverse to the multiplexer. The multiplexer is a
many-to-one circuit whereas the Demultiplexer is a one-to-many circuit. By using Demultiplexer,
the transmission of data can be done through one single input to a number of output data
lines. Multiplexers are called Data Selectors whereas Demultiplexers are Data Distributors
because they transmit similar information which is obtained at the input to various outputs.

Source Code (8 to 1 Multiplexer)

Data flow Model:


module mux81(
input [7:0] i,
input [2:0] s,
output y);
assign y=((~s[2])&(~s[1])&(~s[0])&i[0])|
((~s[2])&(~s[1])&(s[0])&i[1])|
((~s[2])&(s[1])&(~s[0])&i[2])|
((~s[2])&(s[1])&(s[0])&i[3])|
((s[2])&(~s[1])&(~s[0])&i[4])|
((s[2])&(~s[1])&(s[0])&i[5])|
((s[2])&(s[1])&(~s[0])&i[6])|
((s[2])&(s[1])&(s[0])&i[7]);
endmodule

ANURAG UNIVERSITY DIGITAL CIRCUITS AND SIMULATION LAB ECE DEPARTMENT


NAME: P.VARSHITHA DATE:
ROLL NO: 20EG104249 PAGE NO:

Test bench Model:


module mux81_tb();
reg [7:0]i;
reg [2:0]s;
wire y;
mux81 uut(i,s,y);
initial begin
i=8'b10011010;
s=3'b000;#10;
s=3'b001;#10;
s=3'b010;#10;
s=3'b011;#10;
s=3'b100;#10;
s=3'b101;#10;
s=3'b110;#10;
s=3'b111;#10;
end
endmodule

1 to 8 Demultiplexer:
Data flow Model:
module demux(
input i,
input s0,
input s1,
input s2,
output [7:0] d );
assign d[0]=(i & ~s2 & ~s1 & ~s0);
assign d[1]=(i & ~s2 & ~s1 & ~s0);
assign d[2]=(i & ~s2 & ~s1 & s0);
assign d[3]=(i & ~s2 & s1 & ~s0);
assign d[4]=(i & ~s2 & s1 & s0);
assign d[5]=(i & s2 & ~s1 & s0);
assign d[6]=(i & s2 & s1 & ~s0);
assign d[7]=(i & s2 & s1 & s0);
endmodule

ANURAG UNIVERSITY DIGITAL CIRCUITS AND SIMULATION LAB ECE DEPARTMENT


NAME: P.VARSHITHA DATE:
ROLL NO: 20EG104249 PAGE NO:

Test bench Model:


module demux_tb1();
reg i,s0,s1,s2;
wire [7:0]d;
demux uut(i,s0,s1,s2,d);
initial begin
i=0;s0=0;s1=0;s2=0;#100;
i=1;s0=0;s1=0;s2=1;#100;
i=2;s0=0;s1=1;s2=0;#100;
i=3;s0=0;s1=1;s2=1;#100;
i=4;s0=1;s1=0;s2=0;#100;
i=5;s0=1;s1=0;s2=1;#100;
i=6;s0=1;s1=1;s2=0;#100;
i=7;s0=1;s1=1;s2=1;#100;
end
endmodule

Procedure:
1. Open Xilinx Vivado software tool and click on new project.
2. Select Verilog HDL language and proceed to next.
3. Select the Constraints inputs and outputs used for design.
4. Select Zedboard. A file will be selected write the code and save the file.
5. Check for errors, if any correct them.
6. Now add a source file for writing test bench code.
7. Write Test bench code and run synthesis.
8. Now run behavioral simulation for output waveform.

Applications:
1.MUX is used for Multiple Data Transfer at Long Distance.
2.MUX is used to make Complected Circuit.
3.Demultiplexers are used in control systems, microprocessors to enable or select a single signal
from a number of signal.
4.Demux is used to choose several IO devices’ data routing.

Result: 8 to 1 Multiplexer and 1 to 8 Demultiplexer using Verilog HDL is realized in Xilinx ISE 9.2i
Software tool.

ANURAG UNIVERSITY DIGITAL CIRCUITS AND SIMULATION LAB ECE DEPARTMENT


NAME: P.VARSHITHA DATE:
ROLL NO: 20EG104249 PAGE NO:

Output:(8 to 1 Multiplexer)

ANURAG UNIVERSITY DIGITAL CIRCUITS AND SIMULATION LAB ECE DEPARTMENT


NAME: P.VARSHITHA DATE:
ROLL NO: 20EG104249 PAGE NO:

1 to 8 Demultiplexer:

ANURAG UNIVERSITY DIGITAL CIRCUITS AND SIMULATION LAB ECE DEPARTMENT

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