CENTRAL PROCESSING UNIT

• Introduction

• General Register Organization

• Stack Organization

• Instruction Formats

• Addressing Modes

• Data Transfer and Manipulation

• Program Control
 Introduction

MAJOR COMPONENTS OF CPU

Storage Components
Registers
Flags

Execution(Processing) Components
Arithmetic Logic Unit(ALU)
Arithmetic calculations, Logical computations, Shifts/Rotates

Transfer Components
Bus

Control Components
Control Unit
CPU – Designer Point of View –
the computer instruction set provides the specifications Register
File ALU
for the design of the CPU
User – Programmer – Point of View
- aware of the register set, the memory structure, the
type of data supported by the instructions, and the
function that each instruction performs
- 1) Instruction Formats Control Unit
- 2) Addressing Modes
- 3) Register Sets
 GENERAL REGISTER ORGANIZATION
• Register
– Memory locations are needed for storing pointers, counters, return
address, temporary results, and partial products during multiplication
– Memory access is the most time-consuming operation in a computer
– More convenient and efficient way is to store intermediate values in
processor registers
• When a large number of registers are included in the CPU, it is
most efficient to connect them through a common bus system.
• The registers communicate with each other not only for direct
data transfers, but also while performing various
microoperations.
• A common unit that can perform all the arithmetic, logic, and
shift microoperations in the processor.
 GENERAL REGISTER ORGANIZATION
Input
Clock

R1
R2
R3
R4
R5
R6
R7
Load

}
(7 lines)
SELA { MUX MUX SELB

3x8
A bus B bus
decoder

SELD
OPR ALU

Output
 GENERAL REGISTER ORGANIZATION
• Bus organization for 7 CPU registers
–2 MUX : select one of 7 register or external data
input by SELA and SELB
–BUS A and BUS B : form the inputs to a
common ALU
–ALU : OPR determine the arithmetic or logic
microoperation
» The result of the microoperation is available for external
data output and also goes into the inputs of all the
registers
–3 X 8 Decoder : select the register (by SELD)
that receives the information from ALU
 GENERAL REGISTER ORGANIZATION
• Example operation
– R1  R2 + R3
• Binary selector input :
– 1) MUX A selector (SELA) : to place the content of R2 into BUS A
– 2) MUX B selector (SELB) : to place the content of R3 into BUS B
– 3) ALU operation selector (OPR) : to provide the arithmetic addition R2 + R3
– 4) Decoder selector (SELD) : to transfer the content of the output bus into R1
The four control selection variables are generated in the control unit
and must be available at the beginning of a clock cycle.
The data from the two source registers propagate through the gates in
the multiplexers and the ALU, to the output bus, and into the inputs of
the destination register, all during the clock cycle interval.
When the next dock transition occurs, the binary information from the
output bus is transferred into R 1.
 Control

OPERATION OF CONTROL UNIT

The control unit
Directs the information flow through ALU by
- Selecting various Components in the system
- Selecting the Function of ALU
Example: R1 <- R2 + R3
[1] MUX A selector (SELA): BUS A ← R2
[2] MUX B selector (SELB): BUS B ← R3
[3] ALU operation selector (OPR): ALU to ADD
[4] Decoder destination selector (SELD): R1 ← Out Bus
3 3 3 5
Control Word SELA SELB SELD OPR

Encoding of register selection fields

Binary
Code SELA SELB SELD
000 Input Input None
001 R1 R1 R1
010 R2 R2 R2
011 R3 R3 R3
100 R4 R4 R4
101 R5 R5 R5
110 R6 R6 R6
111 R7 R7 R7
 ALU CONTROL

Encoding of ALU operations

OPR Operation Symbol

Select
00000 Transfer A TSFA

00001 Increment A INCA

00010 ADD A + B ADD
00101 Subtract A - B SUB
00110 Decrement A DECA
01000 AND A and B AND
01010 OR A and B OR
01100 XOR A and B XOR
01110 Complement A COMA
10000 Shift right A SHRA
11000 Shift left A SHLA
 Examples of ALU Microoperations

Symbolic Designation Control Word

Microoperation SELA SELB SELD OPR SELA SELB SELD OPR
R1 R2 - R3 R2 R3 R1 SUB 010 011 001 00101
R4R4 ˅ R5 R4 R5 R4 OR 100 101 100 01010
R6  R6 + 1 R6 - R6 INCA 110 000 110 00001
R7  R1 R1 R7 TSFA 001 111 00000
Output  R2 R2 None TSFA 010 000 000 00000
Output  Input Input - None TSFA 000 000 000 00000
R4  shl R4 R4 R4 SHLA 100 000 100 11000
R5 0 R5 R5 R5 XOR 101 101 101 01100
 REGISTER STACK ORGANIZATION
Stack
- Very useful feature for nested subroutines, nested loops control
- Also efficient for arithmetic expression evaluation
- Storage which can be accessed in LIFO
- Pointer: SP
- Only PUSH and POP operations are applicable
Register Stack
stack Address
63
Flags
FULL EMPTY

Stack pointer 4
SP C 3
B 2
A 1 Push, Pop operations
0
DR /* Initially, SP = 0, EMPTY = 1, FULL = 0 */

PUSH POP
SP ← SP + 1 DR ← M[SP]
M[SP] ← DR SP ← SP - 1
If (SP = 0) then (FULL ← 1) If (SP = 0) then (EMPTY ← 1)
EMPTY ← 0 FULL ← 0
 MEMORY STACK ORGANIZATION

1000
Memory with Program, Data, PC
Program
(instructions)
and Stack Segments
Data
AR (operands)

SP 3000
stack
3997
3998
3999
4000
4001
- A portion of memory is used as a stack with a DR
processor register as a stack pointer

- PUSH: SP ← SP - 1
M[SP] ← DR
- POP: DR ← M[SP]
SP ← SP + 1

- Most computers do not provide hardware to check stack overflow (full stack) or underflow
(empty stack)
 Stack Organization

REVERSE POLISH NOTATION

Arithmetic Expressions: A + B
A + B Infix notation
+ A B Prefix or Polish notation
A B + Postfix or reverse Polish notation
- The reverse Polish notation is very suitable for stack manipulation

Evaluation of Arithmetic Expressions

Any arithmetic expression can be expressed in parenthesis-free Polish notation, including
reverse Polish notation

(3 * 4) + (5 * 6) ⇒ 34*56*+

6
4 5 5 30
3 3 12 12 12 12 42
3 4 * 5 6 * +
 Problems
• A bus-organized CPU has 16 registers with 32 bits in each, an ALU, and a destination
decoder.
– a. How many multiplexers are there in the A bus, and what is the size of each multiplexer?
– b. How many selection inputs are needed for MUX A and MUX B?
– c. How many inputs and outputs are there in the decoder?
– d. How many inputs and outputs are there in the ALU for data, including input and output
carries?
– e. Formulate a control word for the system assuming that the ALU has 35 operations
• Solution
– (a) 32 multiplexers, each of size 16 × 1.
(b) 4 inputs each, to select one of 16 registers.
(c) 4-to-16 – line decoder
(d) 32 + 32 + 1 = 65 data input lines
32 + 1 = 33 data output lines.
(e)
• Specify the control word that must be applied to the processor of to implement the
following microoperations.
– R1  R2 + R3

– R4  R4’

– R5  R5 -1

– R6  SHL R1

– R7 INPUT
Determine the microoperations that will be executed in the processor when the following
14-bit control words are applied.
a. 00101001100101 b. 00000000000000

c. 01001001001100 d. 00000100000010

e. 11110001110000
 Convert the following numerical arithmetic expression into reverse Polish
notation and show the stack operations for evaluating the numerical result.
(3 + 4)[10(2 + 6) + 8]