Session 7A: Special Session - 3: Machine Learning-Aided Computer-Aided Design GLSVLSI ’22, June 6–8, 2022, Irvine, CA,

GLSVLSI ’22, June 6–8, 2022, Irvine, CA, USA

Survey of Machine Learning for Electronic Design Automation

Kevin Immanuel Gubbi Sayed Arash Beheshti-Shirazi Tyler Sheaves
[email protected] [email protected] [email protected]
University of California, Davis George Mason University University of California, Davis
Davis, CA, USA Fairfax, VA, USA Davis, CA, USA

Soheil Salehi Sai Manoj PD Setareh Rafatirad

[email protected] [email protected] [email protected]
University of California, Davis George Mason University University of California, Davis
Davis, CA, USA Fairfax, VA, USA Davis, CA, USA

Avesta Sasan Houman Homayoun

[email protected] [email protected]
University of California, Davis University of California, Davis
Davis, CA, USA Davis, CA, USA
ABSTRACT 1 INTRODUCTION
An increase in demand for semiconductor ICs, recent advance- The Electronic Design and Automation (EDA) tools for Integrated
ments in machine learning, and the slowing down of Moore’s law Circuits (ICs) are crucial enablers for the semiconductor industry.
have all contributed to the increased interest in using Machine Advances in EDA tools have enabled the integration of increasing
Learning (ML) to enhance Electronic Design Automation (EDA) number of transistors on a single semiconductor die. With ground-
and Computer-Aided Design (CAD) tools and processes. This paper breaking innovations in IC design and integration, some chips have
provides a comprehensive survey of available EDA and CAD tools, up to 1.2 trillion transistors [41]. The Application Specific Inte-
methods, processes, and techniques for Integrated Circuits (ICs) grated Circuit (ASIC) design flow is complex and time consuming.
that use machine learning algorithms. The ML-based EDA/CAD A typical IC goes through several stages in the design process. Chip
tools are classified based on the IC design steps. They are utilized in architects work together to define specifications for the IC that is
Synthesis, Physical Design (Floorplanning, Placement, Clock Tree to be designed. Once the constraints are set, the behavioural Reg-
Synthesis, Routing), IR drop analysis, Static Timing Analysis (STA), ister Transfer Language (RTL) code is completed, and the desired
Design for Test (DFT), Power Delivery Network analysis, and Sign- foundry is selected, the design is sent through the logic synthesis
off. State-of-the-art ML-based VLSI-CAD tools, current trends, and process, after which the gate-level netlist is obtained. The netlist is
future perspectives of ML in VLSI-CAD are also discussed. then sent to the Physical Design stages where the floorplan for the
design is developed. This includes the design of the Power Deliv-
CCS CONCEPTS ery Network (PDN) and macro placement. Then the placement of
• Hardware → Design databases for EDA. standard cells and other logic blocks is done. Once the placement
is finalized, the clock tree is built. This step is known as the Clock
KEYWORDS Tree Synthesis (CTS). Routing the signals is the next process in the
design flow. Before the final netlist is sent to the foundry for fabri-
Electronic Design Automation (EDA), Computer-Aided Design, Ma- cation, it will go through the sign-off process where the netlist is
chine learning, ASIC design flow rigorously checked for design rule violations, layout vs. schematic
ACM Reference Format: violations, and timing violations. If there are violations pending to
Kevin Immanuel Gubbi, Sayed Arash Beheshti-Shirazi, Tyler Sheaves, So- be fixed, Engineering Change Order (ECO) are introduced to fix
heil Salehi, Sai Manoj PD, Setareh Rafatirad, Avesta Sasan, and Houman the violations with minimal changes to the netlist. Static Timing
Homayoun. 2022. Survey of Machine Learning for Electronic Design Au- Analysis (STA) is done every time a netlist is altered to make sure
tomation. In Proceedings of the Great Lakes Symposium on VLSI 2022 (GLSVLSI there are no new violations. Although this is a brief summary of the
’22), June 6–8, 2022, Irvine, CA, USA. ACM, New York, NY, USA, 6 pages.
design process, it is evident that the IC design flow is complex and
https://doi.org/10.1145/3526241.3530834
time consuming. This gets worse with increase in the design size.
This challenge provides an opportunity to explore the benefits of
Permission to make digital or hard copies of all or part of this work for personal or
classroom use is granted without fee provided that copies are not made or distributed Machine Learning (ML) for optimum design automation given the
for profit or commercial advantage and that copies bear this notice and the full citation complexity of the IC design flow and the data availability. Moreover,
on the first page. Copyrights for components of this work owned by others than the ML methods have been used for various applications like healthcare,
author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or
republish, to post on servers or to redistribute to lists, requires prior specific permission banking, military, scientific computing, automobiles, and consumer
and/or a fee. Request permissions from [email protected]. electronics. ML methods are classified based on the source of data
GLSVLSI ’22, June 6–8, 2022, Irvine, CA, USA that governs the learning mechanism. Herein, we have broadly
© 2022 Copyright held by the owner/author(s). Publication rights licensed to ACM.
ACM ISBN 978-1-4503-9322-5/22/06. . . $15.00 classified the ML methods into four categories: (1) unsupervised
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Session 7A: Special Session - 3: Machine Learning-Aided Computer-Aided Design GLSVLSI ’22, June 6–8, 2022, Irvine, CA, USA

learning, (2) supervised learning, (3) semi-supervised, and (4) re-

inforcement learning. When only the input data is available and
labels are required to be generated in order to distinguish between
the input samples, the learning method is known as unsupervised
learning. In supervised learning, the input data and corresponding
output data samples are available to the algorithm with the struc-
ture or labels. In semi-supervised learning, only some parts of the
input data samples have corresponding output sample pairs.
The Reinforcement Learning (RL) solutions are independent of
data samples and are based on the interaction of an agent with
an environment. The agent exploits and explores opportunities to
achieve new Pareto-frontier optimal spaces beyond the optimiza-
tion space covered by heuristic algorithms. A significant volume of
data is used during the training and learning process. Additionally,
the information that we employ in the process should be of impar-
tial consistency and high quality, which might need the generation
of more data, and as a result, more time, resources, and power are
required for a better quality of results. The other drawback is that
dependable resources are necessary when ML algorithms show er-
rors and complexity. It is vital to ensure that the algorithms utilized,
produce the desired output. To achieve this outcome, an accurate Figure 1: Classification of Machine Learning methods
learning algorithm with high performance is needed. The selec-
tion and availability of such a precise algorithm is also a challenge. for fabrication and validation. This Section discusses recent works
ML solutions still require significant improvements in algorithms utilizing ML to advance the Computer-Aided Design (CAD) process.
and the software that performs the analysis. Moreover, due to the Authors in [11] cast logic optimization as a deterministic Markov
large volume of data, error susceptibility is high, which needs to Decision Process (MDP). They take advantage of recent advances
be addressed. Drawbacks related to specific ML algorithms such as in deep RL to build a system that learns how to navigate this pro-
nonlinearity, sampling errors, overfitting, noisy datasets, incompre- cess. Their design has several desirable properties. It is autonomous
hensible datasets, low performance, complex and expensive compu- because it learns automatically and does not require human inter-
tation, and insufficient runtime memory, should also be considered. vention. It generalizes to large functions after training on small
The ever-increasing need for IC chips for various applications and examples. Additionally, it intrinsically supports both single- and
the need to speed up the design and manufacturing process is an multi-output tasks without the need to handle special cases. In [8],
important task and needs collaborative effort. ML has proved to be an extensive collection of C-to-FPGA results is built from a set
an excellent tool to increase the efficiency and productivity of the of High-Level Synthesis (HLS) applications that are diverse and
IC design and manufacturing processes. This manuscript aims to realistic to estimate post-implementation metrics. These features
provide a comprehensive survey of the landscape of ML-assisted and data are then leveraged to train and compare a range of ML
EDA tools. A taxonomy of ML methods is shown in Figure 1. models to effectively and efficiently close the accuracy gap. The
authors in [19] present some experimental results for application-
2 MACHINE LEARNING FOR VLSI-CAD specific many-core system design optimization and dynamic power
Over the last few decades, there has been substantial imporvements management to demonstrate the efficacy of these methods over
in the semiconductors industry, mainly due to the technological traditional EDA approaches.
progress in IC design and development to improve performance and In [14], a novel RL-based methodology is proposed that navigates
reduce area, power, and cost. These technological advancements the optimization space without human intervention. The training of
have allowed the integration of nearly billions of transistors on an Advantage Actor-Critic (A2C) agent that seeks to minimize area
a single silicon die, commonly categorized as a Very-Large-Scale subject to a timing constraint is demonstrated. Furthermore, the
Integration (VLSI). The VLSI design flow involves several steps. ML authors show that designs can be optimized autonomously without
based EDA tools used have been discussed below. a human intervention using the proposed methodology. Authors
in [31] propose LSOracle, which is a novel automated mixed logic
2.1 Synthesis synthesis framework that is the first to exploit state-of-the-art
Synthesis is a fundamental process in the IC design flow as it en- And-Inverter Graph (AIG) and Majority-Inverter Graph (MIG) logic
ables designers to realize a logical circuit into a physical layout. All optimizers. The proposed method relies on a Deep Neural Network
parameters, including area, timing, and power, can be reported and (DNN) to automatically decide which optimizer should handle dif-
checked by the design team beforehand. Necessary changes can be ferent portions of the circuit. To do so, LSOracle applies k-way
made before the actual fabrication process, thus saving both time partitioning to split a Directed Acyclic Graph (DAG) into multiple
and cost. Several industry-standard tools such as Design Compiler partitions and chooses the best-fit optimizer. In [47], the authors
from Synopsys, RTL compiler from Cadence, and other open-source present an autonomous framework that artificially produces design-
tools, have been used to convert logical netlist into physical layout specific synthesis flows without human guidance and baseline flows,

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using a Convolutional Neural Network (CNN). The demonstrations permutations possible, even for small designs. This is exacerbated
are made by successfully designing logic synthesis flows of three by larger designs, and a solution to find the best placement while
large-scaled designs. The Authors in [20] propose a transfer learn- using reasonable resources is a challenge. Multiple research teams
ing approach that reuses the knowledge obtained from previously have been invested in finding solutions to improve the placement.
explored design spaces in exploring a new target design space. The In [16], the authors first train a model to predict the number of
authors develop a novel neural network model for mixed-sharing Design Rule Check (DRC) violations for the current macro place-
multi-domain transfer learning. In [42] an end-to-end framework ment. DRCs are design rules that make sure the netlist layout is
called IRONMAN is proposed. The main goal is to enable a flex- compliant with the foundry-specific tape-out requirements. To gen-
ible and automated Design Space Exploration (DSE), which can erate macro placements with fewer DRCs, authors in [16] use the
provide optimized solutions under user-specified constraints or predictions obtained from their trained ML model. This is used as
Pareto trade-offs among different objectives, such as resource types, the evaluation function in the simulated annealing process. While
area, and latency. The IRONMAN framework consists of three main this work represents an interesting direction, the results shared are
components: GPP (a graph-neural-network-based performance pre- based on netlists with less than six macros, which are not realistic
dictor), RLMD (an RL-based DSE engine that explores the optimized compared to modern IC netlists. Moreover, their approach does not
resource allocation strategy), and CT (a code transformer that as- include any optimization during the place and route steps. Due to
sists RLMD and GPP by extracting data flow graphs from original the optimization, the placement and routing can change dramat-
HLS C/C++). Authors in [10] have presented MLSBench, a collec- ically, and the actual DRC will change accordingly, invalidating
tion of around 5000 synthesizable designs written in C and C++. the model prediction. In addition, although adhering to the DRC
They provide a methodology to generate designs with variations criteria is necessary, the primary objective of macro placement is
of a design, which creates a potential for creating new designs and to optimize for wire length and timing like Worst Negative Slack
enlarging the database in the future. This is followed by analysis (WNS) and Total Negative Slack (TNS), power, and area, and their
and validation that the generated designs are different. The authors work does not consider these metrics.
in [9] propose MAFIA, a tool to compile ML inference on small Recently, authors in [29] have presented a learning-based ap-
form-factor FPGAs for IoT applications. MAFIA provides native proach for chip placement, and unlike other prior methods, their
support for linear algebra operations and can express a variety of approach has the ability to learn from past experience and progres-
ML algorithms, including state-of-the-art models. In [6] the authors sively improve over time. As the model is trained over a greater
develop hls4ml, which is an open-source hardware-software code- number of chip blocks, it becomes better at generating optimized
sign flow. This is used to interpret and translate ML algorithms for placements for previously unseen chip macros, modules, and blocks.
ASIC and FPGA implementations. The paper introduces readers The authors take chip placement as an RL problem and train an
to the essential features of hls4ml, which includes network opti- agent to place the nodes of a chip netlist onto a chip layout. Rep-
mization techniques like pruning and quantization-aware training, resentation learning is used in the supervised task of predicting
which can be integrated into the device implementations. placement quality in order to enhance their RL policy. The authors
were able to enable feature-rich embeddings of the input netlists
2.2 Physical Design by designing a neural network architecture that could accurately
Once again, attributing to the rise in the need for semiconductor predict reward across the wide variety of input netlists and their
ICs, generating a layout from a netlist is essential in the IC de- placements. This architecture is used as the encoder of their RL
sign process. Physical design is converting a logical netlist or RTL policy and value networks to enable transfer learning. Mirhoseini
into a physical layout. Most fabrication processes require design and colleagues, in [28], use an RL-based graph placement method.
houses to use certain design libraries specific to their fabrication As shown in Fig. 2, an RL agent is used to place macros one after the
process. Generating these design layouts from the design netlist and other, and once all macros are placed, the standard cell placement
other design files is complex and time-consuming. Authors in [4] is done using a force-directed method. The method learns from
review available opportunities for ML with a focus on IC physical past experiences, which in turn improves the speed and quality of
implementation. They give examples like (1) removing unnecessary producing solutions for new instances of the problem.
design and modeling margins through correlation mechanisms, Clock Tree Synthesis (CTS): CTS is a physical design step in
(2) achieving faster design convergence through predictors of low implementing the clock network. Historically, the EDA tools were
downstream outcomes that comprehend both tools and design in- designed to build balanced clock trees by minimizing the clock
stances, and (3) corollaries such as optimizing the usage of design skew, giving each register-to-register timing path equal time. The
resources licenses and available schedule. Some open challenges problem with the zero skew clock tree is that all registers launched
for ML in IC physical design are also discussed herein. simultaneously, resulting in a surge of demanded current from the
Floor planning and Placement: Chip placement and floor battery on the active edge of the clock. In this section, recent works
planning are two important processes in the IC design flow. Find- utilizing ML to advance the CTS process are discussed. In [1] the au-
ing the optimal floor plan and placement of a design is considered thor presents a fully automated RL-based solution for reducing the
one of the most time-consuming and complex processes. Modern peak current. The agent modifies the clock arrival times for each of
IC designs have numerous smaller IPs, macros, and modules that the registers to maximize the distribution of clock arrivals. Using RL
require multiple iterations of placement to figure out the optimal allows the agent to explore optimization opportunities beyond the
position for each instance. Most ICs do not have the most opti- heuristic algorithm. The work in [39] employs a genetic algorithm
mal placement simply because of the high number of placement to optimize the clock-skew by limiting the maximum number of

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Figure 2: Overview of RL-based chip floorplanning method and training scheme in [28] (reproduced from [28])
clock drivers introduced and utilizes clustering techniques. In [26] the need to run a golden IR drop tool. The manuscript also shows
the authors utilize a mixed technique to achieve CTS optimization. significant improvement over an industry-leading golden IR drop
The paper employs a Generative Adversarial Network (GAN) aug- sign-off tool with negligible error rates. Similarly, authors in [4]
mented by RL. It is worth noting that the traditional GAN includes present a design flow to generate a PDN with negligible overhead
a generator and discriminator. In this paper, RL uses a pre-trained for standard cell routing while still meeting the IR drop and EM
regression model as a supervisor of the generator. The work in [21] constraints for a given placement. The ML model used in [4] pre-
estimates the clock tree elements such as how many buffers to be dicts the total wire length of the global route associated with a
used or the wire-loads utilizing Artificial Neural Network (ANN). given PDN configuration to speed up the search process. Calculat-
During CTS, the proposed technique uses ANN to determine the ing the IR drop after each ECO, authors in [7] use timing, power,
number of buffers to be added or removed to achieve the designated and physical features collected before ECO to predict the IR drop of
target clock skew. The result maximizes input transition times for a design after ECO. Regional models for cell instances near IR drop
clock buffers and sinks. The work presented by [34] suggests a violations are built to improve prediction accuracy and training
two-tier hybrid approach to optimization. The paper discusses the time. Results in [7] show that IR drop prediction for a design with
employment of supervised ML techniques such as the Support Vec- 100,000 cell instances can be predicted within 2 minutes. In [24], the
tor Machine (SVM) algorithm to estimate clock buffer and wire authors propose an ML technique to build IR drop prediction mod-
sizing. The report focused on providing an alternative to the ex- els based on circuits before ECO revision. Once the ECO revision is
pensive circuit-level simulations and reducing clock skew without done, these prediction models are reused to predict the IR drop of
significantly increasing power dissipation. The paper [30] utilizes a the ECO-revised circuit. The work in [43] provides a review of the
Convolutions Neural Network (CNN) augmented and enhanced by process in IR drop estimation techniques that use ML algorithms.
K-Means clustering and Linear Programming optimization to esti- Authors in [44] propose PowerNet, a CNN-based dynamic IR drop
mate different parameters of CTS. The paper focuses on decreasing estimation technique that can handle both vector-based and vector-
the power consumption of the clock network by reducing the clock less IR analysis. The CNN model used in PowerNet is general and
sinks along various data paths. transferable to different designs. The authors in [23] propose an
Routing: Routing has been a critical and complex challenge automatic flow to alter IR drop violations by ECO, which provides
for IC designers. Due to the huge number of routing possibilities cell movement and downsize solutions. An ML algorithm is used to
for each design, the need to optimize the EDA tools and routing predict IR drop in order to prevent over-fixing. A novel multi-round
algorithm is paramount especially with larger and more complex bipartite matching is used to optimize the resources used during
designs. ML has been used to improve routing quality and time. the ECO flow. MAVIREC [5] is a tool that uses ML techniques like
Authors in [45] provide insights into learning-free placement and three dimension convolutions and regression-like layers to suggest
routing approaches and then provide a detailed review of recent a larger subset of worst-case test patterns in order to improve test
advances in ML for routing and placement. The proposed method coverage and accurately predict the IR drop. Another method to
in [38] uses a deep learning-based congestion estimation algorithm predict IR drop of an IC layout is presented in [15] where XGBoost,
to improve routing quality. Their routing algorithm extracts ap- an ML technique, is used to make dynamic IR drop predictions,
propriate three dimensional features from already placed netlists. which can be applied to vector-based and vector-less IR drop analy-
The authors also propose a congestion estimator that produces a sis, simultaneously. In [15], the authors use a correlation coefficient
heatmap to serve as a guide for initial pattern during global routing to characterize the symmetry of predicted data and golden data.
phase. In [22], a deep RL method is proposed to solve the global 2.4 Static Timing Analysis
routing problem in a simulated environment and an RL agent is
Static Timing Analysis (STA) is a process that takes several iter-
used to produce an optimal policy for routing.
ations. Each iteration may take several hours for larger designs.
2.3 IR drop STA is a technique to check if a design satisfies the timing rules
The on-chip power delivery network (PDN) is a vital part of any required for the end product to function correctly. The input to an
chip, as it determines the quality and reliability of the fabricated STA tool is the routed netlist, clock definitions (or clock frequency),
IC. Ideally, a grid that is dense and compact is desired. However, a and external environment definitions. The STA validates whether
sparse PDN leaves more room for a clock, signal, and Engineering the design could operate at the rated clock frequency without any
Change Order (ECO) routing. Most complex designs need multiple timing violations. Some of the basic timing violations are setup
iterations of PDN design before finalizing the final PDN layout. violation and hold violation. Almost always, the initial layout will
Authors in [13] extract relevant SOC floorplan and PDN features have multiple timing violations, which the STA tool resolves by an
using superposition and partitioning techniques. An ML model iterative process of buffer insertion, signal and clock-tree re-routing,
is then used to predict the updated static IR drop for each power and layout alterations. Accurate timing closure is an important step
node by a series of SOC floorplan alterations. This is done without in the IC design flow. STA will be done multiple times after each

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design alteration to check for potential timing violations that may

have been inducted into the design.
In [2], as shown in Figure 3, the authors first observe that aging
can be thought of as a type of correlated dynamic On-Chip Vari-
ations (OCV) and identify the problem introduced by such OCV.
In particular, they take the Negative Bias Temperature Instability
(NBTI) as an example dynamic OCV mechanism and then propose
a Learning-based STA (LSTA) library to predict the timing of gates
by capturing the correlation between our designed predictors. A lin- Figure 3: Overview of library characterization and application pro-
ear regressor, support vector regression, and a non-linear method, cesses with learning-based training in [2] (reproduced from [2])
random forest, were used to create the prediction model in their To that end, a training set is built using features of components gen-
experiment. Authors in [35] discuss the timing closure problem ex- erated by a model-driven hardware generator framework. Ground
plaining the root cause of its difficulty. They also explain traditional truth labels for delays, slews, and their inter-dependencies are ex-
techniques that address the timing closure problem. Furthermore, tracted using open-source tools for logic synthesis and STA. In [12],
new challenges that appear at advanced process nodes are high- they propose a stage-based delay model based on an ML technique
lighted, and solutions to these problems are discussed. with a customized loss function to rapidly generate predicted PBA
Authors in [17] propose a ML model based on bigrams of path timing results from the pessimistic GBA timing report considering
stages to predict expensive Path Base Analysis (PBA) results from the asymmetric loss. The model could also enable the designers
relatively inexpensive Graph Base Analysis (GBA) results. They to identify the false violation path in the GBA report within less
identify electrical and structural features of the circuit that affect time, to reduce the margin in the post-route optimization phase.
PBA-GBA divergence with respect to endpoint arrival times and Authors in [40] provide a latency analysis of the inference path of
use GBA and PBA analysis of a given test case along with artificially their proposed hardware design which is intended for the learning
generated timing paths. A pyramid framework is proposed in [27] datapath of the Tsetlin machine algorithm. They use a combination
that estimates the optimal resource and performance utilization of of asynchronous design techniques like petri nets, signal transition
a High Level Synthesis (HLS) design using ML. For this purpose, graphs, bundled data, and dual-rail method, in order to generate
they first create a database of C-to-FPGA results from a diverse set a low energy hardware, which can be used for pervasive Artifi-
of benchmarks. To find the achievable maximum clock frequency, cial Intelligence (AI) applications. In [3], a learning-based timing
Minerva, which is an automated hardware optimization tool, is used. prediction framework is proposed to predict path delays across
Minerva determines the close-to-optimal settings of tools using wide voltage regions by Light Gradient Boosting Machine (Light-
STA along with a heuristic algorithm and targets either optimal GBM) with data augmentation strategies including Conditional
throughput or throughput-to-area. A multivariate linear regression Generative Adversarial Networks (CTGAN) and Synthetic Minority
based data-driven approach is investigated by authors in [18] to Oversampling Technique for Regression (SMOTER), which gener-
predict the timing analysis results at observed corners. The authors ate realistic synthetic data of circuit delays to improve prediction
use a simple backward step-wise selection strategy to choose which precision and reduce data sampling effort. In [46], an efficient and
corners to observe and which to predict. accurate pre-routing path delay prediction framework is proposed
In [32], the impact of Multiple-Input Switching (MIS) is mod- by using a transformer and residual model. Timing and physical
eled by deriving a corrective measure that should be applied to information at the placement stage is extracted as sequence features
the conventional Single-Input Switching (SIS) delay under different while the residual path delay is modeled to calibrate the mismatch
conditions. They call this corrective measure MIS-SIS Difference between the pre- and post-routing path delays.
(MSD). In this work, they have evaluated polynomial regressions,
support vector regression, and ANNs to model MSD. Additionally, 3 DISCUSSION AND CONCLUSION
they integrate the ANN-based MSD model into existing timing The use of ML methods for CAD has become an active area of re-
libraries and employ them in carrying out MIS-aware timing analy- search. Due to the ever increasing complexity and scale of variables
sis. In [36], they present novel Deep Neural Network (DNN) based in an IC design process, there is an increasing need for efficient
operations which can accurately approximate the signal arrival- ML-assisted EDA tools. Moreover, with the advent of emerging
time’s distributions with linear-time complexity. The various DNN hardware security threats, there is a growing need for EDA tools to
architectures have been used to implement both the maximum and incorporate security countermeasures and mitigation techniques
the convolution operations using proper training dataset. An ML- into the IC design flow. Although there has been significant progress
based automatic timing closure solution for relative timed circuits in the development of tools and methods for hardware security, the
is presented in [37]. The ML implementation is expected to speed need for efficient, easy to integrate, and scalable EDA tools is grow-
up the process by learning from the features during each iteration, ing. With growing threats like IC counterfeiting, overproduction,
minimizing the overall run-time to timing close a design. In [33], reverse engineering, hardware trojan insertion, and side-channel
the authors use deep learning non-linear autoencoders to compress attacks, the need to implement security mitigations and counter-
voltage and current waveforms and then compare them with the measures into the IC design process is one to be addressed. In
singular component analysis approach. In [25], they propose an ML- summary, this paper provides an insight on the advancements of
based approach to estimate pin-to-pin delays for RTL combinational using ML algorithms for EDA. The survey is categorized by the
circuits. To gain accuracy, they combine slew and delay estimation. different IC design flow stages and the state-of-the-art ML-assisted

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methods are discussed under the relevant sections. Finally, future 1–4.
perspectives of ML in EDA are given, and opportunities in hardware [22] H. Liao, W. Zhang, X. Dong, et al. 2019. A Deep Reinforcement Learning Approach
for Global Routing. ArXiv abs/1906.08809 (2019).
security automation are discussed. [23] H.-Y. Lin, Y.-C. Fang, S.-T. Liu, et al. 2020. Automatic IR-Drop ECO Using Machine
Learning. In 2020 IEEE International Test Conference in Asia (ITC-Asia). 7–12.
ACKNOWLEDGMENT [24] S.-Y. Lin, Y.-C. Fang, Y.-C. Li, et al. 2018. IR drop prediction of ECO-revised
This work was supported in part by the National Science Foundation circuits using machine learning. In 2018 IEEE 36th VLSI Test Symposium (VTS).
1–6.
through Computing Research Association for CIFellows #2030859. [25] D. S. Lopera, L. Servadei, V. P. Kasi, et al. 2021. RTL Delay Prediction Using
Neural Networks. In 2021 IEEE Nordic Circuits and Systems Conference (NorCAS).
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