1

Unit 3
Q.Draw the logic diagram of half adder& full-adder and its truth table.
Half-adder
• The half-adder operation needs two binary inputs: augenda addend bits; and two binary outputs: sum and
carry.
• The truth table shown in Table Q.38.1 gives the relation between input and output variables for half-adder
operation.

Full adder
• A full-adder combinational is a circuit that forms the arithmetic sum of three input bits.
• It consists of three inputs and two outputs.
• Two of the input variables, denoted by A and B, represent the two significant bits to be added. The third input
Cin represents the carry from the previous lower significant position.
• The truth table for full-adder is shown in Table Q.38.2.
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 3

Q.Implement a full-adder using Demultiplexer.

Implementation:
Steps to implement a Boolean function in a multiplexer:
First, find the number of input variables. If it’s 3 variable functions, then we need a 1:8 multiplexer. If it’s an n
variable function, we require a 1:2n multiplexer.
Put the variables as selector lines of the multiplexer. A 1:2n multiplexer will have n selector lines.
Now, from the truth table of the function, find the minterms and grab the corresponding output lines of the
demultiplexer, and put them into an OR gate. This makes sure that whenever any minterm of the function is
high, the output is high.
Full Adder using Demultiplexer:
We have two outputs and therefore two functions S and Cout. Clearly, we need to use a 1:8 demultiplexer.
Using the above steps, we see that for S, we need to put line numbers 1, 2, 4, and 7 of the demultiplexer to an
OR gate. For the Cout, we have an OR gate, the lines 3, 5, 6, and 7.
The final implementation is shown below
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Q.Explain the working of a half-adder?

The half adder is a basic building block for more complex adder circuits such as full adders and multiple-bit
adders. It performs binary addition of two single-bit inputs, A and B, and provides two outputs, SUM and
CARRY.
The SUM output is the least significant bit (LSB) of the result, which is the XOR of the two inputs A and B.
The XOR gate implements the addition operation for binary digits, where a “1” is generated in the SUM output
only when one of the inputs is “1”.
The CARRY output is the most significant bit (MSB) of the result, indicating whether there was a carry-over
from the addition of the two inputs. The CARRY output is the AND of the two inputs A and B. The AND gate
generates a “1” in the CARRY output only when both inputs are “1”.

Q.Implement the full subtractor using a 1:8 demultiplexer.

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Q.Write a note on a 4-bit parallel binary adder.

Ans.: Fig. Q.3.1 shows 4-bit parallel adder / subtractor circuit..
• The mode input M controls the operation of the circuit. When M = 0, the circuit is an adder, and when M = 1,
the circuit becomes a subtractor
• Each exclusive – OR gate receives input M and one of the inputs Of. B. When M = 0, we have B 0 B. The full-
adders receive the value of B, the input carry is 0 and the circuit performs A plus B.
• When M 1, we have B1 = B and Cin 0 = 1. The B inputs are all complemented and a 1 is added through the
input carry. The circuit performs the operation A plus the 2’s complement of B, i.e. A – B.
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Unit 4
Q.Explain the function of a shift register. Give its application.
Function of a Shift Register:
Data Storage: A shift register can store a certain number of bits. Each storage element holds one bit of data.
Serial Data Shifting: It allows the movement of data, either left or right, by shifting bits through its stages.
Serial Input and Output: New data can be serially inputted into the register, shifting existing data to
accommodate the new bits. Similarly, data can be read out serially as it shifts through the register.
Types of Shift Registers:
Serial In – Serial Out (SISO): Only one bit can be entered or taken out at a time.
Serial In – Parallel Out (SIPO): Serial input, but multiple bits can be read out in parallel.
Parallel In – Serial Out (PISO): Multiple bits entered in parallel, but outputted serially.
Parallel In – Parallel Out (PIPO): Both input and output occur in parallel.
Applications of Shift Registers:
Serial-to-Parallel and Parallel-to-Serial Conversion: Useful for interfacing between serial and parallel data buses
in communication systems.
Shift Register Counters: Employed in digital counters and sequence generators, enabling various counting
sequences based on the shifting of bits.
Data Storage and Temporary Registers: Used in memory units for temporary storage and in microprocessors for
various operations.
Shift Registers in Serial Communication: Commonly used in serial data transmission for sending and receiving
data in a sequential manner.
Shift Registers in Display Systems: Utilized in controlling and refreshing LED or LCD display panels, enabling
the sequential presentation of data for each display element.
Shift Registers in Delay Circuits: Employed in signal processing and time-delay circuits due to their ability to
delay and shift data in a controlled manner.
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Q.Explain with truth table the working of clocked RS flip-flop.

Ans. Fig. Q.7.1 shows the positive edge triggered clocked SR flip-flop

Operation
Case 1: I_{f}S=R=0 and the clock pulse is applied, the output do not change, i.e. Q_{n+1}=Q_{n} This is
indicated in the first row of the truth table.
Case 2: f~S=0 R=1 and the clock pulse is applied, Q_{n+1}=0 This is indicated in the second row of the truth
table.
Case 3: If s=1 R=0 and the clock pulse is applied, Q_{n+1}=1 This is indicated in the third row of the truth
table.
Case 4: S=R=1 and the clock pulse is applied, the state of the flip-flip is undefined and therefore is indicated as
indeterminate in the fourth row of the truth table.
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Q.Explain the types of shift register.

Ans. A group of flip-flops can be used to store a word, which is called register.
• The binary informa ion (data) in a register can be moved from stage to stage within the register or into or out
of the register upon application of clock pulses. Such registers are called ‘shift registers

Q.Explain with diagram the working of D type Flip-flop. Give its truth table.
Ans. In SR Flip-Flop, when both inputs are same the output either does not change or it is invalid
(Inputs \rightarrow00, no change and inputs 11, invalid).
• These input conditions can be avoided by making them complement of each other. This modified SR flip-flop
is known as D flip-flop.
• The D input goes directly to the S input, and its complement is applied to the R input. Due to these
connections, only two input conditions exists, either s=0 and R=1 or S=1 and R=0.
Truth Table
• The truth table for D flip-flop consider only these two conditions and it is as shown in the Fig. Q.8.1 (b)
•Qn+1 function follows D input at the positive going edges of the clock pulses. Hence the characteristic
equation for D flip-flop is Qn+1 = D.
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Q.Design a 3-Bit synchronous counter using JK FF.

Ans.: Design of 3-bit synchronous binary up-counter:
Step 1: Number of flip-flops 3-bit counter so we require 3 flip-flops.
Step 2:Types of flip-flops to be used JK

Step 3: Determine the excitation table for the coun

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Q.With the neat diagram, explain the working operation of 4-bit SISO.
In this shift register, data within the shift register is shifted left one bit position at each clock pulse. The data
input bit is loaded in the right most flip-flop
Fig. Q.3.2 shows serial-in serial-out shift-right register.
In this shift register, data within the shift register is shifted right one bit position at each clock pulse. The data
input bit is loaded in the left most flip-flop.
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Q.Explain S-R flip-flop using NOR gates.

Design of SR Flip Flop with NOR Gate:
Below we have shown that how SR Flip Flop can be designed using NOR gate. In the circuit diagram, there are
two input
Terminals S and R. Understanding of the truth table of NOR gate is important before knowing the working of
the circuit. In the
NOR gate, if the input at both the terminals is low i.e. 0 then only we get the output high i.e. 1. If any of the
input terminals or
Both of the inputs are in high state i.e. 1, then output will be low i.e. 0.
Functioning of SR Flip Flop is very easy.
Now imagine that at the input terminal of Flip Flop, we applied S=0 and R=0, at these condition states of Flip
Flop will not
Change and it will stay on its present condition.
Assume that S=0 and R=1 then in that condition the output at upper NOR gate will be low. Hence the input at
both the
Lower gate is in low state so the output we got will be high. This in turn provide 1 at the R input and as a result
of it Flip Flop
Reaches at stable condition where Q=0 with Q¯=1. I this mode the Flip Flop will reset by its own and LED 1
will start
Glowing this time.
Now assume that S=1 and R is set to 0, at this condition the lower NOR gate output switch to low and turn the
input of the
Upper gate switch to low and output got will be high. Hence at the moment we can articulate that at S=1 the
Flip Flop sets of
Input and Flip Flop move to a stable condition where Q=1 andQ¯=0. In this condition Flip Flop will set by its
own and LED 2
Will glow this time.
Now suppose input at both S and R is 1. In this condition both the output of NOR gate goes to low and as a
result of its
Output at Q and Q¯ is 0 and this will contradict the definition of the Flip Flop which defines that the outputs are
Complimentary of each other. So this condition is practically not possible and both LED will start glowing.
The following table summarizes the above explained working condition of the NOR Flip Flop gate.
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Unit 5
Q.Draw ASM chart for a 2 bit up-down counter having mode control input M. [8] M=1 Up counter. M = 0
Down Center.
 13

Q.Explain in short: [8]

i) State Diagram.
ii) ASM chart.
iii) State table
iv) State assignment

I)State diagram is a pictorial representation of a bahaviour of a sequential circuit. The state is represented by the
circle, and the transition between states is indicated by directed lines connecting the circles. A directed line
cor.necting a circle with itself indicates that next state is same as present state. The binary number inside each
circle identifies the state represented by the circle. The directed lines are labelled with two binary numbers
separated by a symbol ‘/’. The input value that causes the state transition is labelled first and the output value
during the present state is labelled after the symbol ‘/’.

II)A special flowchart that has been developed specifically to define digital hardware algorithms is called an
Algorithmic State Machine (ASM) chart.The ASM chart resembles a conventional flow chart, but is interpreted
somewhat differently. A conventional flow chart describes the sequence of procedural steps and decision paths
for an algorithm without concern for their time relationship. An ASM chart describes the sequence of events as
well as the timing relationship between the states of a sequential controller and the events that occur while
going from one state to the next.

III)It is convenient to translate the information contained in the state diagram into a tabular form called state
synthesis table or simply state table.
It represents relationship between input, output and flip-flop states. It consists of three sections labeled present
state, next state, and output. The present state designates the state of flip-flops before the occurrence of aclock
pulse. The next state is state of theflip-flop after the application of a clock pulse, and the output section gives
the values of the output variables during the present state.

IV)To determine the flip-flop input functions. It is necessary to represent states in the state diagram using binary
values instead of alphabets.
• This procedure is known as state assignment.
• We must assign binary values to the states in such a way that it is possible to implement flip-flop input
functions using minimum logic gates.
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Q.Draw ASM chart for 2 bit binary counter having one enable line E such That: E=1,
 15

Q. Explain [8]
i) Rules for state assignments.
ii) State reduction
I)To determine the flip-flop input functions. It is necessary to represent states in the state diagram using binary
values instead of alphabets.
• This procedure is known as state assignment.
• We must assign binary values to the states in such a way that it is possible to implement flip-flop input
functions using minimum logic gates.
• There are two basic rules for making state assignments.
Rule 1: States having the same NEXT STATES for a given input condition should have assignments which can
be grouped into logically adjacent cells in a K-map.
Fig. Q.8.1 shows the example for Rule 1. As shown in the Fig. Q.8.1, there are four states whose next state is
same. Thus assignments states for these states are 100, 101, 110 and 111 which can be grouped logically into
adjacent cells in a K-inap.
Rule 2: States that are the NEXT STATES of a single state should have assignment which can be grouped into
logically adjacent cells in a K-map.Fig. Q.8.2 shows the example for Rule 2. As shown in the Fig. Q.8.2, for
state 000, there are four next states. These states are assigned as 100, 101, 110 and 111 so that they can be
grouped into logically adjacent cells in K-map and a table shows the state table.

II)The state reduction technique basically avoids the introduction states. Of redundant
The redu. Io in redundant states reduce the number of required flip-flops and logic gates, reducing the cost of
the final circuit.
The two states are said to be redundant or equivalent, ifevery possible set of inputs generate exactly same output
and same next state.
• When two states are equivalent, one of them can be removed without altering the input-output.relationship.
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Unit 6
Q.Explain the classification of memories based on their principle of Operation.

• Broadly semiconductor memories are classified as volatile memories and non-volatile memories. Volatile
memories can retain their state as long as power is applied. On the other hand, non-volatile memories can hold
data even if power is turned off. Read/Write Memories (RWMs) are those memories, which allows both read
and write operations. They are used in applications where data has to change continuously. They are also used
for temporary storage of data. ROM memories allow only read operation. They are used to store monitor
programs and constants used in the program.
• The volatile memories which can hold data as long as power is ON are called Static RAMs (SRAMs).
Dynamic RAMS (DRAMs) stores the data as a charge on the capacitor and they need refreshing of charge on
the capacitor after every few milliseconds to hold the data even if power is ON. EPROM and EEPROM are
erasable memories in which the stored data can be erased and new data can be stored.
• The semiconductor memories are also classified as Bipolar and MOS memories depending upon the type of
transistors used to construct the individual cell.
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Q.Write a short note on concept of PLA and PAL.

.: PLA stands for Programmable Logic Array:
In PLA, both AND and OR gates have fuses at the inputs, therefore in LA both AND and OR gates are
programmable.
Fig. Q.3.1 shows the block diagram of PLA.

• It consists of n-inputs, output buffer with m outputs, m product terms, m sum terms, input and output buffers.
• The product terms constitute a group of m AND gates and the sum terms constitute a group of m OR gates,
called OR matrix.
• Fuses are inserted between all n-inputs and their complement values to each of the AND gates.
• Fuses are also provided between the outputs of the AND gates and the inputs of the OR gates.
• The third set of fuses in the output inverters allows the output function to be generated either in the AND-OR
form or in the AND-OR-INVERT form.
• Input buffers are provided in the PLA to limit loading of the sources that drive the inputs.
• The driving capacity of PLA is increased by providing buffers at the output

PAL (Programmable Array Logic):

We have seen that PLA is a device with a programmable AND array and programmable OR array. However,
PAL programmable array logic is a programmable logic device with a fixed OR array and a programmable AND
array. Because only AND gates are programmable, the PAL is easier to program, but is not as flexible as the
PLA.
Fig. Q.10.1 shows the array logic of a typical PAL. It has four inputs and four outputs. Each input has buffer and
an inverter gate. It is important to note that two gates are shown with one composite graphic symbol with
normal and complement outputs. There are four sections. Each section has three programmable AND gates and
one fixed OR gate. The output of section 1 is connected to a bufter-inverter gate and then fed back into the i
nputs of the AND gates, through fuses. This allows the logic designer to feed an output function back as an
input variable to new function.Such PALS are referred to as create a Programmable I/O PALS.
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 19

Q.Explain with circuit diagram the dynamic MOS memory.

Dynamic MOS (Metal-Oxide-Semiconductor) memory, often referred to as DRAM (Dynamic Random Access
Memory), is a type of semiconductor memory that stores binary information as charge on capacitors. It’s widely
used in computer systems due to its high density and lower cost compared to other types of memory.
Circuit Diagram of a Dynamic MOS Memory Cell:
A basic dynamic memory cell consists of a capacitor and a MOS transistor. Here’s a simplified circuit diagram:
Operation:
Capacitor (Storage Element): Represents the memory storage unit. It holds the charge representing the binary
information (0 or 1). The capacitor is connected to the MOS transistor.
MOS Transistor (Access Transistor): Acts as a switch to control the flow of charge to and from the capacitor. It
provides access to the capacitor when reading or writing data.
Bit Line (BL): The data line through which data is read from or written into the memory cell. It’s connected to
the MOS transistor.
Functionality:
Write Operation: To write data into the cell, a voltage is applied to the gate of the MOS transistor. This turns it
on, allowing charge to flow to or from the capacitor, thereby storing a new charge and updating the stored data.
Read Operation: During a read operation, the voltage is applied to the gate of the MOS transistor. The presence
or absence of charge on the capacitor alters the voltage on the bit line, indicating the stored data (0 or 1).
Dynamic Nature and Refresh:
Dynamic MOS memory cells are dynamic because they require periodic refreshing. Due to charge leakage in
the capacitor, the stored charge slowly dissipates over time. To maintain the stored data, the memory cells need
to be periodically refreshed by rewriting the data into the cells.
Applications:
Dynamic MOS memory is widely used in various applications such as:
Computer Memory: Used as the main memory (RAM) in computers and other digital devices.
Cache Memory: Often used as cache memory due to its higher density and lower cost.
Embedded Systems: Commonly employed in embedded systems and mobile devices due to its compact size and
energy efficiency.
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Q.Explain the meaning of static and dynamic memories. State their Applications.
Static Memory:
Meaning: Static memory uses flip-flops or latches to store data as long as power is supplied. It doesn’t need
periodic refreshing like dynamic memory. Each memory cell typically consists of multiple transistors, making it
more complex compared to dynamic memory cells.
Operation: In static memory, once data is written, it remains stored until explicitly changed. It retains data as
long as power is supplied, making it faster and requiring lower power during normal operation.
Applications:
Cache Memory: Used as cache memory in CPUs due to its speed and ability to quickly access data.
Registers: Used in processors for storing temporary data and in control units.
High-Speed Buffers: Employed in high-speed data processing and applications requiring fast access times.
Dynamic Memory:
Meaning: Dynamic memory uses capacitors to store data as charge. It requires constant refreshing of data due to
charge leakage from the capacitors. Each memory cell typically consists of a single transistor and a capacitor,
making it simpler but requiring refresh circuits.
Operation: In dynamic memory, stored data slowly fades away due to charge leakage. Therefore, it requires
periodic refreshing to maintain data integrity, making it slower and consuming more power during normal
operation.
Applications:
Main Memory (RAM): Used as main memory in computers and digital devices due to its high density and cost-
effectiveness.
Mobile Devices: Commonly used in smartphones, tablets, and other portable devices due to its lower power
consumption and smaller footprint.
Embedded Systems: Used in embedded systems where cost and density are significant factors.
Comparison:
Speed: Static memory is faster as it doesn’t need refreshing, while dynamic memory is slower due to the need
for refresh cycles.
Density and Cost: Dynamic memory offers higher density and lower cost per bit compared to static memory.
Power Consumption: Static memory consumes less power during normal operation, whereas dynamic memory
consumes more power due to the need for refreshing.
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Q.Differentiate between ROM and RAM.

 22

Q.What is meant by ROM? What are the types of ROM? Compare between Them.
ROM stands for Read-Only Memory. It’s a type of non-volatile memory that stores data permanently and is
primarily used for storing instructions required during the boot-up process or for essential system functions in
electronic devices. Unlike RAM (Random Access Memory), ROM retains its data even when the power is
turned off.

Types of ROM:
Mask ROM (MROM): This type of ROM is manufactured with data permanently encoded during the chip
fabrication process. It’s called “mask” ROM because the data is created by masking and etching the silicon
wafers during production. Once programmed, the data is fixed and cannot be changed or reprogrammed. It’s
cost-effective for large-scale production but lacks flexibility.

Programmable ROM (PROM): PROM is initially blank, and users can program it once using a special device
called a PROM programmer. A PROM contains fuses that can be selectively burned or left intact to represent
binary data. Once programmed, the data becomes permanent and cannot be changed. PROM is less expensive
than mask ROM but has a limited programming cycle.

Erasable Programmable ROM (EPROM): EPROM allows multiple programming cycles. It uses a floating-
gate transistor that can be programmed and erased using ultraviolet light. EPROM chips are erased by exposing
them to UV light for a specified duration. While they offer flexibility in programming, the process of erasing
requires the chip to be removed from the system.
Electrically Erasable Programmable ROM (EEPROM or E2PROM): EEPROM, also known as E2PROM,
can be erased and reprogrammed electrically, meaning it doesn’t require UV light for erasure. EEPROM allows
data to be selectively erased and reprogrammed without removing the chip from the system. It’s more flexible
and user-friendly than EPROM but typically has slower write/erase cycles and lower storage density.
Comparison:
Permanence of Data: Mask ROM’s data is fixed during manufacturing, whereas PROM, EPROM, and
EEPROM allow data programming or erasing.
Reprogrammability: PROM is programmable only once, while EPROM and EEPROM offer multiple
programming/erasing cycles.
Erasure Methods: EPROM requires exposure to UV light for erasure, while EEPROM can be erased
electronically, making it more user-friendly.
Flexibility and Cost: EPROM and EEPROM offer greater flexibility for data changes but are costlier compared
to mask ROM or PROM.
Speed and Access: EPROM and EEPROM generally have slower access times compared to mask ROM due to
their erasure and reprogramming mechanisms.