Gate level

AND GATE
Introduction:
The AND gate plays an important role in the digital logic circuit.
The output state of the AND gate will always be low when any
of the inputs states is low. Simply, if any input value in the AND
gate is set to 0, then it will always return low output(0).
Diagram:

Code:
And.v TB
module And_gate(a,b,y); module and_gateTB();
reg A,B;
input a,b; wire Y;
output y; And_gate A1(.a(A),.b(B),.y(Y));
initial
and (y,a,b); begin
endmodule A=0;B=0;
#10
A=0;B=1;
#10
A=1;B=0;
#10
A=1;B=1;
end
endmodule
RTL:

Output:
 Not gate
Introduction:
In digital circuits, the NOT gate is a basic logic gate
having only a single input and a single output. The
output of the NOT gate is logic 0 when its input is
logic 1 and the output is logic 1 when its input is
logic 0.
Diagram:

Code:
module Not_gate(a,y ); module Not_gateTB();
input a; reg A;
output y; wire Y;
not (y,a); Not_gate A2(.a(A),.y(Y));
endmodule initial
begin
A=0;
#100
A=1;
end
endmodule
RTL:

Output:
 Half Adder

Introduction:
A half adder is a digital logic circuit that performs
binary addition of two single bit binary numbers. It
has two inputs, A and B, and two outputs, SUM and
CARRY. The SUM output is the least significant bit
(LSB) of the result, while the CARRY output is the
most significant bit (MSB) of the result, indicating
whether there was a carry-over from the addition
of the two inputs. The half adder can be
implemented using basic gates such as XOR and
AND gates.
Diagram:
Code:
Half_adder.V TB
module module Half_adderTB(); reg
Half_adder(a,b,s,c); input A,B; wire S,C; Half_adder
a,b; A3(.a(A),.b(B),.s(S),.c(C));
initial begin A=0;B=0;
output s,c; #100
and(c,a,b); A=0;B=1;
xor(s,a,b); #100
endmodule A=1;B=0;
#100
A=1;B=1;
end endmodule

RTL:
Output:

Mux 4x1
Introduction:
A 4-to-1 multiplexer takes 4 inputs and directs a
single selected input to output. The selection of
input is controlled by selection inputs. A 4-to-1
multiplexer consists of a 2-to-4 decoder and 4X2
AND-OR. This multiplexer however takes 4 8-bit bus
as inputs and outputs a single 8-bit bus.
Diagram:
Code:
Mux_4x1. V TB
module module Mux_4x1TB();
Mux_4x1(I0,I1,I2,I3,S0,S1,Y) reg i0,i1,i2,i3,s0,s1;
; wire y;
input I0,I1,I2,I3,S0,S1; Mux_4x1 M(i0,i1,i2,i3,s0,s1,y);
output Y; initial
wire begin
w1,w2,w3,w4,w5,w6,w7, s1=0;s0=0;i0=1;i1=0;i2=0;i3=0;
w8,w9,w10,w11,w12,w13,w #100
14; s1=0;s0=1;i0=0;i1=1;i2=0;i3=0;
not(w1,S0); #100
not(w2,S1); s1=1;s0=0;i0=0;i1=0;i2=1;i3=0;
and(w3,w1,w2); #100
and(w4,w3,I0); s1=1;s0=1;i0=0;i1=0;i2=0;i3=1;
not(w6,S1); end
and(w7,w6,S0); initial
and(w5,w7,I1); begin
or(w8,w4,w5); $display("\t\t\t\t\tTime\ti0\ti1\ti2\ti3\ts1\ts0\ty");
not(w9,S0); $monitor("\t",$time,"\t",i0,"\t",i1,"\t",i2,"\t",i3,"\
and(w10,w9,S1); t",s1,"\t",s0,"\t",y);
and(w11,w10,I2); end
and(w13,S1,S0); endmodule
and(w14,w13,I3);
or(w12,w11,w14);
or(Y,w8,w12);
endmodule

RTL:
Output:

TCL console:
 MUX_16X1
Introduction:
Diagram:

Code:
RTL:
Output:
TCL console:

Boolean _expression
Introduction:
Diagram:
Code:
Boolean _expression.v TB
module boolean_function(a,b,c,d,f); module booleanTB( );
input a,b,c,d; reg w,x,y,z;
output f; wire F;
wire boolean_function H(w,x,y,z,F);
w1,w2,w3,w4,w5,w6,w7,w8,w9,w10; initial
and g1(w1,a,b); begin
not g2(w2,d); w=0;x=0;y=0;z=0;
or g3(w3,w2,c); #100
and g4(w4,w1,w3); w=0;x=0;y=0;z=1;
not g5(w5,b); #100
not g6(w6,c); w=0;x=0;y=1;z=0;
and g7(w7,a,w5,w6); #100
not g8(w8,a); w=0;x=1;y=0;z=0;
not g9(w9,b); #100
and g10(w10,a,b,d); w=0;x=1;y=1;z=0;
or g11(f,w4,w7,w10); #100
endmodule w=1;x=1;y=1;z=1;
end
initial
begin
$display("w x y z F");
$monitor(w,x,y,z,F);
end
endmodule

RTL:

Output:
TCL console: