III YEAR, V SEMESTER B.

TECH EXAMINATION NOV-DEC 2019

200503 - Microprocessors & Interfacing (GS)

Solution

1. a)
MICROPROCESSOR-
 Microprocessor is a semiconductor device based on LSI or VLSI technique.
 Memory and I/O device are connected externally.
 Microprocessor can be used for multitasking.
 In microprocessor memory connected externally so it can be used for large program.
 It is more flexible.
MICROCOMPUTER-
 Microcomputer is a device which consists of CPU, I/O device, and memory
fabricated on single PCB.
 Here memory and I/O devices are connected internally on single PCB
 Microcomputer can be used for general purpose.
 In microcomputer memory is fixed so it can be used for the small program.
 Microcomputer is less flexible.

1b)

1c) Interrupt: Interrupt is a mechanism by which an I/O or an instruction can temporarily

suspend the normal execution of processor and jump to a subroutine program. Interrupts are used
to in case some urgent priority task has to be accomplished.
Interrupt Subroutine (Interrupt Service Routine): ISR is a small program that the processor
executes when the corresponding Interrupt is being requested.The program then jumps to the
assigned vector address of the interrupt where the subroutine is present
1d) The internal architecture (Functional Block Diagram of 8085 Microprocessor) is shown in
figure.
1e) Accumulator (A-register)

It is an 8-bit register. It is associated with ALU. The accumulator is also called A-register. During the
arithmetic / logic operations, one of the operand is available in Accumulator. The result of the arithmetic /
logic operations is also stored in the Accumulator.

Program Counter (PC)

The Program Counter (PC) is a 16-bit register. It is used to point the address of the next instruction to be
fetched from the memory. When one instruction is fetched from memory, PC is automatically
incremented to point out the next instruction.

Instruction register

When an instruction is fetched from memory, it is stored in the Instruction register. It is an 8-bit register.
This resister cannot be used in the programs.

. Serial I/O control

Serial data is transmitted to the peripherals through SOD(serial output data) pin and received through the
SID(serial input data) pin. The SOD and SID pins are handled by the Serial I/O control unit using the SIM
and RIM instructions.
2 a)

2b)
Instruction cycle :
The fetching, decoding and execution of a single instruction constitutes an instruction cycle, which
consists of one to five read or write operations between processor and memory or input/output devices.

Machine cycle.
:Each memory or I/O operation requires a particular time period, called machine cycle. In other words, to
move byte of data in or out of the microprocessor, a machine cycle is required.

T-states.
Each machine cycle consists of 3 to 6 clock periods/cycles, referred to as T-states.
2c) Memory read cycle

Memory write cycle

2d) Ten 8-bit numbers are stored from starting memory location 2050. Value of count is stored at memory
location 3050.

MEMORY ADDRESS MNEMONICS

2000 LXI H 204F

2003 MVI C, 00

2005 MVI D, 0A

2007 INX H

2008 MOV A, M

2009 ANI 01

200B JNZ 200F

200E INR C

200F DCR D

2010 JNZ 2007

2013 MOV A, C

2014 STA 3050

2017 HLT

2e) In 8085 microprocessor there are 5 types of addressing modes:

1. Immediate Addressing Mode –

In immediate addressing mode the source operand is always data. If the data is 8-bit, then
the instruction will be of 2 bytes, if the data is of 16-bit then the instruction will be of 3
bytes.
Example:
MVI B 45 (move the data 45H immediately to register B)

2. Register Addressing Mode –

In register addressing mode, the data to be operated is available inside the register(s) and
register(s) is(are) operands. Therefore the operation is performed within various registers
of the microprocessor.
Example:
MOV A, B (move the contents of register B to register A)
 3. Direct Addressing Mode –
In direct addressing mode, the data to be operated is available inside a memory location
and that memory location is directly specified as an operand. The operand is directly available
in the instruction itself.
Example:
LDA 2050 (load the contents of memory location into accumulator A)

4. Register Indirect Addressing Mode –

In register indirect addressing mode, the data to be operated is available inside a memory
location and that memory location is indirectly specified b a register pair.
Example:
MOV A, M (move the contents of the memory location pointed by the H-L pair to the
accumulator)

5. Implied/Implicit Addressing Mode –

In implied/implicit addressing mode the operand is hidden and the data to be operated is
available in the instruction itself.
Example: CMA (finds and stores the 1’s complement of the contains of accumulator A in
A)

3a) 8251 universal synchronous asynchronous receiver transmitter (USART) acts as a mediator
between microprocessor and peripheral to transmit serial data into parallel form and vice
versa.
1. It takes data serially from peripheral (outside devices) and converts into parallel data.
2. After converting the data into parallel form, it transmits it to the CPU.
3. Similarly, it receives parallel data from microprocessor and converts it into serial form.
4. After converting data into serial form, it transmits it to outside device (peripheral).

3 b) 8155
The essential features of 8155 are
1. 8-bit 256 word RAM memory
2. Two programmable 8-bit I/O port
3. One programmable 6-bit IO port
4. One programmable 14-bit binary Timer/Counter
5. An internal address latch
6. A control/status (C/S) register
7. An internal decoder.
Functionally, it has two sections—(i) R/W memory and (b) programmable I/O and timer
section

8255
1. Basically there are three ports in 8255, viz., Port A, Port B and Port C, each having 8 pins.
2. Again Port C can be divided into Ports C and Port Clower—each having four pins upper
i.e., a nibble.
3. Thus 8255 can be viewed to have four ports—Port A, Port B, Port Cupper and Port C lower.
4. PPI 8255 can operate in three modes. (a) Mode 0 (b) Mode 1 and (c) Mode 2.
5. Apart from the above, there is another mode called BSR mode (Bit Set/Reset mode)

3c) Direct memory access (DMA) is a feature of computer systems that allows certain hardware
subsystems to access main system memory (random-access memory), independent of the central
processing unit or microprocessor.
Without DMA, when the CPU is using programmed input/output, it is typically fully occupied
for the entire duration of the read or write operation, and is thus unavailable to perform other
work. With DMA, the CPU first initiates the transfer, then it does other operations while the
transfer is in progress, and it finally receives an interrupt from the DMA controller (DMAC)
when the operation is done. This feature is useful at any time that the CPU cannot keep up with
the rate of data transfer, or when the CPU needs to perform work while waiting for a relatively
slow I/O data transfer. Many hardware systems use DMA, including disk
drive controllers, graphics cards, network cards and sound cards. DMA is also used for intra-chip
data transfer in multi-core processors. In 8085 HOLD and HLDA pins support DMA operation.

3d) Assumption – 1. Assume the port addresses are 80 H, 81 H, 82 H, 83 H for C0 (Counter 0),
C1(Counter 1), C2(Counter 2), CR(Control Register).
2. Clock frequency of 8254 is 2 MHz

For the above problem, 8254 must work in Mode 3 which is the square wave generator.

Count for register is given as clock frequency / square wave frequency

count = 2 MHz / 1 KHz = 2000 = (07D0) H

Now the data is 16 bit so value of RW1 = 1 and RW0 = 1 in Control Register.
Select C1 (Counter 1) the value of SC1 = 0 and SC0 = 1 in Control Register.
Value of M2 = 0, M1 = 1 and M2 = 1 for Mode 3 in Control Register.
For binary counter value of LSB in CR is 0.
Therefore the control word is 76H
 Program –
MEMORY ADDRESS MNEMONICS

2000 MVI A 76

2002 OUT 83

2004 MVI A D0

2006 OUT 81

2008 MVI A 07

200A OUT 81

200C HLT

3e)
Interfacing circuit for memory mapped

Interfacing circuit for I/O Mapped I/O

4a)

BHE : Bus High Enable/Status.

BHE stands for Bus High Enable. It is available at pin 34 and used to indicate the transfer of
data using data bus D8-D15. This signal is low during the first clock cycle, thereafter it is
active.
.

PIN A1 is used to carry address and data bits

4b)

1. Enable Interrupt (EI) – The interrupt enable flip-flop is set and all interrupts are enabled
following the execution of next instruction followed by EI. No flags are affected. After a
system reset, the interrupt enable flip-flop is reset, thus disabling the interrupts. This
instruction is necessary to enable the interrupts again (except TRAP).
2. Disable Interrupt (DI) – This instruction is used to reset the value of enable flip-flop
hence disabling all the interrupts. No flags are affected by this instruction.

4c) ALP to add 10 numbers in a array for 8086 microprocessor

START
MOV AX,DATA
MOV DS,AX
MOV SI,ARRAY pointer
MOV AX,0
MOV CX,0A
REPEAT:
MOV BL,ARRAY[SI]
 MOV BH,0
ADD AX,BX
INC SI
LOOP REPEAT
MOV SUM, AX
INT 21H
END

4 e) Minimum Mode 8086 System

•In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode by strapping
its MN/MX pin to logic 1.
•In this mode, all the control signals are given out by the microprocessor chip itself. There is a single
microprocessor in the minimum mode system.
•The remaining components in the system are latches, transreceivers, clock generator, memory and I/O
devices. Some type of chip selection logic may be required for selecting memory or I/O devices,
depending upon the address map of the system.
s indicate the type of data transfer as specified in table below.

Maximum Mode 8086 System •In the maximum mode, the 8086 is operated by strapping the MN/MX
pin to ground.
•In this mode, the processor derives the status signal S2, S1, S0. Another chip called bus controller
derives the control signal using this status information.
•In the maximum mode, there may be more than one microprocessor in the system configuration.
•The components in the system are same as in the minimum mode system.
•The basic function of the bus controller chip IC8288, is to derive control signals like RD and WR ( for
memory and I/O devices), DEN, DT/R, ALE etc. using the information by the processor on the status
lines.
•The bus controller chip has input lines S2, S1, S0 and CLK. These inputs to 8288 are driven by CPU.
•It derives the outputs ALE, DEN, DT/R, MRDC, MWTC, AMWC, IORC, IOWC and AIOWC.

Timing diagrams are given below:-

8086 Architecture
4 d) Architecture of 8086 microprocessor
EU (Execution Unit)
Execution unit gives instructions to BIU stating from where to fetch the data and then decode
and execute those instructions. Its function is to control operations on data using the instruction
decoder & ALU. EU has no direct connection with system buses as shown in the above figure,
it performs operations over data through BIU
BIU (Bus Interface Unit)
BIU takes care of all data and addresses transfers on the buses for the EU like sending
addresses, fetching instructions from the memory, reading data from the ports and the memory
as well as writing data to the ports and the memory. EU has no direction connection with
System Buses so this is possible with the BIU. EU and BIU are connected with the Internal Bus.

5a)
5 b) PSW (program status word) register.

The program status word (PSW) register is an 8-bit register. It is also referred to as the flag register.
Although the PSW register is 8 bits wide, only 6 bits of it are used by the 8051. The two unused bits are
user-definable flags.
The four of the flags are called conditional flags, meaning that they indicate some conditions that results
after an instruction is executed, these four are CY(carry), AC(auxiliary carry), P(parity) and
OV(overflow) the bits PSW.3 and PSW.4 are designated as RS0 and RS1 register selection bit and are
used to change the bank register.

5c)
The watchdog timer is an important device in the embedded system , which is used to develop
reliable products. Most of the embedded systems need to be self-reliant in order to restart and restore the
system if any software bug disturbs the system. It is not always possible for human operators to wait for
rebooting the system for every software problem. The watchdog timer is a piece of hardware that provides
ultimate solutions for the real-time industries, which used to detect system abnormalities automatically
and to reset the processor.

The watchdog timer is a simple electronic device that is responsible to resetting the microcontroller or
microprocessor for invalid software status. Generally a microcontroller is programmed with software that
contains several loops and number of subroutines that direct variety of activities. If any reason, if the loop
isfail to execute, then it finds and resets the device at starting or top of the loop.

5 d) An embedded system is a combination of computer hardware and software, either fixed in capability
or programmable, designed for a specific function or functions within a larger system.

An Embedded System is one which contains both hardware and software components for a system which
makes it to dedicate for a specific application..Right from the time we wake up in the early morning to the
time we return to bed we live along with embedded systems which makes lives simpler in this earth.

Digital Clocks we use daily either in our wrist or in the wall is a very good example of an embedded
system. It displays us the time along with the alarm, calendar facilities. Other examples like like Washing
machine, Micro wave oven, Traffic light signals, and various luxury operations in the latest cars, etc.
Similarly 8051 Embedded System can be built based on the platform of 8051 family of microcontroller.
The hardware module varies depending upon the application which is connected to the 8051
microcontroller. an example of digital thermostat embedded system is given below:- the processor used is
8051 microcontroller.
You may any example
 Counters/Timers
The 8051 has two counters/timers timer0 and timer1. which can be used either as timer to generate a
time delay or as counter to count events happening outside the microcontroller. Both timers are 16 bits
wide. Since the 8051 has an 8-bit architecture, each 16-bit is accessed as two separate registers of low
byte and high byte. First we shall discuss about Timer0 registers.

Timer 0 registers is a 16 bits register and accessed as low byte and high byte. The low byte is referred as
a TL0 and the high byte is referred as TH0. These registers can be accessed like any other registers.

Timer1 registers is also a 16 bits register and is split into two bytes, referred to as TL1 and
TH1.
TMOD (timer mode) Register: This is an 8-bit register which is used by both timers 0 and 1 to
set the various timer modes. In this TMOD register, lower 4 bits are set aside for timer0 and the
upper 4 bits are set aside for timer1. In each case, the lower 2 bits are used to set the timer mode
and upper 2 bits to specify the operation.

TMOD

In upper or lower 4 bits, first bit is a GATE bit. Every timer has a means of starting and
stopping. The second bit is C/T bit and is used to decide whether a timer is used as a time
delay generator or an event counter. If this bit is 0 then it is used as a timer and if it is 1 then it is
used as a counter.

In upper or lower 4 bits, the last bits third and fourth are known as M1 and M0 respectively.
These are used to select the timer mode.

M0 M1 Mode Operating Mode

0 0 0 13-bit timer mode, 8-bit timer/counter THx and

TLx as 5-bit prescalar.

0 1 1 16-bit timer mode, THx and

TLx are cascaded;

1 0 2 8-bit auto reload mode, 8

1 1 3 Spilt timer mode.

TCON register- Bits and symbol and functions of every bits of TCON are as follows:
BIT Symbol Functions

7 TF1 Timer1 over flow flag.

6 TR1 Timer 1 run control bit.

5 TF0 Timer 0 over flow flag. Same as TF1.

4 TR0 Timer 0 run control bit. Same as TR1.

3 IE1 External interrupt 1 Edge flag.

2 IT1 External interrupt1 signal type control bit.

1 IE0 External interrupt 0 Edge flag.

0 IT0 External interrupt 0 signal type control bit