Indian Institute of Technology

Roorkee

Analog VLSI Circuit Design

(ECC-537)
(Assignment-2)

Submitted to: Submitted by:

Dr Bishnu Prasad Das Simranjit Singh
24915017
PhD
Simranjit Singh 24915017

Assignment - 2
AIM: Capacitance Measurement
For NMOS transistor with W=6μm and Vds= 0.9V for three different transistor sizes L=0.18,
0.36, 0.72,1, 2 μm. perform DC sweep of Vgs from 0 to 1.8V with a step size of 0.18V.
(a) Plot Cgs, Cgd and Cgb vs Vgs
(b) Plot gm/Id versus (Vgs - Vth)
(c) Plot gm/gds versus (gm/Id) where gds = 1/ro = output conductance
(d) Plot Cgg/W vs (gm/Id)
(e) Plot Cdd/W vs (gm/Id)
(f) Plot Css/W vs (gm/Id)

Schematic/Theory: An NMOS (N-channel Metal-Oxide-Semiconductor) transistor is a type

of MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) used in electronic
circuits for switching and amplification. It has three terminals: the gate (G), the drain (D),
and the source (S). The operation of the NMOS transistor is controlled by the voltage applied
to the gate terminal relative to the source terminal.

Working Principle

• Gate Voltage (Vgs): When a positive voltage is applied to the gate relative to the
source, it creates an electric field that attracts electrons to the channel, forming a
conductive path between the drain and source.
• Drain-Source Voltage (Vds): This voltage drives the current through the channel
from the drain to the source.

Capacitances in NMOS: In an NMOS (N-type Metal-Oxide-Semiconductor) transistor,

capacitances arise due to the various charge storage phenomena associated with the device's
structure. These capacitances are crucial for determining the transistor's speed and are divided into
three main types:

1. Gate Capacitance (Cgs, Cgd, Cgb):

• Cgs (Gate-to-Source Capacitance): This capacitance occurs between the

gate and the source terminals. It is primarily due to the overlap of the gate
with the source region and the oxide layer separating them.
• Cgd (Gate-to-Drain Capacitance): Similar to Cgs, this capacitance occurs
between the gate and the drain. It is significant because it affects the Miller
effect, which can slow down the switching speed of the transistor.
• Cgb (Gate-to-Body Capacitance): This capacitance is between the gate and
the bulk (body) of the transistor. It is usually smaller compared to Cgs and
Cgd.

2. Junction Capacitance (Cjs, Cjd):

• Cjs (Source-to-Body Capacitance): This capacitance is due to the depletion

region formed at the p-n junction between the source and the bulk. It varies
with the source-to-body voltage.
 • Cjd (Drain-to-Body Capacitance): Similar to Cjs, this capacitance is due to
the p-n junction between the drain and the bulk. It also varies with the drain-
to-body voltage and is more significant when the drain is reverse-biased.

3. Overlap Capacitance:

• Overlap capacitance occurs due to the overlap of the gate with the source and
drain regions beyond the channel length. It contributes to both Cgs and Cgd.

These capacitances are critical in determining the switching speed of the NMOS transistor,
as they influence the charging and discharging times during operation. Reducing these
capacitances is key to enhancing the performance of high-speed circuits.

The current flowing from the drain to the source (ID) is controlled by the gate-source voltage
(Vgs).

Fig 1: Schematic of NMOS Transistor

Components and Connections

1. NMOS Transistor (M0):

o Symbol: The rectangle with an arrow pointing inward at the source indicates
an NMOS transistor.
o Parameters:
▪ n18: Likely indicates the transistor is from an n18 process technology,
which typically refers to a 180nm technology node.
▪ w=6: This parameter specifies the width of the transistor in
micrometers (µm).
▪ l=L: This indicates the length of the transistor's channel.
▪ m=1: This specifies the multiplier for the number of transistors,
meaning a single transistor is being used.
2. Voltage Sources (V0 and V1):
o V0:
▪ Connected to the gate of the NMOS (M0).
 ▪ Labeled as vdc=Vgs, suggesting it provides the gate-source voltage
(Vgs) necessary to control the NMOS.
o V1:
▪ Connected to the drain of the NMOS.
▪ Labeled as vdc=900.0m, which means it supplies 900 mV or 0.9V to
the drain.
3. Connections:
o Gate Connection (Vgs): The gate of the NMOS (M0) is connected to the
voltage source V0, which controls the transistor by setting the gate-source
voltage (Vgs).
o Drain Connection: The drain of the NMOS (M0) is connected to the voltage
source V1, providing a 0.9V potential.
o Source Connection: The source of the NMOS (M0) is connected to ground
(gnd), meaning it is at 0V.
o Bulk Connection: Although not explicitly shown, typically the bulk (body) of
the NMOS is connected to the source or to a ground potential in an n-well
technology.
4. Ground (gnd):
o The circuit is grounded at multiple points: at the source of the NMOS
transistor and at the negative terminals of the voltage sources.

Functionality:

This circuit sets up a basic NMOS transistor configuration where the gate voltage (Vgs)
controls the current flow from the drain (connected to V1) to the source (connected to
ground). Depending on the value of Vgs provided by V0, the transistor either turns on,
allowing current to flow, or turns off, blocking current. The source is grounded, making this
a common-source configuration.

This type of setup is common in basic transistor operation studies or in building larger
circuits like amplifiers or switches.

Procedure: Following is the procedure to make plot for gm/Id vs Vgs−Vth. For all other
plots same procedure is being followed.

1. Set Up the Schematic:

• Ensure your NMOS transistor is correctly connected with the appropriate sources.
• Apply a voltage source to the gate (for Vgs) and connect the drain to a power supply.
The source should be connected to the ground.

2. Simulation Setup (DC Analysis):

• Open ADE L (Analog Design Environment):

o Go to Launch > ADE L.
• Set Up DC Sweep:
o Go to Analyses > Choose.
o Select dc for a DC sweep analysis.
o In the DC analysis window, select to sweep the gate voltage (Vgs) from a
suitable range 0V to 1.8V.
 o We also use parametric analysis plot graphs for different device lengths given
in the assignment that is 0.18, 0.36, 0.72, 1, 2 μm.

3. Save Operating Point Parameters:

• Go to Outputs > Save All.

• Ensure you save the "Selected Devices" operating point parameters, which include
gm (transconductance), Id (drain current), and Vth (threshold voltage).
• Specifically, ensure that gm, id, and Vth for your NMOS transistor (e.g., M0) are
saved.

4. Run the Simulation:

• Click the green Run button or go to Simulation > Run to perform the DC sweep.
• Cadence will sweep the Vgs and extract the necessary operating point data.

5. Create Output Expressions for gm/Id and Vgs−Vth:

• Go to Outputs > Setup.

• Add an output expression for gm/Id:
o Expression: gm("/M0")/id("/M0")
• Add another output expression for Vgs−Vth:
o Expression: Vgs - Vth("/M0")
o Replace Vgs with the name of the net connected to the gate.

6. Using wavevswave Function to Plot gm/Id vs Vgs−Vth:

• After running the simulation and defining the expressions:

o Go to Results > Direct Plot > Calculator.
• In the Calculator window:
o Click on the wavevswave function.
o For the numerator, select the expression for gm/Id.
o For the denominator, select the expression for Vgs−Vth.
• The Calculator will now create a waveform representing gm/Id versus Vgs−Vth.
• Click on the Plot button in the Calculator to visualize the waveform.

7. Fine-Tune the Plot:

• Adjust the axis labels and plot title for clarity.

• Use the Tools > Markers feature to analyze specific points on the plot if needed.
(a) Plot Cgs, Cgd and Cgb vs Vgs

Fig 2: Cgs vs Vgs Plot

Explanation of Cgs vs Vgs:

• Low Vgs: At low Vgs, the MOSFET is off or in the subthreshold region,
where Cgs is dominated by the gate oxide capacitance and the overlap
capacitance.
• Threshold Region: As Vgs approaches the threshold voltage, Cgs
increases as the channel forms, which couples the gate more strongly to
the source.
• Saturation: In the saturation region, Cgs is primarily due to the channel
capacitance, and it stabilizes because the channel charge distribution
becomes relatively stable, particularly for long channel devices.

Explanation of Cgd vs Vgs:

• Low Vgs : At low Vgs, the MOSFET is in the cutoff or subthreshold
region, and the Cgd is relatively low because the gate-drain overlap
capacitance dominates.
• Increasing Vgs: As Vgs increases and the device enters the linear region,
Cgd starts to rise due to the increased overlap between the gate and the
depletion region in the channel. As the device moves into saturation, Cgd
increases further due to the expansion of the depletion region around the
drain.
• Channel Length Dependency: For shorter channel lengths, the increase
in Cgd is more pronounced because the electric field control from the gate
becomes stronger, leading to a more significant modulation of the
depletion region.
 Fig 3: Cgd vs Vgs Plot

Fig 4: Cgb vs Vgs Plot

Explanation of Cgb vs Vgs:

• Low Vgs: At low Vgs, Cgb is relatively high because the bulk (substrate)
is strongly coupled to the gate through the depletion region.
• Inversion Region: As Vgs increases and the MOSFET enters the inversion
region, the channel forms, which screens the bulk from the gate, leading
to a decrease in Cgb.
 • Channel Length Dependency: The dependency on channel length is less
pronounced in Cgb compared to Cgs and Cgd because the bulk effect is
more uniform across different lengths.

(b) Plot gm/Id versus (Vgs - Vth)

Fig 5: Plot gm/Id versus (Vgs - Vth)

Explanation:
• Strong Inversion: At higher overdrive voltages, the NMOS operates in
strong inversion, where the increase in drain current becomes less
proportional to the increase in gate voltage, resulting in a decrease in
gm/Id.
• Channel Length Impact: Devices with longer channel lengths have a
slightly higher gm/Id at lower overdrive voltages, as they exhibit less
short-channel effects and thus better performance in terms of current
efficiency.
• Short Channels: Short-channel devices show a faster decline in gm/Id as
(Vgs - Vth) increases due to increased short-channel effects like velocity
saturation.

(c) Plot gm/gds versus (gm/Id)

Explanation:
• Short Channel Effects: In short-channel devices, such as L = 0.18 µm,
the output conductance (gds) increases due to short-channel effects like
Drain-Induced Barrier Lowering (DIBL). This results in a lower gm/gds
ratio.
• Longer Channels: For longer channels (e.g., L = 2 µm), short-channel
effects are reduced, leading to a lower gds and thus a higher gm/gds ratio.
This explains why the plot shows higher intrinsic gain for longer channel
lengths.
 Fig 6: Plot gm/gds versus (gm/Id)

(d) Plot Cgg/W vs (gm/Id)

Fig 7: Plot Cgg/W versus gm/Id

Explanation:
• Capacitance Dependency: Gate capacitance increases with channel length because longer
channels have more gate overlap and larger depletion regions under the gate, which increases
capacitance.
• gm/Id Ratio: As gm/Id increases, the device operates more efficiently, often in the
subthreshold or weak inversion region, where the gate capacitance decreases.
• The reduction in gate capacitance for higher gm/Id values is typical as the device moves into
more energy-efficient regimes of operation.
(e) Plot Cdd/W vs (gm/Id)

Fig 8: Plot Cdd/W versus gm/Id

• As shown in the plot, the Cdd/W ratio decreases rapidly as gm/Id

increases, then levels off at higher values of gm/Id. This behavior can be
attributed to the fact that at low gm/Id, the transistor operates in a sub-
threshold or near-threshold region, where parasitic capacitances like Cdd
are higher.
• As the transistor moves towards saturation (higher gm/Id), the parasitic
capacitances decrease, leading to a reduction in Cdd. This is because in
the saturation region, the voltage across the drain decreases, reducing the
effect of parasitic capacitances.
• For shorter channel lengths (e.g., L=0.18um), the Cdd is lower compared
to longer channel lengths (e.g., L=2um), which is expected because
shorter channels typically have less parasitic capacitance.

(f) Plot Css/W vs (gm/Id)

• In contrast to Cdd, the Css/W ratio decreases more gradually as gm/Id

increases, indicating a different dependency of source capacitance on the
transistor operation region.
• The graph shows that as gm/Id increases, the Css/W ratio tends to decrease
but at a slower rate compared to Cdd. This slower decline might be due to
the fact that source capacitance is more influenced by the body effect and
less by the channel length.
• The different lines represent different channel lengths (L). Similar to the
Cdd plot, shorter channel lengths exhibit lower capacitance values, as
shorter channels generally have less parasitic capacitance.
Fig 9: Plot Css/W versus gm/Id