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Logic Gates

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Naresh Goud
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14 views6 pages

Logic Gates

Uploaded by

Naresh Goud
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Expt.

1: LOGIC GATES

Aim:
 To design all logic gates.
 To write the Verilog HDL code for the realization of logic gates circuits.
 To write the testbench and simulate the design in Xilinx ISE environment
for verifying its functionality.
 To synthesize the design, implement it on Artix-7 FPGA kit and verify its
functionality.
Apparatus:
 Computer System
 Xilinx Vivado 2018.2
 Artix 7NEXYS DDR4 FPGA Boards
Logic Diagram:

AND GATE: TRUTH TABLE

OR GATE: TRUTH TABLE

NOT GATE: TRUTH TABLE

NAND GATE: TRUTH TABLE

NOR GATE: TRUTH TABLE

EXOR GATE: TRUTH TABLE

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EXNOR GATE: TRUTH TABLE

Experimental Procedure:
1. Write a Verilog program for the design of Logic Gate Functionalities
2. Write the testbench program for the given design.
3. Simulate the design using Xilinx ISim Simulator and verify its
functionality.
4. Synthesize the design using Xilinx XST tool.
5. Obtain the RTL schematic and Technology schematic diagrams.
6. Assign pin packages using PlanAhead as per given in the evaluation
board (Spartan 3 FPGA).
7. Create Timing constraints for the design.
8. Implement the design with the user constraints specified in step 6 and 7.
9. Properly connect the FPGA evaluation board to the PC.
10.Generate the FPGA bitmap file and configure the device using iMPACT
tool.
11.Verify the functionality of the design in the FPGA Board.

Verilog Source Code:


module logicgates (x,y,A,B,C,D,E,F,G); // Starting of module //
input x,y; // Input variables //
output A,B,C,D,E,F,G; // Output variables //
assign A= ~x;
assign B= x&y;
assign C= x|y;
assign D= ~(x&y);
assign E= ~(x|y);
assign F= x^y;
assign G= ~(x^y);
endmodule // End of module //

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Verilog Testbench Code:
module logicgates_tb;
reg x;reg y; // Inputs
wire A,B,C,D,E,F, G; // Outputs

// Instantiate the Unit Under Test (UUT)

logicgatesuut (.x(x), .y(y), .A(A), .B(B), .C(C), .D(D), .E(E), .F(F), .G(G));
initial
begin
// Initialize Inputs
#100 x = 0; y = 0;
#100 x = 0; y = 1;
#100 x = 1; y = 0;
#100 x = 1; y = 1;
end
endmodule

RTL Schematic:

Fig.1.1 RTL Schematic of the module

Register-transfer-level abstraction is used in hardware description languages


(HDLs) like Verilog and VHDL to create high-level representations of a circuit,
from which lower-level representations and ultimately actual wiring can be
derived. In digital circuit design, register-transfer level (RTL) is a design

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abstraction which models a digital circuit in terms of the flow of digital signals
(data) between hardware registers, and the logical operations performed on
those signals. Viewing an RTL schematic opens an NGR file that can be viewed
as a gate-level schematic.

This schematic is generated after the HDL synthesis phase of the synthesis
process. It shows a representation of the pre-optimized design in terms of
generic symbols, such as adders, multipliers, counters, AND gates, and OR
gates, that are independent of the targeted Xilinx device.

Technology Schematic:

Fig.1.2 Technology Schematic of the module

Viewing a Technology schematic opens an NGC file that can be viewed as an


architecture-specific schematic.This schematic is generated after the
optimization and technology targeting phase of the synthesis process. It shows a
representation of the design in terms of logic elements optimized to the target
Xilinx device or "technology"; for example, in terms of of LUTs, carry logic,
I/O buffers, and other technology-specific components. Viewing this schematic
allows you to see a technology-level representation of your HDL optimized for

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a specific Xilinx architecture, which might help you discover design issues early
in the design process. We should always refer to technology schematic for
synthesized result.

Simulated Waveforms:

Fig.1.3 Simulated Waveform of the module

Simulation is a technique of applying different input stimulus to the design at


different times to check if the rtl code behaves the intended way. It is used to
verify the robustness of the design.It is also similar to how a fabricated chip will
be used is the real world andf how it reacts to different inputs.

Synthesis Reports:
Power Report:

Fig.1.4 Power Report of the module

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Power report gives us an insight into the power consumed by the module, a
report like this helps to know where the power is consumed and if any
redesigning is necessary.

XDC REPORT:

Fig.1.5 XDC Report of the module

It explains about the input and output pins of the module.

Device utilization summary:

Fig.1.6 Utilisation Report of the module

Utilisation report gives us an insight into the no. of LUTs, sliced registers and
Bonded IOB consumed by the module.

Result:
The design of a Logic gates circuit is obtained and simulated using Verilog
HDL in Xilinx ISE environment. The design is then synthesized, implemented
in Artix-7 FPGA kit and its functionality is verified.

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