SPRS161K − MARCH 2001 − REVISED JULY 2007

D High-Performance Static CMOS Technology D Small Foot-Print (7 mm × 7 mm) Ideally

− 25-ns Instruction Cycle Time (40 MHz) Suited for Space-Constrained Applications
− 40-MIPS Performance D Watchdog (WD) Timer Module
− Low-Power 3.3-V Design
D 10-Bit Analog-to-Digital Converter (ADC)
D Based on TMS320C2xx DSP CPU Core − 5 Multiplexed Input Channels
− Code-Compatible With 240x and − 500 ns Minimum Conversion Time
F243/F241/C242 − Selectable Twin 8-State Sequencers
− Instruction Set Compatible With F240 Triggered by Event Manager
D On-Chip Memory
D Serial Communications Interface (SCI)
− Up to 8K Words x 16 Bits of Flash
EEPROM (2 Sectors) (LF2401A) D Phase-Locked-Loop (PLL)-Based Clock
− 8K Words x 16 Bits of ROM (LC2401A) Generation
− Programmable “Code-Security” Feature D Up to 13 Individually Programmable,
for the On-Chip Flash/ROM Multiplexed General-Purpose Input / Output
− Up to 1K Words x 16 Bits of (GPIO) Pins
Data/Program RAM D User-Selectable Dual External Interrupts
− 544 Words of Dual-Access RAM (XINT1 and XINT2)
− Up to 512 Words of Single-Access
D Power Management:
RAM
− Three Power-Down Modes
D Boot ROM − Ability to Power Down Each Peripheral
− SCI Bootloader Independently
D Event-Manager (EV) Module (EVA), Which D Real-Time JTAG-Compliant Scan-Based
Includes: Emulation, IEEE Standard 1149.1† (JTAG)
− Two 16-Bit General-Purpose Timers
− Seven 16-Bit Pulse-Width Modulation
D Development Tools Include:
− Texas Instruments (TI) ANSI C Compiler,
(PWM) Channels Which Enable:
Assembler/ Linker, and Code Composer
− Three-Phase Inverter Control
Studio Debugger
− Center- or Edge-Alignment of PWM
− Evaluation Modules
Channels
− Scan-Based Self-Emulation (XDS510)
− Emergency PWM Channel Shutdown
− Broad Third-Party Digital Motor Control
With External PDPINTA Pin
Support
− Programmable Deadband (Deadtime)
Prevents Shoot-Through Faults D 32-Pin VF Low-Profile Quad Flatpack
− One Capture Unit for Time-Stamping of (LQFP)
External Events D Extended Temperature Options (A and S)
− Input Qualifier for Select Pins − A: − 40°C to 85°C
− Synchronized A-to-D Conversion − S: − 40°C to 125°C
− Designed for AC Induction, BLDC,
Switched Reluctance, and Stepper Motor
Control

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Code Composer Studio and XDS510 are trademarks of Texas Instruments.

All trademarks are the property of their respective owners.
† IEEE Standard 1149.1−1990, IEEE Standard Test-Access Port; however, boundary scan is not supported in this device family.

 
  !"   #!$% &"' Copyright  2007, Texas Instruments Incorporated
&!   #" #" (" " 
") !"
&& *+' &! #", &"  ""%+ %!&"
",  %% #""'

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 1


 
  
 

SPRS161K − MARCH 2001 − REVISED JULY 2007

Table of Contents

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 46

TMS320x240xA device summary . . . . . . . . . . . . . . . 4 clock domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 other power-down options . . . . . . . . . . . . . . . . . . . 47
TMS320x240xA device summary . . . . . . . . . . . . . . . 5 digital I/O and shared pin functions . . . . . . . . . . . . 48
functional block diagram of the LF2401A watchdog (WD) timer module . . . . . . . . . . . . . . . . 49
DSP controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 development support . . . . . . . . . . . . . . . . . . . . . . . . 52
functional block diagram of the LC2401A device and development support
DSP controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 tool nomenclature . . . . . . . . . . . . . . . . . . . . . . 53
terminal functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 documentation support . . . . . . . . . . . . . . . . . . . . . . 55
constraints while emulating with JTAG LF2401A AND LC2401A ELECTRICAL
port pins and GPIO functions . . . . . . . . . . . . 17 SPECIFICATIONS DATA . . . . . . . . . . . . . . . . 57
in-circuit emulation options . . . . . . . . . . . . . . . . . . 18 absolute maximum ratings over
memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 operating temperature range . . . . . . . . . . . . . 57
peripheral memory map . . . . . . . . . . . . . . . . . . . . . 21 recommended operating conditions . . . . . . . . . . . 57
device reset and interrupts . . . . . . . . . . . . . . . . . . . 22 current consumption graphs . . . . . . . . . . . . . . . . . 60
interrupt request structure . . . . . . . . . . . . . . . . . . . 24 reducing current consumption . . . . . . . . . . . . . . . . 60
DSP CPU core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 emulator connection without signal buffering
TMS320Lx2401A instruction set . . . . . . . . . . . . . . 25 for the DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . 25 PARAMETER MEASUREMENT
scan-based emulation . . . . . . . . . . . . . . . . . . . . . . . 26 INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . 62
functional block diagram of the 2401A signal transition levels . . . . . . . . . . . . . . . . . . . . . . . 62
DSP CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 timing parameter symbology . . . . . . . . . . . . . . . . . 63
2401A legend for the internal hardware . . . . . . . . 28 general notes on timing parameters . . . . . . . . . . . 63
status and control registers . . . . . . . . . . . . . . . . . . 29 external reference crystal/clock with PLL
central processing unit . . . . . . . . . . . . . . . . . . . . . . 30 circuit enabled . . . . . . . . . . . . . . . . . . . . . . . . . 64
internal memory . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 timing with the PLL circuit enabled . . . . . . . . . . . . 64
dual-access RAM (DARAM) . . . . . . . . . . . . . . . . . 34 RS timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
single-access RAM (SARAM) . . . . . . . . . . . . . . . . 34 low-power mode timing . . . . . . . . . . . . . . . . . . . . . . 68
ROM (LC2401A) . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 LPM2 wake-up timing . . . . . . . . . . . . . . . . . . . . . . . 70
Flash EEPROM (LF2401A) . . . . . . . . . . . . . . . . . . 34 timing event manager interface . . . . . . . . . . . . . . . 71
boot ROM† . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 PWM timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Flash/ROM security . . . . . . . . . . . . . . . . . . . . . . . . . 36 capture timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
event manager module (EVA) . . . . . . . . . . . . . . . . 37 general-purpose input/output timing . . . . . . . . . . . 74
enhanced analog-to-digital converter 10-bit analog-to-digital converter (ADC) . . . . . . . . 75
(ADC) module . . . . . . . . . . . . . . . . . . . . . . . . . 41 migrating from other 240xA
serial communications interface devices to Lx2401A . . . . . . . . . . . . . . . . . . . . 77
(SCI) module . . . . . . . . . . . . . . . . . . . . . . . . . . 43 migrating from LF240xA (Flash)
PLL-based clock module . . . . . . . . . . . . . . . . . . . . 45 devices to LC240xA (ROM) devices . . . . . . 78
external reference crystal clock option . . . . . . . . . 46 peripheral register description . . . . . . . . . . . . . . . . 79
external reference oscillator clock option . . . . . . . 46 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

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SPRS161K − MARCH 2001 − REVISED JULY 2007

REVISION HISTORY

This data sheet revision history highlights the technical changes made to the SPRS161J device-specific data
sheet to make it an SPRS161K revision.

Scope:

PAGE HIGHLIGHTS

20 Modified On−chip ROM part of Figure 10, TMS320LC2401A Memory Map

42 Added sentence to paragraph following Figure 15

57 Added note to receommended operating conditions table

60 Added section on emulator connection without signal buffering for the DSP

78 Added section on migrating from LF2401A to LC2401A

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SPRS161K − MARCH 2001 − REVISED JULY 2007

description
The TMS320Lx2401A† device, a new member of the TMS320C24x generation of digital signal processor
(DSP) controllers, is part of the TMS320C2000 platform of fixed-point DSPs. The Lx2401A device offers the
enhanced TMS320 DSP architectural design of the C2xx core CPU for low-cost, low-power, and
high-performance processing capabilities. Several advanced peripherals, optimized for digital motor and
motion control applications, have been integrated to provide a true single-chip DSP controller. While
code-compatible with the existing 240x and C24x DSP controller devices, the Lx2401A offers increased
processing performance (40 MIPS) and a higher level of peripheral integration. See the TMS320x240xA Device
Summary section for device-specific features.
The Lx2401A device offers a peripheral suite tailored to meet the specific price/performance points required
by various applications. The Lx2401A also offers a cost-effective reprogrammable solution for volume
production. A password-based “code security” feature on the device is useful in preventing unauthorized
duplication of proprietary code stored in on-chip Flash/ROM. Note that the LF2401A contains a 256-word boot
ROM to facilitate in-circuit programming. The boot ROM on LC2401A is used for test purposes.
The Lx2401A offers an event manager module which has been optimized for digital motor control and power
conversion applications. Capabilities of this module include center- and/or edge-aligned PWM generation,
programmable deadband to prevent shoot-through faults, and synchronized analog-to-digital conversion.
Select EV pins have been provided with an “input-qualifier” circuitry, which minimizes inadvertent pin-triggering
by glitches.
The high-performance, 10-bit analog-to-digital converter (ADC) has a minimum conversion time of 500 ns and
offers up to 5 channels of analog input. The autosequencing capability of the ADC allows a maximum of
16 conversions to take place in a single conversion session without any CPU overhead.
A serial communications interface (SCI) is integrated on all devices to provide asynchronous communication
to other devices in the system. To maximize device flexibility, functional pins are also configurable as
general-purpose inputs/outputs (GPIOs).
To streamline development time, JTAG-compliant scan-based emulation has been integrated into all devices.
This provides non-intrusive real-time capabilities required to debug digital control systems. A complete suite
of code-generation tools from C compilers to the industry-standard Code Composer Studio debugger
supports this family. Numerous third-party developers not only offer device-level development tools, but also
system-level design and development support.
NOTE: The Lx2401A device has reduced peripheral functionality compared to other 24x/240x devices. While
peripherals such as SPI and CAN are absent on the Lx2401A, peripherals such as EV and ADC have reduced
functionality. For example, in the case of EV, there is no QEP unit and the Capture unit has only one capture
pin (as opposed to three or six pins in other devices). The ADC has only five input channels (as opposed to eight
or sixteen channels in other devices). For these reasons, some bits that are valid in other 24x/240x devices are
not applicable in the Lx2401A. The registers and their valid bits are described in Table 16, Lx2401A DSP
Peripheral Register Description. For a description of those registers and bits that are valid, refer to the
TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number
SPRU357). Any exceptions to SPRU357 have been described in the respective peripheral sections in this data
sheet.

TMS320C24x, TMS320C2000, TMS320, and C24x are trademarks of Texas Instruments.

† Throughout this document, TMS320Lx2401A is used as a generic name for the TMS320LF2401A and TMS320LC2401A devices. An
abbreviated name, Lx2401A, denotes both devices as well.

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SPRS161K − MARCH 2001 − REVISED JULY 2007

TMS320x240xA device summary

Table 1. Device Feature Comparison Between Lx2401A and Lx2402A

FEATURE LF2401A LC2401A LF2402A LC2402A
C2xx DSP Core Yes Yes Yes Yes
Instruction Cycle 25 ns 25 ns 25 ns 25 ns
MIPS (40 MHz) 40 MIPS 40 MIPS 40 MIPS 40 MIPS
Dual-Access
544 544 544 544
RAM (DARAM)
RAM (16-bit word)
Single-Access
512 512 512 —
RAM (SARAM)
3.3-V Flash (Program Space, 16-bit word) 8K — 8K —
Flash Sectors 4K/4K — 4K/4K —
On-chip ROM (Program Space, 16-bit word) — 8K — 6K
Code Security for On-Chip Flash/ROM Yes Yes Yes Yes
Boot ROM Yes Yes Yes —
External Memory Interface — — — —
Event Manager A (EVA) EVA EVA EVA EVA
S General-Purpose (GP) Timers 2 2 2 2
S Compare (CMP)/PWM 7 7 8 8
S Capture (CAP)/QEP 1 1 3/2 3/2
S Input qualifier circuitry on
PDPINTx, CAPn, XINT1/2, and Yes† Yes† Yes Yes
ADCSOC pins
Watchdog Timer Yes Yes Yes Yes
10-Bit ADC Yes Yes Yes Yes
S Channels 5 5 8 8
S Conversion Time (minimum) 500 ns 500 ns 500 ns 500 ns
SPI — — — —
SCI Yes Yes Yes Yes
CAN — — — —
Digital I/O Pins (Shared) 13 13 21 21
External Interrupts 2 2 3 3
Core 3.3 V 3.3 V 3.3 V 3.3 V
Supply Voltage
I/O 3.3 V 3.3 V 3.3 V 3.3 V
Packaging 32-pin VF 32-pin VF 64-pin PG 64-pin PG
Product Status‡ :
Product Preview (PP)
PD PD PD PD
Advance Information (AI)
Production Data (PD)
† Some pins may not be applicable to Lx2401A.
‡ PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include testing of all parameters.

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SPRS161K − MARCH 2001 − REVISED JULY 2007

functional block diagram of the LF2401A DSP controller

XTAL1/CLKIN
VDD (3.3 V) DARAM (B0)
PLL Clock XTAL2
VSS 256 Words
RS
XF C2xx
DARAM (B1)
DSP ADCIN00−ADCIN04
XINT1† Core
256 Words
10-Bit ADC VCCA
XINT2‡
(With Twin VSSA
CLKOUT‡ Autosequencer)
DARAM (B2) ADCSOC‡
32 Words

SCITXD/IOPB3
SARAM (512 Words) SCI SCIRXD/IOPB4

VCCP (5V) Flash WD

(8K Words −
4K/4K Sectors)
Digital I/O Port A(0−7) IOPA[0:7]‡
(Shared With Port B(0−5) IOPB[0:5]†
PDPINTA/IOPA0 Other Pins)
PWM1/IOPA1
PWM2/IOPA2
Event Manager A
PWM3/IOPA3
TRST
PWM4/IOPA4 D 1 × Capture Input TDO/IOPB2
PWM5/IOPA5 D 7 × Compare/PWM
Output TDI/OPB5
PWM6/IOPA6 JTAG Port
D 2 × GP Timers/PWM TMS/XF
CAP1‡
TCK/IOPB1
T2PWM†

† T2PWM, XINT1, and IOPB0 functionalities are multiplexed into a single pin, T2PWM/XINT1/IOPB0.
‡ XINT2, ADCSOC, CAP1, IOPA7, and CLKOUT functionalities are multiplexed into a single pin, XINT2/ADCSOC/CAP1/IOPA7/CLKOUT.

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SPRS161K − MARCH 2001 − REVISED JULY 2007

functional block diagram of the LC2401A DSP controller

XTAL1/CLKIN
VDD (3.3 V) DARAM (B0)
PLL Clock XTAL2
VSS 256 Words
RS
XF C2xx
DARAM (B1)
DSP ADCIN00−ADCIN04
XINT1† Core
256 Words
10-Bit ADC VCCA
XINT2‡
(With Twin VSSA
CLKOUT‡ Autosequencer)
DARAM (B2) ADCSOC‡
32 Words

SCITXD/IOPB3
SARAM (512 Words) SCI SCIRXD/IOPB4

ROM WD
(8K Words)

Digital I/O Port A(0−7) IOPA[0:7]‡

(Shared With Port B(0−5) IOPB[0:5]†
PDPINTA/IOPA0 Other Pins)
PWM1/IOPA1
PWM2/IOPA2
Event Manager A
PWM3/IOPA3
TRST
PWM4/IOPA4 D 1 × Capture Input TDO/IOPB2
PWM5/IOPA5 D 7 × Compare/PWM
Output TDI/OPB5
PWM6/IOPA6 JTAG Port
D 2 × GP Timers/PWM TMS/XF
CAP1‡
TCK/IOPB1
T2PWM†

† T2PWM, XINT1, and IOPB0 functionalities are multiplexed into a single pin, T2PWM/XINT1/IOPB0.
‡ XINT2, ADCSOC, CAP1, IOPA7, and CLKOUT functionalities are multiplexed into a single pin, XINT2/ADCSOC/CAP1/IOPA7/CLKOUT.

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SPRS161K − MARCH 2001 − REVISED JULY 2007

32-PIN VF PACKAGE
(TOP VIEW)

XINT2/ADCSOC/CAP1/IOPA7 /CLKOUT
TDO/ IOPB2
TDI/ OPB5

ADCIN00
VCCA

VSSA
TRST
VSS
24 23 22 21 20 19 18 17
VDD 25 16 ADCIN01

VCCP† 26 15 ADCIN02

PWM1/IOPA1 27 14 ADCIN03

PWM2/IOPA2 28 13 ADCIN04

PWM3/IOPA3 29 12 PWM6/IOPA6

VSS 30 11 PWM5/IOPA5

T2PWM/XINT1/IOPB0 31 10 PWM4/IOPA4

PDPINTA/IOPA0 32 9 RS
1 2 3 4 5 6 7 8
XTAL2
XTAL1/CLKIN

VSS
TCK/ IOPB1
TMS/ XF

VDD
SCIRXD/ IOPB4

SCITXD/ IOPB3

† Pin 26 is VCCP on LF2401A and is a No Connect (NC) on LC2401A.

NOTE A: Bold face type indicates function of the device pin after reset.

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SPRS161K − MARCH 2001 − REVISED JULY 2007

terminal functions
Terminal Functions†
TERMINAL
DESCRIPTION
NAME NO.
Device Reset (in) and Watchdog Reset (out).

Device reset. RS causes the device to terminate execution and to set PC = 0. When RS is brought to
a high level, execution begins at location 0x0000 of program memory. This pin is driven low by the DSP
RS 9 when a watchdog reset occurs. During watchdog reset, the RS pin will be driven low for the watchdog
reset duration of 128 CLKIN cycles.

The output buffer of this pin is an open-drain with an internal pullup (20 µA, typical). It is recommended
that this pin be driven by an open-drain device. (↑)
Power drive protection input. When this pin is pulled low by an external event, an interrupt is generated
and all PWM outputs go to high-impedance state. PDPINTA will keep PWM outputs in high-impedance
state even when the DSP is not executing. (↑)

NOTES:
1) Upon reset, the PDPINTA function is active, in addition to the GPIO function. If the IOPA0 function
PDPINTA/IOPA0 32
is desired, the PDPINTA function must be disabled. (This can be done by writing to bit 0 of the
EVAIMRA register.) Otherwise, the PWM outputs could inadvertently be put into a high-impedance
state when the IOPA0 pin is driven low.
2) When PDPINTA is used to “wake up” the DSP from LPM2, the pin should be held low for
(98304 CLKIN + 12 CLKOUT) cycles.
3) This pin must be held high when on-chip boot ROM is invoked.
PWM1/IOPA1 27 Compare/PWM output 1 or GPIO (↑)
PWM2/IOPA2 28 Compare/PWM output 2 or GPIO (↑)
PWM3/IOPA3 29 Compare/PWM output 3 or GPIO (↑)
PWM4/IOPA4 10 Compare/PWM output 4 or GPIO (↑)
PWM5/IOPA5 11 Compare/PWM output 5 or GPIO (↑)
PWM6/IOPA6 12 Compare/PWM output 6 or GPIO (↑)
Upon reset, this pin comes up as XINT1/IOPB0 pin. To enable the XINT1 function, the appropriate bit
in the XINT1CR register must be set. No special configuration sequence is needed to use this pin as
a GPIO. However, a write to the PADATDIR register is necessary to configure this pin as a
T2PWM/XINT1/IOPB0 31 general-purpose output. Configuration of this pin as T2PWM is achieved by writing a one to bit 8 of the
MCRA register. Note that the value of bit 8 in the MCRA register does not affect the XINT1 functionality
of this pin. The XINT1 function is enabled/disabled by the value written into the XINT1CR register and
is independent of the value written in bit 8 in the MCRA register. (↑)
Upon reset, this pin can be configured as any one of the following: XINT2, ADCSOC, CAP1, or IOPA7.
To configure this pin for XINT2 function, the appropriate bit in the XINT2CR register must be set. To
configure this pin for ADCSOC function, the appropriate bit in the ADCTRL2 register must be set. To
configure this pin for CAP1 function, the appropriate bits in the CAPCONA register must be configured.
XINT2/ADCSOC/CAP1/
22 To summarize, the XINT2, ADCSOC, and CAP1 functions are enabled at the respective peripheral level.
IOPA7/CLKOUT
No special configuration sequence is needed to use this pin as a GPIO. However, a write to the
PADATDIR register is necessary to configure this pin as a general-purpose output. This pin can also
function as the CPU clock output. This is achieved by writing a one to bit 7 of the MCRA register. When
CLKOUT is chosen, the internal logic for the XINT2, ADCSOC, and CAP1 sees the pin as a “1”. (↑)
† Bold face type indicates function of the device pin after reset.
‡ It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy
and improve the noise immunity of the ADC.
§ TDI is MUXed with digital output, not digital I/O.
¶ Pin 26 is VCCP on LF2401A and is a No Connect (NC) on LC2401A.
LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±20 µA.)
NOTE: On the target hardware, pins 13 and 14 (EMU0/EMU1) of the JTAG header must be pulled high.

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SPRS161K − MARCH 2001 − REVISED JULY 2007

terminal functions (continued)

Terminal Functions† (Continued)
TERMINAL
DESCRIPTION
NAME NO.
ADCIN00 17 Analog input channel 0
ADCIN01 16 Analog input channel 1
ADCIN02 15 Analog input channel 2
ADCIN03 14 Analog input channel 3
ADCIN04 13 Analog input channel 4
VCCA 19 Analog supply voltage for ADC (3.3 V)‡ Internally connected to VREFHI
VSSA 18 Analog ground reference for ADC. Internally connected to VREFLO .
SCITXD/IOPB3 3 SCI asynchronous serial port transmit data or GPIO (↑)
SCIRXD/IOPB4 2 SCI asynchronous serial port receive data or GPIO (↑)
JTAG test clock or GPIO (↑)
TCK/IOPB1 4
Function when TRST = 0: IOPB1
Function when TRST = 1: TCK
JTAG test data input or GPO. When TRST is low (i.e., when the JTAG connector is not connected to the
DSP), the TDI/OPB5 pin acts as an output. When RS is low, the OPB5 pin is asynchronously forced into
a high-impedance state and when RS subsequently rises, it will remain in high-impedance state until
software configures this pin as an output. The B5DIR bit (bit 13 of the PBDATDIR register) controls the
enable to this output buffer. Bit 13 of the MCRA register will have no effect on this pin. (↑)
TDI/OPB5§ 24
This pin must be held low during a reset to invoke the on-chip boot ROM.

Function when TRST = 0: OPB5

Function when TRST = 1: TDI
JTAG scan out, test data output or GPIO (↓)
TDO/IOPB2 23
Function when TRST = 0: IOPB2
Function when TRST = 1: TDO
JTAG test mode select or GPO. External flag output (latched software-programmable signal). XF is a
general-purpose output pin. It is set/reset by the SETC XF/CLRC XF instruction. This pin is configured
as an external flag output by all device resets. (↑)

Function when TRST = 0: XF

TMS/XF 1
Function when TRST = 1: TMS

NOTE: The enabling/disabling of the XF pin is controlled by Bit 0 of the SCSR4 register at address
0x701B (in addition to the TRST pin). Upon reset, this bit is zero, disabling the XF pin. This bit must be
set by user code before it can be used. This bit is not readable; hence, its status cannot be determined.
† Bold face type indicates function of the device pin after reset.
‡ It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy
and improve the noise immunity of the ADC.
§ TDI is MUXed with digital output, not digital I/O.
¶ Pin 26 is VCCP on LF2401A and is a No Connect (NC) on LC2401A.
LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±20 µA.)
NOTE: On the target hardware, pins 13 and 14 (EMU0/EMU1) of the JTAG header must be pulled high.

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SPRS161K − MARCH 2001 − REVISED JULY 2007

terminal functions (continued)

Terminal Functions† (Continued)
TERMINAL
DESCRIPTION
NAME NO.
JTAG test reset. The function of the TCK, TDI, TDO, and TMS pins depend on the state of the TRST
pin. If TRST = 1 (Test or Debugging mode), the function of these pins will be JTAG function (the GPIO
function of these pins is not available). If TRST = 0 (Functional mode), these pins function as GPIO. (↓)

NOTE: Do not use pullup resistors on TRST; it has an internal pulldown device. TRST is an active high
TRST 20 test pin and must be maintained low at all times during normal device operation. In a low-noise
environment, TRST may be left floating. In other instances, an external pulldown resistor is highly
recommended. The value of this resistor should be based on drive strength of the debugger pods
applicable to the design. A 2.2-kΩ resistor generally offers adequate protection. Since this is
application-specific, it is recommended that each target board be validated for proper operation of the
debugger and the application.
XTAL1/CLKIN 6 Crystal/Clock input to PLL
XTAL2 7 Crystal output
Flash programming voltage pin. This pin must be connected to a 5-V supply for Flash programming. The
Flash cannot be programmed if this pin is connected to GND. When not programming the Flash (i.e.,
during normal device operation), this pin can either be left connected to the 5-V supply or it can be tied
VCCP¶ 26 to GND. This pin must not be left floating at any time. Do not use any current-limiting resistor in series
with the 5-V supply on this pin. This pin is a “no connect” (NC) on ROM parts (i.e., this pin is not connected
to any circuitry internal to the device). Connecting this pin to 5 V or leaving it open makes no difference
on ROM parts.
VDD 5 Core supply (3.3 V)
VDD 25 Core supply (3.3 V)
VSS 8 Core ground
VSS 21 Core ground
VSS 30 Core ground
† Bold face type indicates function of the device pin after reset.
‡ It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy
and improve the noise immunity of the ADC.
§ TDI is MUXed with digital output, not digital I/O.
¶ Pin 26 is VCCP on LF2401A and is a No Connect (NC) on LC2401A.
LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±20 µA.)
NOTE: On the target hardware, pins 13 and 14 (EMU0/EMU1) of the JTAG header must be pulled high.

NOTE:
The I/O pins that are MUXed with the JTAG function cannot be used while debugging, since the
emulator needs complete control of the JTAG pins. While debugging, there should not be any
circuitry connected on these MUXed pins that could disturb the JTAG debug process.

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SPRS161K − MARCH 2001 − REVISED JULY 2007

terminal functions (continued)

NOTE: The multiplexing diagrams are functional representations of the multiplexing scheme. They do not
represent the actual circuit elements within the silicon.

PADATDIR.n
[IOPAn − input data]

PADATDIR.m
(Direction) 0
Pullup

FCOMPOE PWMn/IOPAn Pin

[COMCONA.9] 1

MCRA.k

PADATDIR.n
[IOPAn − Output Data] 0

PWMn 1

MCRA.k PWMn/IOPAn DIRECTION BIT DATA BIT

MCRA.1 PWM1/IOPA1 PADATDIR.9 PADATDIR.1
MCRA.2 PWM2/IOPA2 PADATDIR.10 PADATDIR.2
MCRA.3 PWM3/IOPA3 PADATDIR.11 PADATDIR.3
MCRA.4 PWM4/IOPA4 PADATDIR.12 PADATDIR.4
MCRA.5 PWM5/IOPA5 PADATDIR.13 PADATDIR.5
MCRA.6 PWM6/IOPA6 PADATDIR.14 PADATDIR.6

Figure 1. PWMn/IOPAn Pin Multiplexing Functional Block Diagram

PADATDIR.0
[IOPA0 − Input Data]

PADATDIR.0
[IOPA0 − Output Data] Pullup

PDPINTA/IOPA0 Pin
MCRA.0 PADATDIR.8

Input
PDPINTA Qualifier
Circuit

EVAIMRA.0

Figure 2. PDPINTA/IOPA0 Pin Multiplexing Functional Block Diagram

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SPRS161K − MARCH 2001 − REVISED JULY 2007

terminal functions (continued)

1

1
PADATDIR.7
[IOPA7 − Input Data]
XINT2 and XINT2 0
LPM1 Wakeup Logic Input
Qualifier
Circuit
XINT2CR.0

CAP1

CAPCONA[14,13]
Pullup
ADSOC XINT2/ADCSOC/
CAP1/IOPA7/
CLKOUT Pin
ADCTRL2.7
MCRA.7

PADATDIR.15
(Direction)

CLKOUT 1

PADATDIR.7 0
[IOPA7 − Output Data]

Figure 3. XINT2/ADCSOC/CAP1/IOPA7/CLKOUT Pin Multiplexing Functional Block Diagram

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SPRS161K − MARCH 2001 − REVISED JULY 2007

terminal functions (continued)

PBDATDIR.0
[IOPB0 − Input Data]

XINT1CR.0

XINT1 and Input

XINT1 LPM1 Qualifier
Wakeup Logic Circuit
Pullup

T2PWM/XINT1/IOPB0 Pin
PBDATDIR.8
(Direction Bit) 0

TCOMPOE
[GPTCONA.6] 1

MCRA.8

PBDATDIR.0
[IOPB0 − Output Data] 0

T2PWM 1
[PWM Signal]

Figure 4. T2PWM/XINT1/IOPB0 Pin Multiplexing Functional Block Diagram

PBDATDIR.3
[IOPB3 − Input Data]

PBDATDIR.11
(Direction Bit) Pullup
SCITXD/
MCRA.11 IOPB3 Pin

PBDATDIR.3
[IOPB3 − Output Data] 0

SCITXD 1

Figure 5. SCITXD/IOPB3 Pin Multiplexing Functional Block Diagram

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SPRS161K − MARCH 2001 − REVISED JULY 2007

terminal functions (continued)

SCIRXD

PBDATDIR.4
[IOPB4 − Input Data]
Pullup
PBDATDIR.12
(Direction Bit) SCIRXD/IOPB4 Pin

MCRA.12

PBDATDIR.4
[IOPB4 − Output Data]

Figure 6. SCIRXD/IOPB4 Pin Multiplexing Functional Block Diagram

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SPRS161K − MARCH 2001 − REVISED JULY 2007

terminal functions (continued)

TCK
Pullup
PBDATDIR.1
[IOPB1 − Input Data]
TCK/IOPB1 Pin
PBDATDIR.1
[IOPB1 − Output Data]

TRST
To CPU

RS
PBDATDIR.9
(Direction Bit)
Pullup
TDI
TDI/OPB5 Pin
PBDATDIR.5
[OPB5 − Output Data]

TRST

RS
PBDATDIR.13
(Direction Bit)

IOPBDATDIR.2
[IOPB2 − Input Data]

TDO/IOPB2 Pin
PBDATDIR.2
[IOPB2 − Output Data] 0
Pulldown

TDO 1

TRST

RS
PBDATDIR.10
(Direction Bit)
Pullup
TMS
TMS/XF Pin
XF
TRST

Bit 0† of SCSR4

TRST Pin

Pulldown

† This bit is a write-only bit.

Figure 7. JTAG/GPIO Pins Multiplexing Functional Block Diagram

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SPRS161K − MARCH 2001 − REVISED JULY 2007

constraints while emulating with JTAG port pins and GPIO functions
This section highlights the constraints that are encountered if the emulation/debugging tool attempts to use the
multiplexed JTAG/GPIO pins in their JTAG configuration while the application attempts to use them in the GPIO
configuration at the same time:
1. Since the emulation/debugging tools need complete control of the JTAG port pins, the GPIO functions that
are multiplexed with the JTAG port pins cannot be used when the JTAG pod is connected to the JTAG
header.
2. Applications using the JTAG port pins for its GPIO function must provide some isolation mechanism (such
as jumpers) to isolate the external circuitry associated with the GPIO circuits. This will ensure that the GPIO
circuit does not conflict with the signals from the JTAG pod. To reiterate, the circuitry associated with the
GPIO pins must be isolated from the DSP before the JTAG pod is connected to the JTAG header.
3. It is recommended that the Lx2401A application software does not enable GPIO function for the multiplexed
JTAG/GPIO pins if emulation tools are ever planned to be used concurrently. This will avoid drive conflicts
between JTAG pod signals and GPIO signals—particularly on TCK, TDI and TMS pins. Table 2 shows the
configuration of the multiplexed JTAG/GPIO pins depending on the status of the TRST pin.

Table 2. Configuration of Multiplexed JTAG/GPIO Pins

TRST = 1 TRST = 0
TCK (signal from the JTAG pod) Can be configured as IOPB1
TDI (signal from the JTAG pod) Can be configured as OPB5
TMS (signal from the JTAG pod) Can be configured as XF

4. TRST pin is internally pulled down. When this pin is left unconnected, it puts the multiplexed JTAG/GPIO
pins in their GPIO configuration. If TRST is driven high, it puts the multiplexed JTAG/GPIO pins in their JTAG
configuration and the device enters emulation mode. All the emulation and flash programming tools use the
JTAG port and will drive this pin high. TRST pin controls the functionality of the multiplexed JTAG/GPIO pins.

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in-circuit emulation options

The GPIO functionality of the JTAG/GPIO pins cannot be used when the JTAG function is used for debugging.
In applications which require full emulation, it is easy to build an in-circuit emulation system using a 2407A EVM
(or any TMS320LF240x target board). This requires some additional planning in the Lx2401A target board
design. The following suggestions may be used as a guideline while planning the board layout:
1. Make provisions for a connector (port) which will bring out all the Lx2401A signals.
2. Map these signals (such as PWM, SCI, ADC, GPIO) through a cable to the 2407A EVM connector signals.
3. Using the 2407A EVM emulation device, there are two options to build your software:
a. Use assembler directives to enable 2407A register mapping.
− Build your application using 2407A emulation board with the 2401A target board connected using
the harness suggested above.
− After software development is complete, rebuild the code using the assembler directive to use
2401A registers.
− Map and flash the code in Lx2401A. The end application should now run seamlessly on the 2401A
target with Lx2401A device.
b. Use the device IDs of 2407A and 2401A devices to select the required pin-mapping for your application.
− The Device ID for these devices is a unique number located at 701Ch.
− Build your application using the 2407A emulation board with the 2401A target board connected
using the harness suggested above.
− After software development is complete, flash the code in Lx2401A. The end application will select
the map and the registers based on the device ID and should now run seamlessly on the 2401A
target with Lx2401A device.

Lx2401A Target

Lx2401A/EVM Harness

JTAG Link

LF2407A EVM as Code Composer for

In-Circuit Emulator LF2407A EVM

Figure 8. Lx2401A Emulation Using LF2407A EVM as In-Circuit Emulator (Optional)

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SPRS161K − MARCH 2001 − REVISED JULY 2007

memory map

ÈÈÈÈÈÈÈÈÈ
Hex Program Hex Data Hex I/O

ÈÈÈÈÈÈÈÈÈ
0000 FLASH SECTOR 0 (4K) 0000 Memory-Mapped 0000
Interrupt Vectors (0000−003Fh) Registers/Reserved Addresses

ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ
005F
Reserved † (0040−0043h) 0060 On-Chip DARAM B2

ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ
User code begins at 0044h 007F
0FFF 0080 Illegal

ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ

1000 FLASH SECTOR 1 (4K) 00FF
1FFF 0100 Reserved

ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ
2000 01FF
0200 On-Chip DARAM (B0)§ (CNF = 0)

ÈÈÈÈÈÈÈÈÈ 02FF Reserved (CNF = 1)

ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ
0300 On-Chip DARAM (B1)¶
03FF

ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ

Reserved 0400 Reserved
04FF

ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ
ÉÉÉÉÉÉÉÉÉ ÈÈÈÈÈÈÈÈÈ
0500 Illegal

ÈÈÈÈÈÈÈÈÈ ÉÉÉÉÉÉÉÉÉ ÈÈÈÈÈÈÈÈÈ

07FF
0800 SARAM (512 words) Reserved
7FFF
ÈÈÈÈÈÈÈÈÈ
ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉ
Internal (DON = 1)
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ
ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉ
ÈÈÈÈÈÈÈÈÈ
8000 Reserved (DON = 0)
SARAM (512 words) 09FF

ÉÉÉÉÉÉÉÉÉ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ

Internal (PON = 1) 0A00
Reserved

ÉÉÉÉÉÉÉÉÉ
ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ
Reserved (PON = 0)
0FFF
81FF
1000

ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ

8200 Illegal
Reserved
87FF 6FFF

ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ
8800 7000 Peripheral Memory-Mapped

ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ

Registers (System, WD, ADC,
EV, SCI, I/O)

ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ

7FFF
8000

ÈÈÈÈÈÈÈÈÈ Reserved
ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ FEFF
ÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ
FF00
Reserved

ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ
FF0E

ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ

FDFF Illegal FF0F Flash Control Mode Register

ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ

FE00
Reserved‡ FF10

ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ

Reserved
FFFE

ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ
FEFF
FF00
On-Chip DARAM (B0)‡ (CNF = 1)

ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ
Reserved (CNF = 0) Reserved

ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ
FFFF
FFFF FFFF

ÉÉÉ
ÉÉÉ
ÈÈÈ
On-Chip Flash Memory (Sectored) SARAM (See Table 1 for details.)

ÈÈÈ Reserved or Illegal

NOTE A: Boot ROM: If the boot ROM is enabled, then addresses 0000−00FF in the program space will be occupied by boot ROM.
† Addresses 0040h−0043h in program memory are reserved for code security passwords.
‡ When CNF = 1, addresses FE00h−FEFFh and FF00h−FFFFh are mapped to the same physical block (B0) in program-memory space. For
example, a write to FE00h has the same effect as a write to FF00h. For simplicity, addresses FE00h−FEFFh are referred to as reserved.
§ When CNF = 0, addresses 0100h−01FFh and 0200h−02FFh are mapped to the same physical block (B0) in data-memory space. For example,
a write to 0100h has the same effect as a write to 0200h. For simplicity, addresses 0100h−01FFh are referred to as reserved.
¶ Addresses 0300h−03FFh and 0400h−04FFh are mapped to the same physical block (B1) in data-memory space. For example, a write to 0400h
has the same effect as a write to 0300h. For simplicity, addresses 0400h−04FFh are referred to as reserved.

Figure 9. TMS320LF2401A Memory Map

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SPRS161K − MARCH 2001 − REVISED JULY 2007

memory map (continued)

ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ
Hex Program Hex Data Hex I/O
0000 0000 Memory-Mapped 0000

ÈÈÈÈÈÈÈÈÈÈ
On-chip ROM (8K)
Interrupt Vectors (0000−003Fh) 005F Registers/Reserved Addresses

ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ
Reserved† (0040−0043h) 0060 On-Chip DARAM B2
007F

ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ
1FBF User code begins at 0044h
0080 Illegal
1FCO 00FF

ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ

Reserved
1FFF 0100 Reserved
01FF

ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ
2000
0200 On-Chip DARAM (B0)§ (CNF = 0)

ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ
02FF Reserved (CNF = 1)

ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ

0300 On-Chip DARAM (B1)¶
03FF
Reserved

ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ

0400 Reserved
04FF

ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ

ÉÉÉÉÉÉÉÉÉÉ
0500 Illegal
07FF

ÈÈÈÈÈÈÈÈÈÈ
ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÈÈÈÈÈÈÈÈÈÈ
0800 SARAM (512 words) Reserved

ÉÉÉÉÉÉÉÉÉÉ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ

ÉÉÉÉÉÉÉÉÉÉ
Internal (DON = 1)
7FFF
Reserved (DON = 0)

ÉÉÉÉÉÉÉÉÉÉ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ

8000
SARAM (512 words) 09FF
0A00

ÉÉÉÉÉÉÉÉÉÉ
ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ
Internal (PON = 1)
Reserved
Reserved (PON = 0)
0FFF

ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ

81FF
1000
8200 Illegal

ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ

Reserved
87FF 6FFF

ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ
8800 7000 Peripheral Memory-Mapped
Registers (System, WD, ADC,

ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ

7FFF
EV, SCI, I/O)

ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ

8000

ÈÈÈÈÈÈÈÈÈÈ Reserved
ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ
FEFF
FF00

ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ

ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ
Reserved

ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ

FDFF Illegal
FE00

ÈÈÈÈÈÈÈÈÈÈ Reserved‡
ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ FF10
Reserved

ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ

FEFF FFFE

ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ
FF00
On-Chip DARAM (B0)‡ (CNF = 1)

ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ
Reserved (CNF = 0) Reserved

ÉÉÉ
FFFF
FFFF FFFF

ÉÉÉ
ÈÈÈ
On-chip ROM SARAM (See Table 1 for details.)

ÈÈÈ
Reserved or Illegal

NOTE A: Boot ROM: If the boot ROM is enabled, then addresses 0000−00FF in the program space will be occupied by boot ROM.
† Addresses 0040h−0043h in program memory are reserved for code security passwords.
‡ When CNF = 1, addresses FE00h−FEFFh and FF00h−FFFFh are mapped to the same physical block (B0) in program-memory space. For
example, a write to FE00h has the same effect as a write to FF00h. For simplicity, addresses FE00h−FEFFh are referred to as reserved.
§ When CNF = 0, addresses 0100h−01FFh and 0200h−02FFh are mapped to the same physical block (B0) in data-memory space. For example,
a write to 0100h has the same effect as a write to 0200h. For simplicity, addresses 0100h−01FFh are referred to as reserved.
¶ Addresses 0300h−03FFh and 0400h−04FFh are mapped to the same physical block (B1) in data-memory space. For example, a write to 0400h
has the same effect as a write to 0300h. For simplicity, addresses 0400h−04FFh are referred to as reserved.

Figure 10. TMS320LC2401A Memory Map

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peripheral memory map

Hex
0000
Reserved
0003
Interrupt-Mask Register 0004
Reserved 0005
Interrupt Flag Register 0006
Emulation Registers 0007
and Reserved 005F

ÈÈÈÈÈÈÈÈÈ
Hex
0000

ÈÈÈÈÈÈÈÈÈ
Memory-Mapped Registers
and Reserved Illegal 7000−700F
005F
0060 System Configuration and

ÈÈÈÈÈÈÈÈÈ
On-Chip DARAM B2 7010−701F
007F Control Registers

ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ
0080
Illegal
Watchdog Timer Registers 7020−702F

ÈÈÈÈÈÈÈÈÈ
00FF
0100

ÈÈÈÈÈÈÈÈÈ
Reserved Illegal 7030−703F
01FF
0200
On-Chip DARAM B0 Reserved 7040−704F

ÈÈÈÈÈÈÈÈÈ
02FF
0300
On-Chip DARAM B1 SCI 7050−705F

ÈÈÈÈÈÈÈÈÈ
03FF
0400 Illegal 7060−706F

ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ
Reserved
04FF External interrupt registers 7070−707F

ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ
0500 Illegal Illegal 7080−708F
07FF
0800 Digital I/O Control Registers 7090−709F

ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ
SARAM (512 words)
09FF ADC Control Registers 70A0−70BF

ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ
0A00
Illegal
Illegal 70C0−70FF
6FFF

ÈÈÈÈÈÈÈÈÈ
7000
Peripheral Frame 1 (PF1) Reserved

ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ
73FF 7100−710E
7400

ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ
Peripheral Frame 2 (PF2) Illegal
743F 710F−71FF
7440

ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ
Illegal Reserved
74FF 7200−722F

ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ
7500
Reserved Illegal 7230−73FF

ÈÈÈÈÈÈÈÈÈ
753F
7540

ÈÈÈÈÈÈÈÈÈ
Illegal
77EF

ÈÈÈÈÈÈÈÈÈ
77F0 Event Manager − EVA
Code Security Passwords

ÈÈÈÈÈÈÈÈÈ
77F3 General-Purpose
Timer Registers 7400−7408
77F4

ÈÈÈÈÈÈÈÈÈ
Reserved Compare, PWM, and
77FF 7411−7419
Deadband Registers

ÈÈÈÈÈÈÈÈÈ
7800 Illegal Capture Registers 7420−7429

ÈÈÈÈÈ
FFFF
Interrupt Mask, Vector and

ÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ
Flag Registers 742C−7431
“Illegal” indicates that access to

ÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ
Illegal these addresses causes a
nonmaskable interrupt (NMI). Illegal 7432−743F

“Reserved” indicates addresses that

Reserved
are reserved for test.

Figure 11. Peripheral Memory Map

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device reset and interrupts

The TMS320Lx2401A software-programmable interrupt structure supports flexible on-chip and external interrupt
configurations to meet real-time interrupt-driven application requirements. The Lx2401A recognizes three types
of interrupt sources.
D Reset (hardware- or software-initiated) is unarbitrated by the CPU and takes immediate priority over any
other executing functions. All maskable interrupts are disabled until the reset service routine enables them.
The Lx2401A devices have two sources of reset: an external reset pin and a watchdog timer time-out
(reset).
D Hardware-generated interrupts are requested by external pins or by on-chip peripherals. There are two
types:
− External interrupts are generated by one of three external pins corresponding to the interrupts XINT1,
XINT2, and PDPINTA. These three can be masked both by dedicated enable bits and by the CPU
interrupt mask register (IMR), which can mask each maskable interrupt line at the DSP core.
− Peripheral interrupts are initiated internally by these on-chip peripheral modules: event manager A,
SCI, and ADC. They can be masked both by enable bits for each event in each peripheral and by the
CPU IMR, which can mask each maskable interrupt line at the DSP core.
D Software-generated interrupts for the Lx2401A devices include:
− The INTR instruction. This instruction allows initialization of any Lx2401A interrupt with software. Its
operand indicates the interrupt vector location to which the CPU branches. This instruction globally
disables maskable interrupts (sets the INTM bit to 1).
− The NMI instruction. This instruction forces a branch to interrupt vector location 24h. This instruction
globally disables maskable interrupts. Lx2401A devices do not have the NMI hardware signal, only
software activation is provided.
− The TRAP instruction. This instruction forces the CPU to branch to interrupt vector location 22h. The
TRAP instruction does not disable maskable interrupts (INTM is not set to 1); therefore, when the CPU
branches to the interrupt service routine, that routine can be interrupted by the maskable hardware
interrupts.
− An emulator trap. This interrupt can be generated with either an INTR instruction or a TRAP instruction.
Six core interrupts (INT1−INT6) are expanded using a peripheral interrupt expansion (PIE) module identical to
the F24x devices. The PIE manages all the peripheral interrupts from the Lx2401A peripherals and are grouped
to share the six core level interrupts. Figure 12 shows the PIE block diagram for hardware-generated interrupts.
The PIE block diagram (Figure 12) and the interrupt table (Table 3) explain the grouping and interrupt vector
maps. Lx2401A devices have interrupts identical to those of the F24x devices. See Table 3 for details.

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device reset and interrupts (continued)

PIE IMR
PDPINTA IFR
ADCINT
RXINT Level 1
TXINT IRQ GEN
XINT1 INT1
XINT2

INT2

CMP1INT
CMP2INT
CMP3INT
T1PINT Level 2
T1CINT IRQ GEN
T1UFINT
T1OFINT

CPU

INT3
T2PINT
T2CINT Level 3
T2UFINT IRQ GEN
T2OFINT

INT4

Level 4
CAP1INT
IRQ GEN

RXINT Level 5 INT5

TXINT IRQ GEN

ADCINT INT6
Level 6
XINT1 IRQ GEN
XINT2 IACK

PIVR & Logic

PIRQR#
PIACK#

Data Bus Addr Bus

Interrupt from external interrupt pin. The remaining interrupts are internal to the peripherals.

Figure 12. Peripheral Interrupt Expansion (PIE) Module Block Diagram for Hardware-Generated Interrupts

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interrupt request structure

Table 3. TMS320Lx2401A Interrupt Source Priority and Vectors

CPU
BIT PERIPHERAL
INTERRUPT SOURCE
INTERRUPT OVERALL POSITION IN INTERRUPT MASK-
AND PERIPHERAL DESCRIPTION
NAME PRIORITY PIRQRx AND VECTOR ABLE?
VECTOR MODULE
PIACKRx (PIV)
ADDRESS
RSN RS pin, Reset from pin, watchdog
Reset 1 N/A N
0000h Watchdog timeout
−
Reserved 2 N/A N CPU Emulator trap
0026h
NMI Nonmaskable Nonmaskable interrupt,
NMI 3 N/A N
0024h Interrupt software interrupt only
Power device protection
PDPINTA 4 0.0 0020h Y EVA
interrupt pin
ADC interrupt in
ADCINT 6 0.1 0004h Y ADC
high-priority mode
External
XINT1 7 0.2 0001h Y
INT1 Interrupt Logic External interrupt pins in high
0002h External priority
XINT2 8 0.3 0011h Y
Interrupt Logic
SCI receiver interrupt in
RXINT 10 0.5 0006h Y SCI
high-priority mode
SCI transmitter interrupt in
TXINT 11 0.6 0007h Y SCI
high-priority mode
CMP1INT 14 0.9 0021h Y EVA Compare 1 interrupt
CMP2INT 15 0.10 0022h Y EVA Compare 2 interrupt
CMP3INT 16 0.11 0023h Y EVA Compare 3 interrupt
INT2
T1PINT 17 0.12 0027h Y EVA Timer 1 period interrupt
0004h
T1CINT 18 0.13 0028h Y EVA Timer 1 compare interrupt
T1UFINT 19 0.14 0029h Y EVA Timer 1 underflow interrupt
T1OFINT 20 0.15 002Ah Y EVA Timer 1 overflow interrupt
T2PINT 28 1.0 002Bh Y EVA Timer 2 period interrupt
T2CINT 29 INT3 1.1 002Ch Y EVA Timer 2 compare interrupt
T2UFINT 30 0006h 1.2 002Dh Y EVA Timer 2 underflow interrupt
T2OFINT 31 1.3 002Eh Y EVA Timer 2 overflow interrupt
INT4
CAP1INT 36 1.4 0033h Y EVA Capture 1 interrupt
0008h
SCI receiver interrupt
RXINT 43 1.8 0006h Y SCI
INT5 (low-priority mode)
000Ah SCI transmitter interrupt
TXINT 44 1.9 0007h Y SCI
(low-priority mode)
† Refer to the TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number SPRU357) for more information.
NOTE: Some interrupts may not be available in a particular device due to the absence of a peripheral. See Table 1 for more details.

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interrupt request structure (continued)

Table 3. TMS320Lx2401A Interrupt Source Priority and Vectors (Continued)
CPU
BIT PERIPHERAL
INTERRUPT SOURCE
INTERRUPT OVERALL POSITION IN INTERRUPT MASK-
AND PERIPHERAL DESCRIPTION
NAME PRIORITY PIRQRx AND VECTOR ABLE?
VECTOR MODULE
PIACKRx (PIV)
ADDRESS
ADC interrupt
ADCINT 47 1.12 0004h Y ADC
(low priority)
INT6 External
XINT1 48 1.13 0001h Y
000Ch Interrupt Logic External interrupt pins
External (low-priority mode)
XINT2 49 1.14 0011h Y
Interrupt Logic
Reserved 000Eh N/A Y CPU Analysis interrupt
TRAP N/A 0022h N/A N/A CPU TRAP instruction
Phantom
Interrupt N/A N/A 0000h N/A CPU Phantom interrupt vector
Vector
INT8−INT16 N/A 0010h−0020h N/A N/A CPU
Software interrupt vectors†
INT20−INT31 N/A 00028h−0603Fh N/A N/A CPU
† Refer to the TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number SPRU357) for more information.
NOTE: Some interrupts may not be available in a particular device due to the absence of a peripheral. See Table 1 for more details.

DSP CPU core

The TMS320Lx2401A device uses an advanced Harvard-type architecture that maximizes processing power
by maintaining two separate memory bus structures — program and data — for full-speed execution. This
multiple bus structure allows data and instructions to be read simultaneously. Instructions support data transfers
between program memory and data memory. This architecture permits coefficients that are stored in program
memory to be read in RAM. This, coupled with a four-deep pipeline, allows the Lx2401A device to execute most
instructions in a single cycle. See the functional block diagram of the 2401A DSP CPU for more information.

TMS320Lx2401A instruction set

The 2401A DSP implements a comprehensive instruction set that supports both numeric-intensive
signal-processing operations and general-purpose applications, such as multiprocessing and high-speed
control.
For maximum throughput, the next instruction is prefetched while the current one is being executed.
addressing modes
The TMS320Lx2401A instruction set provides four basic memory-addressing modes: direct, indirect,
immediate, and register.
In direct addressing, the instruction word contains the lower seven bits of the data memory address. This field
is concatenated with the nine bits of the data memory page pointer (DP) to form the 16-bit data memory address.
Therefore, in the direct-addressing mode, data memory is paged effectively with a total of 512 pages, with each
page containing 128 words.
Indirect addressing accesses data memory through the auxiliary registers. In this addressing mode, the address
of the instruction operand is contained in the currently selected auxiliary register. Eight auxiliary registers
(AR0−AR7) provide flexible and powerful indirect addressing. To select a specific auxiliary register, the auxiliary
register pointer (ARP) is loaded with a value from 0 to 7 for AR0 through AR7, respectively.

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scan-based emulation
TMS320x2xx devices incorporate scan-based emulation logic for code-development and hardware-
development support. Scan-based emulation allows the emulator to control the processor in the system without
the use of intrusive cables to the full pinout of the device. The scan-based emulator communicates with the x2xx
by way of the IEEE 1149.1-compatible (JTAG) interface. The Lx2401A DSP does not include boundary scan.
The scan chain of the device is useful for emulation function only.

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functional block diagram of the 2401A DSP CPU

Program Bus

MUX
XTAL1
CLKOUT

Program Bus
Data Bus
XTAL2 NPAR

Control
XF
RS 16 PC PAR MSTACK MUX

Stack 8 × 16

XINT[1−2]
2

FLASH EEPROM Program Control

(PCTRL)

16

16
16

Data Bus

16 16
Data Bus

16
16
3 9 7 16
LSB 16 16
AR0(16) from
AR1(16) DP(9) IR 16
MUX
AR2(16)
MUX 16
ARP(3) AR3(16)
3 9
3 AR4(16)
AR5(16) TREG0(16)
ARB(3) AR6(16)
Multiplier
AR7(16)

3 ISCALE (0−16) PREG(32)

16
32

PSCALE (−6,ā 0,ā 1,ā 4)

32 32

16
MUX

ARAU(16) MUX
32

CALU(32)
32
16 Memory Map
Register
MUX MUX 32
IMR (16)
IFR (16)
Program Bus

Data/Prog Data
C ACCH(16) ACCL(16)
GREG (16) DARAM DARAM
B0 (256 × 16) B2 (32 × 16) 32

B1 (256 × 16)
OSCALE (0−7)
MUX 16
16 16
16

NOTES: A. See Table 4 for symbol descriptions.

B. For clarity, the data and program buses are shown as single buses although they include address and data bits.
C. Refer to the TMS320F/C24x DSP Controllers Reference Guide: CPU and Instruction Set (literature number SPRU160) for CPU
instruction set information.

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2401A legend for the internal hardware

Table 4. Legend for the 2401A DSP CPU Internal Hardware

SYMBOL NAME DESCRIPTION
32-bit register that stores the results and provides input for subsequent CALU operations. Also includes shift
ACC Accumulator
and rotate capabilities
Auxiliary Register An unsigned, 16-bit arithmetic unit used to calculate indirect addresses using the auxiliary registers as inputs
ARAU
Arithmetic Unit and outputs
These 16-bit registers are used as pointers to anywhere within the data space address range. They are
AUX Auxiliary Registers
operated upon by the ARAU and are selected by the auxiliary register pointer (ARP). AR0 can also be used
REGS 0 −7
as an index value for AR updates of more than one and as a compare value to AR.
Register carry output from CALU. C is fed back into the CALU for extended arithmetic operation. The C bit
C Carry resides in status register 1 (ST1), and can be tested in conditional instructions. C is also used in accumulator
shifts and rotates.
32-bit-wide main arithmetic logic unit for the TMS320C2xx core. The CALU executes 32-bit operations in a
Central Arithmetic
CALU single machine cycle. CALU operates on data coming from ISCALE or PSCALE with data from ACC, and
Logic Unit
provides status results to PCTRL.
If the on-chip RAM configuration control bit (CNF) is set to 0, the reconfigurable data dual-access RAM
(DARAM) block B0 is mapped to data space; otherwise, B0 is mapped to program space. Blocks B1 and B2
DARAM Dual-Access RAM
are mapped to data memory space only, at addresses 0300−03FF and 0060−007F, respectively. Blocks 0
and 1 contain 256 words, while block 2 contains 32 words.
Data Memory The 9-bit DP register is concatenated with the seven least significant bits (LSBs) of an instruction word to
DP
Page Pointer form a direct memory address of 16 bits. DP can be modified by the LST and LDP instructions.
Global Memory
GREG specifies the size of the global data memory space. Since the global memory space is not used in
GREG Allocation
the 240x devices, this register is reserved.
Register
Interrupt Mask
IMR IMR individually masks or enables the seven interrupts.
Register
Interrupt Flag The 7-bit IFR indicates that the TMS320C2xx has latched an interrupt from one of the seven maskable
IFR
Register interrupts.
INT# Interrupt Traps A total of 32 interrupts by way of hardware and/or software are available.
Input Data-Scaling 16- to 32-bit barrel left-shifter. ISCALE shifts incoming 16-bit data 0 to16 positions left, relative to the 32-bit
ISCALE
Shifter output within the fetch cycle; therefore, no cycle overhead is required for input scaling operations.
16 × 16-bit multiplier to a 32-bit product. MPY executes multiplication in a single cycle. MPY operates either
MPY Multiplier
signed or unsigned 2s-complement arithmetic multiply.
MSTACK provides temporary storage for the address of the next instruction to be fetched when program
MSTACK Micro Stack
address-generation logic is used to generate sequential addresses in data space.
MUX Multiplexer Multiplexes buses to a common input
Next Program
NPAR NPAR holds the program address to be driven out on the PAB in the next cycle.
Address Register
Output 16- to 32-bit barrel left-shifter. OSCALE shifts the 32-bit accumulator output 0 to 7 bits left for quantization
OSCALE Data-Scaling management and outputs either the 16-bit high- or low-half of the shifted 32-bit data to the data-write data
Shifter bus (DWEB).
Program Address PAR holds the address currently being driven on PAB for as many cycles as it takes to complete all memory
PAR
Register operations scheduled for the current bus cycle.
PC increments the value from NPAR to provide sequential addresses for instruction-fetching and sequential
PC Program Counter
data-transfer operations.
Program
PCTRL PCTRL decodes instruction, manages the pipeline, stores status, and decodes conditional operations.
Controller

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2401A legend for the internal hardware (continued)

Table 4. Legend for the 2401A DSP CPU Internal Hardware (Continued)
SYMBOL NAME DESCRIPTION
PREG Product Register 32-bit register holds results of 16 × 16 multiply
0-, 1-, or 4-bit left shift, or 6-bit right shift of multiplier product. The left-shift options are used to manage the
additional sign bits resulting from the 2s-complement multiply. The right-shift option is used to scale down
Product-Scaling
PSCALE the number to manage overflow of product accumulation in the CALU. PSCALE resides in the path from the
Shifter
32-bit product shifter and from either the CALU or the data-write data bus (DWEB), and requires no cycle
overhead.
STACK is a block of memory used for storing return addresses for subroutines and interrupt-service
STACK Stack
routines, or for storing data. The C2xx stack is 16 bits wide and 8 levels deep.
Temporary 16-bit register holds one of the operands for the multiply operations. TREG holds the dynamic shift count
TREG
Register for the LACT, ADDT, and SUBT instructions. TREG holds the dynamic bit position for the BITT instruction.

status and control registers

Two status registers, ST0 and ST1, contain the status of various conditions and modes. These registers can
be stored into data memory and loaded from data memory, thus allowing the status of the machine to be saved
and restored for subroutines.
The load status register (LST) instruction is used to write to ST0 and ST1. The store status register (SST)
instruction is used to read from ST0 and ST1 — except for the INTM bit, which is not affected by the LST
instruction. The individual bits of these registers can be set or cleared when using the SETC and CLRC
instructions. Figure 13 shows the organization of status registers ST0 and ST1, indicating all status bits
contained in each. Several bits in the status registers are reserved and are read as logic 1s. Table 5 lists status
register field definitions.

15 13 12 11 10 9 8 0
ST0 ARP OV OVM 1 INTM DP

15 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ST1 ARB CNF TC SXM C 1 1 1 1 XF 1 1 PM

Figure 13. Organization of Status Registers ST0 and ST1

Table 5. Status Register Field Definitions

FIELD FUNCTION
Auxiliary register pointer buffer. When the ARP is loaded into ST0, the old ARP value is copied to the ARB except during an LST
ARB
instruction. When the ARB is loaded by way of an LST #1 instruction, the same value is also copied to the ARP.
Auxiliary register (AR) pointer. ARP selects the AR to be used in indirect addressing. When the ARP is loaded, the old ARP value
ARP is copied to the ARB register. ARP can be modified by memory-reference instructions when using indirect addressing, and by the
LARP, MAR, and LST instructions. The ARP is also loaded with the same value as ARB when an LST #1 instruction is executed.
Carry bit. C is set to 1 if the result of an addition generates a carry, or reset to 0 if the result of a subtraction generates a borrow.
Otherwise, C is reset after an addition or set after a subtraction, except if the instruction is ADD or SUB with a 16-bit shift. In these
C cases, ADD can only set and SUB can only reset the carry bit, but cannot affect it otherwise. The single-bit shift and rotate
instructions also affect C, as well as the SETC, CLRC, and LST #1 instructions. Branch instructions have been provided to branch
on the status of C. C is set to 1 on a reset.
On-chip RAM configuration control bit. If CNF is set to 0, the reconfigurable data dual-access RAM blocks are mapped to data
CNF space; otherwise, they are mapped to program space. The CNF can be modified by the SETC CNF, CLRC CNF, and LST #1
instructions. RS sets the CNF to 0.

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status and control registers (continued)

Table 5. Status Register Field Definitions (Continued)
FIELD FUNCTION
Data memory page pointer. The 9-bit DP register is concatenated with the 7 LSBs of an instruction word to form a direct memory
DP
address of 16 bits. DP can be modified by the LST and LDP instructions.
Interrupt mode bit. When INTM is set to 0, all unmasked interrupts are enabled. When set to 1, all maskable interrupts are disabled.
INTM is set and reset by the SETC INTM and CLRC INTM instructions. RS also sets INTM. INTM has no effect on the unmaskable
INTM
RS and NMI interrupts. Note that INTM is unaffected by the LST instruction. This bit is set to 1 by reset. It is also set to 1 when
a maskable interrupt trap is taken.
Overflow flag bit. As a latched overflow signal, OV is set to 1 when overflow occurs in the arithmetic logic unit (ALU). Once an
OV
overflow occurs, the OV remains set until a reset, BCND/D on OV/NOV, or LST instruction clears OV.
Overflow mode bit. When OVM is set to 0, overflowed results overflow normally in the accumulator. When set to 1, the accumulator
OVM is set to either its most positive or negative value upon encountering an overflow. The SETC and CLRC instructions set and reset
this bit, respectively. LST can also be used to modify the OVM.
Product shift mode. If these two bits are 00, the multiplier’s 32-bit product is loaded into the ALU with no shift. If PM = 01, the PREG
output is left-shifted one place and loaded into the ALU, with the LSB zero-filled. If PM = 10, the PREG output is left-shifted by 4 bits
PM and loaded into the ALU, with the LSBs zero-filled. PM = 11 produces a right shift of 6 bits, sign-extended. Note that the PREG
contents remain unchanged. The shift takes place when transferring the contents of the PREG to the ALU. PM is loaded by the
SPM and LST #1 instructions. PM is cleared by RS.
Sign-extension mode bit. SXM = 1 produces sign extension on data as it is passed into the accumulator through the scaling shifter.
SXM = 0 suppresses sign extension. SXM does not affect the definitions of certain instructions; for example, the ADDS instruction
SXM
suppresses sign extension regardless of SXM. SXM is set by the SETC SXM instruction and reset by the CLRC SXM instruction
and can be loaded by the LST #1 instruction. SXM is set to 1 by reset.
Test/control flag bit. TC is affected by the BIT, BITT, CMPR, LST #1, and NORM instructions. TC is set to a 1 if a bit tested by BIT
or BITT is a 1, if a compare condition tested by CMPR exists between AR (ARP) and AR0, if the exclusive-OR function of the 2 most
TC
significant bits (MSBs) of the accumulator is true when tested by a NORM instruction. The conditional branch, call, and return
instructions can execute based on the condition of TC.
XF pin status bit. XF indicates the state of the XF pin, a general-purpose output pin. XF is set by the SETC XF instruction and reset
XF
by the CLRC XF instruction. XF is set to 1 by reset.

central processing unit

The TMS320Lx2401A central processing unit (CPU) contains a 16-bit scaling shifter, a 16 x 16-bit parallel
multiplier, a 32-bit central arithmetic logic unit (CALU), a 32-bit accumulator, and additional shifters at the
outputs of both the accumulator and the multiplier. This section describes the CPU components and their
functions. The functional block diagram shows the components of the CPU.
input scaling shifter
The TMS320Lx2401A provides a scaling shifter with a 16-bit input connected to the data bus and a 32-bit output
connected to the CALU. This shifter operates as part of the path of data coming from program or data space
to the CALU and requires no cycle overhead. It is used to align the 16-bit data coming from memory to the 32-bit
CALU. This is necessary for scaling arithmetic as well as aligning masks for logical operations.
The scaling shifter produces a left shift of 0 to 16 on the input data. The LSBs of the output are filled with zeros;
the MSBs can either be filled with zeros or sign-extended, depending upon the value of the SXM bit
(sign-extension mode) of status register ST1. The shift count is specified by a constant embedded in the
instruction word or by a value in TREG. The shift count in the instruction allows for specific scaling or alignment
operations specific to that point in the code. The TREG base shift allows the scaling factor to be adaptable to
the system’s performance.

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multiplier
The TMS320Lx2401A device uses a 16 x 16-bit hardware multiplier that is capable of computing a signed or
an unsigned 32-bit product in a single machine cycle. All multiply instructions, except the MPYU (multiply
unsigned) instruction, perform a signed multiply operation. That is, two numbers being multiplied are treated
as 2s-complement numbers, and the result is a 32-bit 2s-complement number. There are two registers
associated with the multiplier, as follow:
D 16-bit temporary register (TREG) that holds one of the operands for the multiplier
D 32-bit product register (PREG) that holds the product
Four product-shift modes (PM) are available at the PREG output (PSCALE). These shift modes are useful for
performing multiply/accumulate operations, performing fractional arithmetic, or justifying fractional products.
The PM field of status register ST1 specifies the PM shift mode, as shown in Table 6.

Table 6. PSCALE Product-Shift Modes

PM SHIFT DESCRIPTION
00 No shift Product feed to CALU or data bus with no shift
01 Left 1 Removes the extra sign bit generated in a 2s-complement multiply to produce a Q31 product
Removes the extra 4 sign bits generated in a 16x13 2s-complement multiply to a produce a Q31 product when
10 Left 4
using the multiply-by-a-13-bit constant
11 Right 6 Scales the product to allow up to 128 product accumulation without the possibility of accumulator overflow

The product can be shifted one bit to compensate for the extra sign bit gained in multiplying two 16-bit
2s-complement numbers (MPY instruction). A four-bit shift is used in conjunction with the MPY instruction with
a short immediate value (13 bits or less) to eliminate the four extra sign bits gained in multiplying a 16-bit number
by a 13-bit number. Finally, the output of PREG can be right-shifted 6 bits to enable the execution of up to
128 consecutive multiply/accumulates without the possibility of overflow.
The LT (load TREG) instruction normally loads TREG to provide one operand (from the data bus), and the MPY
(multiply) instruction provides the second operand (also from the data bus). A multiplication also can be
performed with a 13-bit immediate operand when using the MPY instruction. Then, a product is obtained every
two cycles. When the code is executing multiple multiplies and product sums, the CPU supports the pipelining
of the TREG load operations with CALU operations using the previous product. The pipeline operations that
run in parallel with loading the TREG include: load ACC with PREG (LTP); add PREG to ACC (LTA); add PREG
to ACC and shift TREG input data (DMOV) to next address in data memory (LTD); and subtract PREG from ACC
(LTS).
Two multiply/accumulate instructions (MAC and MACD) fully utilize the computational bandwidth of the
multiplier, allowing both operands to be processed simultaneously. The data for these operations can be
transferred to the multiplier each cycle by way of the program and data buses. This facilitates single-cycle
multiply/accumulates when used with the repeat (RPT) instruction. In these instructions, the coefficient
addresses are generated by program address generation (PAGEN) logic, while the data addresses are
generated by data address generation (DAGEN) logic. This allows the repeated instruction to access the values
from the coefficient table sequentially and step through the data in any of the indirect addressing modes.
The MACD instruction, when repeated, supports filter constructs (weighted running averages) so that as the
sum-of-products is executed, the sample data is shifted in memory to make room for the next sample and to
throw away the oldest sample.

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multiplier (continued)
The MPYU instruction performs an unsigned multiplication, which greatly facilitates extended-precision
arithmetic operations. The unsigned contents of TREG are multiplied by the unsigned contents of the addressed
data memory location, with the result placed in PREG. This process allows the operands of greater than 16 bits
to be broken down into 16-bit words and processed separately to generate products of greater than 32 bits. The
SQRA (square / add) and SQRS (square/subtract) instructions pass the same value to both inputs of the
multiplier for squaring a data memory value.
After the multiplication of two 16-bit numbers, the 32-bit product is loaded into the 32-bit product register
(PREG). The product from PREG can be transferred to the CALU or to data memory by way of the SPH (store
product high) and SPL (store product low) instructions. Note: the transfer of PREG to either the CALU or data
bus passes through the PSCALE shifter, and therefore is affected by the product shift mode defined by PM. This
is important when saving PREG in an interrupt-service-routine context save as the PSCALE shift effects cannot
be modeled in the restore operation. PREG can be cleared by executing the MPY #0 instruction. The product
register can be restored by loading the saved low half into TREG and executing a MPY #1 instruction. The high
half, then, is loaded using the LPH instruction.
central arithmetic logic unit
The TMS320Lx2401A central arithmetic logic unit (CALU) implements a wide range of arithmetic and logical
functions, the majority of which execute in a single clock cycle. This ALU is referred to as central to differentiate
it from a second ALU used for indirect-address generation called the auxiliary register arithmetic unit (ARAU).
Once an operation is performed in the CALU, the result is transferred to the accumulator (ACC) where additional
operations, such as shifting, can occur. Data that is input to the CALU can be scaled by ISCALE when coming
from one of the data buses (DRDB or PRDB) or scaled by PSCALE when coming from the multiplier.
The CALU is a general-purpose ALU that operates on 16-bit words taken from data memory or derived from
immediate instructions. In addition to the usual arithmetic instructions, the CALU can perform Boolean
operations, facilitating the bit-manipulation ability required for a high-speed controller. One input to the CALU
is always provided from the accumulator, and the other input can be provided from the product register (PREG)
of the multiplier or the output of the scaling shifter (that has been read from data memory or from the ACC). After
the CALU has performed the arithmetic or logical operation, the result is stored in the accumulator.
The TMS320Lx2401A device supports floating-point operations for applications requiring a large dynamic
range. The NORM (normalization) instruction is used to normalize fixed-point numbers contained in the
accumulator by performing left shifts. The four bits of the TREG define a variable shift through the scaling shifter
for the LACT/ADDT/SUBT (load/add to/subtract from accumulator with shift specified by TREG) instructions.
These instructions are useful in floating-point arithmetic where a number must be denormalized — that is,
floating-point to fixed-point conversion. They are also useful in the execution of an automatic gain control (AGC)
going into a filter. The BITT (bit test) instruction provides testing of a single bit of a word in data memory based
on the value contained in the four LSBs of TREG.
The CALU overflow saturation mode can be enabled/disabled by setting/resetting the OVM bit of ST0. When
the CALU is in the overflow saturation mode and an overflow occurs, the overflow flag is set and the accumulator
is loaded with either the most positive or the most negative value representable in the accumulator, depending
on the direction of the overflow. The value of the accumulator at saturation is 07FFFFFFFh (positive) or
080000000h (negative). If the OVM (overflow mode) status register bit is reset and an overflow occurs, the
overflowed results are loaded into the accumulator with modification. (Note that logical operations cannot result
in overflow.)
The CALU can execute a variety of branch instructions that depend on the status of the CALU and the
accumulator. These instructions can be executed conditionally based on any meaningful combination of these
status bits. For overflow management, these conditions include OV (branch on overflow) and EQ (branch on
accumulator equal to zero). In addition, the BACC (branch to address in accumulator) instruction provides the
ability to branch to an address specified by the accumulator (computed goto). Bit test instructions (BIT and
BITT), which do not affect the accumulator, allow the testing of a specified bit of a word in data memory.

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central arithmetic logic unit (continued)

The CALU also has an associated carry bit that is set or reset depending on various operations within the device.
The carry bit allows more efficient computation of extended-precision products and additions or subtractions.
It is also useful in overflow management. The carry bit is affected by most arithmetic instructions as well as the
single-bit shift and rotate instructions. It is not affected by loading the accumulator, logical operations, or other
such non-arithmetic or control instructions.
The ADDC (add to accumulator with carry) and SUBB (subtract from accumulator with borrow) instructions use
the previous value of carry in their addition/subtraction operation.
The one exception to the operation of the carry bit is in the use of ADD with a shift count of 16 (add to high
accumulator) and SUB with a shift count of 16 (subtract from high accumulator) instructions. This case of the
ADD instruction can set the carry bit only if a carry is generated, and this case of the SUB instruction can reset
the carry bit only if a borrow is generated; otherwise, neither instruction affects it.
Two conditional operands, C and NC, are provided for branching, calling, returning, and conditionally executing,
based upon the status of the carry bit. The SETC, CLRC, and LST #1 instructions also can be used to load the
carry bit. The carry bit is set to one on a hardware reset.
accumulator
The 32-bit accumulator is the registered output of the CALU. It can be split into two 16-bit segments for storage
in data memory. Shifters at the output of the accumulator provide a left shift of 0 to 7 places. This shift is
performed while the data is being transferred to the data bus for storage. The contents of the accumulator
remain unchanged. When the postscaling shifter is used on the high word of the accumulator (bits 16−31), the
MSBs are lost and the LSBs are filled with bits shifted in from the low word (bits 0−15). When the postscaling
shifter is used on the low word, the LSBs are zero-filled.
The SFL and SFR (in-place one-bit shift to the left / right) instructions and the ROL and ROR (rotate to the
left/right) instructions implement shifting or rotating of the contents of the accumulator through the carry bit. The
SXM bit affects the definition of the SFR (shift accumulator right) instruction. When SXM = 1, SFR performs an
arithmetic right shift, maintaining the sign of the accumulator data. When SXM = 0, SFR performs a logical shift,
shifting out the LSBs and shifting in a zero for the MSB. The SFL (shift accumulator left) instruction is not affected
by the SXM bit and behaves the same in both cases, shifting out the MSB and shifting in a zero. Repeat (RPT)
instructions can be used with the shift and rotate instructions for multiple-bit shifts.
auxiliary registers and auxiliary-register arithmetic unit (ARAU)
The 2401A provides a register file containing eight auxiliary registers (AR0 −AR7). The auxiliary registers are
used for indirect addressing of the data memory or for temporary data storage. Indirect auxiliary-register
addressing allows placement of the data memory address of an instruction operand into one of the auxiliary
registers. These registers are referenced with a 3-bit auxiliary register pointer (ARP) that is loaded with a value
from 0 through 7, designating AR0 through AR7, respectively. The auxiliary registers and the ARP can be loaded
from data memory, the ACC, the product register, or by an immediate operand defined in the instruction. The
contents of these registers also can be stored in data memory or used as inputs to the CALU.
The auxiliary register file (AR0−AR7) is connected to the ARAU. The ARAU can autoindex the current auxiliary
register while the data memory location is being addressed. Indexing either by ±1 or by the contents of the AR0
register can be performed. As a result, accessing tables of information does not require the CALU for address
manipulation; therefore, the CALU is free for other operations in parallel.

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internal memory
The TMS320Lx2401A device is configured with the following memory modules:
D Dual-access random-access memory (DARAM)
D Single-access random-access memory (SARAM)
D ROM (LC2401A)
D Flash (LF2401A)
D Boot ROM
dual-access RAM (DARAM)
There are 544 words × 16 bits of DARAM on the 2401A device. The 2401A DARAM allows writes to and reads
from the RAM in the same cycle. The DARAM is configured in three blocks: block 0 (B0), block 1 (B1), and
block 2 (B2). Block 1 contains 256 words and Block 2 contains 32 words, and both blocks are located only in
data memory space. Block 0 contains 256 words, and can be configured to reside in either data or program
memory space. The SETC CNF (configure B0 as program memory) and CLRC CNF (configure B0 as data
memory) instructions allow dynamic configuration of the memory maps through software.
When using on-chip RAM, the 2401A runs at full speed with no wait states. The ability of the DARAM to allow
two accesses to be performed in one cycle, coupled with the parallel nature of the 2401A architecture, enables
the device to perform three concurrent memory accesses in any given machine cycle.
single-access RAM (SARAM)
There are 512 words × 16 bits of SARAM on the Lx2401A. The PON and DON bits select SARAM (512 words)
mapping in program space, data space, or both. See Table 16 for details on the SCSR2 register and the PON
and DON bits. At reset, these bits are 11, and the on-chip SARAM is mapped in both the program and data
spaces.
ROM (LC2401A)
There are 8K words × 16 bits of ROM on the LC2401A.
Flash EEPROM (LF2401A)
Flash EEPROM provides an attractive alternative to masked program ROM. Like ROM, Flash is nonvolatile.
However, it has the advantage of “in-target” reprogrammability. The LF2401A incorporates one 8K  16-bit
Flash EEPROM module in program space. The Flash module has two sectors that can be individually protected
while erasing or programming. The sector size is partitioned as 4K/4K sectors.
Unlike most discrete Flash memory, the LF2401A Flash does not require a dedicated state machine, because
the algorithms for programming and erasing the Flash are executed by the DSP core. This enables several
advantages, including: reduced chip size and sophisticated, adaptive algorithms. For production programming,
the IEEE Standard 1149.1† (JTAG) scan port provides easy access to the on-chip RAM for downloading the
algorithms and Flash code. This Flash requires 5 V for programming (at VCCP pin only) the array. The Flash runs
at zero wait state while the device is powered at 3.3 V.

† IEEE Standard 1149.1−1990, IEEE Standard Test Access Port.

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boot ROM†
Boot ROM is a 256-word ROM mapped in program space 0000h−00FFh. This ROM will be enabled if the
BOOT_EN mode is enabled during reset. Boot-enable function is implemented using combinational logic of the
TDI, TRST, and RS pins as described below. The on-chip bootloader is invoked when:
TRST = 0
RS = 0
TDI = 0

(In addition to the three pins mentioned above, the application must ensure that PDPINTA stays high during the
execution of the boot ROM code.) Since it has an internal pulldown, the TRST pin will be low, provided the JTAG
connector is not connected. Therefore, the BOOT_EN bit (bit 3 of the SCSR2 register) will be set to 0 if TDI is
low upon reset. If on-chip bootloader is desired while debugging with the JTAG connector connected
(TRST = 1), it can be achieved by writing a “0” into bit 3 of the SCSR2 register.
The boot ROM has a generic bootloader to transfer code through the SCI port. The incoming code should
disable the BOOT_ROM bit by writing 1 to bit 3 of the SCSR2 register, or else, the whole Flash array will not
be enabled.
The boot ROM code sets the PLL to x2 or x4 option based on the condition of the SCITXD pin during reset. The
SCITXD pin should be pulled high/low to select the PLL multiplication factor. The choices made are as follows:
D If the SCITXD pin is pulled low, the PLL multiplier is set to 2.
D If the SCITXD pin is pulled high, the PLL multiplier is set to 4. (Default)
D If the SCITXD pin is not driven at reset, the internal pullup selects the default multiplier of 4.
Care should be taken such that a combination of CLKIN and the PLL multiplication factor does not result in a
CPU clock speed of greater than 40 MHz, the maximum rated speed. For restrictions concerning the maximum
frequency of CLKIN, see the latest revision of the TMS320LF2401A DSP Controller Silicon Errata (literature
number SPRZ013).
Furthermore, when the bootloader is used, only specific values of CLKIN would result in a baud-lock for the SCI.
Refer to the TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature
number SPRU357) for more details about the bootloader operation.

† The boot ROM on LC2401A is used for test purposes.

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Flash/ROM security
The 2401A device has a security feature that prevents external access to Flash/ROM memory. This feature is
useful in preventing unauthorized duplication of proprietary code resident on the Flash/ROM memory.
If access to Flash/ROM contents are desired for debugging purposes, two actions need to be taken:
1. A “dummy” read of locations 40h, 41h, 42h and 43h (of program memory space) is necessary. The word
“dummy” indicates that the destination address of this read is not relevant. If 40h−43h contain all zeros or
ones, then Step 2 is not required.
2. A 64-bit password (split as four 16-bit words) must be written to the data-memory locations 77F0h, 77F1h,
77F2h, and 77F3h. The four 16-bit words written to these locations must match the four words stored in 40h,
41h, 42h, and 43h (of program memory space), respectively. The device becomes “unsecured” one cycle
after the last instruction that unsecures the part.

Code Security Module Disclaimer

The Code Security Module (“CSM”) included on this device was designed to password
protect the data stored in the associated memory (either ROM or Flash) and is warranted
by Texas Instruments (TI), in accordance with its standard terms and conditions, to
conform to TI’s published specifications for the warranty period applicable for this device.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE
ASSOCIATED MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS.
MOREOVER, EXCEPT AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR
REPRESENTATIONS CONCERNING THE CSM OR OPERATION OF THIS DEVICE,
INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR
A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL,
INDIRECT, INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING
IN ANY WAY OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT
TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED
DAMAGES INCLUDE, BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF
GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER
ECONOMIC LOSS.

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PERIPHERALS
The integrated peripherals of the TMS320Lx2401A are described in the following subsections:
D Event-manager module (EVA)
D Enhanced analog-to-digital converter (ADC) module
D Serial communications interface (SCI) module
D PLL-based clock module
D Digital I/O and shared pin functions
D Watchdog (WD) timer module

event manager module (EVA)

The event-manager module includes general-purpose (GP) timers, full-compare/PWM units, and a capture unit.
Table 7 shows the module and signal names used. Table 7 also shows the features and functionality available
for the event-manager module.
The EVA peripheral register set starts at 7400h. The paragraphs in this section describe the function of the GP
timers, the compare units, and the capture unit.

Table 7. Module and Signal Names for EVA

EVENT MANAGER MODULES MODULE SIGNAL
Timer 1 —
GP Timers
Timer 2 T2PWM/T2CMP
Compare 1 PWM1/2
Compare Units Compare 2 PWM3/4
Compare 3 PWM5/6
Capture Unit Capture 1 CAP1

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event manager module (EVA) (continued)

2401A DSP Core

Data Bus ADDR Bus Reset INT2,3,4 Clock

16 3
16
16
EV Control Registers ADC Start of
and Control Logic Conversion

16 GP Timer 1
Compare

16 CLKOUT
GP Timer 1 Prescaler
(Internal)

T1CON[8,9,10]
16

SVPWM PWM1
16 Full-Compare 3 State 3 Deadband 3 Output
Units Machine Units Logic
PWM6

16 GP Timer 2 Output
Compare Logic T2PWM

16
GP Timer 2 Prescaler CLKOUT
(Internal)

T2CON[8,9,10]
16

16

MUX

16
Capture Unit CAP1
16

Figure 14. Event Manager A Block Diagram

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general-purpose (GP) timers

There are two GP timers. GP timer x (x = 1 or 2) includes:
D A 16-bit timer, up-/down-counter, TxCNT, for reads or writes
D A 16-bit timer-compare register, TxCMPR (double-buffered with shadow register), for reads or writes
D A 16-bit timer-period register, TxPR (double-buffered with shadow register), for reads or writes
D A 16-bit timer-control register,TxCON, for reads or writes
D Internal input clock
D A programmable prescaler for internal clock input
D Control and interrupt logic, for four maskable interrupts: underflow, overflow, timer compare, and period
interrupts
The GP timers can be operated independently or synchronized with each other. The compare register
associated with GP timer 2 can be used for compare function and PWM-waveform generation. There are three
continuous modes of operations for each GP timer in up- or up / down-counting operations. An internal input
clock with programmable prescaler is used for each GP timer. GP timers also provide the time base for the other
event-manager submodules: GP timer 1 for all the compares and PWM circuits, and GP timer 2/1 for the capture
unit. Double-buffering of the period and compare registers allows programmable change of the timer (PWM)
period and the compare/PWM pulse width as needed.
full-compare units
There are three full-compare units on the event manager (EVA). These compare units use GP timer1 as the
time base and generate six outputs for compare and PWM-waveform generation using programmable
deadband circuit. The state of each of the six outputs is configured independently. The compare registers of
the compare units are double-buffered, allowing programmable change of the compare/PWM pulse widths as
needed.
programmable deadband generator
The deadband generator circuit includes three 8-bit counters and an 8-bit compare register. Desired deadband
values (from 0 to 16 µs) can be programmed into the compare register for the outputs of the three compare units.
The deadband generation can be enabled/disabled for each compare unit output individually. The
deadband-generator circuit produces two outputs (with or without deadband zone) for each compare unit output
signal. The output states of the deadband generator are configurable and changeable as needed by way of the
double-buffered ACTR register.
PWM waveform generation
Up to eight PWM waveforms (outputs) can be generated simultaneously by EVA: three independent pairs (six
outputs) by the three full-compare units with programmable deadbands, and two independent PWMs by the
GP-timer compares.

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PWM characteristics
Characteristics of the PWMs are as follows:
D 16-bit registers
D Programmable deadband for the PWM output pairs, from 0 to 12 µs
D Minimum deadband width of 25 ns
D Change of the PWM carrier frequency for PWM frequency wobbling as needed
D Change of the PWM pulse widths within and after each PWM period as needed
D External-maskable power and drive-protection interrupts
D Pulse-pattern-generator circuit, for programmable generation of asymmetric, symmetric, and four-space
vector PWM waveforms
D Minimized CPU overhead using auto-reload of the compare and period registers
D The PWM pins are driven to a high-impedance state when the PDPINTA pin is driven low and after
PDPINTA signal qualification. The status of the PDPINTA pin (after qualification) is reflected in bit 8 of the
COMCONA register.
capture unit
The capture unit provides a logging function for different events or transitions. The values of the selected GP
timer counter is captured and stored in the two-level-deep FIFO stack when selected transitions are detected
on the capture input pin, CAP1. The capture unit consists of three capture circuits.
The capture unit includes the following features:
D One 16-bit capture control register, CAPCONA (R/W)
D One 16-bit capture FIFO status register, CAPFIFOA
D Selection of GP timer 1/2 as the time base
D One 16-bit 2-level-deep FIFO stack
D One capture input pin (CAP1). [The input is synchronized with the device (CPU) clock. In order for a
transition to be captured, the input must hold at its current level to meet two rising edges of the device clock.]
D User-specified transition (rising edge, falling edge, or both edges) detection
D One maskable interrupt flag
input qualifier circuitry
An input-qualifier circuitry qualifies the input signal to the CAP1, XINT1/2, ADCSOC, and PDPINTA pins in the
2401A device. (The I/O functions of these pins do not use the input-qualifier circuitry). The state of the internal
input signal will change only after the pin is high/low for 6(12) clock edges. This ensures that a glitch smaller
than 5(11) CLKOUT cycles wide will not change the internal pin input state. The user must hold the pin high/low
for 6(12) cycles to ensure the device will see the level change. Bit 6 of the SCSR2 register controls whether
6 clock edges (bit 6 = 0) or 12 clock edges (bit 6 = 1) are used to block 5- or 11-cycle glitches.

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enhanced analog-to-digital converter (ADC) module

A simplified functional block diagram of the ADC module is shown in Figure 15. The ADC module consists of
a 10-bit ADC with a built-in sample-and-hold (S / H) circuit. Functions of the ADC module include:
D 10-bit ADC core with built-in S/H
D Fast conversion time (S/H + Conversion) of 500 ns
D 5-channel, MUXed inputs
D Autosequencing capability provides up to 16 “autoconversions” in a single session. Each conversion can
be programmed to select any 1 of 5 input channels
D Sequencer can be operated as two independent 8-state sequencers or as one large 16-state sequencer
(i.e., two cascaded 8-state sequencers)
D Sixteen result registers (individually addressable) to store conversion values
− The digital value of the input analog voltage is derived by:
Input Analog Voltage * V REFLO
Digital Value + 1023
V REFHI * V REFLO

NOTE: VREFLO is internally tied to VSSA ; VREFHI is internally tied to VCCA .

D Multiple triggers as sources for the start-of-conversion (SOC) sequence
− S/W − software immediate start
− EVA − Event manager A (multiple event sources within EVA)
− Ext − External pin (ADCSOC)
D Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS
D Sequencer can operate in “start/stop” mode, allowing multiple “time-sequenced triggers” to synchronize
conversions
D EVA triggers can operate independently in dual-sequencer mode
D Sample-and-hold (S/H) acquisition time window has separate prescale control
NOTE: The 2401A ADC module is identical to the LF2407A ADC module. However, only channels ADCIN00
through ADCIN04 are bonded out of the device. For this reason, the valid values for the CONVnn bit fields in
the CHSELSEQn registers are from 0 to 4. Attempting to convert channels 5 through 15 would yield
indeterminate results.

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enhanced analog-to-digital converter (ADC) module (continued)

The ADC module in the 2401A has been enhanced to provide flexible interface to the event manager (EVA).
The ADC interface is built around a fast, 10-bit ADC module with total conversion time of 500 ns (S/H +
conversion). The ADC module has 5 channels to service EVA. Although there are multiple input channels and
two sequencers, there is only one converter in the ADC module. Figure 15 shows the block diagram of the
2401A ADC module.

Analog MUX Result Registers

Result Reg 0 70A8h

ADCIN00
Result Reg 1

ADCIN01
10-Bit
ADC Result Reg 7 70AFh
ADCIN02 Module Result Reg 8 70B0h
(500 ns)
ADCIN03

ADCIN04
Result Reg 15 70B7h

ADC Control Registers

S/W
EVA SOC Sequencer 1 Sequencer 2 SOC S/W
ADCSOC

Figure 15. Block Diagram of the 2401A ADC Module

To obtain the specified accuracy of the ADC, proper board layout is very critical. To the best extent possible,
traces leading to the ADCINn pins should not run in close proximity to the digital signal paths. This is to minimize
switching noise on the digital lines from getting coupled to the ADC inputs. Furthermore, proper isolation
techniques must be used to isolate the ADC module power pins (such as VCCA and VSSA) from the digital supply.
Unused ADC inputs should be connected to analog ground for improved accuracy and ESD protection.

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serial communications interface (SCI) module

The 2401A device includes a serial communications interface (SCI) module. The SCI module supports digital
communications between the CPU and other asynchronous peripherals that use the standard
non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own
separate enable and interrupt bits. Both can be operated independently or simultaneously in the full-duplex
mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun, and framing
errors. The bit rate is programmable to over 65 000 different speeds through a 16-bit baud-select register.
Features of the SCI module include:
D Two external pins:
− SCITXD: SCI transmit-output pin
− SCIRXD: SCI receive-input pin
NOTE: Both pins can be used as GPIO if not used for SCI.

D Baud rate programmable to 64K different rates

− Up to 2500 Kbps at 40-MHz CPUCLK†
D Data-word format
− One start bit
− Data-word length programmable from one to eight bits
− Optional even/odd/no parity bit
− One or two stop bits
D Four error-detection flags: parity, overrun, framing, and break detection
D Two wake-up multiprocessor modes: idle-line and address bit
D Half- or full-duplex operation
D Double-buffered receive and transmit functions
D Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with
status flags.
− Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and
TX EMPTY flag (transmitter-shift register is empty)
− Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag
(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
D Separate enable bits for transmitter and receiver interrupts (except BRKDT)
D NRZ (non-return-to-zero) format
D Ten SCI module control registers located in the control register frame beginning at address 7050h
NOTE: All registers in this module are 8-bit registers that are connected to the 16-bit peripheral bus. When a register is accessed, the
register data is in the lower byte (7 −0), and the upper byte (15 −8) is read as zeros. Writing to the upper byte has no effect.

Figure 16 shows the SCI module block diagram.

† SCI speed will be limited by the I/O buffer speed and external transceiver performance.

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serial communications interface (SCI) module (continued)

SCI TX Interrupt
TXWAKE SCITXBUF.7−0
TXRDY TX INT ENA
Frame Format and Mode SCICTL1.3 Transmitter-Data TXINT
SCICTL2.7 External
Buffer Register Connections
1 SCICTL2.0
Parity TX EMPTY
Even/Odd Enable 8
SCICTL2.6
SCICCR.6 SCICCR.5 WUT
TXSHF TXENA
SCITXD
Register SCITXD
SCICTL1.1
SCIHBAUD. 15 −8
SCI Priority Level
Baud Rate 1
MSbyte Level 5 Int.
Register 0
Internal Level 1 Int.
Clock SCI TX
SCILBAUD. 7 −0 Priority

Baud Rate SCIPRI.6

LSbyte 1
Register Level 5 Int.
0
Level 1 Int.
SCI RX
Priority
SCIPRI.5

RXSHF SCIRXD
Register SCIRXD
RXWAKE
SCIRXST.1

RX ERR INT ENA RXENA

SCICTL1.6 SCICTL1.0
8 SCI RX Interrupt
RXRDY RX/BK INT ENA
Receiver-Data
SCIRXST.6
Buffer
RXINT

RX Error Register
BRKDT SCICTL2.1

SCIRXST.7 SCIRXST.4 −2 SCIRXBUF.7−0 SCIRXST.5

RX Error FE OE PE

Figure 16. Serial Communications Interface (SCI) Module Block Diagram

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PLL-based clock module

The 2401A has an on-chip, PLL-based clock module. This module provides all the necessary clocking signals
for the device, as well as control for low-power mode entry. The PLL has a 3-bit ratio control to select different
CPU clock rates. See Figure 17 for the PLL Clock Module Block Diagram and Table 8 for clock rates.
The PLL-based clock module provides two modes of operation:
D Crystal-operation
This mode allows the use of an external crystal/resonator to provide the time base to the device.
D External clock source operation
This mode allows the internal oscillator to be bypassed. The device clocks are generated from an external
clock source input on the XTAL1/CLKIN pin. In this case, an external oscillator clock is connected to the
XTAL1/CLKIN pin.

XTAL1/CLKIN
Fin
Cb1 PLL CLKOUT

RESONATOR/ XTAL
CRYSTAL OSC

3-bit
PLL Select
XTAL2 (SCSR1.[11:9])
Cb2

Figure 17. PLL Clock Module Block Diagram

Table 8. PLL Clock Selection Through Bits (11−9) in SCSR1 Register

CLK PS2 CLK PS1 CLK PS0 CLKOUT
0 0 0 4 × Fin
0 0 1 2 × Fin
0 1 0 1.33 × Fin
0 1 1 1 × Fin
1 0 0 0.8 × Fin
1 0 1 0.66 × Fin
1 1 0 0.57 × Fin
1 1 1 0.5 × Fin

Default multiplication factor after reset is (1,1,1), i.e., 0.5 × Fin.

CAUTION:
The bootloader sets the PLL to x2 or x4 option. If the bootloader is used, the value of CLKIN
used should not force CLKOUT to exceed the maximum rated device speed. See the “Boot
ROM” section for more details.

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external reference crystal clock option

The internal oscillator is enabled by connecting a crystal across the XTAL1/CLKIN and XTAL2 pins as shown
in Figure 18a. The crystal should be in fundamental operation and parallel resonant, with an effective series
resistance of 30 Ω−150 Ω and draws no more than 1 mW; it should be specified at a load capacitance of 20 pF.
To ensure reliable starting of the internal oscillator upon power up, a 1-M Ω resistor in parallel with the crystal
(across the XTAL1 and XTAL2 pins) is recommended. See the TMS320LF2401A, TMS320LC2401A DSP
Controller Silicon Errata (literature number SPRZ013) for more details.

external reference oscillator clock option

The internal oscillator is disabled by connecting a clock signal to XTAL1/CLKIN and leaving the XTAL2 input
pin unconnected as shown in Figure 18b.

XTAL1/CLKIN XTAL2 XTAL1/CLKIN XTAL2

Cb1 Cb2 External Clock Signal

(see Note A) Crystal (see Note A) (Toggling 0 −3.3 V) NC
(a) (b)

NOTE A: TI recommends that customers have the resonator/crystal vendor characterize the operation of their device with the DSP chip. The
resonator/crystal vendor has the equipment and expertise to tune the tank circuit. The vendor can also advise the customer regarding
the proper tank component values that will ensure start-up and stability over the entire operating range.

Figure 18. Recommended Crystal / Clock Connection

low-power modes
The 2401A has an IDLE instruction. When executed, the IDLE instruction stops the clocks to all circuits in the
CPU, but the clock output from the CPU continues to run. With this instruction, the CPU clocks can be shut down
to save power while the peripherals (clocked with CLKOUT) continue to run. The CPU exits the IDLE state if
it is reset, or, if it receives an interrupt request.

clock domains
All 2401A-based devices have two clock domains:
1. CPU clock domain − consists of the clock for most of the CPU logic
2. System clock domain − consists of the peripheral clock (which is derived from CLKOUT of the CPU) and
the clock for the interrupt logic in the CPU.
When the CPU goes into IDLE mode, the CPU clock domain is stopped while the system clock domain continues
to run. This mode is also known as IDLE1 mode. The 2401A CPU also contains support for a second IDLE mode,
IDLE2. By asserting IDLE2 to the 2401A CPU, both the CPU clock domain and the system clock domain are
stopped, allowing further power savings. A third low-power mode, HALT mode, the deepest, is possible if the
oscillator and WDCLK are also shut down when in IDLE2 mode.
Two control bits, LPM1 and LPM0, specify which of the three possible low-power modes is entered when the
IDLE instruction is executed (see Table 9). These bits are located in the System Control and Status
Register 1 (SCSR1), and they are described in the TMS320LF/LC240xA DSP Controllers Reference Guide:
System and Peripherals (literature number SPRU357).

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clock domains (continued)

Table 9. Low-Power Modes Summary
LPMx BITS CPU SYSTEM
WDCLK PLL OSC FLASH EXIT
LOW-POWER MODE SCSR1 CLOCK CLOCK
STATUS STATUS STATUS POWER CONDITION
[13:12] DOMAIN DOMAIN
CPU running normally XX On On On On On On —

Peripheral
Interrupt,
IDLE1 − (LPM0) 00 Off On On On On On External Interrupt,
Reset,
PDPINTA

Wakeup
Interrupts,
IDLE2 − (LPM1) 01 Off Off On On On On External Interrupt,
Reset,
PDPINTA

HALT − (LPM2) Reset,

1X Off Off Off Off Off Off†
[PLL/OSC power down] PDPINTA

† The Flash must be powered down by the user code prior to entering LPM2. For more details, see the TMS320LF/LC240xA DSP Controllers
Reference Guide: System and Peripherals (literature number SPRU357).

other power-down options

2401A devices have clock-enable bits to the following on-chip peripherals: ADC, SCI, and EVA. Clock to these
peripherals are disabled after reset; thus, start-up power can be low for the device.
Depending on the application, these peripherals can be turned on/off to achieve low power.
Refer to the SCSR1 register for details on the peripheral clock enable bits.

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digital I/O and shared pin functions

The 2401A has up to 13 general-purpose, bidirectional, digital I/O (GPIO) pins—most of which are shared
between primary functions and I/O. Most I/O pins of the 2401A are shared with other functions. The digital I/O
ports module provides a flexible method for controlling both dedicated I/O and shared pin functions. All I/O and
shared pin functions are controlled using eight 16-bit registers. These registers are divided into two types:
D Output Control Registers — used to control the multiplexer selection that chooses between the primary
function of a pin or the general-purpose I/O function.
D Data and Control Registers — used to control the data and data direction of bidirectional I/O pins.
description of shared I/O pins
Each shared I/O pin has three bits that define its operation:
D MUX control bit — this bit selects between the primary function (1) and I/O function (0) of the pin.
D I/O direction bit — if the I/O function is selected for the pin (MUX control bit is set to 0), this bit determines
whether the pin is an input (0) or an output (1).
D I/O data bit — if the I/O function is selected for the pin (MUX control bit is set to 0) and the direction selected
is an input, data is read from this bit; if the direction selected is an output, data is written to this bit.
The MUX control bit, I/O direction bit, and I/O data bit are in the I/O control registers.
A summary of shared pin configurations and associated bits is shown in Table 10.
Table 10. Shared Pin Configurations
PIN FUNCTION SELECTED MUX MUX CONTROL I/O PORT DATA AND DIRECTION†
(MCRA.n = 0) CONTROL VALUE AT
(MCRA.n = 1)
Secondary REGISTER RESET REGISTER DATA BIT NO.‡ DIR BIT NO.§
Primary Function (name.bit #) (MCRx.n)
Function
PORT A
PDPINTA IOPA0¶ MCRA.0 0 PADATDIR 0 8
PWM1 IOPA1 MCRA.1 0 PADATDIR 1 9
PWM2 IOPA2 MCRA.2 0 PADATDIR 2 10
PWM3 IOPA3 MCRA.3 0 PADATDIR 3 11
PWM4 IOPA4 MCRA.4 0 PADATDIR 4 12
PWM5 IOPA5 MCRA.5 0 PADATDIR 5 13
PWM6 IOPA6 MCRA.6 0 PADATDIR 6 14
XINT2/ADCSOC/
CLKOUT MCRA.7 0 PADATDIR 7 15
CAP1/IOPA7
PORT B
T2PWM XINT1/IOPB0 MCRA.8 0 PBDATDIR 0 8
IOPB1 IOPB1 MCRA.9 0 PBDATDIR 1 9
IOPB2 IOPB2 MCRA.10 0 PBDATDIR 2 10
SCITXD IOPB3 MCRA.11 0 PBDATDIR 3 11
SCIRXD IOPB4 MCRA.12 0 PBDATDIR 4 12
OPB5 OPB5 MCRA.13 0 PBDATDIR 5 13
− MCRA.14 0 PBDATDIR 6 14
− MCRA.15 0 PBDATDIR 7 15
† Valid only if the I/O function is selected on the pin
‡ If the GPIO pin is configured as an output, these bits can be written to. If the pin is configured as an input, these bits are read from.
§ If the DIR bit is 0, the GPIO pin functions as an input. For a value of 1, the pin is configured as an output.
¶ Even when MCRA.0 = 0, the PDPINT circuitry is still active.

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digital I/O control registers

Table 11 lists the registers available in the digital I/O module. As with other 2401A peripherals, these registers
are memory-mapped to the data space.

Table 11. Addresses of Digital I/O Control Registers

ADDRESS REGISTER NAME
7090h MCRA I/O MUX control register A
7098h PADATDIR I/O port A data and direction register
709Ah PBDATDIR I/O port B data and direction register

CAUTION:
The bit definitions of the MCRA, PADATDIR, and PBDATDIR registers are not compatible
with those of other 24x/240x/240xA devices.

watchdog (WD) timer module

The 2401A device includes a watchdog (WD) timer module. The WD function of this module monitors software
and hardware operation by generating a system reset if it is not periodically serviced by software by having the
correct key written. The WD timer operates independently of the CPU. It does not need any CPU initialization
to function. When a system reset occurs, the WD timer defaults to the fastest WD timer rate available (WDCLK
signal = CLKOUT/512). As soon as reset is released internally, the CPU starts executing code, and the WD timer
begins incrementing. This means that, to avoid a premature reset, WD setup should occur early in the power-up
sequence. See Figure 19 for a block diagram of the WD module. The WD module features include the following:
D WD Timer
− Seven different WD overflow rates
− A WD-reset key (WDKEY) register that clears the WD counter when a correct value is written, and
generates a system reset if an incorrect value is written to the register
− WD check bits that initiate a system reset if an incorrect value is written to the WD control register
(WDCR)
D Automatic activation of the WD timer, once system reset is released
− Three WD control registers located in control register frame beginning at address 7020h.
NOTE: All registers in this module are 8-bit registers. When a register is accessed, the register data is in the lower byte, the upper byte
is read as zeros. Writing to the upper byte has no effect.
Table 12 shows the different WD overflow (time-out) selections. Figure 19 shows the WD block diagram.
The watchdog can be disabled in software by writing ‘1’ to bit 6 of the WDCR register (WDCR.6) while bit 5 of
the SCSR2 register (SCSR2.5) is 1. If SCSR2.5 is 0, the watchdog will not be disabled. SCSR2.5 is equivalent
to the WDDIS pin of the TMS320F243/241 devices.

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watchdog (WD) timer module (continued)

Table 12. WD Overflow (Time-out) Selections

WATCHDOG
WD PRESCALE SELECT BITS
WDCLK DIVIDER CLOCK RATE†
WDPS2 WDPS1 WDPS0 FREQUENCY (Hz)
0 0 X‡ 1 WDCLK/1
0 1 0 2 WDCLK/2
0 1 1 4 WDCLK/4
1 0 0 8 WDCLK/8
1 0 1 16 WDCLK/16
1 1 0 32 WDCLK/32
1 1 1 64 WDCLK/64
† WDCLK = CLKOUT/512
‡ X = Don’t care

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watchdog (WD) timer module (continued)

CLKOUT 3-bit CLKIN

÷ 512 PLL
Prescaler
6-Bit
Free- /64
Running /32 On-Chip
Counter /16 Oscillator or
WDCLK External
/8
Clock
System /4
Reset CLR
/2

000
001
010
WDPS 011
WDCR.2 − 100
0 0
2 1 101
110
WDCR.6 111 WDFLAG
WDDIS WDCR.7 Reset Flag
WDCNTR.7 −0
8-Bit Watchdog
Counter One-Cycle Internal
Delay PS/257 Pullup
CLR
RS pin

WDKEY.7 −0 System
Bad Key Reset
Watchdog 55 + AA Request
Reset Key Good Key WDCHK2−0
Detector
Register
WDCR.5 −3†
Bad WDCR Key
3
3
System
Reset 1 0 1
(Constant
Value)
† Writing to bits WDCR.5 −3 with anything but the correct pattern (101) generates a system reset.

Figure 19. Block Diagram of the WD Module

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development support
Texas Instruments (TI) offers an extensive line of development tools for the 240x generation of DSPs, including
tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and
fully integrate and debug software and hardware modules.
The following products support development of 240x-based applications:
Software Development Tools:
Assembler/linker
Simulator
Optimizing ANSI C compiler
Application algorithms
C/Assembly debugger and code profiler
Hardware Development Tools:
Emulator XDS510 (supports x24x multiprocessor system debug)
TMS320LF2407 EVM (Evaluation module for 2407 DSP)
See Table 13 and Table 14 for complete listings of development support tools for the 240x. For information on
pricing and availability, contact the nearest TI field sales office or authorized distributor.
Table 13. Development Support Tools
DEVELOPMENT TOOL PLATFORM PART NUMBER
Software
Code Composer Studio v.2.2 PC TMDSCCS2000-1
Hardware − Emulation Debug Tools
XDS510PP Pod (Parallel Port) with JTAG cable PC TMDS3P701014

Table 14. TMS320x24x-Specific Development Tools

DEVELOPMENT TOOL PLATFORM PART NUMBER
Hardware − Evaluation/Starter Kits
2401A eZdsp PC TMDSeZD2401
F2407A EVM PC TMDS3P701016A

XDS510, Code Composer Studio, and XDS510PP are trademarks of Texas Instruments.
PC is a trademark of International Business Machines Corp.

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device and development support tool nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320 DSP devices and support tools. Each TMS320 DSP commercial family member has one of three
prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from
engineering prototypes (TMX / TMDX) through fully qualified production devices/tools (TMS / TMDS).

Device development evolutionary flow:

TMX Experimental device that is not necessarily representative of the final device’s electrical specifications
TMP Final silicon die that conforms to the device’s electrical specifications but has not completed quality
and reliability verification
TMS Fully qualified production device

Support tool development evolutionary flow:

TMDX Development-support product that has not yet completed Texas Instruments internal qualification
testing.
TMDS Fully qualified development-support product

TMX and TMP devices and TMDX development-support tools are shipped with appropriate disclaimers
describing their limitations and intended uses. Experimental devices (TMX) may not be representative of a
final product and Texas Instruments reserves the right to change or discontinue these products without notice.

TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI’s standard warranty applies.

Predictions show that prototype devices ( TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.

TMS320 is a trademark of Texas Instruments.

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device and development support tool nomenclature (continued)

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, VF) and temperature range (for example, A). Figure 20 provides a legend for reading the complete
TMS320Lx2401A device name.

TMS 320 LF 2401A VF A

PREFIX
TMX = experimental device TEMPERATURE RANGE
TMP = prototype device A = −40°C to 85°C
TMS = qualified device S = −40°C to 125°C

DEVICE FAMILY PACKAGE TYPE†

320 = TMS320 DSP Family VF = 32-pin LQFP

DEVICE
TECHNOLOGY 2401A
LC = Low-voltage CMOS (3.3 V)
LF = Flash EEPROM (3.3 V)

† LQFP = Low-Profile Quad Flatpack

Figure 20. TMS320Lx2401A Device Nomenclature

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documentation support
Extensive documentation supports all of the TMS320 DSP family generations of devices from product
announcement through applications development. The types of documentation available include: data sheets,
such as this document, with design specifications; complete user’s guides for all devices and development
support tools; and hardware and software applications. Useful reference documentation includes:
D Silicon Errata
− TMS320LF2401A, TMS320LC2401A DSP Controller Silicon Errata (literature number SPRZ013)
describes the known advisories of various revisions of the silicon.
D User’s Guides
− TMS320F/C24x DSP Controllers Reference Guide: CPU and Instruction Set (literature number
SPRU160) describes the TMS320C24x 16−bit fixed−point digital signal processor controller. Covered
are its architecture, internal register structure, data and program addressing, and instruction set. Also
includes instruction set comparisons and design considerations for using the XDS510 emulator.
− TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number
SPRU357). This reference guide describes the architecture, system hardware, peripherals, and
general operation of the TMS320Lx2407A/x2406A/x2404A/x2403A/x2402A/x2401A digital signal
processor (DSP) controllers. This book is also applicable to TMS320Lx2407/2406/2402 and future
derivatives of the 240x family.
D Application Reports
− Getting Started in C and Assembly Code with the TMS320LF240x DSP (literature number SPRA755)
This application report presents basic code for initializing and operating the TMS320LF240x DSP
devices. Two functionally equivalent example programs are presented: one written in assembly
language and the other in C language. Detailed discussions of each program are provided that explain
numerous compiler and assembler directives, code requirements, and hardware-related requirements.
The programs are ready to run on either the TMS320LF2407 Evaluation Module (EVM) or the eZdspo.si
LF2407 development kit. However, they are also intended for use as a code template for any
TMS320LF240x (LF240x) or TMS320LF240xA (LF240xA) DSP target system.
− Motor Speed Measurement Considerations Using TMS320C24x DSPs (literature number SPRA771)
The TMS320C24x generation of DSPs provide appropriate internal hardware for interfacing with
low-cost, external-speed sensors for motor speed measurement applications. The periodic output
signal from the speed sensor is applied to the capture input pin of the DSP and the signal’s period is
measured. This information is then used to calculate the motor speed. However, this calculation of
motor speed depends on several system parameters. These parameters affect the scaling and
normalization factors that must be used in the speed calculation routine for accurate measurements.
This application report, therefore, gives an analysis of the speed measurement system to show the
effect of system parameters on the calculated speed. The choice of appropriate scaling and
normalization factors for a given system is also discussed. Finally, code examples are given to show the
software implementation of the speed calculation routine.
− 3.3 V DSP for Digital Motor Control (literature number SPRA550) describes a scenario of a 3.3-V-only
motor controller indicating that for most applications, no significant issue of interfacing between 3.3 V
and 5 V exists. On-chip 3.3−V analog-to-digital converter (ADC) versus 5-V ADC is also discussed.
Guidelines for component layout and printed circuit board (PCB) design that can reduce system noise
and EMI effects are summarized.
To receive copies of TMS320 DSP literature, contact the Literature Response Center at 800-477-8924.

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A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal
processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is published
quarterly and distributed to update TMS320 DSP customers on product information.
Updated information on the TMS320 DSP controllers can be found on the worldwide web at:
http://www.ti.com.
To send comments regarding the TMS320LF2401A/TMS320LC2401A data sheet (literature number
SPRS161), use the [email protected] email address, which is a repository for feedback. For
questions and support, contact the Product Information Center listed at the
http://www.ti.com/sc/docs/pic/home.htm site.

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LF2401A AND LC2401A ELECTRICAL SPECIFICATIONS DATA

This document contains information on products in more than one phase of development. The electrical
specifications for the TMS320LF2401A device are Production Data (PD) and those for the TMS320LC2401A
device are Product Preview (PP). These electrical specifications are subject to change.

absolute maximum ratings over operating temperature range (unless otherwise noted)†
Supply voltage range, VDD, VDDO, and VCCA (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 4.6 V
VCCP range (LF2401A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 5.5 V
Input voltage range, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 4.6 V
Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 4.6 V
Input clamp current, IIK (VIN < 0 or VIN > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Operating ambient temperature ranges, TA: A version‡ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 40°C to 85°C
S version‡ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 65°C to 150°C
† Clamp current stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡ Long-term high-temperature storage and/or extended use at maximum temperature conditions may result in a reduction of overall device life.
For additional information, see IC Package Thermal Metrics Application Report (literature number SPRA953) and Reliability Data for
TMS320LF24x and TMS320F281x Devices Application Report (literature number SPRA963).
NOTE 1: All voltage values are with respect to VSS.

recommended operating conditions§

MIN NOM MAX UNIT
VDD/VDDO Supply voltage VDDO = VDD ± 0.3 V 3 3.3 3.6 V
VSS Supply ground 0 0 0 V
VCCA¶ ADC supply voltage 3 3.3 3.6 V
VCCP Flash programming supply voltage (LF2401A)# 4.75 5 5.25 V
fCLKOUT Device clock frequency (system clock) 2 40 MHz
VIH High-level input voltage All inputs 2 V
VIL Low-level input voltage All inputs 0.8 V
Output pins Group 1|| −2 mA
IOH High-level output source current, VOH = 2.4 V Output pins Group 2|| −4 mA
Output pins Group 3|| −8 mA
Output pins Group 1|| 2 mA
IOL Low-level output sink current, VOL = VOL MAX Output pins Group 2|| 4 mA
Output pins Group 3|| 8 mA
A version − 40 85 °C
TA Ambient temperature
S version − 40 125 °C
Nf Flash endurance for the array (Write/erase cycles) − 40°C to 85°C 10K cycles
§ See the mechanical data package page for thermal resistance values, ΘJA (junction-to-ambient) and ΘJC (junction-to-case).
¶ VCCA should not exceed VDD by 0.3 V.
# For applications that involve millions of power cycles, it is recommended that VCCP be powered after VDD.
|| Primary signals and their groupings:
Group 1: PDPINTA/IOPA0, T2PWM, PWM1−PWM6 (IOPA1−IOPA6), IOPB0, IOPB1, OPB5, TMS/XF, RS, TCK, TDI
Group 2: SCITXD/IOPB3, SCIRXD/IOPB4, TDO/IOPB2
Group 3: CAP1, IOPA7, CLKOUT

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SPRS161K − MARCH 2001 − REVISED JULY 2007

electrical characteristics over recommended operating temperature range (unless otherwise

noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDD = 3.0 V, IOH = IOHMAX 2.4
VOH High-level output voltage V
All outputs at 50 µA VDDO − 0.2
VOL Low-level output voltage IOL = IOLMAX 0.4 V
With pullup −10 −16 −30
IIL Input current (low level) VDD = 3.3 V, VIN = 0 V µA
A
With pulldown ±2
With pullup ±2
IIH Input current (high level) VDD = 3.3 V, VIN = VDD µA
A
With pulldown 10 16 30
IOZ Output current, high-impedance state (off-state) VO = VDD or 0 V ±2 µA
Ci Input capacitance 2 pF
Co Output capacitance 3 pF

current consumption by power-supply pins over recommended operating temperature range at

40-MHz CLOCKOUT† (LF2401A)
PARAMETER TEST CONDITIONS TEMPERATURE MIN TYP MAX‡ UNIT
A test code running in Flash does the
following:
1. Enables clock to all peripherals −40°C to 85°C (A) 75 90 mA
2. Toggles all PWM outputs at
20 kHz
IDD Operational Current 3. Performs a continuous
conversion of all ADC channels
4. An infinite loop which transmits a
character out of SCI and −40°C to 125°C (S) 75 110 mA
executes MACD instructions
NOTE: All I/O pins are floating.
−40°C to 85°C (A)
ICCA ADC module current 10 22 mA
−40°C to 125°C (S)
† IDD is the current flowing into the VDD and VDDO pins. IDD current includes the current drawn by the PLL module.
‡ The MAX numbers are at maximum temperature and voltage.

current consumption by power-supply pins over recommended operating temperature range at

40-MHz CLOCKOUT† (LC2401A)
PARAMETER TEST CONDITIONS TEMPERATURE MIN TYP MAX UNIT
A test code running in Flash does the
following:
1. Enables clock to all peripherals −40°C to 85°C (A) 55 70 mA
2. Toggles all PWM outputs at
20 kHz
IDD Operational Current 3. Performs a continuous
conversion of all ADC channels
4. An infinite loop which transmits a
character out of SCI and −40°C to 125°C (S) 55 90 mA
executes MACD instructions
NOTE: All I/O pins are floating.
−40°C to 85°C (A)
ICCA ADC module current 11 25 mA
−40°C to 125°C (S)
† IDD is the current flowing into the VDD and VDDO pins. IDD current includes the current drawn by the PLL module.

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current consumption by power-supply pins over recommended operating temperature range

during low-power modes at 40-MHz CLOCKOUT† (LF2401A)
PARAMETER MODE OPERATING CONDITIONS TEMPERATURE MIN TYP MAX UNIT

Operational Clock to all peripherals is enabled. −40°C to 85°C (A) 60 70 mA

IDD
Current No I/O pins are switching. −40°C to 125°C (S) 60 90 mA
LPM0
ADC module Clock to all peripherals is enabled. −40°C to 85°C (A) 12 18 mA
ICCA
current No I/O pins are switching. −40°C to 125°C (S) 12 18 mA

Operational Clock to all peripherals is disabled. −40°C to 85°C (A) 35 40 mA

IDD
Current No I/O pins are switching. −40°C to 125°C (S) 35 50 mA
LPM1
ADC module Clock to all peripherals is disabled. −40°C to 85°C (A) 5 10 µA
ICCA
current No I/O pins are switching. −40°C to 125°C (S) 5 20 µA

Operational Clock to all peripherals is disabled. −40°C to 85°C (A) 80 100 µA

IDD
Current Flash is powered down. −40°C to 125°C (S) 80 200 µA
LPM2
ADC module Clock to all peripherals is disabled. −40°C to 85°C (A) 5 10 µA
ICCA
current Flash is powered down. −40°C to 125°C (S) 5 20 µA
† IDD is the current flowing into the VDD and VDDO pins.

current consumption by power-supply pins over recommended operating temperature range

during low-power modes at 40-MHz CLOCKOUT† (LC2401A)
PARAMETER MODE OPERATING CONDITIONS TEMPERATURE MIN TYP MAX UNIT

Operational Clock to all peripherals is enabled. −40°C to 85°C (A) 40 50 mA

IDD
Current No I/O pins are switching. −40°C to 125°C (S) 40 70 mA
LPM0
ADC module Clock to all peripherals is enabled. −40°C to 85°C (A) 12 18 mA
ICCA
current No I/O pins are switching. −40°C to 125°C (S) 12 18 mA

Operational Clock to all peripherals is disabled. −40°C to 85°C (A) 15 22 mA

IDD
Current No I/O pins are switching. −40°C to 125°C (S) 15 32 mA
LPM1
ADC module Clock to all peripherals is disabled. −40°C to 85°C (A) 5 10 µA
ICCA
current No I/O pins are switching. −40°C to 125°C (S) 5 15 µA

Operational −40°C to 85°C (A) 50 70 µA

IDD Clock to all peripherals is disabled.
Current −40°C to 125°C (S) 50 170 µA
LPM2
ADC module −40°C to 85°C (A) 5 10 µA
ICCA Clock to all peripherals is disabled.
current −40°C to 125°C (S) 5 15 µA
† IDD is the current flowing into the VDD and VDDO pins.

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current consumption graphs

100
90
80
70
Current (mA)
60
I DD
50
40
30
20
10
0
0 5 10 15 20 25 30 35 40 45
CLKOUT Frequency (MHz)

Figure 21. LF2401A Typical Current Consumption (With Peripheral Clocks Enabled)

reducing current consumption

240x DSPs incorporate a unique method to reduce the device current consumption. A reduction in current
consumption can be achieved by turning off the clock to any peripheral module which is not used in a given
application. Table 15 indicates the typical reduction in current consumption achieved by turning off the clocks
to various peripherals. Refer to the TMS320LF/LC240xA DSP Controllers Reference Guide: System and
Peripherals (literature number SPRU357) for further information on how to turn off the clock to the peripherals.

Table 15. Typical Current Consumption by Various Peripherals (at 40 MHz)

PERIPHERAL MODULE CURRENT REDUCTION (mA)
EVA 6.1
ADC† 2.8†

SCI 1.9
† ADC current shown is at 30 MHz.

emulator connection without signal buffering for the DSP

Figure 22 shows the connection between the DSP and JTAG header for a single-processor configuration. If the
distance between the JTAG header and the DSP is greater than 6 inches, the emulation signals must be
buffered. If the distance is less than 6 inches, buffering is typically not needed. Figure 22 shows the simpler,
no-buffering situation. For the pullup/pulldown resistor values, see the pin description section. For details on
buffering JTAG signals and multiple processor connections, see TMS320F/C24x DSP Controllers CPU and
Instruction Set Reference Guide (literature number SPRU160).

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SPRS161K − MARCH 2001 − REVISED JULY 2007

emulator connection without signal buffering for the DSP (continued)

6 inches or less

VDD VDD

13 5
EMU0 EMU0 PD
14
EMU1 EMU1
2 4
TRST TRST GND
1 6
TMS TMS GND
3 8
TDI TDI GND
7 10
TDO TDO GND
11 12
TCK TCK GND
9
TCK_RET
DSP
JTAG Header

Figure 22. Emulator Connection Without Signal Buffering for the DSP

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PARAMETER MEASUREMENT INFORMATION

IOL

Tester Pin
Electronics

50 Ω Output
VLOAD Under
Test
CT

IOH

Where: IOH = −2 mA (all outputs)

VLOAD = 1.5 V
CT = 50-pF typical load-circuit capacitance
Figure 23. Test Load Circuit
signal transition levels
The data in this section is shown for the 3.3-V version. Note that some of the signals use different reference
voltages, see the recommended operating conditions table. Output levels are driven to a minimum logic-high
level of 2.4 V and to a maximum logic-low level of 0.4 V.
Figure 24 shows output levels.
2.4 V (VOH)
80%

20%
0.4 V (VOL)

Figure 24. Output Levels

Output transition times are specified as follows:
D For a high-to-low transition, the level at which the output is said to be no longer high is below 80% of the
total voltage range and lower and the level at which the output is said to be low is 20% of the total voltage
range and lower.
D For a low-to-high transition, the level at which the output is said to be no longer low is 20% of the total voltage
range and higher and the level at which the output is said to be high is 80% of the total voltage range and
higher.
Figure 25 shows the input levels.
2.0 V (VIH)
90%

10%
0.8 V (VIL)

Figure 25. Input Levels

Input transition times are specified as follows:
D For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is 90%
of the total voltage range and lower and the level at which the input is said to be low is 10% of the total voltage
range and lower.
D For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is 10%
of the total voltage range and higher and the level at which the input is said to be high is 90% of the total
voltage range and higher.

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PARAMETER MEASUREMENT INFORMATION

timing parameter symbology

Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols,
some of the pin names and other related terminology have been abbreviated as follows:

CI XTAL1
CO CLKOUT
RS RESET pin RS
INT XINT1, XINT2

Lowercase subscripts and their meanings: Letters and symbols and their meanings:
a access time H High
c cycle time (period) L Low
d delay time V Valid
f fall time X Unknown, changing, or don’t care level
h hold time Z High impedance
r rise time
su setup time
t transition time
v valid time
w pulse duration (width)

general notes on timing parameters

All output signals from the 2401A device (including CLKOUT) are derived from an internal clock such that all
output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles.
For actual cycle examples, refer to the appropriate cycle description section of this data sheet.

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external reference crystal/clock with PLL circuit enabled

timing with the PLL circuit enabled

PARAMETER MIN MAX UNIT
Resonator 4 13
fx Input clock frequency† Crystal 4 20 MHz
CLKIN 4 20
† Input frequency should be adjusted (CLK PS bits in SCSR1 register) such that CLKOUT = 40 MHz maximum, 4 MHz minimum.

switching characteristics over recommended operating conditions [H = 0.5 tc(CO)] (see Figure 26)
PARAMETER PLL MODE MIN TYP MAX UNIT
tc(CO) Cycle time, CLKOUT X4 mode† 25 ns
tf(CO) Fall time, CLKOUT 4 ns
tr(CO) Rise time, CLKOUT 4 ns
tw(COL) Pulse duration, CLKOUT low LF2401A X4 mode† @ 2 mA load H −3 H H +3 ns
tw(COH) Pulse duration, CLKOUT high LF2401A X4 mode† @ 2 mA load H −3 H H +3 ns
tw(COL) Pulse duration, CLKOUT low LC2401A X4 mode† @ 2 mA load H −5 H H +5 ns
tw(COH) Pulse duration, CLKOUT high LC2401A X4 mode† @ 2 mA loadH −5 H H +5 ns
† Input frequency should be adjusted (CLK PS bits in SCSR1 register) such that CLKOUT = 40 MHz maximum, 2 MHz minimum.

timing requirements (see Figure 26)

MIN MAX UNIT
tc(Cl) Cycle time, XTAL1/CLKIN 250 ns
tf(Cl) Fall time, XTAL1/CLKIN 5 ns
tr(Cl) Rise time, XTAL1/CLKIN 5 ns
tw(CIL) Pulse duration, XTAL1/CLKIN low as a percentage of tc(Cl) 40 60 %
tw(CIH) Pulse duration, XTAL1/CLKIN high as a percentage of tc(Cl) 40 60 %

tc(CI)
tw(CIH)
tf(Cl) tr(Cl)

tw(CIL)
XTAL1/CLKIN

tw(COH)
tw(COL) tf(CO)
tc(CO) tr(CO)

CLKOUT

Figure 26. CLKIN-to-CLKOUT Timing With PLL and External Clock in ×4 Mode

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RS timing
timing requirements for a reset [H = 0.5tc(CO)] (see Figure 27 and Figure 28)
MIN NOM MAX UNIT
tw(RSL) Pulse duration, stable CLKIN to RS high 8tc(CI)† cycles
tw(RSL2) Pulse duration, RS low 8tc(CI) cycles
tp PLL lock-up time 98304tc(CI) cycles
td(EX) Delay time, reset vector executed after PLL lock time 36H cycles
† During power-on reset, the device can continue to hold the RS pin low for another 128 CLKIN cycles.

VDD/VDDO

td(EX)
tp
tw(RSL)
RS

CLKIN

XTAL1
(See tOSCST
Note B) (See Note C)

TDI TDI/OPB5
(See
Note D) BOOT_EN

CLKOUT
(See
Note E)

I/Os Hi-Z Code-Dependent

NOTES: A. Be certain that the emulation logic is reset before de-asserting the device reset. That is, TRST of the device is not driven high before
the device reset is de-asserted. This is applicable to XDS510, XDS510PP, and XDS510PP+ class of emulators. New
generation emulators such as SPI515 and XDS510 USB emulators have a built-in protection mechanism to take care of this
requirement.
B. XTAL1 refers to the internal oscillator clock if an on-chip oscillator is used.
C. tOSCST is the oscillator start-up time, which is dependent on crystal/resonator and board design.
D. The TDI pin is used to determine whether or not the on-chip boot ROM is invoked in the BOOT_EN phase. In the “TDI/OPB5” phase,
this pin functions as TDI (if TRST is high) or OPB5 (if TRST is low).
E. Unlike other 24x/240x devices, the CLKOUT signal does not appear on the CLKOUT pin by default (after a device reset). The
CLKOUT waveform depicted in the figure is present internally in the DSP. However, in order to route the internal CLKOUT signal
to the XINT2/ADCSOC/CAP1/IOPA7/CLKOUT pin, bit 7 of the MCRA register must be programmed appropriately.

Figure 27. Power-On Reset

XDS510PP+, SP515, and XDS510 USB are trademarks of Spectrum Digital.

XDS510 and XDS510PP, are trademarks of Texas Instruments.

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RS timing (continued)
td(EX)
tp
tw(RSL2)
RS

CLKIN

XTAL1†

TDI‡ TDI/OPB5
BOOT_EN

CLKOUT§

I/Os Hi-Z Code-Dependent

† XTAL1 refers to internal oscillator clock if on-chip oscillator is used.

‡ The TDI pin is used to determine whether or not the on-chip boot ROM is invoked in the BOOT_EN phase. In the “TDI/OPB5” phase, this pin
functions as TDI (if TRST is high) or OPB5 (if TRST is low).
§ Unlike other 24x/240x devices, the CLKOUT signal does not appear on the CLKOUT pin by default (after a device reset). The CLKOUT waveform
depicted in the figure is present internally in the DSP. However, in order to route the internal CLKOUT signal to the
XINT2/ADCSOC/CAP1/IOPA7/CLKOUT pin, bit 7 of the MCRA register must be programmed appropriately.
NOTE A: During warm resets, if the watchdog module is enabled and issues a reset, then the RS pin will be an output and driven low for the WD
pulse duration − 128 CLKIN cycles.

Figure 28. Warm Reset

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RS timing (continued)
switching characteristics over recommended operating conditions for a reset [H = 0.5tc(CO)]
(see Figure 29)
PARAMETER MIN MAX UNIT
tw(RSL1) Watchdog reset pulse width 128tc(CI) ns
td(EX) Delay time, reset vector executed after PLL lock time 36H ns
tp PLL lock time (input cycles) 98 304tc(CI) ns

td(EX)
tp
tw(RSL1)
RS

CLKIN

XTAL1†

TDI‡ TDI/OPB5
BOOT_EN

CLKOUT§

I/Os Hi-Z Code-Dependent

† XTAL1 refers to internal oscillator clock if on-chip oscillator is used.

‡ The TDI pin is used to determine whether or not the on-chip boot ROM is invoked in the BOOT_EN phase. In the “TDI/OPB5” phase, this pin
functions as TDI (if TRST is high) or OPB5 (if TRST is low).
§ Unlike other 24x/240x devices, the CLKOUT signal does not appear on the CLKOUT pin by default (after a device reset). The CLKOUT waveform
depicted in the figure is present internally in the DSP. However, in order to route the internal CLKOUT signal to the
XINT2/ADCSOC/CAP1/IOPA7/CLKOUT pin, bit 7 of the MCRA register must be programmed appropriately.

Figure 29. Watchdog Initiated Reset

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low-power mode timing

switching characteristics over recommended operating conditions [H = 0.5tc(CO)]

(see Figure 30, Figure 31, and Figure 32)
PARAMETER LOW-POWER MODES MIN TYP MAX UNIT

Delay time, CLKOUT switching to IDLE1 LPM0 12 × tc(CO)

td(WAKE-A) ns
program execution resume IDLE2 LPM1 15 × tc(CO)
Delay time, Idle instruction executed to
td(IDLE-COH) IDLE2 LPM1 4tc(CO) ns
CLKOUT high
OSC start-up
Delay time, wake-up interrupt
td(WAKE-OSC) and PLL lock ms
asserted to oscillator running HALT
LPM2 time
{PLL/OSC power down}
Delay time, Idle instruction executed to
td(IDLE-OSC) 4tc(CO) ns
oscillator power off
td(EX) Delay time, reset vector executed after RS high 36H ns

td(WAKE−A)

A0−A15

CLKOUT†‡

WAKE INT§

† In 2401A, CLKOUT will not be seen at the pin, only in some modes; it can be enabled in software.
‡ Unlike other 24x/240x devices, the CLKOUT signal does not appear on the CLKOUT pin by default (after a device reset). The CLKOUT waveform
depicted in the figure is present internally in the DSP. However, in order to route the internal CLKOUT signal to the
XINT2/ADCSOC/CAP1/IOPA7/CLKOUT pin, bit 7 of the MCRA register must be programmed appropriately.
§ WAKE INT can be any valid interrupt or RESET.

Figure 30. IDLE1 Entry and Exit Timing − LPM0

td(IDLE−COH)

A0−A15

CLKOUT†‡

WAKE INT§
td(WAKE−A)

† In 2401A, CLKOUT will not be seen at the pin, only in some modes; it can be enabled in software.
‡ Unlike other 24x/240x devices, the CLKOUT signal does not appear on the CLKOUT pin by default (after a device reset). The CLKOUT waveform
depicted in the figure is present internally in the DSP. However, in order to route the internal CLKOUT signal to the
XINT2/ADCSOC/CAP1/IOPA7/CLKOUT pin, bit 7 of the MCRA register must be programmed appropriately.
§ WAKE INT can be any valid interrupt or RESET.

Figure 31. IDLE2 Entry and Exit Timing − LPM1

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low-power mode timing (continued)

td(EX)
tp
A0−A15

td(IDLE−OSC)
td(IDLE−COH)

CLKOUT
td(WAKE−OSC)
tw(RSL)

RESET
† In 2401A, CLKOUT will not be seen at the pin, only in some modes; it can be enabled in software.
‡ Unlike other 24x/240x devices, the CLKOUT signal does not appear on the CLKOUT pin by default (after a device reset). The CLKOUT waveform
depicted in the figure is present internally in the DSP. However, in order to route the internal CLKOUT signal to the
XINT2/ADCSOC/CAP1/IOPA7/CLKOUT pin, bit 7 of the MCRA register must be programmed appropriately.

Figure 32. HALT Mode − LPM2

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LPM2 wake-up timing

switching characteristics over recommended operating conditions (see Figure 33)

PARAMETER MIN MAX UNIT

Delay time, PDPINTA low to PWM if bit 6 of SCSR2 = 0 (6 + 1)tc(CO) + 12† ns

td(PDP-PWM)HZ
high-impedance state if bit 6 of SCSR2 = 1 (12+ 1)tc(CO) + 12† ns
Delay time, INT low/high to interrupt-vector
td(INT) 10tc(CO) + tw(PDP−WAKE) ns
fetch
† Includes i/p qualifier cycles plus synchronization plus propagation delay

timing requirements (see Figure 33)

MIN MAX UNIT
if bit 6 of SCSR2 = 0 6tc(CO)
tw(PDP−WAKE) Pulse duration, PDPINTA input low ns
if bit 6 of SCSR2 = 1 12tc(CO)
tp PLL lock-up time 98 304tc(CI) cycles

XTAL1 Oscillator Disabled

tOSC†
tp

CLKIN

CLKOUT‡§

tw(PDP−WAKE)

PDPINTA

td(PDP-PWM)HZ

PWM

td(INT)

CPU IDLE State (LPM2) Interrupt Vector¶ or

CPU Status Next Instruction#

† tOSC is the oscillator start-up time.

‡ CLKOUT frequency after LPM2 wake-up will be the same as that upon entering LPM2 (x4 shown as an example).
§ Unlike other 24x/240x devices, the CLKOUT signal does not appear on the CLKOUT pin by default (after a device reset). The CLKOUT
waveform depicted in the figure is present internally in the DSP. However, in order to route the internal CLKOUT signal to the
XINT2/ADCSOC/CAP1/IOPA7/CLKOUT pin, bit 7 of the MCRA register must be programmed appropriately.
¶ PDPINTA interrupt vector, if PDPINTA interrupt is enabled.
# If PDPINTA interrupt is disabled.

Figure 33. LPM2 Wakeup Using PDPINTA

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TIMING EVENT MANAGER INTERFACE

PWM timing
PWM refers to all PWM outputs on EVA.

switching characteristics over recommended operating conditions for PWM timing

[H = 0.5tc(CO)] (see Figure 34)
PARAMETER MIN MAX UNIT
tw(PWM)† Pulse duration, PWMx output high/low 2H+5 ns
td(PWM)CO Delay time, CLKOUT low to PWMx output switching 13 21 ns
† PWM outputs may be 100%, 0%, or increments of tc(CO) with respect to the PWM period.

CLKOUT

td(PWM)CO
tw(PWM)

PWMx

Figure 34. PWM Output Timing

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capture timing

timing requirements (see Figure 35)

MIN MAX UNIT
if bit 6 of SCSR2 = 0 6tc(CO)
tw(CAP) Pulse duration, CAP1 input low/high ns
if bit 6 of SCSR2 = 1 12tc(CO)

CLKOUT

tw(CAP)

CAP1

Figure 35. Capture Input Timing

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interrupt timing
INT refers to XINT1, XINT2, and PDPINTA.

switching characteristics over recommended operating conditions (see Figure 36)

PARAMETER MIN MAX UNIT

Delay time, PDPINTA low to PWM if bit 6 of SCSR2 = 0 (6 + 1)tc(CO) + 12† ns

td(PDP-PWM)HZ
high-impedance state if bit 6 of SCSR2 = 1 (12+ 1)tc(CO) + 12† ns
Delay time, INT low/high to interrupt-vector
td(INT) 10tc(CO) +tw(INT) ns
fetch
† Includes i/p qualifier cycles plus synchronization plus propagation delay

timing requirements (see Figure 36)

MIN MAX UNIT
if bit 6 of SCSR2 = 0 6tc(CO)
tw(INT) Pulse duration, INT input low/high ns
if bit 6 of SCSR2 = 1 12tc(CO)
if bit 6 of SCSR2 = 0 6tc(CO)
tw(PDP) Pulse duration, PDPINTA input low ns
if bit 6 of SCSR2 = 1 12tc(CO)

CLKOUT

tw(PDP)

PDPINTA

td(PDP-PWM)HZ

PWM†

tw(INT)

XINT1, XINT2

td(INT)

A0−A15 Interrupt Vector

(Internal Bus)

† PWM refers to all the PWM pins in the device (i.e., PWMn and TnPWM pins). The state of the PWM pins after PDPINTA is taken
high depends on the state of the FCOMPOE bit.

Figure 36. External Interrupts Timing

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general-purpose input/output timing

switching characteristics over recommended operating conditions (see Figure 37)

PARAMETER MIN MAX UNIT
td(GPO)CO Delay time, CLKOUT low to GPIO low/high All GPIOs 13 21 ns
tr(GPO) Rise time, GPIO switching low to high All GPIOs 12 ns
tf(GPO) Fall time, GPIO switching high to low All GPIOs 15 ns

timing requirements [H = 0.5tc(CO)] (see Figure 38)

MIN MAX UNIT
tw(GPI) Pulse duration, GPI high/low 2H+15 ns

CLKOUT

td(GPO)CO

GPIO

tr(GPO)
tf(GPO)

Figure 37. General-Purpose Output Timing

CLKOUT

tw(GPI)

GPIO

Figure 38. General-Purpose Input Timing

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SPRS161K − MARCH 2001 − REVISED JULY 2007

10-bit analog-to-digital converter (ADC)

The 10-bit ADC has a separate power bus for its analog circuitry. These pins are referred to as VCCA and VSSA.
The power bus isolation is to enhance ADC performance by preventing digital switching noise of the logic
circuitry that can be present on VSS and VCC from coupling into the ADC analog stage. All ADC specifications
are given with respect to VSSA unless otherwise noted.
Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-bit (1024 values)
Monotonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Assured
Output conversion mode . . . . . . . . . . . . . . . . . . . . . . . 000h to 3FFh (000h for VI ≤ VSSA; 3FFh for VI ≥ VCCA)
Conversion time (including sample time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 ns

recommended operating conditions

MIN NOM MAX UNIT
VCCA† Analog supply voltage 3.0 3.3 3.6 V
VSSA† Analog ground 0 V
VAI Analog input voltage, ADCIN00−ADCIN04 VREFLO VREFHI V
† VCCA and VSSA must be stable, within ±1/2 LSB of the required resolution, during the entire conversion time.

ADC operating frequency

MIN MAX UNIT
ADC operating frequency 2 30 MHz

operating characteristics over recommended operating condition ranges

PARAMETER DESCRIPTION MIN TYP MAX UNIT
IADCIN Analog input leakage 1 mA

Typical capacitive load on Non-sampling 10

Cai Analog input capacitance pF
analog input pin Sampling 30
Difference between the actual step width and the
EDNL Differential nonlinearity error ±2 LSB
ideal value
Maximum deviation from the best straight line
EINL Integral nonlinearity error through the ADC transfer characteristics, excluding ±2 LSB
the quantization error
Delay time, power-up to ADC
td(PU) Time to stabilize analog stage after power-up 10 ms
valid

Analog input source impedance needed for

ZAI Analog input source impedance conversions to remain within specifications at min 10 Ω
tw(SH)
Zero-offset error 8 10 LSB

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internal ADC module timing† (see Figure 39)

MIN MAX UNIT
tc(AD) Cycle time, ADC prescaled clock 33.3 ns
tw(SHC) Pulse duration, total sample/hold and conversion time‡ 500 ns
tw(SH) Pulse duration, sample and hold time 2tc(AD)§ 32tc(AD) ns
tw(C) Pulse duration, total conversion time 10tc(AD) ns
td(SOC-SH) Delay time, start of conversion to beginning of sample and hold 2tc(CO) ns
td(EOC) Delay time, end of conversion to data loaded into result register 2tc(CO) ns
td(ADCINT) Delay time, ADC flag to ADC interrupt 2tc(CO) ns
† The ADC timing diagram represents a typical conversion sequence. Refer to the ADC chapter in the TMS320LF/LC240xA DSP Controllers
Reference Guide: System and Peripherals (literature number SPRU357) for more details.
‡ The total sample/hold and conversion time is determined by the summation of td(SOC-SH), tw(SH), tw(C), and td(EOC) .
§ Can be varied by ACQ Prescaler bits in the ADCCTRL1 register

tc(AD)

Bit Converted 9 8 7 6 5 4 3 2 1 0

ADC Clock

Analog Input
ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ tw(C)

EOC/Convert

tw(SH)
Internal Start/
Sample Hold

td(SOC−SH)
Start of Convert

td(EOC)
tw(SHC)

XFR to RESULTn
td(ADCINT)

ADC Interrupt

Figure 39. Analog-to-Digital Internal Module Timing

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SPRS161K − MARCH 2001 − REVISED JULY 2007

Flash parameters @40 MHz CLOCKOUT (LF2401A)

PARAMETER MIN TYP MAX UNIT
Time/Word (16-bit) 30 µs
Clear/Programming time†
Time/4K Sector 130 ms
Erase time† Time/4K Sector 350 ms
Indicates the typical/maximum current consumption during the
ICCP (VCCP pin current) 5 15 mA
Clear-Erase-Program (C-E-P) cycle
† The indicated time does not include the time it takes to load the C-E-P algorithm and the code (to be programmed) onto on-chip RAM. The values
specified are when VDD = 3.3 V and VCCP = 5 V, and any deviation from these values could affect the timing parameters. Aging and process
variance could also impact the timing parameters.

migrating from other 240xA devices to Lx2401A

This section outlines some of the issues to be considered while migrating a design from the 240xA family to the
Lx2401A. The Lx2401A shares the same CPU core (and hence, the same instruction set) as the 240xA.
Furthermore, the peripherals implemented on the Lx2401A are a subset of those found in the 240xA family.
However, some features of a particular peripheral may not be present on the 2401A. This must be taken into
consideration while porting code to the Lx2401A. Other issues to be considered for migration are as follows.
PLL
The PLL used in the Lx2401A is different than the one used in the 240xA family. The Lx2401A PLL does not
need the external loop-filter components. The PLL is bypassed when the TMS and TRST pins are sensed low
at reset.
NOTE: The device may come up in PLL bypass mode if the TMS and TRST pins are sensed low when the
emulator/debugger is brought up (with the XDS510/XDS510PP/XDS510PP+ pod connected to the target
hardware). If this happens, the device reset pin (RS) must be activated once (after the emulator is up and
running) to bring it out of PLL bypass mode. Note that this is a concern only when the JTAG connector is
connected for debug and does not have an impact when the code is free-run without the JTAG connector—i.e.,
there are no issues when the target hardware is powered up without the JTAG connector. Before attempting
to program flash through JTAG, it must be ensured that the PLL is not in bypass mode.
on-chip bootloader
Boot ROM is a 256-word ROM mapped in program space 0000h−00FFh. This ROM will be enabled if the
BOOT_EN mode is enabled during reset. Boot-enable function is implemented using combinational logic of the
TDI, TRST, and RS pins as described below. The on-chip bootloader is invoked when:
TRST = 0
RS = 0
TDI = 0

(In addition to the three pins mentioned above, the application must ensure that PDPINTA stays high during the
execution of the boot ROM code.) Since it has an internal pulldown, the TRST pin will be low, provided the JTAG
connector is not connected. Therefore, the BOOT_EN bit (bit 3 of the SCSR2 register) will be set to 0 if TDI is
low upon reset. If on-chip bootloader is desired while debugging with the JTAG connector connected
(TRST = 1), it can be achieved by writing a “0” into bit 3 of the SCSR2 register.
GPIO
The multiplexing scheme of the GPIO pins with other functional pins is different in the Lx2401A. Because of this,
the bit assignments for the MCRA, PADATDIR, and PBDATDIR registers of the Lx2401A is not compatible with
the bit assignments of the 240xA family.

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EV
The Event Manager of the Lx2401A has reduced functionality when compared to that of the 240xA family.
Following are the important differences:
D There is no QEP unit.
D There is only one “Capture” input (CAP1).
D Although Timer 1 is present, there is no compare output pin (T1CMP/T1PWM).
D There is no provision to feed an external clock to the timers.
D There is no external direction control pin for the timers.
Due to these differences, some of the bits in the EV registers are not applicable in the Lx2401A and are shaded
gray. Refer to Table 16, Lx2401A DSP Peripheral Register Description, for more details.
ADC
The Lx2401A ADC has only five input channels as compared to eight or sixteen channels in the 240xA family.
Therefore, the 4-bit fields in the CHSELSEQn registers should be programmed with values from 0−4 only.
The Lx2401A ADC does not have dedicated VREFHI and VREFLO pins. Instead, the VCCA and VSSA pins provide
the necessary reference.
pins
The following pins, which are available in other 240xA devices, have been internally tied as indicated:
CAP2, CAP3 − low
TDIRA − low
TCLKINA − low
BIO − high
DINR
The device ID contained in the DINR register is 0810h for LF2401A and 0910h for LC2401A.
XF pin
The XF pin has to be enabled by writing a 1 to Bit 0 of the SCSR4 register before it can be used.

migrating from LF2401A (Flash) device to LC2401A (ROM) device

When migrating from Flash to ROM device, be sure to review this section for a list of important differences that
should be considered. Customer applications should consider these differences in their design, prior to ROM
code submission. Due to the fact that the flash and ROM are different silicon, the following parameters may be
similar but not exactly identical. Refer to the respective datasheet sections for more detail:
D EMI/ESD behavior
D ADC performance
D Current consumption
D Device ID register values
D The last 64 words of ROM are reserved for TI internal testing. User code should not occupy these locations.
See the device memory map for details.

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SPRS161K − MARCH 2001 − REVISED JULY 2007

peripheral register description

Table 16 is a collection of all the programmable registers of the Lx2401A and is provided as a quick reference.

Table 16. Lx2401A DSP Peripheral Register Description

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8

ADDR REG
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
DATA MEMORY SPACE
CPU STATUS REGISTERS
ARP OV OVM 1 INTM DP(8)
ST0
DP(7) DP(6) DP(5) DP(4) DP(3) DP(2) DP(1) DP(0)
ARB CNF TC SXM C 1
ST1
1 1 1 XF 1 1 PM
GLOBAL MEMORY AND CPU INTERRUPT REGISTERS
— — — — — — — —
00004h IMR
— — INT6 MASK INT5 MASK INT4 MASK INT3 MASK INT2 MASK INT1 MASK
00005h Reserved GREG
— — — — — — — —
00006h IFR
— — INT6 FLAG INT5 FLAG INT4 FLAG INT3 FLAG INT2 FLAG INT1 FLAG
SYSTEM REGISTERS
IRQ0.15 IRQ0.14 IRQ0.13 IRQ0.12 IRQ0.11 IRQ0.10 IRQ0.9 IRQ0.8
07010h PIRQR0
IRQ0.7 IRQ0.6 IRQ0.5 IRQ0.4 IRQ0.3 IRQ0.2 IRQ0.1 IRQ0.0
IRQ1.15 IRQ1.14 IRQ1.13 IRQ1.12 IRQ1.11 IRQ1.10 IRQ1.9 IRQ1.8
07011h PIRQR1
IRQ1.7 IRQ1.6 IRQ1.5 IRQ1.4 IRQ1.3 IRQ1.2 IRQ1.1 IRQ1.0
IRQ2.15 IRQ2.14 IRQ2.13 IRQ2.12 IRQ2.11 IRQ2.10 IRQ2.9 IRQ2.8
07012h PIRQR2
IRQ2.7 IRQ2.6 IRQ2.5 IRQ2.4 IRQ2.3 IRQ2.2 IRQ2.1 IRQ2.0
07013h Illegal
IAK0.15 IAK0.14 IAK0.13 IAK0.12 IAK0.11 IAK0.10 IAK0.9 IAK0.8
07014h PIACKR0
IAK0.7 IAK0.6 IAK0.5 IAK0.4 IAK0.3 IAK0.2 IAK0.1 IAK0.0
IAK1.15 IAK1.14 IAK1.13 IAK1.12 IAK1.11 IAK1.10 IAK1.9 IAK1.8
07015h PIACKR1
IAK1.7 IAK1.6 IAK1.5 IAK1.4 IAK1.3 IAK1.2 IAK1.1 IAK1.0
IAK2.15 IAK2.14 IAK2.13 IAK2.12 IAK2.11 IAK2.10 IAK2.9 IAK2.8
07016h PIACKR2
IAK2.7 IAK2.6 IAK2.5 IAK2.4 IAK2.3 IAK2.2 IAK2.1 IAK2.0
07017h Illegal
— CLKSRC LPM1 LPM0 CLK PS2 CLK PS1 CLK PS0 —
07018h SCSR1
ADC CLKEN SCI CLKEN SPI CLKEN CAN CLKEN EVB CLKEN EVA CLKEN — ILLADR
— — — — — — — —
I/P
07019h WD SCSR2
— QUALIFIER — BOOT_EN — DON PON
OVERRIDE
CLOCKS
0701Ah Illegal
— — — — — — — —
0701Bh SCSR4
— — — — — — — XF ENABLE
DIN15 DIN14 DIN13 DIN12 DIN11 DIN10 DIN9 DIN8
0701Ch DINR
DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0
0701Dh Illegal
V15 V14 V13 V12 V11 V10 V9 V8
0701Eh PIVR
V7 V6 V5 V4 V3 V2 V1 V0
0701Fh Illegal

These bits are not applicable in the Lx2401A since either (i) the peripheral functionality is absent or (ii) the corre-
sponding pins have not been bonded out of the device.

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SPRS161K − MARCH 2001 − REVISED JULY 2007

peripheral register description (continued)

Table 16. Lx2401A DSP Peripheral Register Description (Continued)

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8

ADDR REG
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
WD CONTROL REGISTERS
07020h
to Illegal
07022h
07023h D7 D6 D5 D4 D3 D2 D1 D0 WDCNTR
07024h Illegal
07025h D7 D6 D5 D4 D3 D2 D1 D0 WDKEY
07026h
to Illegal
07028h
07029h WDFLAG WDDIS WDCHK2 WDCHK1 WDCHK0 WDPS2 WDPS1 WDPS0 WDCR
0702Ah
to Illegal
0703Fh
07040h
to Reserved
0704Fh
SERIAL COMMUNICATIONS INTERFACE (SCI) CONFIGURATION CONTROL REGISTERS
STOP EVEN/ODD PARITY LOOP BACK ADDR/IDLE SCI SCI SCI
07050h SCICCR
BITS PARITY ENABLE ENA MODE CHAR2 CHAR1 CHAR0
RX ERR
07051h — SW RESET — TXWAKE SLEEP TXENA RXENA SCICTL1
INT ENA
BAUD15
07052h BAUD14 BAUD13 BAUD12 BAUD11 BAUD10 BAUD9 BAUD8 SCIHBAUD
(MSB)
BAUD0
07053h BAUD7 BAUD6 BAUD5 BAUD4 BAUD3 BAUD2 BAUD1 SCILBAUD
(LSB)
RX/BK TX
07054h TXRDY TX EMPTY — — — — SCICTL2
INT ENA INT ENA
07055h RX ERROR RXRDY BRKDT FE OE PE RXWAKE — SCIRXST
07056h ERXDT7 ERXDT6 ERXDT5 ERXDT4 ERXDT3 ERXDT2 ERXDT1 ERXDT0 SCIRXEMU
07057h RXDT7 RXDT6 RXDT5 RXDT4 RXDT3 RXDT2 RXDT1 RXDT0 SCIRXBUF
07058h Illegal
07059h TXDT7 TXDT6 TXDT5 TXDT4 TXDT3 TXDT2 TXDT1 TXDT0 SCITXBUF
0705Ah
to Illegal
0705Eh
SCITX SCIRX SCI SCI
0705Fh — — — — SCIPRI
PRIORITY PRIORITY SOFT FREE
07060h
to Illegal
0706Fh

These bits are not applicable in the Lx2401A since either (i) the peripheral functionality is absent or (ii) the corre-
sponding pins have not been bonded out of the device.

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SPRS161K − MARCH 2001 − REVISED JULY 2007

peripheral register description (continued)

Table 16. Lx2401A DSP Peripheral Register Description (Continued)

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8

ADDR REG
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
EXTERNAL INTERRUPT CONTROL REGISTERS
XINT1
— — — — — — —
FLAG
07070h XINT1CR
XINT1 XINT1 XINT1
— — — — —
POLARITY PRIORITY ENA
XINT2
— — — — — — —
FLAG
07071h XINT2CR
XINT2 XINT2 XINT2
— — — — —
POLARITY PRIORITY ENA
07072h
to Illegal
0708Fh
DIGITAL I/O CONTROL REGISTERS
MCRA.15 MCRA.14 MCRA.13 MCRA.12 MCRA.11 MCRA.10 MCRA.9 MCRA.8
07090h MCRA
MCRA.7 MCRA.6 MCRA.5 MCRA.4 MCRA.3 MCRA.2 MCRA.1 MCRA.0
07091h Illegal
MCRB.15 MCRB.14 MCRB.13 MCRB.12 MCRB.11 MCRB.10 MCRB.9 MCRB.8
07092h MCRB
MCRB.7 MCRB.6 MCRB.5 MCRB.4 MCRB.3 MCRB.2 MCRB.1 MCRB.0
07093h Illegal
MCRC.15 MCRC.14 MCRC.13 MCRC.12 MCRC.11 MCRC.10 MCRC.9 MCRC.8
07094h MCRC
MCRC.7 MCRC.6 MCRC.5 MCRC.4 MCRC.3 MCRC.2 MCRC.1 MCRC.0
E7DIR E6DIR E5DIR E4DIR E3DIR E2DIR E1DIR E0DIR
07095h PEDATDIR
IOPE7 IOPE6 IOPE5 IOPE4 IOPE3 IOPE2 IOPE1 IOPE0
— F6DIR F5DIR F4DIR F3DIR F2DIR F1DIR F0DIR
07096h PFDATDIR
— IOPF6 IOPF5 IOPF4 IOPF3 IOPF2 IOPF1 IOPF0
07097h Illegal
A7DIR A6DIR A5DIR A4DIR A3DIR A2DIR A1DIR A0DIR
07098h PADATDIR
IOPA7 IOPA6 IOPA5 IOPA4 IOPA3 IOPA2 IOPA1 IOPA0
07099h Illegal
B7DIR B6DIR B5DIR B4DIR B3DIR B2DIR B1DIR B0DIR
0709Ah PBDATDIR
IOPB7 IOPB6 IOPB5 IOPB4 IOPB3 IOPB2 IOPB1 IOPB0
0709Bh Illegal
C7DIR C6DIR C5DIR C4DIR C3DIR C2DIR C1DIR C0DIR
0709Ch PCDATDIR
IOPC7 IOPC6 IOPC5 IOPC4 IOPC3 IOPC2 IOPC1 IOPC0
0709Dh Illegal
D7DIR D6DIR D5DIR D4DIR D3DIR D2DIR D1DIR D0DIR
0709Eh PDDATDIR
IOPD7 IOPD6 IOPD5 IOPD4 IOPD3 IOPD2 IOPD1 IOPD0
0709Fh Illegal

These bits are not applicable in the Lx2401A since either (i) the peripheral functionality is absent or (ii) the corre-
sponding pins have not been bonded out of the device.

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peripheral register description (continued)

Table 16. Lx2401A DSP Peripheral Register Description (Continued)

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8

ADDR REG
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
ANALOG-TO-DIGITAL CONVERTER (ADC) REGISTERS
ADC ACQ ACQ ACQ ACQ
— SOFT FREE
S/W RESET PRESCALE3 PRESCALE2 PRESCALE1 PRESCALE0
070A0h ADCCTRL1
CONV PRE- CONTIN- INT SEQ1/2
— — — —
SCALE (CPS) UOUS RUN PRIORITY CASCADE
EVB SOC INT ENA INT ENA INT FLAG EVA SOC
Reset SEQ1 SOC SEQ1 SEQ1 BUSY
EN SEQ1 SEQ1 Mode1 SEQ1 Mode0 SEQ1 EN SEQ1
070A1h ADCCTRL2
EXT SOC INT ENA INT ENA INT FLAG EVB SOC
Reset SEQ2 SOC SEQ2 SEQ2 BUSY
EN SEQ1 SEQ2 Mode1 SEQ2 Mode0 SEQ2 EN SEQ2
— — — — — — — —
070A2h MAXCONV2 MAXCONV2 MAXCONV2 MAXCONV1 MAXCONV1 MAXCONV1 MAXCONV1 MAXCONV
—
2 1 0 3 2 1 0
CONV 3 CONV 3 CONV 3 CONV 3 CONV 2 CONV 2 CONV 2 CONV 2
070A3h CHSELSEQ1
CONV 1 CONV 1 CONV 1 CONV 1 CONV 0 CONV 0 CONV 0 CONV 0
CONV 7 CONV 7 CONV 7 CONV 7 CONV 6 CONV 6 CONV 6 CONV 6
070A4h CHSELSEQ2
CONV 5 CONV 5 CONV 5 CONV 5 CONV 4 CONV 4 CONV 4 CONV 4
CONV 11 CONV 11 CONV 11 CONV 11 CONV 10 CONV 10 CONV 10 CONV 10
070A5h CHSELSEQ3
CONV 9 CONV 9 CONV 9 CONV 9 CONV 8 CONV 8 CONV 8 CONV 8
CONV 15 CONV 15 CONV 15 CONV 15 CONV 14 CONV 14 CONV 14 CONV 14
070A6h CHSELSEQ4
CONV 13 CONV 13 CONV 13 CONV 13 CONV 12 CONV 12 CONV 12 CONV 12
— — — — SEQ CNTR3 SEQ CNTR2 SEQ CNTR1 SEQ CNTR0
070A7h SEQ2 SEQ2 SEQ2 SEQ2 SEQ1 SEQ1 SEQ1 SEQ1 AUTO_SEQ_SR
STATE 3 STATE 2 STATE 1 STATE 0 STATE 3 STATE 2 STATE 1 STATE 0
D9 D8 D7 D6 D5 D4 D3 D2
070A8h RESULT0
D1 D0 0 0 0 0 0 0
D9 D8 D7 D6 D5 D4 D3 D2
070A9h RESULT1
D1 D0 0 0 0 0 0 0
D9 D8 D7 D6 D5 D4 D3 D2
070AAh RESULT2
D1 D0 0 0 0 0 0 0
D9 D8 D7 D6 D5 D4 D3 D2
070ABh RESULT3
D1 D0 0 0 0 0 0 0
D9 D8 D7 D6 D5 D4 D3 D2
070ACh RESULT4
D1 D0 0 0 0 0 0 0
D9 D8 D7 D6 D5 D4 D3 D2
070ADh RESULT5
D1 D0 0 0 0 0 0 0
D9 D8 D7 D6 D5 D4 D3 D2
070AEh RESULT6
D1 D0 0 0 0 0 00 0
D9 D8 D7 D6 D5 D4 D3 D2
070AFh RESULT7
D1 D0 0 0 0 0 0 0

These bits are not applicable in the Lx2401A since either (i) the peripheral functionality is absent or (ii) the cor-
responding pins have not been bonded out of the device.

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peripheral register description (continued)

Table 16. Lx2401A DSP Peripheral Register Description (Continued)

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8

ADDR REG
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
ANALOG-TO-DIGITAL CONVERTER (ADC) REGISTERS (CONTINUED)
D9 D8 D7 D6 D5 D4 D3 D2
070B0h RESULT8
D1 D0 0 0 0 0 0 0
D9 D8 D7 D6 D5 D4 D3 D2
070B1h RESULT9
D1 D0 0 0 0 0 0 0
D9 D8 D7 D6 D5 D4 D3 D2
070B2h RESULT10
D1 D0 0 0 0 0 0 0
D9 D8 D7 D6 D5 D4 D3 D2
070B3h RESULT11
D1 D0 0 0 0 0 0 0
D9 D8 D7 D6 D5 D4 D3 D2
070B4h RESULT12
D1 D0 0 0 0 0 0 0
D9 D8 D7 D6 D5 D4 D3 D2
070B5h RESULT13
D1 D0 0 0 0 0 0 0
D9 D8 D7 D6 D5 D4 D3 D2
070B6h RESULT14
D1 D0 0 0 0 0 0 0
D9 D8 D7 D6 D5 D4 D3 D2
070B7h RESULT15
D1 D0 0 0 0 0 0 0
070B8h Reserved
070B9h
to Illegal
070FFh
07100h
to Reserved
073FFh
GENERAL-PURPOSE (GP) TIMER CONFIGURATION CONTROL REGISTERS − EVA
— T2STAT T1STAT — T2TOADC T1TOADC(1)
07400h GPTCONA
T1TOADC(0) TCOMPOE — T2PIN T1PIN
D15 D14 D13 D12 D11 D10 D9 D8
07401h T1CNT
D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8
07402h T1CMPR
D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8
07403h T1PR
D7 D6 D5 D4 D3 D2 D1 D0
FREE SOFT — TMODE1 TMODE0 TPS2 TPS1 TPS0
07404h T1CON
— TENABLE TCLKS1 TCLKS0 TCLD1 TCLD0 TECMPR —

These bits are not applicable in the Lx2401A since either (i) the peripheral functionality is absent or (ii) the corre-
sponding pins have not been bonded out of the device.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 83


 
  
 

SPRS161K − MARCH 2001 − REVISED JULY 2007

peripheral register description (continued)

Table 16. Lx2401A DSP Peripheral Register Description (Continued)

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8

ADDR REG
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
GENERAL-PURPOSE (GP) TIMER CONFIGURATION CONTROL REGISTERS − EVA (CONTINUED)
D15 D14 D13 D12 D11 D10 D9 D8
07405h T2CNT
D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8
07406h T2CMPR
D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8
07407h T2PR
D7 D6 D5 D4 D3 D2 D1 D0
FREE SOFT — TMODE1 TMODE0 TPS2 TPS1 TPS0
07408h T2CON
T2SWT1 TENABLE TCLKS1 TCLKS0 TCLD1 TCLD0 TECMPR SELT1PR
07409h
to Illegal
07410h
FULL AND SIMPLE COMPARE UNIT REGISTERS − EVA
PDPINTA
CENABLE CLD1 CLD0 SVENABLE ACTRLD1 ACTRLD0 FCOMPOE
07411h STATUS COMCONA
— — — — — — — —
07412h Illegal
SVRDIR D2 D1 D0 CMP6ACT1 CMP6ACT0 CMP5ACT1 CMP5ACT0
07413h ACTRA
CMP4ACT1 CMP4ACT0 CMP3ACT1 CMP3ACT0 CMP2ACT1 CMP2ACT0 CMP1ACT1 CMP1ACT0
07414h Illegal
— — — — DBT3 DBT2 DBT1 DBT0
07415h DBTCONA
EDBT3 EDBT2 EDBT1 DBTPS2 DBTPS1 DBTPS0 — —
07416h Illegal
D15 D14 D13 D12 D11 D10 D9 D8
07417h CMPR1
D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8
07418h CMPR2
D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8
07419h CMPR3
D7 D6 D5 D4 D3 D2 D1 D0
0741Ah
to Illegal
0741Fh

These bits are not applicable in the Lx2401A since either (i) the peripheral functionality is absent or (ii) the corre-
sponding pins have not been bonded out of the device.

84 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443


 
  
 

SPRS161K − MARCH 2001 − REVISED JULY 2007

peripheral register description (continued)

Table 16. Lx2401A DSP Peripheral Register Description (Continued)

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8

ADDR REG
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CAPTURE UNIT REGISTERS − EVA
CAPRES CAPQEPN CAP3EN — CAP3TSEL CAP12TSEL CAP3TOADC
07420h CAPCONA
CAP1EDGE CAP2EDGE CAP3EDGE —
07421h Illegal
— CAP3FIFO CAP2FIFO CAP1FIFO
07422h CAPFIFOA
— — — — — — — —
D15 D14 D13 D12 D11 D10 D9 D8
07423h CAP1FIFO
D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8
07424h CAP2FIFO
D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8
07425h CAP3FIFO
D7 D6 D5 D4 D3 D2 D1 D0
07426h Illegal
D15 D14 D13 D12 D11 D10 D9 D8
07427h CAP1FBOT
D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8
07428h CAP2FBOT
D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8
07429h CAP3FBOT
D7 D6 D5 D4 D3 D2 D1 D0
0742Ah
to Illegal
0742Bh
EVENT MANAGER (EVA) INTERRUPT CONTROL REGISTERS
T1OFINT T1UFINT T1CINT
— — — — —
ENA ENA ENA
0742Ch EVAIMRA
T1PINT CMP3INT CMP2INT CMP1INT PDPINTA
— — —
ENA ENA ENA ENA ENA
— — — — — — — —
0742Dh T2OFINT T2UFINT T2CINT T2PINT EVAIMRB
— — — —
ENA ENA ENA ENA
— — — — — — — —
0742Eh CAP3INT CAP2INT CAP1INT EVAIMRC
— — — — —
ENA ENA ENA

These bits are not applicable in the Lx2401A since either (i) the peripheral functionality is absent or (ii) the corre-
sponding pins have not been bonded out of the device.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 85


 
  
 

SPRS161K − MARCH 2001 − REVISED JULY 2007

peripheral register description (continued)

Table 16. Lx2401A DSP Peripheral Register Description (Continued)

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8

ADDR REG
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
EVENT MANAGER (EVA) INTERRUPT CONTROL REGISTERS (CONTINUED)
T1OFINT T1UFINT T1CINT
— — — — —
FLAG FLAG FLAG
0742Fh EVAIFRA
T1PINT CMP3INT CMP2INT CMP1INT PDPINTA
— — —
FLAG FLAG FLAG FLAG FLAG
— — — — — — — —
07430h T2OFINT T2UFINT T2CINT T2PINT EVAIFRB
— — — —
FLAG FLAG FLAG FLAG
— — — — — — — —
07431h CAP3INT CAP2INT CAP1INT EVAIFRC
— — — — —
FLAG FLAG FLAG
07432h
to Illegal
074FFh
07500h
to Reserved
0753Fh
I/O MEMORY SPACE
— — — — — — — —
0FF0Fh FCMR
— — — — — — — —
WAIT-STATE GENERATOR CONTROL REGISTER
— — — — — BVIS.1 BVIS.0 ISWS.2
0FFFFh WSGR
ISWS.1 ISWS.0 DSWS.2 DSWS.1 DSWS.0 PSWS.2 PSWS.1 PSWS.0

These bits are not applicable in the Lx2401A since either (i) the peripheral functionality is absent or (ii) the corre-
sponding pins have not been bonded out of the device.

86 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443


 
  
 

SPRS161K − MARCH 2001 − REVISED JULY 2007

MECHANICAL DATA
VF (S-PQFP-G32) PLASTIC QUAD FLATPACK

0,45 0,20 M
0,80
0,25
24 17

25 16

32 9

0,13 NOM
1 8

5,60 TYP
7,20
SQ
6,80 Gage Plane
9,20
SQ
8,80
0,25
0,05 MIN
0°−ā 7°
1,45
1,35
0,75
Seating Plane 0,45

1,60 MAX 0,10

4040172/D 04/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

Typical Thermal Resistance Characteristics

PARAMETER DESCRIPTION °C / W
ΘJA Junction-to-ambient 55.61
ΘJC Junction-to-case 13.89
ψJT Junction-to-top of package 2.5

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 87

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