Sequential Logic Design

D IIgor Ivkovic
Dr. I k i
[email protected]
@

[with material from “Computer Organization and Design” by Patterson and Hennessy, and “Digital Design and
Computer Architecture” by Harris and Harris, both published by Morgan Kaufmann]
Objectives

 Introduction to Sequential Logic Circuits

 Latches, Flip-Flops, and Registers
 Synchronous Logic Design
 Finite S
State Machines

2
Sequential Logic Circuit /1
 Sequential Logic Circuit – It Has Memory
 Outputs of a sequential logic circuit depend on the current and
th prior
the i iinputt values
l

 State:
 All the information about a circuit necessary to explain its future
behavior

 Latches and Flip-Flops:

p p
 State elements that store one bit of state

 Synchronous
y Sequential
q Circuits:
 Combinational logic followed by a bank of flip-flops

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Sequential Logic Circuit /2
 Sequential Logic Circuits:
 Give sequence to events
 Have (short-term) memory
 Use feedback from output to input to store information

 St t El
State Elements:
t
 The state of a circuit influences its future behavior
 State elements store the circuit state

 State elements include:

 Bistable circuit
 SR Latch
 D Latch
 D Flip-flop

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Bistable Circuit /1
 Bistable Circuit:
 Fundamental building block of other state elements
 Two outputs: Q, Q
 No inputs

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Bistable Circuit /2
 Consider the two possible cases:
 Q = 0: then Q = 1, Q = 0 (stable)

 Q = 1: then Q = 0, Q = 1 (also stable); 1

I1 Q
hence, called bistable 0

1 0
I2 Q
 Stores 1 bit of state in the state variable, Q (or Q)
 But there are no inputs to control the state

6
SR (Set/Reset) Latch /1
 SR (Set/Reset) Latch:
 Composed of two cross-coupled
NOR gates
t
 It has two inputs, S and R, and
two outputs, Q and Q

 Consider the four possible cases:

 S = 1, R = 0
 S = 0, R = 1
 S = 0, R = 0
 S = 1,
1 R=1

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SR (Set/Reset) Latch /2
 SR Latch analysis:
 S = 1, R = 0:
th Q = 1 and
then dQ=0

 S = 0, R = 1:
then Q = 1 and Q = 0

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SR (Set/Reset) Latch /3
 SR Latch Qprev Qprev
 S = 0, R = 0:
then Q = Qprev R R
Q Q

 That is,
is we have
MEMORY since
Q = Qprev Q Q
S S

 S = 1, R = 1:
then Q = 0, Q = 0
 We have an invalid state
since Q ≠ NOT Q

9
SR (Set/Reset) Latch /4
 SR Latch Summary:
 Stores one bit of state (Q)
 Control what value is being stored with S, R as inputs
 Set: Make the output 1 (S = 1, R = 0, Q = 1)
 Reset: Make the output 0 (S = 0
0, R = 1
1, Q = 0)
 Must do something to avoid invalid state (when S = R = 1)

 Can be implemented in different ways as long as it

corresponds to the following truth table

10
D Latch /1
 D Latch:  Operational
 Sequential logic circuit functionality:
element
l t that
th t separates
t  When CLK = 1, D passes
the state data from the through to Q (transparent)
timing of state change
 When CLK = 0, Q holds
 Two inputs: clock input its previous value
signal (CLK), data input (opaque)
signal (D)
 Avoids invalid case
 CLK signal: controls when Q ≠ NOT Q
when the output
changes
 D signal/bit: controls to
what the output
changes

11
D Latch /2
Remembers the
previous state if CLK = 0;
 D Latch Internals: otherwise Q equals D

S and R cannot
both be 1

12
D Flip-Flop /1
 D Flip-Flop:
 Sequential logic circuit built from two D latches controlled by
CLK and
d its
it complement
l t
 Two Inputs: CLK, D

 Operational functionality:
 Samples D on the rising edge of CLK
 When CLK rises from 0 to 1,
D passes through to Q
 Otherwise, Q holds its previous value
 Hence Q changes only on the rising edge of CLK
Hence,

 Also called edge-triggered

 Since it is activated on the clock edge

13
D Flip-Flop /2
 D Flip-Flop explained:
 Two back-to-back latches (L1 and L2) controlled by the clock
(CLK) signal and its complement
 When CLK = 0
 L1 is transparent
 L2 is opaque
 D passes through to N1
 When CLK = 1
 L2 is transparent
 L1 is opaque
 N1 passes through to Q
 Hence, on the edge of the clock (when CLK rises from 0 to 1)
 D passes th
through
h to
t Q

 Fun Trivia:
 How many transistors are needed to build a typical D flip flop?
 Hint: 2 transistors for NOT gate, 4 for NAND and NOR

14
D Flip-Flop /3
 D Latch vs. D Flip-Flop:

Q changes to D on Q changes to D on
clock edge only clock edge only
15
Register Introduced
 N-bit Register:
 A grouping of N flip-flops that
share
h a common CLK iinput, t so
that all bits of the register are 0 0
updated at the same time

 Example: 4-bit register

1 1

2 2

3 3

16
Enabled Flip-Flop
 Enabled D Flip-Flop:
 D passes through to Q only when enable (EN) is true
 Inputs: CLK, D, EN
 The enable input (EN) controls when new data (D) is stored

 O
Operational
ti l functionality:
f ti lit
 EN = 1: D passes through to Q on the clock edge
 EN = 0: the flip-flop
flip flop retains its previous state

17
Set and Reset Flip-Flops
 Set Flip-Flop:
 Inputs: CLK, D, Set

 Operational functionality:
 Set = 1: Q is forced to 1
 Set = 0: flip-flop behaves as
an ordinary D flip-flop

 Reset Flip-Flop:
 Inputs: CLK, D, Reset

 Operational functionality:
 Reset = 1: Q is forced to 0
 Reset = 0: flip-flop behaves as
an ordinary
di D fli
flip-flop
fl r

18
Synchronous Logic Design /1
 Consider the following problematic circuit:

 No inputs and 1
1-3
3 outputs
 The circuit oscillates and it is not stable
 It has a cyclic path: output is fed back as input

19
Synchronous Logic Design /2
 Breaks cyclic paths by inserting registers
 Registers contain state of the system
 St t changes
State h att clock
l k edge:
d system
t synchronized
h i d tto th
the clock
l k
 Rules of synchronous sequential circuit
composition:
 Every circuit element is either a register or a combinational
logic circuit
 At least one circuit element is a register
 All registers receive the same clock signal
 Every cyclic path contains at least one register
 Two common synchronous sequential circuits:
 Finite State Machines (FSMs)
 Pipelines

20
Synchronous Logic Design /3
 Finite State Machine (FSM) consists of:
 State register
 Combinational logic

 State register:
 Stores the current state
 Loads the next state at clock edge

 C
Combinational
bi ti l (combinatorial)
( bi t i l) logic:
l i
 Computes the next state
 Computes
p the outputs
p
Next State
Logic
Next
e t
State

21
Finite State Machines /1
 In a FSM:
 The next state is determined by the current state and inputs
 Two types of finite state machines differ in output logic:
 Moore FSM: outputs depend only on the current state
 Mealy FSM: outputs depend on the current state and inputs

22
Finite State Machines /2
 Finite-State Digital Controller:

23
Finite State Machines /3
 Traffic light problem:
 Traffic sensors: TA, TB (TRUE when there’s traffic)
 Lights: LA, LB

24
Finite State Machines /4
 Traffic light controller:
 Inputs: CLK, Reset, TA, TB
 Outputs: LA, LB
Seagram
Drr.

25
Finite State Machines /5
 Traffic light FSM:
 Moore FSM: outputs labeled in each state
 States: Circles TA
Reset
 Transitions: Arcs TA
LA LA
Seagram

LB LB

LA LA
LB LB
Drr.

TB
TB
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 Finite State Machines /6
 Traffic light FSM:

Reset
TA Current Next
S0 TA S1 State Inputs State
LA: green LA: yellow
ll
LB: red LB: red S TA TB S'
S0 0 X S1
S0 1 X S0
S3 S2 S1 X X S2
LA: red LA: red
LB: yellow
TB
LB: green S2 X 0 S3
TB
S2 X 1 S2
S3 X X S0

27
 Finite State Machines /7
 FSM state encoding and state transition table:

St t
State E
Encoding
di Current Next
State Inputs State
S0 00 S1 S0 TA TB S'1 S'0
S1 01 0 0 0 X 0 1
S2 10 0 0 1 X 0 0
0 1 X X 1 0
S3 11
1 0 X 0 1 1
S'1 = S1 ⊕ S0 1 0 X 1 1 0
S'0 = S1S0TA + S1S0TB 1 1 X X 0 0

28
Finite State Machines /8
 FSM output encoding and output table:

Current
Output Encoding
State Outputs
green 00 S1 S0 LA1 LA0 LB1 LB0
yellow 01 0 0 0 0 1 0
red
d 10 0 1 0 1 1 0
1 0 1 0 0 0
LA1 = S1 1 1 1 0 0 1
LA0 = S1S0
LB1 = S1
LB0 = S1S0
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Finite State Machines /9
 FSM Schematic: State Register

30
Finite State Machines /10
 FSM Schematic: Next State Logic

S'1 = S1 ⊕ S0
S'0 = S1S0TA + S1S0TB
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Finite State Machines /11
 FSM Schematic: Output Logic

LA1 = S1 LB1 = S1
LA0 = S1S0 LB0 = S1S0
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Finite State Machines /12
 FSM binary state encoding:
 For four states: 00, 01, 10, 11

 FSM one-hot encoding:

 One state bit per state
 Only one state bit is true at one time
 For four states: 0001, 0010, 0100, 1000
 One hot encoding can run at higher clock rate but it requires
One-hot
more circuitry (i.e., a flip-flop for each bit)

33
More on Finite State Machines /1
 Snail’s Brain Example:
 Alyssa P. Hacker has a snail that crawls down a paper tape
with
ith 1’
1’s and
d 0’
0’s on it
 The snail smiles whenever the last two digits it has crawled
over are 01
 Design Moore FSM of the snail’s brain

34
More on Finite State Machines /2
 Snail’s Brain Example:
 Alyssa P. Hacker has a snail that crawls down a paper tape
with
ith 1’
1’s and
d 0’
0’s on it
 The snail smiles whenever the last two digits it has crawled
over are 01
 Design Moore and Mealy FSMs of the snail’s brain

35
More on Finite State Machines /3
 Snail’s Brain Example:

Current Next
State Inputs State
S1 S0 A S'1 S'0
0 0 0 0 1
0 0 1 0 0
0 1 0 0 1
0 1 1 1 0
State Encoding
1 0 0 0 1
S0 00 1 0 1 0 0
S1 01 Not always true;
S1’ = S0A but why here?
S2 10
S0’ = A (S1 + S0) = A
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More on Finite State Machines /4
 Snail’s Brain Example:

Current
State Output
S1 S0 Y
0 0 0
0 1 0
1 0 1
Y = S1

37
More on Finite State Machines /5
 Snail’s Brain Example:
 Mealy FSM: arcs indicate input/output
Mealy FSM
Reset
0/0 Current Next
State Input State Output
S0 S1
S0 A S'0 Y
1/0 0/0

1/1
0 0 1 0
0 1 0 0
1 0 1 0
State Encoding 1 1 0 1
S0 00
Y = S0A
S1 01 S0’= A

38
More on Finite State Machines /6
 Moore FSM Schematic:
Y = S1
A CLK
S'1 S1
Y

S 1’ = S 0A
S'0 S0 S 0’ = A
r
Reset

39
More on Finite State Machines /7
 Mealy FSM Schematic:

CLK
S'0 S0 Y

Y = S0A r
S 0’ = A Reset

40
More on Finite State Machines /8
 Designing FSMs Summary:
1. Identify inputs and outputs
2. Sketch a state transition diagram
3. Write state transition table
4
4. Select state encodings
5. Rewrite state transition table with state encodings
6. Write output table
7. Sketch the circuit schematic

41
Factoring State Machines /1
 Factoring a FSM:
 Break a complex FSMs into smaller interacting FSMs

 Example:
 Modify traffic light controller to add Special Mode
 Two more inputs: P, R
 When P = 1, enter the Special Mode and Seagram Dr. light
stays green (e.g., under construction, special University events)
 When R = 1, leave the Special Mode

42
Factoring State Machines /2
 Unfactored FSM:  Factored FSM:

TA LA

TB LB

43
Factoring State Machines /3
 Unfactored FSM:

44
Factoring State Machines /4
 Factored FSM:

45
Food for Thought
 Download and Read Assignment #1 Specifications:
 Assignment #1 is intended as an introduction to the
combinatorial
bi t i l llogic
i ddesign
i

 Read:
 Appendix C and Appendix D of the course textbook
 Review the material discussed in the lecture notes in more detail
 (Optional) Chapter 3 of the Harris and Harris textbook

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