lOMoARcPSD|49222686

Computer architecture-21-40

Computer Organization & Architecture (Babu Banarasi Das University)

Scan to open on Studocu

Studocu is not sponsored or endorsed by any college or university

Downloaded by The Bold ([email protected])
 lOMoARcPSD|49222686

Timing and Control

The timing for all registers in the basic computer is controlled by a master clock generator.
The clock pulses are applied to all flip-flops and registers in the system, including the flip-
flops and registers in the control unit. The control signals are generated in the control unit and
provide control inputs for the multiplexers in the common bus, control inputs in processor
registers, and microoperations for the accumulator.
There are two major types of control organization:
1- hardwired control : the control logic is implemented with gates, flip-flops, decoders,
and other digital circuits. It has the advantage that it can be optimized to produce a fast
mode of operation.
2- microprogrammed control: the control information is stored in a control memory. The
control memory is programmed to initiate the required sequence of microoperations.

The block diagram of the control unit is shown in Fig(17):

SC is incremented with every positive clock transition, unless its CLR input is active.
This produces the sequence of timing signals T0, T1, T2, T3, T4, and so on, as shown in the
diagram. (Note the relationship between the timing signal and its corresponding positive
21

Downloaded by The Bold ([email protected])

 lOMoARcPSD|49222686

clock transition.) If SC is not cleared, the timing signals will continue with T5, T6, up to T15
and back to T0.
As an example, consider the case where SC is incremented to provide timing signals T 0, T1
T2, T3, and T4 in sequence. At time T4, SC is cleared to 0 if decoder output D3 is active. This
is expressed symbolically by the statement
𝐷3 𝑇4 : 𝑆𝐶 ← 0

Instruction Cycle
A program residing in the memory unit of the computer consists of a sequence of
instructions. The program is executed in the computer by going through a cycle for each
instruction. In the basic computer each instruction cycle consists of the following phases:
1. Fetch an instruction from memory.
2. Decode the instruction.
3. Read the effective address from memory if the instruction has an indirect address.
4. Execute the instruction.
This process continues indefinitely unless a HALT instruction is encountered. Initially, the
program counter PC is loaded with the address of the first instruction in the program. The
sequence counter SC is cleared to 0, providing a decoded timing signal T 0. After each clock
pulse, SC is incremented by one, so that the timing signals go through a sequence T0, T1, T2,
and so on. The microoperations for the fetch and decode phases can be specified by the
following register transfer statements.
𝑇0 : 𝐴𝑅 ← 𝑃𝐶
𝑇1 : 𝐼𝑅 ← 𝑀[𝐴𝑅], 𝑃𝐶 = 𝑃𝐶 + 1
𝑇2 : 𝐷0 , , , , 𝐷7 ← 𝐷𝑒𝑐𝑜𝑑𝑒 𝐼𝑅(12 − 14), 𝐴𝑅 ← 𝐼𝑅(0 − 11), 𝐼 ← 𝐼𝑅(15)

22

Downloaded by The Bold ([email protected])

 lOMoARcPSD|49222686

It is necessary to use timing signal T1 to provide the following connections in the bus system.

1. Enable the read input of memory.

2. Place the content of memory onto the bus by making S2S1S0 =111.
3. Transfer the content of the bus to IR by enabling the LD input of IR.
4. Increment PC by enabling the INR input of PC.

Memory - Reference Instructions

The table(11) lists the seven memory-reference instructions. The decoded output D, for
i = 0,1, 2, 3, 4, 5, and 6 from the operation decoder that belongs effective address to each
instruction is included in the table. The effective address of the instruction is in the address
register AR and was placed there during timing signal T2 when I = 0, or during timing signal
T3 when I=1. The symbolic description of each instruction is specified in the table in terms of
register transfer notation. The actual execution of the instruction in the bus system will require
a sequence of microoperations.

Input - Output and Interrupt

A computer can serve no useful purpose unless it communicates with the external
environment. Instructions and data stored in memory must come from some input device. The
input-output configuration is shown in Fig(18). The transmitter interface receives serial
information from the keyboard and transmits it to INPR. The receiver interface receives
information from OUTR and sends it to the printer serially. The 1-bit input flag FGI is a
control flip-flop. The flag bit is set to 1 when new information is available in the input device
and is cleared to 0 when the information is accepted by the computer. The output register
OUTR works similarly but the direction of information flow is reversed. Initially, the output
flag FGO is set to 1. The computer checks the flag bit; if it is 1, the information from AC is
transferred in parallel to OUTR and FGO is cleared to 0.

23

Downloaded by The Bold ([email protected])

 lOMoARcPSD|49222686

Input and output instructions are needed for transferring information to and from AC
register, for checking the flag bits, and for controlling the interrupt facility. Input-output
instructions have an operation code 1111 and are recognized by the control when D7 = 1 and I
= 1. The remaining bits of the instruction specify the particular operation. The control
functions and microoperations for the input-output instructions are listed in Table(12). These
instructions are executed with the clock transition associated with timing signal T3.

Consider a computer that can go through an instruction cycle in 1µs. Assume that the
input-output device can transfer information at a maximum rate of 10 characters per second.
This is equivalent to one character every 100,000µs. Two instructions are executed when the
computer checks the flag bit and decides not to transfer the information. This means that at the
maximum rate, the computer will check the flag 50,000 times between each transfer. The
computer is wasting time while checking the flag instead of doing some other useful
processing task.

24

Downloaded by The Bold ([email protected])

 lOMoARcPSD|49222686

The way that the interrupt is handled by the computer can be explained by means of the
flowchart of Fig(19). An interrupt flip-flop R is included in the computer.

Design of Basic Computer

The basic computer consists of the following hardware components:
1. A memory unit with 4096 words of 16 bits each
2. Nine registers: AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC
3. Seven flip-flops: I, S, E, R, IEN, FGI, and FGO
4. Two decoders: a 3 x 8 operation decoder and a 4 x 16 timing decoder
5. A 16-bit common bus
6. Control logic gates
7. Adder and logic circuit connected to the input of AC
The outputs of the control logic circuit are:
1. Signals to control the inputs of the nine registers
2. Signals to control the read and write inputs of memory
3. Signals to set, clear, or complement the flip-flops
4. Signals for S2, S1, and S0 to select a register for the bus
5. Signals to control the AC adder and logic circuit.
25

Downloaded by The Bold ([email protected])

 lOMoARcPSD|49222686

Design of Accumulator Logic

The circuits associated with the AC register are shown in Fig(20). The adder and logic
circuit has three sets of inputs.

In order to design the logic associated with AC, it is necessary to go over the register transfer
statements and extract all the statements that change the content of AC.

Control Memory
The function of the control unit in a digital computer is to initiate sequences of
microoperations. The number of different types of microoperations that are available in a
given system is finite.A control unit whose binary control variables are stored in memory is
called a microprogrammed control unit. Each word in control memory contains within it a
microinstruction. The microinstruction specifies one or more microoperations for the system.
A sequence of microinstructions constitutes a microprogram.
A computer that employs a microprogrammed control unit will have two separate memories: a
main memory and a control memory. The main memory is available to the user for storing the
programs. The contents of main memory may alter when the data are manipulated and every
time that the program is changed. The user's program in main memory consists of machine
26

Downloaded by The Bold ([email protected])

 lOMoARcPSD|49222686

instructions and data. While the control memory holds a fixed microprogram that cannot be
altered by the occasional user.
The general configuration of a microprogrammed control unit is demonstrated in the block
diagram of Fig(21).

Address Sequencing
Microinstructions are stored in control memory in groups, with each group routine
specifying a routine. An initial address is loaded into the control address register when power
is turned on in the computer. This address is usually the address of the first microinstruction
that activates the instruction fetch routine. The fetch routine may be sequenced by
incrementing the control address register through the rest of its microinstructions.
In summary, the address sequencing capabilities required in a control memory are:
1. Incrementing of the control address register.
2. Unconditional branch or conditional branch, depending on status bit conditions.
3. A mapping process from the bits of the instruction to an address for control memory.
4. A facility for subroutine call and return.

Instruction format:
The computer instruction format is depicted in Fig(22-a). It consists of three fields: a 1-
bit held for indirect addressing symbolized by J, a 4-bit operation code (opcode), and an 11-
bit address field. Fig(22-b) lists four of the 16 possible memory-reference instructions.

27

Downloaded by The Bold ([email protected])

 lOMoARcPSD|49222686

Microinstruction Format
The microinstruction format for the control memory is shown in Fig(23). The format 20
bits of the microiristruction are divided into four functional parts. The three fields Fl, F2, and
F3 specify microoperations for the computer. The CD field selects status bit conditions. The
BR field specifies the type of branch to be used. The AD field contains a branch address. The
address field is seven bits wide, since the control memory has 128 = 2 7 words.
The microoperations are subdivided into three fields of three bits each. The three bits in each
field are encoded to specify seven distinct microoperations as listed in Table(13). This gives a
total of 21 microoperations.
The CD (condition) field consists of two bits which are encoded to specify four status bit
conditions as listed in Table. The first condition is always a 1, so that a reference to CD = 00
(or the symbol U) will always find the condition to be true. When this condition is used in
conjunction with the BR (branch) field, it provides an unconditional branch operation. The
indirect bit I is available from bit 15 of DR after an instruction is read from memory. The sign
bit of AC provides the next status bit.

28

Downloaded by The Bold ([email protected])

 lOMoARcPSD|49222686

Design of Control Unit

The Fig(24) shows the three decoders and some of the connections that must be made
from their outputs. Each of the three fields of the microinstruction presently available in the
output of control memory are decoded with a 3x8 decoder to provide eight outputs. For
example, when Fl = 101 (binary 5), the next clock pulse transition transfers the content of
DK(0-10) to AR (symbolized by DRTAR in Table). Similarly, when Fl = 110 (binary 6) there
is a transfer from PC to AR (symbolized by PCTAR).

Central Processing Unit

The CPU is made up of three major parts, as shown in Fig(25).
1- The register set stores intermediate data used during the execution of the instructions.
The arithmetic
2- logic unit (ALU) performs the required microoperations for executing the instructions.
3- The control unit supervises the transfer of information among the registers and instructs
the ALU as to which operation to perform.

29

Downloaded by The Bold ([email protected])

 lOMoARcPSD|49222686

General Register Organization

The memory locations are needed for storing pointers, counters, return addresses,
temporary results, and partial products during multiplication.
A bus organization for seven CPU registers is shown in Fig(26):

The control unit that operates the CPU bus system directs the information flow through
the registers and ALU by selecting the various components in the system. For example, to
perform the operation:
30

Downloaded by The Bold ([email protected])

 lOMoARcPSD|49222686

𝑅1 ← 𝑅2 + 𝑅3

The control must provide binary selection variables to the following selector inputs:
1. MUX A selector (SELA): to place the content of R2 into bus A.
2. MUX B selector (SELB): to place the content of R3 into bus B.
3. ALU operation selector (OPR): to provide the arithmetic addition A + B.
4. Decoder destination selector (SELD): to transfer the content of the output bus into Rl.
To achieve a fast response time, the ALU is constructed with high-speed circuits.
There are 14 binary selection inputs in the unit, and their combined value control word
specifies a control word. The three bits of SELA select a source register for the A input of the
ALU. The three bits of SELB select a register for the B input of the ALU. The three bits of
SELD select a destination register using the decoder and its seven load outputs. The five bits
of OPR select one of the operations in the ALU.
The encoding of the register selections is specified in Table(14):

Table(15) OPR field has five bits and each operation is designated with a symbolic name.

31

Downloaded by The Bold ([email protected])

 lOMoARcPSD|49222686

For example, the subtract microoperation given by the statement:

𝑅1 ← 𝑅2 − 𝑅3

The binary control word for the subtract microoperation is 010 01l 001 00101 and is obtained
as follows:

Stack Organization
A useful feature that is included in the CPU of most computers is a stack or last-in, first-
out (LIFO) list. The two operations of a stack are the insertion and deletion of items. The
operation of insertion is called push, while the operation of deletion is called pop. In a 64-word
stack, the stack pointer contains 6 bits because 26 = 64.
The push operation is implemented with the following sequence of microoperations:

The pop operation consists of the following sequence of microoperations:

Instruction Formats
The format of an instruction is usually depicted in a rectangular box symbolizing the
bits of the instruction as they appear in memory words or in a control register. The bits of the
instruction are divided into groups called fields. The most common fields found in instruction
formats are:
1. An operation code field that specifies the operation to be performed.
2. An address field that designates a memory address or a processor register.
3. A mode field that specifies the way the operand or the effective address is determined.
An example of an accumulator-type organization, the instruction that specifies an arithmetic
addition is defined by an assembly language instruction as:
32

Downloaded by The Bold ([email protected])

 lOMoARcPSD|49222686

𝐴𝐷𝐷 𝑋
Where 𝑋 is the address of the operand. The ADD instruction in this case results in the
operation:
𝐴𝐶 ← 𝐴𝐶 + 𝑀[𝑋]
An example of a general register type of organization the instruction for an arithmetic addition
may be written in an assembly language as:
𝐴𝐷𝐷 𝑅1, 𝑅2, 𝑅3
to denote the operation:
𝑅1 ← 𝑅2 + 𝑅3
The following is a program to evaluate 𝑋 = (𝐴 + 𝑏) ∗ (𝐶 + 𝐷) :
with three-address instruction formats as:

Two-address instructions formats as:

One-address instructions use an implied accumulator (AC) register for all data manipulation
as:

Addressing Modes
Computers use addressing mode techniques for the purpose of accommodating one or
both of the following provisions:
1. To give programming versatility to the user by providing such facilities as pointers to
memory, counters for loop control, indexing of data, and program relocation.
2. To reduce the number of bits in the addressing field of the instruction.
PC holds the address of the instruction to be executed next and is incremented each time an
instruction is fetched from memory. An example of an instruction format with a distinct
addressing mode field is shown in Fig(27).

33

Downloaded by The Bold ([email protected])

 lOMoARcPSD|49222686

Immediate Mode: In this mode the operand is specified in the instruction itself. In other
words, an immediate-mode instruction has an operand field rather than an address field.
Register Mode: In this mode the operands are in registers that reside within the CPU. The
particular register is selected from a register field in the instruction.
Register Indirect Mode: In this mode the instruction specifies a register in the CPU whose
contents give the address of the operand in memory.
Auto-increment or Auto-decrement Mode: This is similar to the register indirect mode
except that the register is incremented or decremented after (or before) its value is used to
access memory.
The effective address is defined to be the memory address obtained from the computation
dictated by the given addressing mode.
Direct Address Mode: In this mode the effective address is equal to the address part of the
instruction.
Indirect Address Mode: In this mode the address field of the instruction gives the address
where the effective address is stored in memory.
The effective address in these modes is obtained from the following computation:
effective address = address part of instruction + content of CPU register
Relative Address Mode: In this mode the content of the program counter is added to the
address part of the instruction in order to obtain the effective address.
Indexed Addressing Mode: In this mode the content of an index register is added to the
address part of the instruction to obtain the effective address.
Base Register Addressing Mode: In this mode the content of a base register is added to the
address part of the instruction to obtain the effective address.

Numerical Example:
1- The two-word instruction at address 200 and 201 is a "load to AC" instruction with an
address field equal to 500.
2- The first word of the instruction specifies the operation code and mode, and the second
word specifies the address part.
3- PC has the value 200 for fetching this instruction.
4- The content of processor register Rl is 400, and the content of an index register XR is
100.
AC receives the operand after the instruction is executed. The Fig(28) lists a few pertinent
addresses and shows the memory content at each of these addresses.
34

Downloaded by The Bold ([email protected])

 lOMoARcPSD|49222686

Answer:
1- In the direct address mode the effective address is the address part of the instruction 500
and the operand to be loaded into AC is 800.
2- In the immediate mode the second word of the instruction is taken as the operand rather
than an address, so 500 is loaded into AC. (The effective address in this case is 201)
3- In the indirect mode the effective address is stored in memory at address 500. Therefore,
the effective address is 800 and the operand is 300.
4- In the relative mode the effective address is 500 + 202 = 702 and the operand is 325.
(Note that the value in PC after the fetch phase and during the execute phase is 202)
5- In the index mode the effective address is XR + 500 = 100 + 500 = 600 and the operand
is 900.
6- In the register mode the operand is in Rl and 400 is loaded into AC. (There is no
effective address in this case)
7- In the register indirect mode the effective address is 400, equal to the content of Rl and
the operand loaded into AC is 700.
8- The auto-increment mode is the same as the register indirect mode except that Rl is
incremented to 401 after the execution of the instruction.
9- The auto-decrement mode decrements Rl to 399 prior to the execution of the instruction.
The operand loaded into AC is now 450.
Table (16) lists the values of the effective address and the operand loaded into AC for the
nine addressing modes.
35

Downloaded by The Bold ([email protected])

 lOMoARcPSD|49222686

Data Transfer and Manipulation

Most computer instructions can be classified into three categories:
1. Data transfer instructions.
2. Data manipulation instructions.
3. Program control instructions.
Data transfer instructions cause transfer of data from one location to another without changing
the binary information content. The table(17) list the Data transfer instructions:

Data manipulation instructions are those that perform arithmetic, logic, and shift operations.
The data manipulation instructions in a typical computer are usually divided into three basic
types:
1- Arithmetic instructions.
2. Logical and bit manipulation instructions.
3. Shift instructions.

Reduced Instruction Set Computer (RISC)

An important aspect of computer architecture is the design of the instruction set for the
processor. The instruction set chosen for a particular computer determines the way that
machine language programs are constructed. A computer with a large number of instructions is
classified as a complex instruction set computer, abbreviated CISC. In the early 1980s, a
36

Downloaded by The Bold ([email protected])

 lOMoARcPSD|49222686

number of computer designers recommended that computers use fewer instructions with
simple constructs so they can be executed much faster within the CPU without having to use
memory as often. This RISC type of computer is classified as a reduced instruction set
computer or RISC.
In summary, the major characteristics of CISC architecture are:
1. A large number of instructions—typically from 100 to 250 instructions.
2. Some instructions that perform specialized tasks and are used infrequently.
3. A large variety of addressing modes—typically from 5 to 20 different modes.
4. Variable-length instruction formats.
5. Instructions that manipulate operands in memory.
The major characteristics of a RISC processor are:
1. Relatively few instructions.
2. Relatively few addressing modes.
3. Memory access limited to load and store instructions.
4. All operations done within the registers of the CPU.
5. Fixed-length, easily decoded instruction format.
6. Single-cycle instruction execution.
7. Hardwired rather than microprogrammed control.

Memory Hierarchy
The memory unit is an essential component in any digital computer since it is needed
for storing programs and data. The memory unit that communicates directly with the CPU is
called the main memory. Devices that provide backup storage are called auxiliary memory.
They are used for storing system programs, large data files, and other backup information.
Only programs and data currently needed by the processor reside in main memory. All other
information is stored in auxiliary memory and transferred to main memory when needed.
A special very-high-speed memory called a cache is sometimes used to increase the speed of
processing by making current programs and data available to the CPU at a rapid rate. Fig(29)
shows the Memory Hierarchy:

37

Downloaded by The Bold ([email protected])

 lOMoARcPSD|49222686

Main Memory The main memory is the central storage unit in a computer system. It is a
relatively large and fast memory used to store programs and data during the computer
operation. The principal technology used for the main memory is based on semiconductor
integrated circuits. Integrated circuit RAM chips are available in two possible operating
modes:
The static RAM consists essentially of internal flip-flops that store the binary information.
The dynamic RAM stores the binary information in the form of electric charges that are applied
to capacitors.

Associative Memory
Many data-processing applications require the search of items in a table stored in
memory. An assembler program searches the symbol address table in order to extract the
symbol's binary equivalent.
A memory unit accessed by content is called an associative memory or content
addressable memory (CAM). When a word is written in an associative memory is capable of
finding an empty unused location to store the word. When a word is to be read from an
associative memory, the content of the word, or part of the word, is specified. The memory
locates all words which match the specified content and marks them for reading.
The block diagram of an associative memory is shown in Fig(30):

To illustrate with a numerical example, suppose that the argument register A and the key
register K have the bit configuration shown below. Only the three left most bits of A are
compared with memory words because K has l's in these positions.

38

Downloaded by The Bold ([email protected])

 lOMoARcPSD|49222686

Word 2 matches the unmasked argument field because the three leftmost bits of the argument
and the word are equal.

Cache Memory
If the active portions of the program and data are placed in a fast small memory, the
average memory access time can be reduced, thus reducing the total execution time of the
program. Such a fast small memory is referred to as a cache memory. It is placed between the
CPU and main memory.
The basic operation of the cache is as follows. When the CPU needs to access memory,
the cache is examined. If the word is found in the cache, it is read from the fast memory. If the
word addressed by the CPU is not found in the cache, the main memory is accessed to read the
word. The performance of cache memory is frequently measured in terms of a quantity called
hit ratio. When the CPU refers to memory and finds the word in cache, it is said to produce a
hit. If the word is not found in cache, it is in main memory and it counts as a miss.
Three types of mapping procedures are of practical interest when considering the
organization of cache memory:
1. Associative mapping
2. Direct mapping
3. Set-associative mapping

Virtual Memory
Virtual memory is a concept used in some large computer systems that permit the user to
construct programs as though a large memory space were available, equal to the totality of
auxiliary memory. Virtual memory is used to give programmers the illusion that they have a
very large memory at their disposal, even though the computer actually has a relatively small
main memory. A virtual memory system provides a mechanism for translating program-
generated addresses into correct main memory locations.
As an illustration, consider a computer with a main-memory capacity of 32K words (K =
1024). Fifteen bits are needed to specify a physical address in memory since 32K = 2 15.
Suppose that the computer has available auxiliary memory for storing 2 20 = 1024K words.
Thus auxiliary memory has a capacity for storing information equivalent to the capacity of 32
main memories. Denoting the address space by N and the memory space by M, we then have
for this example N = 1024K and M = 32K.
The mapping table may be stored in a separate memory as shown in Fig(31) or in main
memory. In the first case, an additional memory unit is required as well as one extra memory

39

Downloaded by The Bold ([email protected])

 lOMoARcPSD|49222686

access time. In the second case, the table takes space from main memory and two accesses to
memory are required with the program running at half speed.

The table implementation of the address mapping is simplified if the information in the
address space and the memory space are each divided into groups of fixed size. The physical
memory is broken down into groups of equal size pages and blocks called blocks, which may
range from 64 to 4096 words each. The term page refers to groups of address space of the
same size. For example, if a page or block consists of IK words, then, using the previous
example, address space is divided into 1024 pages and main memory is divided into 32 blocks.
The organization of the memory mapping table in a paged system is shown in Fig(32).
The memory-page table consists of eight words, one for each page. The address in the page
table denotes the page number and the content of the word gives the block number where that
page is stored in main memory. The table shows that pages 1, 2, 5, and 6 are now available in
main memory in blocks 0, 1, 2, and 3, respectively. A presence bit in each location indicates
whether the page has been transferred from auxiliary memory into main memory. A0 in the
presence bit indicates that this page is not available in main memory.

40

Downloaded by The Bold ([email protected])