Chapter 4

Register Transfer Language and Micro Operations

Microinstructions

The control unit seems a reasonably simple device. Nevertheless, to implement a control unit as
an interconnection of basic logic elements is no easy task. The design must include logic for
sequencing through micro-operations, for executing micro operations, for interpreting opcodes,
and for making decisions based on ALU flags. It is difficult to design and test such a piece of
hardware. Furthermore, the design is relatively inflexible. For example, it is difficult to change
the design if one wishes to add a new machine instruction.

To implement a microprogrammed control unit microinstructions mainly used in CISC

processors. A programming language used to write microinstructions is called
microprogramming language. Each line describes a set of micro-operations occurring at one time
and is known as a microinstruction. A sequence of instructions is known as a microprogram, or
firmware.

Microprogram is midway between hardware and software. It is easier to design in firmware than
hardware, but it is more difficult to write a firmware program than a software program.
Microprogram initiates the functions of control unit. Control unit has a special component that
stores the arrangement of control words or microinstructions.

4.1. Register Transfer Language

Mostly register transfer language referred as assembly language. Assembly language is the
symbolic representation of a computer’s binary encoding the machine language. Machine
language is a binary representation used for communication within a computer system. The
symbols in assembly language name commonly occur in bit patterns, such as opcodes and
register specifiers, so people can read and remember them. In addition, assembly language
permits programmers to use labels to identify and name particular memory words that hold
instructions or data. A tool called an assembler translates assembly language into binary
instructions. Assemblers provide a friendlier representation than a computer’s 0s and 1s, which
simplifies writing and reading programs.

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4.2. Bus and Memory Transfer

Bus is collection of data lines that is treated together as a single logical signal; also, a shared
collection of lines with multiple sources and uses.

4.3. Arithmetic and Logic Operations

4.4. Shift Micro Operations

The execution of an instruction involves the execution of a sequence of sub-steps, generally

called cycles. For example, an execution may consist of fetch, indirect, execute, and interrupt
cycles. Each cycle is in turn made up of a sequence of more fundamental operations, called
micro-operations. A single micro-operation generally involves a transfer between registers, a
transfer between a register and an external bus, or a simple ALU operation. Each instruction is
executed during an instruction cycle made up of shorter sub-cycles. Micro-operations are the
functional or atomic operations of a processor.

Figure 4.1. Constituent Elements of a Program Execution

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 Fetch Cycle

A fetch cycle occurs at the beginning of each instruction cycle and causes an instruction to be
fetched from memory. Four registers are involved:

 Memory address register (MAR): Is connected to the address lines of the system bus. It
specifies the address in memory for a read or write operation.
 Memory buffer register (MBR): Is connected to the data lines of the system bus. It
contains the value to be stored in memory or the last value read from memory.
 Program counter (PC): Holds the address of the next instruction to be fetched.
 Instruction register (IR): Holds the last instruction fetched.

Figure 4.1 elaborates the sequence of events for the fetch cycle. At the beginning of the fetch
cycle, the address of the next instruction to be executed is in the program counter (PC); in this
case, the address is 1100100. The first step is to move that address to the memory address
register (MAR) because this is the only register connected to the address lines of the system bus.

The second step is to bring in the instruction. The desired address (in the MAR) is placed on the
address bus, the control unit issues a READ command on the control bus, and the result appears
on the data bus. Meanwhile, the PC is incremented by 1, to get ready for the next instruction.
Because these two actions (read word from memory, increment PC) do not interfere with each
other, they can be done simultaneously to save time.

The third step is to move the contents of the MBR to the instruction register (IR). This frees up
the MBR for use during a possible indirect cycle.

Figure 4.2 Sequence of Events, Fetch Cycle

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Thus, the simple fetch cycle actually consists of three steps and four microoperations. Each
micro-operation involves the movement of data into or out of a register. So long as these
movements do not interfere with one another, several of them can take place during one step,
saving time. Symbolically, we can write this sequence of events as follows:

t1: MAR ← (PC)

t2: MBR ← Memory PC ← (PC) + 1

t3: IR ← (MBR)

Each micro-operation can be performed within the time of a single time unit.The notation
represents successive time units.

 First time unit: Move contents of PC to MAR.

 Second time unit: Move contents of memory location specified by MAR to MBR.
Increment by 1 the contents of the PC.
 Third time unit: Move contents of MBR to IR.

Note that the second and third micro-operations both take place during the second time unit. The
third micro-operation could have been grouped with the fourth without affecting the fetch
operation:

t1: MAR ← (PC)

t2: MBR ← Memory

t3: PC ← (PC) + 1

IR ← (MBR)

The groupings of micro-operations must follow two simple rules:

1. The proper sequence of events must be followed. Thus must precede because the memory
read operation makes use of the address in the MAR.
2. Conflicts must be avoided. One should not attempt to read to and write from the same
register in one time unit, because the results would be unpredictable. For example, the
micro-operations and should not occur during the same time unit.

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Indirect Cycle

Once an instruction is fetched, the next step is to fetch source operands. For example, assume a
one-address instruction format, with direct and indirect addressing allowed. If the instruction
specifies an indirect address, then an indirect cycle must precede the execute cycle.

Figure 4.3 Data Flow, Indirect Cycle

 Indirect cycle includes the following micro-operations:

t1: MAR ← (IR(Address))
t2: MBR ← Memory
t3: IR(Address) ← (MBR(Address))

The address field of the instruction is transferred to the MAR. This is then used to fetch the
address of the operand. Finally, the address field of the IR is updated from the MBR, so that it
now contains a direct rather than an indirect address. The IR is now in the same state as if
indirect addressing had not been used, and it is ready for the execute cycle.

The Interrupt Cycle

At the completion of the execute cycle, a test is made to determine whether any enabled
interrupts have occurred. If so, the interrupt cycle occurs. The nature of this cycle varies greatly
from one machine to another.

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 Figure 4.4 Data Flow, Interrupt Cycle

 Sequence of events involved during interrupt cycle:

t1: MBR ← (PC)

t2: MAR ← Save_Address

PC ← Routine_Address

t3: Memory ← (MBR)

In the first step, the contents of the PC are transferred to the MBR, so that they can be saved for
return from the interrupt. Then the MAR is loaded with the address at which the contents of the
PC are to be saved, and the PC is loaded with the address of the start of the interrupt-processing
routine. These two actions may each be a single micro-operation. However, because most
processors provide multiple types and/or levels of interrupts, it may take one or more additional
micro-operations to obtain the Save_Address and the Routine_Address before they can be
transferred to the MAR and PC, respectively. In any case, once this is done, the final step is to
store the MBR, which contains the old value of the PC, into memory. The processor is now ready
to begin the next instruction cycle.

The Execute Cycle

The fetch, indirect, and interrupt cycles are simple and predictable. Each involves a small, fixed
sequence of micro-operations, and in each case, the same micro-operations are repeated each
time around. This is not true of the execute cycle. Because of the variety opcodes, there are a
number of different sequences of micro-operations that can occur. Consider hypothetical
examples illustrated below.

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First, consider an add instruction:

ADD R1, X, which adds the contents of the location X to register R1. The following
sequence of micro-operations might occur:

t1: MAR ← (IR(address))

t2: MBR ← Memory
t3: R1 ← (R1) + (MBR)
It begins with the IR containing the ADD instruction. In the first step, the address portion of the
IR is loaded into the MAR. Then the referenced memory location is read. Finally, the contents of
R1 and MBR are added by the ALU. Additional micro-operations may be required to extract the
register reference from the IR and perhaps to stage the ALU inputs or outputs in some
intermediate registers.

A subroutine call instruction and conditional actions are more complex form of execution.
Example for condition and action:

A common instruction is increment and skip if zero:

ISZ X The content of location X is incremented by 1.

If the result is 0, the next instruction is skipped. A possible sequence of micro-operations is

t1: MAR ← (IR(address))

t2: MBR ← Memory
t3: MBR ← (MBR) + 1
t4: Memory ← (MBR)
If ((MBR) = 0) then (PC ← (PC) + 1)
The new feature introduced here is the conditional action. The PC is incremented if(MBR=0).
This test and action can be implemented as one micro-operation. Note also that this micro-
operation can be performed during the same time unit during which the updated value in MBR is
stored back to memory. Example for subroutine call instruction:

As an example, consider a branch and-save-address instruction:

 BSA X

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The address of the instruction that follows the BSA instruction is saved in location X, and
execution continues at location X+I. The saved address will later be used for return. This is a
straightforward technique for providing subroutine calls. The following micro-operations serve:

t1: MAR ← (IR(address))

MBR ← (PC)
t2: PC ← (IR(address))
Memory ← (MBR)
t3: PC ← (PC) + I
The address in the PC at the start of the instruction is the address of the next instruction in
sequence. This is saved at the address designated in the IR. The latter address is also incremented
to provide the address of the instruction for the next instruction cycle.

The Instruction Cycle

The instruction cycle can be decomposed into a sequence of elementary micro-operations (the
fetch, indirect, and interrupt cycles), and for the execute cycle there is one sequence of micro-
operations for each opcode.

2-bit register called the instruction cycle code (ICC), describes the state of the processor in terms
of which portion of the cycle it is in:

Code Name

00: Fetch

01: Indirect

10: Execute

11: Interrupt

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 Shift Register

A shift register is a sequential logic circuit that acts as a unit to store and transfer binary data.
Basically shift registers are bidirectional FIFO circuit that shifts every single bit of the data
present in its input towards its output on each clock pulse. Clock is one cycle in which micro-
operation executed.

Registers are the circuits constructed using flip-flops for storing binary data. One-bit of data is
stored by each flip-flop at a time. So, the storage of multiple bits of data requires multiple flip-
flops. Thus, the storing capacity of the register depends on the number of flip-flops used in its
construction.

The data bit movement inside the shift register give rise to various configurations which are as
follows:

 SISO: Serial-in Serial-out: It permits the insertion of data serially and taking the
output also in a serial manner.
 SIPO: Serial-in Parallel-out: Here the data is inserted serially but the output is
taken parallel.
 PISO: Parallel-in Serial-out: This type of shift register allows the parallel input
of data bit, but the output is taken serially.
 PIPO: Parallel-in Parallel-out: PIPO shift register permits both in and out of data
bit in a parallel manner.

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The above figure represents the 4 data output of the flip-flops.

Initially, all the outputs were 0, this is clearly shown in the waveform representation. However,
the output Q3 changes from 0 to 1 on arrival of first clock pulse. While rest other outputs are still
0. In a similar way, the second clock pulse changes Q 2 from 0 to 1. Thus, now both Q3 and Q2 are
showing logic high in the waveform representation. So, in this way the above figure is clearly
showing the SISO operation of the shift register and on the arrival of 4 th clock pulse the output of
all the 4 registers will be 1.

Applications of Shift Registers

The different configurations of shift registers provide uses in various fields like a SISO shift
register is used to generate time delay in digital circuits. A SIPO shift register can act as serial to
parallel converter. In a similar way, PISO shift register changes parallel input into serial output
thereby performing the job of a parallel to serial converter.

Shift Micro-Operations in Computer Architecture

Shift micro-operations are micro-operations that are used for the serial transfer of information.
These are also used in conjunction with arithmetic micro-operation, logic micro-operation, and
other data processing operations. There are three types of shift micro-operations:

1. Logical Shift:

It transfers the zero(0) through the serial input. We use the symbols ‘<<‘ for the logical left shift
and ‘>>‘ for the logical right shift.

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  Logical Left Shift:

In this shift, one position moves each bit to the left one by one. The Empty least significant bit
(LSB) is filled with zero (i.e, the serial input), and the most significant bit (MSB) is rejected. The
left shift operator is denoted by the double left arrow key (<<). The general syntax for the left
shift is shift-expression << k.

Note: Every time we shift a number towards the left by 1 bit it multiplies that number by 2.

 Logical Right Shift

In this shift, each bit moves to the right one by one and the least significant bit(LSB) is rejected
and the empty MSB is filled with zero. The right shift operator is denoted by the double right
arrow key (>>). The general syntax for the right shift is “shift-expression >> k”.

Note: Every time we shift a number towards the right by 1 bit it divides that number by 2.

2. Arithmetic Shift:

The arithmetic shift micro-operation moves the signed binary number either to the left or to the
right position. Following are the two ways to perform the arithmetic shift.

 Arithmetic Left Shift

 Arithmetic Right Shift
Arithmetic Left Shift:

In this shift, each bit is moved to the left one by one. The empty least significant bit (LSB) is
filled with zero and the most significant bit (MSB) is rejected. Same as the Left Logical Shift.

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Arithmetic Right Shift:

In this shift, each bit is moved to the right one by one and the least significant (LSB) bit is
rejected and the empty most significant bit (MSB) is filled with the value of the previous MSB.

 101010, here in given binary data, MSB is 1 and LSB is also 1. By Arithmetic

right shift it will be 11010

3. Circular Shift:

The circular shift circulates the bits in the sequence of the register around both ends without any
loss of information. Following are the two ways to perform the circular shift.
 Circular Shift Left
 Circular Shift Right
Circular Left Shift:

In this micro shift operation each bit in the register is shifted to the left one by one. After
shifting, the LSB becomes empty, so the value of the MSB is filled in there

Circular Right Shift:

In this micro shift operation each bit in the register is shifted to the right one by one. After
shifting, the MSB becomes empty, so the value of the LSB is filled in there.

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 End

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