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Test Pattern Verification

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Ranjit Kumar Rawani
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14 views

Test Pattern Verification

Uploaded by

Ranjit Kumar Rawani
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Test Pattern Verification: Tessent Scan & ATPG

This article introduces the Verify Test Pattern of Chapter 8 Test Pattern
Generation
in UG.
Why do we need to do timing-based simulation? The significance is that
we can
compare the differences between ATPG tools and simulator tools.
The difference in timing leads to different results.
Design Simulation with Timing.
First you need to write the pattern using the write_pattern cmd line. The
default
mode is parallel, unless you specify to write serial with -serial. Because
serial files are
very large, you can use the -sample switch to write a partial pattern. The
tool will
save at least one pattern for each type.
In addition, you can also use the -start -end switch to reduce the file size,
but such
interception is unreliable and not as reliable as -sample. In the end, you
still have to
run the full pattern set.
If no error occurs in the simulator, the following message will be printed:
no error between simulated and excepted patterns
Parameter passing adopts + default Verilog testbench supports several
Verilog
parameter passing:
 STARTPAT Set pattern number to start simulation.
 ENDPAT Set pattern number to end the simulation pattern number
 CHAINTEST causes the STARTPAT and ENDPAD parameters to be applied
to the
chain test pattern instead of the scan test.
 END_AFTER_SETUP causes the simulation to simulate only the vectors in
the
test_setup phase and then ends the simulation.
 SKIP_SETUP causes the testbench to skip simulating the test_setup
vector and
start simulating the first pattern, chain or scan test.
 CONFIG specifies the .cfg file, which controls the .vec waveform file. For
specific
usage, see CONFIG Usage
 NEWPATH The file path of the tb file. The default file name length is 512
bytes.

Example of parameter passing:


1. By default, CHAINTEST=0, which means that only the scan test pattern
will be
simulated, unless you specify CHAINTEST=1.
2. If CHAINTEST=1 and ENDPAT is specified, it will start from the chaintest
pattern,
but will not simulate the scan test pattern.
3. If CHAINTEST=1 and STARTAT is specified, it will also start simulation
from the
specified STARTPAT chain test pattern and continue to all scan test
patterns.
vsim <testbench_tp> -c -do “run -all” +STARTPAT=5 +ENDPAT=8

STARTPAT,END PAT, and CHAINTEST Usage:


Parallel vs Serial Patterns.
Although parallel simulation is faster, it cannot locate some scan shift
problems.
Therefore, it is recommended to run several serial patterns and then run
parallel
patterns.
Potential causes of Simulation Mismatches
1. There are many reasons for simulation mismatch. The biggest difficulty
is to
know where to start.
2. First, does the chain test fail?
3. Does the scan test serial/parallel pass?
4. DRC problem causes: C6 and T24 are the most likely to cause
mismatch. You can
avoid C6 problems by using set_clock_off_simulation
Simulation mismatch investigation:
 Does the mismatch occur in PO, scan cell, or both? If
 the mismatch occurs in the scan cell, it is usually due to a capture
problem or a
timing problem. However, if it occurs in the PO port, it is more likely that
the
data loaded into the scan cell is incorrect. (I don’t understand???) Does
 the mismatch occur in part of the pattern or the entire pattern?
 If it is a partial patern, it can be cut separately. If it is the entire pattern,
it is
generally a common problem.
 Does the mismatch occur in a few cells/pins or in most of the cells/pins?
If it
occurs in a few cells/pins, it indicates a problem with a small number of
instances or logic. If it occurs in most of the cells/pins, it is more likely to
be
some common problems.
 Does the chain test fail?
 To determine whether the serial pattern fails, the chain test simply
shifts the
data from scanin to scanout. This is also the debugging method I will add
later,
that is, to turn on the EDT bypass mode.
 Is it a specific pattern type that fails?
 If only the ram sequential pattern fails, then the problem may be with
the ram
(incorrect model). If only the clock_sequential pattern fails, then the
problem is
most likely related to the non-scan FF and latch.

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