Dynamic Analog Circuit Netlisting for Solving the

Boolean Satisfiability Problem

Sejal Singh∗ , Bhavani Namrata∗ , and Venkatnarayan Hariharan∗
∗ Department of Electrical Engineering, Shiv Nadar University, Delhi NCR, India
Email: {ss147, bn467, venkatnarayan.h}@snu.edu.in

Abstract—Techniques to solve the Boolean Satisfiability prob- originally introduced by Yin et al in 2018 [7], based on the
lem (SAT) lend themselves to various applications in computer- techniques developed in [8], emerged as a faster alternative to
aided design, circuit design, automated reasoning, formal verifi- the previously existing solvers. The AC-SAT has been shown
cation, etc. The SAT problem falls under the class of NP (Non-
deterministic Polynomial time) problems, hence, solving them on to offer more than 600x speedup on certain FPGA hardware-
digital computers is intractable as the increase in the number based solvers, such as [9].
of variables results in an exponential increase in solution time. AC-SAT is an analog hardware solver, what we term as
This hurdle has led to the development of many alternative a hardware-hardware implementation in this paper, which
hardware solutions, one of which, is a novel technique based solves any 3-SAT instance. A 3-SAT instance is a special
on the solution of suitably designed analog circuits. In this work,
the implementation of a hardware-software technique for a 3- case of SAT instance in which every clause has at most three
SAT solution is demonstrated by leveraging a methodology that literals. It is known that a k-SAT instance for any k > 3 can be
was presented in prior work that showed a hardware-hardware reduced to 3-SAT in polynomial time [10]. Hence, reducing the
implementation. The similarity and differences between the two solver to 3-SAT does not restrict the capabilities of AC-SAT.
techniques are also discussed in the paper. This paper takes the AC-SAT and extends upon its usability
Index Terms—SAT, NP, CNF, k-SAT, Analog circuits
by implementing a hardware-software solution, that involves
the dynamic generation and circuit simulation of netlists as
I. I NTRODUCTION
per the requirements of the CNF. Our methodology continues
The SAT problem assesses Boolean formulae in their with the techniques in [8] to express the CNF as a matrix. This
Conjunctive Normal Form (CNF) to determine if they are matrix is taken in as the input in our implementation, which
satisfiable. A boolean expression is said to be satisfiable if parses it to instantiate the necessary circuit blocks for the
there exists some assignment of 1 or 0 to its variables for hardware-software implementation of AC-SAT, as described
which the expression evaluates to 1. For example, the CNF in [7]. The script dynamically assembles the final netlist
{{a}{ā}} is unsatisfiable since it is the conjunction of a by combining the instantiated circuit blocks with required
and ā, i.e. a ∧ ā. Methods of resolution, conditioning, and instances according to the CNF input. The code then initiates
existential quantification can be used to determine the unsat- a circuit simulation for the generated netlist file, which gives
isfiability or satisfiability of any CNF [1]. Some other popular the solution for SAT which is extracted and displayed.
algorithms to determine satisfiability include the DPLL and In this paper, we describe the implementation of our
CDCL algorithms [1]. Several software solvers are based on hardware-software solution and show its validation. The paper
these algorithms. is organized as follows: Section II presents some background,
k-SAT for k >= 3 has been shown to be an NP-complete Section III discusses our implementation and simulation re-
problem [2]. An NP problem is one whose solution is very sults, Section IV presents our automated hardware-software
hard to find, but once found it can be verified very easily. An solution, and Section V concludes with future scope.
NP-complete problem is an NP problem with the additional
property that if an efficient solution is found for it, then all II. BACKGROUND
NP problems can be solved efficiently, which is extremely To make SAT solvers using analog hardware, one must first
advantageous. Specifically, it is known that every problem in find a way to express an instance of SAT as a continuous
NP can be reduced to SAT in polynomial time [3]. This means equation. This is done in [8], where a CNF is expressed
that if we can solve SAT efficiently, we can also efficiently as a Continuous Time Dynamical System (CTDS). After
solve all problems in the NP class. developing the continuous equation, a circuit is developed,
SAT solving thus emerged as a rich field with the devel- whose behavior models the CTDS behavior asymptotically,
opment of several software and hardware solvers. Some of even if intermediate trajectory points of the circuit response
the well-known software solvers include: MiniSAT [4] and may not necessarily model the CTDS behavior. We describe
WalkSAT [5]. Hardware solvers such as SAT-Hard [6] soon below the methodology of [8] based upon which we have built
developed as a faster alternative to their software counterparts. the present implementation. For the sake of continuity, we
Analog hardware solutions for SAT solving, the AC-SAT, present some background, but in the interest of brevity and
to focus more on our implementation, we skip the details and
urge the reader to look up [8] for more details.
A. From CNF to CTDS
To solve a k−SAT problem one aims to find an assignment
to N Boolean variables such that they satisfy the Boolean
formula F . One can represent F as a CNF with M clauses
and at most k literals per clause. To facilitate the CTDS
theory, the following are defined in [8]:

1) A Boolean formula F with N variables xi ∈ {0, 1}, i =

1, 2, .., N , within M clauses Cm , m = 1, 2, .., M ,
formed by the disjunction of k literals (variables or their
complements).
VM
F = m Cm where Cm = (xi ∨ xi2 , . . . , ∨xik )
2) An analog variable si ∈ [−1, 1], associated with the
Boolean variable xi such that si = −1 when xi is
FALSE and si = 1 when xi is TRUE.

3) An M xN matrix C = {cm , i}, with cm,i = 1 when xi

appears in the clause Cm , cm,i = −1 when its negation
x̄i appears in the clause Cm and cm,i = 0 when neither
appears in the clause Cm . Fig. 1: Block diagram based on [7].

With the above as an input specification, two functions are

defined in [8] [7] as: B. From CTDS to Circuit
In [7], the authors develop the CTDS as an analogous
1. An analog function Km (s) ∈ [0, 1],
Analog Circuit in three circuit blocks: the signal dynamics
N
Y circuit (SDC), the auxiliary variable circuit (AVC), and the
Km (s) = 2−k (1 − cm,i si ) (1) digital verification circuit (DVC). These blocks are assembled
i=1
and inputs to them are decided based on the CNF for which
2. A potential energy function V (s) ∈ [0, 1], SAT is to be determined. Fig.1 shows the block diagram of
M
X all the circuit blocks and their connections. Refer to [7] for a
2
V (s, a) = am Km (2) more detailed explanation.
m=1
SAT is thus redefined as, a search in s for V (s) = 0 where
s is the global minimum for V and the solution to k-SAT. To III. I MPLEMENTATION
overcome the risk of the algorithm getting stuck at a local
minima, [7] introduces the auxiliary variable, am ∈ (0, ∞). In this section we discuss how we implemented the cir-
cuits as described in [7]. Our simulations of the AC-SAT
From (1) and (2), [7] derives: are implemented at the transistor level in Cadence Virtuoso
1. Gradient descent on V : [11] using a 45nm technology model. The supply voltage is
VDD = 1.2V and the transistor sizes are set to L = 45nm and
M W = 1µm except in certain circuits where sizes are selected
dsi X
= am Dm,i (3) according to the transistor’s specific role. This is the first
dt m=1 step in coming up with a generalized netlisting script. After
manually implementing the circuit for set CNFs, we ensure
where that it simulates correctly, after which, we acquire its netlists.
N
Y These netlists are then templated to automate the creation of
Dm,i = 2Km cm,i (1 − cm,j sj ) (4) other netlists as per the requirements of the CNF.
j=1j̸=i
2. Exponential growth is driven by the level of non-SAT in A. Signal Dynamics Circuit (SDC)
Km :
For a 3-SAT problem, one can infer from (5) that,
dam
a˙m = = am Km , m = 1, ..., M (5) Dm,i = 2−2 x cm,i (1 − cm,i si )(1 − cm,i2 si2 )2 (1 − cm,i3 si3 )
dt
 Fig. 2: SDC schematic for CNF:{{A, B, C}{B, D}}


−2 2 2
2 (1 − si )(1 − cm,i2 si2 ) (1 − cm,i3 si3 )
 ifcm,i = 1 The SDC block comprises a combination of these circuits,
Dm,i = 0 ifcm,i = 0
2−2 (−1 − s )(1 − c
 2 2 one for each variable, whose output end is also connected to
i m,i2 si2 ) (1 − cm,i3 si3 ) ifcm,i = −1
(6) a Schmitt trigger inverter to obtain the digital value of si . Our
implementation of the SDC circuit is shown in Fig.2.
M
dVi X
C = Im,i (7) B. Auxiliary Variable Circuit (AVC)
dt m=1
 The AVC is a simple circuit with an operational amplifier,
(VDD − Vi )/(Rm,i ||Ram + Rm,i2 + Rm,i3 )
 ifcm,i = 1
which has the three tunable resistors in series given to it as
Im,i = 0 ifcm,i = 0

(GND − V )/(R inputs. The operational amplifier outputs the voltage analogy
i m,i ||Ram + Rm,i2 + Rm,i3 ) ifcm,i = −1
(8) of am , Vam , which follows an exponential growth driven by
the level of non-SAT to ensure that none of the solutions get
stuck in the local minima of the potential energy function in
From (7), [7] develops a circuit analogy with the current- (2). Each clause has its own AVC circuit to generate am as per
voltage relations described in (9). The resistances mentioned the SAT conditions of its variables. The first order differential
in the formula are obtained through tunable resistors which equation of Vam [7] is given as,
resist current through the circuit based on the level of satisfi-
ability of the variable. Each resistor Rm,i , Rm,i2 , and Rm,i3 dVa,m
C = Va,m /(Rm,i1 + Rm,i2 + Rm,i3 ) (9)
correspond to the three variables of one clause in the 3-SAT dt
instance, such that this circuit block is replicated with different Our simulation uses a Verilog-A behavioral model of an ideal
Rm,i , Rm,i2 , and Rm,i3 conditions for each variable. This op-amp [12]. The schematic of our AVC implementation is
voltage output signal of this circuit is analogous to our si shown in Fig.3. There is an upper bound of VDD on Vam by
variable, as defined earlier, which is the solution to k-SAT. setting the supply voltage of the op-amp to VDD . When any
 Fig. 3: AVC schematic for chosen CNF Fig. 5: DVC schematic for chosen CNF

TABLE I: Simulation results for different CNFs from our

hardware-software solution
N CNF SAT/UNSAT Solution
2 {{A} {A′ , B ′ } {B}} UNSAT 11
3 {{A, B, C ′ } {A′ , B ′ , C} {A′ , B, C}} SAT 000
3 {{A, B, C} {A, B, C ′ } {A, B ′ , C} UNSAT 000
{A, B ′ , C ′ } {A′ , B, C} {A′ , B, C ′ }
{A′ , B ′ , C } {A′ , B ′ , C ′ }}
4 {{A, B, C ′ } {B ′ , D}} SAT 1011
4 {{A, B, C} {B ′ , C ′ } {D}} SAT 1101
4 {{A, B, C} {B ′ , C ′ } {D} {D′ }} UNSAT 1100
4 {{A, B ′ } {A′ , C, D} {B, D′ }} SAT 0010
4 {{A, B, C} {A′ , B ′ , C ′ } {A, B, D′ } SAT 0010
{A′ , B ′ , D}}
6 {{A′ , B ′ , C ′ } {D, E ′ , F ′ } {A, B, C}} SAT 100100
6 {{A, B, C} {D, E, F ′ } {F, D′ , C ′ } SAT 110010
Fig. 4: Virtuoso simulation for the waveform of Vam s over time. {A′ , B ′ , C ′ }}
7 {{A, B, C ′ } {B ′ , D, E ′ } {F, G, E ′ } SAT 1000011
{C, B, D′ }}
one variable in the clause is satisfied, the Vam of that clause is
saturated to a certain voltage. The waveform of one such case
is shown in Fig.4, where we can see Vam rising exponentially signal passes through the AND gate outputting a true, which
until CNF is satisfied. means that the CNF is satisfiable. In other words, every clause
of the CNF must have at least one variable that has a value
C. Digital Verification Circuit (DVC) following the form it exists in, for that CNF to be satisfiable.
Our implementation of the DVC is shown in Fig.5.
This block determines if a solution to the CNF has been
found. It is implemented through an array of 3M XOR gates D. Simulation Results
and an array of M NAND gates. The inputs to the DVC Our implementation successfully determines if the CNF is
are the digital representations of the si signals, as output satisfiable and outputs both SAT and the solution at which
from the SDC, and the cm,i signals as obtained from the C SAT is discovered. Figs. 6-8 show waveforms of some of our
matrix (defined in A. From CNF to CTDS). If the variable i, simulation results. If the CNF is satisfiable the voltage output
exists in the clause m, in its non-negated form, the digital of the DVC is high, i.e., SAT = 1 (≈ 1.2V ), else, SAT = 0
voltage associated with cm,i , Qcm,i = VDD and if it exists (≈ 0V ). Table 1 describes the different CNFs and shows the
in its negated form, the digital voltage associated with cm,i , solutions at which SAT/UNSAT is found.
Qcm,i = GN D. These two inputs are to the battery of XOR
gates and if the value of the variable matches with the form IV. T HE AUTOMATED H ARDWARE -S OFTWARE S OLUTION
it exists in, in the CNF, a false value is sent to the NAND Upon understanding the connections between circuit ele-
gate. If every NAND gate gets at least one false value, the ments at the lowest level of the hierarchy, the process of
 Fig. 6: Simulation results for CNF: {{A, B, C}{B, D}}. Fig. 8: Simulation results for CNF: {{A, B, C}{B, C}{D}{D}}.

Fig. 7: Simulation results for CNF: {{A, B, C}{B, C}{D}}.

writing a script for netlisting becomes apparent. Netlisting Fig. 9: Sample input file for CNF: {{A, B}{A, C, D}}
the scripts as per the M and N values of the CNF makes
the process of circuit generation a lot simpler than manually
creating the circuit in the GUI of a tool like Cadence Virtuoso, 3) Sub-circuit netlisting: Once we have the first and last
which would be a lot harder for CNFs with a large number of non-zero variables of the clauses, this part of the script
clauses and variables, as it is in real-world applications. Our generates netlists for the SDC, AVC, and DVC as per
hardware-software solution is implemented through a Python their circuits as described in Section III.
script designed to generate a netlist for the Analog SAT solver 4) Creating templates for reusable blocks: After that we
circuit as described in [7]. append the template in the netlist for blocks like logic
The following steps break down the functionality of our code: gates, tunable resistors, and switches that are repeatedly
1) Input: The script reads the CNF through a text file, used in the circuit.
into which the user may input the CNF in a suitable 5) Generating the AVC block: This script then writes
format (as shown in Fig. 9). Our code accepts the CNF netlists of all internal connections of the AVC block
input as a matrix of M rows and N columns. The rows according to the variable information of each clause, as
represent the M clauses and the columns represent the obtained on parsing the matrix.
N variables. This representation of the CNF as a matrix 6) Generating the AVC top element: The script creates
is better explained in Section II of this paper where the the top module for the AVC block connecting internal
Cm,i matrix is defined. AVC element pins to the external circuit. This AVC
2) Parsing the matrix: Before parsing, the script first dis- circuit is then connected to the other blocks, namely,
plays the input matrix as a Product-Of-Sums expression the SDC and DVC.
(POS). The POS representation is similar to the CNF 7) Generating the SDC element: The script generates the
representation of a Boolean Formula. After this, the circuit and netlist connections for the SDC block.
script parses through the expression to find the index 8) Generating elements for the DVC block: The script
of the first and last non-zero variable of each M clause. generates circuit elements for the DVC block. A sub-
This parsing is done for our sub-circuit netlisting. circuit for an M -input (M clauses) NAND gate is also
 created for the DVC circuit. [3] S. A. Cook, “The complexity of theorem-proving procedures,” in
9) Generating the DVC element: The script creates all Proceedings of the Third Annual ACM Symposium on Theory of
Computing, ser. STOC ’71. New York, NY, USA: Association
the circuit connections for the DVC circuit block. for Computing Machinery, 1971, pp. 151–158. [Online]. Available:
10) Netlist instantiation: Post the netlisting of all circuit https://doi.org/10.1145/800157.805047
blocks, the script instantiates the top-level modules for [4] N. Eén and N. Sörensson, “An extensible sat-solver,” in Theory and
Applications of Satisfiability Testing, E. Giunchiglia and A. Tacchella,
the SDC, AVC, and DVC blocks to dynamically assem- Eds. Berlin, Heidelberg: Springer Berlin Heidelberg, 2004, pp. 502–
ble the overall circuit. 518.
11) Analysis and results: After netlisting, the script sets [5] B. Selman, H. A. Kautz, and B. Cohen, “Local search strategies for
satisfiability testing,” in Cliques, Coloring, and Satisfiability, 1993.
up analysis for the simulation of the circuit by initiating [Online]. Available: https://api.semanticscholar.org/CorpusID:3215289
Spectre simulation. Post simulation the script extracts [6] B. Ustaoglu, S. Huhn, F. Sill Torres, D. Große, and R. Drechsler, “Sat-
the SAT solution and prints it. hard: A learning-based hardware sat-solver,” in 2019 22nd Euromicro
Conference on Digital System Design (DSD), 2019, pp. 74–81.
The Python code of the hardware-software implementation [7] X. Yin, B. Sedighi, M. Varga, M. Ercsey-Ravasz, Z. Toroczkai, and
described in this section has been made available by the X. S. Hu, “Efficient analog circuits for boolean satisfiability,” IEEE
Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26,
authors at [13]. no. 1, pp. 155–167, 2018.
[8] M. Ercsey-Ravasz and Z. Toroczkai, “Optimization hardness as
transient chaos in an analog approach to constraint satisfaction,”
V. C ONCLUSION AND F UTURE S COPE Nature Physics, vol. 7, no. 12, pp. 966–970, 2011. [Online]. Available:
https://doi.org/10.1038/nphys2105
Throughout this paper, we have discussed possibilities for [9] J. Thong and N. Nicolici, “Fpga acceleration of enhanced boolean
extending the capabilities of SAT solvers. Such extensions in constraint propagation for sat solvers,” in 2013 IEEE/ACM International
Conference on Computer-Aided Design (ICCAD), 2013, pp. 234–241.
the capability of hardware solvers through the development of [10] J. E. Hopcroft and J. D. Ullman, Introduction to Automata Theory,
hardware-software solutions, improve their efficiency opening Languages, and Computation. Addison-Wesley Publishing Company,
up avenues for the creation of better solvers. These interfaces 1979.
[11] Cadence Design Systems, Inc., “Cadence eda virtuoso
leverage the speed of hardware solvers and the extensibility suite.” [Online]. Available: https://www.cadence.com/en US/home/tools/
of software overlays. Listed below are some more ideas that custom-ic-analog-rf-design/circuit-design/virtuoso-ade-suite.html
can be incorporated to make the hardware-software interface [12] M. Brinson, “Qucs: Verilog-a modular macromodel for operational
amplifiers,” Tech. Rep., 2007.
smoother: [13] S. Singh, “3-SATSolver Netlist Generator,” 2024, GitHub repository.
• This implementation does not make use of certain de- [Online]. Available: https://github.com/SejalS01/3-SATSolver.git
terministic features of other solvers such as conditioning
on unit clauses or conditioning on pure literals in the
CNF. Several theoretical techniques, such as eliminating
unitary clauses, conditioning pure literals, implementing
clause satisfiability constraints, etc., used to simplify CNF
instances, can be added to the script.
• Moreover, as discussed, since algorithms to reduce k-SAT
to 3-SAT in polynomial time already exist, we can add
those to our script to extend the usability of the solver to
all k-SAT problems.
• In [7] several alternative AVC implementations are dis-
cussed that conserve area and power. Some remove the
operational amplifier completely and obtain results in the
solver of the same order as with an op-amp. Our script
has not focused on these aspects because it was not meant
as a hardware-hardware solution (ie. one that is realized
as an ASIC or FPGA). But if needed, it can be modified
to optimize for that aspect also, albeit it is arguable if that
can be deemed an optimization in a hardware-software-
targeted implementation.

R EFERENCES
[1] A. Biere, M. Heule, H. van Maaren, and T. Walsh, Eds., Handbook of
Satisfiability - Second Edition, ser. Frontiers in Artificial Intelligence
and Applications. IOS Press, 2021, vol. 336. [Online]. Available:
https://doi.org/10.3233/FAIA336
[2] M. R. Garey and D. S. Johnson, Computers and Intractability; A Guide
to the Theory of NP-Completeness. USA: W. H. Freeman & Co., 1990.