AN INTERNSHIP REPORT ON

DESIGN FOR TESTABILITY (DFT)

Submitted in partial fulfillment of the requirements for award of the degree of

BACHELOR OF TECHNOLOGY
In

ELECTRONICS & COMMUNICATION

ENGINEERING
by

CH.HARI CHANDRIKA(20A81A04D5)

Under the Esteemed guidance of

Mr. K. PASIPALANA RAO, M.Tech
Assistant Professor

Department of ECE

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINERING

SRI VASAVI ENGINEERING COLLEGE

(Affiliated to Jawaharlal Nehru Technological University Kakinada, Kakinada)
(Approved by AICTE, New Delhi, Accredited by NBA & NAAC with ’A’ grade)

Pedatadepalli, Tadepalligudem- 534101, WG.Dist, AP

(2020 – 2024)
 PROGRAM BOOK FOR
SEMESTER INTERNSHIP

CH. HARI CHANDRIKA

SRI VASAVI ENGINEERING COLLEGE

20A81A04D5

01/12/23 31/4/24

BIST Technologies Pvt.Ltd.Door No: 33-21-4, First Floor,

Seetharampuram Signals, Eluru Road, Vijayawada-520002.
Phone NO. s: 8919651415, 9848238245

JNTUK University
4th
 An Internship Report on

DESIGN FOR TESTABILITY (DFT)

Submitted in accordance with the requirement for the degree of

Under the Faculty Guideship of

Mr. K. PASIPALANA RAO,

M.Tech,
Assistant Professor

Department of ELECTRONICS AND COMMUNICATION

ENGINEERING

SRI VASAVI ENGINEERING COLLEGE

Submitted by:

CH. HARI CHANDRIKA

Reg. No: 20A81A04D5

Department of ELECTRONICS AND COMMUNICATION

ENGINEERING

SRI VASAVI ENGINEERING COLLEGE

 Student’s Declaration
I, CH HARI CHANDRIKA a student of B.Tech Program, Reg. No. 20A81A04D5
of the Department of ELECTRONICS AND COMMUNICATION
ENGINEERING in SRI VASAVI ENGINEERING COLLEGE do hereby declare
that I have completed the mandatory internship from 01-12-2023 to 31-04-2024 in
BIST TECHNOLOGIES PVT.LTD. under the Faculty Guideship of Mr. K.
PASIPALANA RAO M.Tech, Assistant Professor, Department of
ELECTRONICS AND COMMUNICATION ENGINEERING in SRI VASAVI
ENGINEERING COLLEGE.

(Signature and Date)

1
 Official Certification
This is to certify that CH HARI CHANDRIKA Reg. No. 20A81A04D5 has
completed his/her Internship in BIST TECHNOLOGIES PVT.LTD. on DESIGN
FOR TESTABILITY (DFT) under my supervision as a part of partial fulfillment of
the requirement for the Degree of B.Tech in the department of ELECTRONICS AND
COMMUNICATON ENGINEERING in SRI VASAVI ENGINEERING
COLLEGE.

This is accepted for evaluation.

(Signatory with Date and Seal)

Endorsements

Faculty Guide

Head of the Department

Principal

2
Certificate from Intern Organization

3
 Acknowledgements

We take this opportunity to express our profound sense of gratitude in all its
humbleness to our beloved Mr. K. PASIPALANA RAO., M.Tech, Assistant Professor
in Electronics and Communication Engineering, Sri Vasavi Engineering College,
Tadepalligudem. For his excellent guidance, meticulous care and enthusiastic
encouragement in motivating us to take up this challenging task and helped us in the
completion of the Internship.

We are indebted to Dr. E. KUSUMA KUMARI, Ph.D., Professor & Head of the
Department of Electronics and Communication Engineering, for her constant
encouragement during execution of the Internship.

We would like to express our gratitude to Dr. G.V.N.S.R. RATNAKARA RAO,

Ph.D., Principal and Management of our college for their valuable advice and
Supervision up without which this project would not have seen the light of the day. We
sincerely wish to thank all the staff members of the department of Electronics and
Communication Engineering.

CH. HARI CHANDRIKA

(20A81A04D5)

4
 Contents

Chapter -1 Executive Summary 06

Chapter -2 Overview of the Organization 08
Chapter -3 Internship Part 10
Chapter -4 Outcome description 40

5
 CHAPTER 1: EXECUTIVE SUMMARY

The internship program embarked on an immersive journey into the intricate world of
Application-Specific Integrated Circuit (ASIC) design and testing methodologies. Spanning
across 14 weeks, the program aimed to equip participants with advanced knowledge and
practical skills essential for navigating the complexities of ASIC development. Through a
structured curriculum and hands-on activities, participants delved deep into various aspects of
ASIC design optimization, fault diagnosis, testing efficiency enhancement, and automation.

The first module laid the groundwork by introducing participants to fundamental concepts
such as clock gating, X-propagation, and fault aliasing. These concepts formed the cornerstone
of ASIC testing, providing participants with a solid understanding of the challenges inherent in
ensuring the reliability and functionality of ASIC designs. Practical exercises and case studies
enabled participants to grasp the real-world implications of these concepts, setting the stage for
further exploration.

Subsequent modules delved into advanced ASIC testing techniques, including scan
compression, adaptive scan, and at-speed testing. Participants gained insights into the latest
methodologies and tools used to optimize testing efficiency and maximize fault coverage.
Hands-on sessions with industry-standard tools allowed participants to apply theoretical
knowledge to practical scenarios, reinforcing their understanding and skillset.

A significant focus was placed on scripting languages such as Tool Command Language
(TCL) for automation. Participants learned how to leverage TCL scripting to streamline ASIC
design and testing processes, automate repetitive tasks, and enhance productivity.

Through practical exercises, participants honed their scripting abilities, empowering them to
create efficient and scalable solutions for ASIC development projects.

Furthermore, participants developed proficiency in creating comprehensive test protocols and

verifying ASIC designs for compliance. The importance of thorough verification and
compliance testing was emphasized, ensuring that ASIC designs meet industry standards and
specifications. Additionally, participants explored the implementation of on-chip clock
controllers, vital for managing clock signals within ASICs efficiently.

6
 The internship culminated in an exploration of advanced hierarchical scan design
methodologies and top-down scan insertion approaches. Participants learned how to efficiently
manage large-scale ASIC designs, optimize scan chain architectures, and integrate scan testing
seamlessly into the design flow. Practical exercises and project work provided participants with
hands-on experience in applying these methodologies to the real-world ASIC projects.

7
 CHAPTER 2: OVERVIEW OF THE ORGANIZATION

 Company Name: BIST Technologies Pvt.Ltd.

 Established Date: 24-07-2023
 Physical Address per Location: Door No: 33-21-4, First Floor,
Seetharampuram Signals, Eluru Road, Vijayawada-520002
 Phone Numbers: 8919651415, 9848238245
 Website: www.bisttechnologies.com
 Email Address: [email protected]

We are at the forefront of innovation in the world of software and hardware technologies.
As a prominent systems integrator and technology provider, we have established ourselves with
the core objective of delivering cutting-edge and intelligent technical solutions along with top-
tier consulting services. Our mission is to empower businesses, organizations, and government
entities with efficient, secure, and intelligent access to valuable information resources.

OUR COMMITMENT
We take pride in our exceptional team, comprising some of the most talented technical and
non-technical professionals. Continual investment in skills and know-how development is at the
heart of our operations. This commitment ensures that our clients benefit from world-class
solutions and services delivered in the most cost-effective manner.

SERVICES AND EXPERTISE

Software and Hardware Technologies:

We excel in both software and hardware technologies. Our software solutions are designed
to streamline business processes, enhance productivity, and drive innovation.
We offer an array of hardware solutions to support these software systems, ensuring seamless
integration and optimal performance.

System Integration:
8
 Our expertise lies in seamlessly connecting various systems and technologies to create
holistic solutions that cater to the unique needs of our clients. We understand that different
technologies and platforms can coexist, and our team excels at making them work together
seamlessly.

VISION
we are driven by a clear vision: to be the foremost technology company that transcends the
boundaries of the IT and non-IT sectors. We are dedicated to advancing beyond our current
position in the market and becoming a pioneering force in the realm of technology.

MISSION
we are a professional firm specializing in web development, mobile applications, robotics,
communication, machine learning, and digital marketing. Our mission is to provide our valued clients
with customer-centric, results-driven, and cost-competitive IT & non-IT solutions that are marked by
innovation.

9
 CHAPTER 3: INTERNSHIP PART

Internship Experience at BIST Technologies Pvt. Ltd.

During the internship at BIST Technologies Pvt. Ltd., I was immersed in a dynamic and
collaborative learning environment, where I had the opportunity to gain hands-on experience
and enhance my skills in various aspects of technology and engineering. The internship
provided me with exposure to real-world projects, practical training sessions, and mentorship
from experienced professionals, allowing me to grow both personally and professionally.

Description of Activities/Responsibilities:
 Working Conditions: The working conditions at BIST Technologies were conducive
to learning and growth. The office environment was vibrant and inclusive, fostering
collaboration and creativity among interns and employees alike. The organization prioritized
employee well-being and provided necessary amenities to ensure a comfortable and productive
workspace.

 Weekly Work Schedule: The internship program followed a structured weekly

schedule, comprising training sessions, project work, and mentorship meetings. Each week, I
was assigned specific tasks and projects related to my area of interest, allowing me to gain
practical experience and apply theoretical knowledge to real-world scenarios.

 Equipment Used: Throughout the internship, I had access to state-of-the-art equipment

and software tools used in the field of technology and engineering. This included computers
equipped with industry-standard software, lab equipment for hands-on experiments, and online
resources for research and learning.

 Tasks Performed: My responsibilities during the internship varied depending on the

projects and assignments assigned to me. Some of the tasks I performed include:
 Assisting in training programs by preparing materials and conducting demonstrations.

 Participating in real-time projects by collaborating with team members and contributing to

project deliverables.
 Conducting research on emerging technologies and industry trends to stay updated with the

latest developments.
 Developing technical documentation, reports, and presentations for internal and external

stakeholders.

10
Skills Acquired:
The internship at BIST Technologies provided me with a valuable learning experience and
helped me acquire a range of skills, including:
 Technical proficiency in software tools and technologies relevant to my field of study.

 Project management skills, including task prioritization, time management, and teamwork.

 Communication and presentation skills through interactions with colleagues and

stakeholders.
 Problem-solving and critical thinking abilities, honed through hands-on projects and real-

world challenges.
 Adaptability and resilience in navigating complex and fast-paced work environments.

11
 ACTIVITY LOG FOR THE FIRST WEEK

Day Person In-

Brief description of the daily
& Learning Outcome Charge
activity
Date Signature

Understand the basic

Day – 1 Introduction to ASIC Flow steps involved in ASIC
design flow.

Grasp the concept of

System-on-Chip (SOC)
Day - 2 Introduction to SOC
architecture.

Identify various
Different Blocks in SOC components/modules
Day – 3 within a SOC.

Learn about different

Classification of ICs types of Integrated
Day – 4 Circuits (ICs).

Understand the role and

Introduction to Libraries (LVT, HVT, types of libraries in ASIC
RVT)
Day – 5 design.

Recognize common
defects in silicon
Defects in Silicon
Day –6 manufacturing.

12
 WEEKLY REPORT
WEEK – 1 (From Dt 01/12/2023 to Dt 06/12/2023)

Objective of the Activity Done:

1. ASIC Design Fundamentals and SOC Understanding:
 Learn basics of ASIC design flow and grasp SOC architecture.
2. Comprehension of SOC Components and IC Classification:
 Identify SOC blocks and understand IC classifications.
 Gain insight into library types used in ASIC design.
3. Understanding Silicon Defects:
 Recognize common silicon defects and their implications.
Detailed Report:
During the first week, participants embarked on an immersive journey into the world of ASIC
design, beginning with an introduction to the intricate flow of ASIC development. They grasped the
sequential steps involved, from the conceptualization of a design to its fabrication, laying a crucial
groundwork for the weeks ahead. Subsequently, attention turned to System-on-Chip (SOC)
architecture, where attendees dissected the intricate web of components and modules that constitute
modern SOC designs. This understanding served as a cornerstone for navigating the complexities of
integrated circuit design, setting a solid foundation for further exploration.
As the week progressed, participants dived into the practical realities of ASIC design, confronting
the challenges posed by silicon defects head-on. By identifying common defects inherent in silicon
manufacturing processes, attendees gained a deeper appreciation for the meticulous quality assurance
measures required to ensure ASIC reliability. Moreover, they delved into the classification of
Integrated Circuits (ICs) and the pivotal role of libraries in ASIC design. This knowledge equipped
participants with the discernment needed to select the appropriate IC types and libraries, optimizing
ASIC designs for specific applications. The week culminated in a reflective recap session, affording
participants the opportunity to consolidate their newfound knowledge and prepare for the advanced
concepts awaiting them in the coming weeks.

13
 ACTIVITY LOG FOR THE SECOND WEEK

Day Person In-

Brief description of the daily
& Learning Outcome Charge
activity
Date Signature

Day – 1 Understand the testing

Testing Process process in ASIC
development.

Day - 2 Quality (Yield, DPPM) Learn about quality

metrics such as Yield and
DPPM.

Day – 3 ATE Block Diagram & Multi-site Understand ATE setup

Testing and multi-site testing
concepts.

Day – 4 Introduction to DFT Understand the concept

of Design for Testability
(DFT).

Day – 5 Types of DFT Learn about different DFT

techniques and
methodologies.

Learn techniques for

Day –6 How to Generate Quality Patterns by generating quality
Using D-Algorithm patterns for testing.

14
 WEEKLY REPORT
WEEK – 2 (From Dt 08/12/2023 to Dt 13/12/2023)

Objective of the Activity Done:

1. Testing and Quality Assurance:
 Understand testing processes and quality metrics like Yield and DPPM.
2. ATE Setup and DFT Introduction:
 Learn about ATE setup, multi-site testing, and the basics of Design for Testability
(DFT).
3. DFT Techniques and Quality Pattern Generation:
 Explore DFT techniques and methods for generating quality patterns.
Detailed Report:
During the second week of the program, participants delved deeper into the intricacies of ASIC
testing and quality assurance processes. The week commenced with an in-depth exploration of
testing methodologies, where attendees gained a comprehensive understanding of the testing
process involved in ASIC development. They learned about the various techniques and tools
utilized to detect and rectify faults, ensuring the reliability and functionality of ASICs.
Additionally, participants delved into quality metrics such as Yield and Defective Parts Per Million
(DPPM), crucial indicators of manufacturing success and product quality. This session underscored
the importance of rigorous testing and quality control measures in ASIC design.
Following the examination of testing processes, participants shifted their focus to the setup of
Automatic Test Equipment (ATE) and the concept of multi-site testing. Through detailed
discussions and practical examples, attendees gained insights into the configuration and operation
of ATE systems, as well as the benefits of multi-site testing in improving testing efficiency and
throughput. Moreover, participants were introduced to the fundamentals of Design for Testability
(DFT), a critical aspect of ASIC design aimed at enhancing the ease and effectiveness of testing.
They explored the principles and techniques of DFT, laying the groundwork for implementing
robust testing strategies in ASIC development. Finally, the week concluded with a deep dive into
DFT techniques and methods for generating quality patterns to ensure comprehensive test coverage
and fault detection. Overall, the second week provided participants with a holistic understanding
of ASIC testing, quality assurance measures, and DFT principles, equipping them with the
knowledge and skills needed to navigate the intricacies of ASIC design and development with
confidence.

15
 ACTIVITY LOG FOR THE THIRD WEEK

Day Person In-

Brief description of the daily
& Learning Outcome Charge
activity
Date Signature

Day – 1 Comparison Between Defects, Understand distinctions

Faults, Failure among defects, faults, and
failures.

Day - 2 Functional vs. Structural ATPG Differentiate between

functional and structural
ATPG.

Day – 3 Design Environment Setup Learn how to set up the

design environment
effectively.

Day – 4 Understand the

Libraries - Link Library, Target importance and usage of
Library, Search Path different libraries.

Day – 5 Stuck at Fault Models Learn about stuck-at fault

models in testing.

Understand
Day –6 Controllability, Observability & controllability,
Testability observability, and
testability concepts.

16
 WEEKLY REPORT
WEEK – 3 (From Dt 15/12/2023 to Dt 20/12/2023)

Objective of the Activity Done:

Gain foundational knowledge and skills in ASIC design and testing, including understanding
defects and faults, setting up design environments, utilizing libraries effectively, and enhancing
ASIC testability.
Detailed Report:
Throughout the week, participants delved into foundational concepts and practical aspects of
ASIC design and testing. They began by understanding the distinctions between defects, faults, and
failures in semiconductor devices, recognizing the importance of quality assurance measures in
ASIC development. This was followed by a deep dive into testing methodologies, including
functional and structural Automatic Test Pattern Generation (ATPG), providing participants with
insights into efficient test pattern generation techniques. Additionally, participants learned how to
set up the design environment effectively, ensuring a conducive workspace for ASIC development
tasks.

Moreover, attendees explored the utilization of libraries in ASIC design, including link libraries,
target libraries, and search paths, optimizing design efficiency and accuracy. The week also covered
stuck-at fault models and concepts of controllability, observability, and testability, enhancing
participants' understanding of fault detection and testability enhancement in ASIC designs.

17
 ACTIVITY LOG FOR THE FORTH WEEK

Day Person In-

Brief description of the daily
& Learning Outcome Charge
activity
Date Signature

Day – 1 Scan Design Learn the basics of scan

design in ASIC testing.

Day - 2 Working of Scan Operation Understand how scan

operations work in
testing.

Learn about the flow of

Day – 3 Scan Insertion Flow inserting scan into
designs.

Understand techniques
Day – 4 Optimization of Clock Pulses for optimizing clock
pulses in scan designs.

Day – 5 Scan Benefits & Scan Models Explore the benefits and
different models of scan
testing.

Day –6 Comparison of Scan Designs Compare various designs

and their effectiveness in
scan testing.

18
 WEEKLY REPORT
WEEK – 4 (From Dt 22/12/2023 to Dt 27/12/2023)

Objective of the Activity Done:

Deepen understanding of scan testing methodologies, including scan design principles,
operation, integration, clock pulse optimization, and evaluation of different scan models and
designs.
Detailed Report:

During the fourth week, participants delved deeper into scan testing methodologies, which
are widely used for fault detection in ASICs. They began by understanding the principles and
implementation of scan testing, including its operation and integration into ASIC designs.
Additionally, attendees learned about clock pulse optimization techniques to improve the
efficiency and accuracy of scan testing.

Furthermore, participants explored different scan models and designs, assessing their benefits
and limitations for optimized ASIC testing. The week concluded with a comparison of various
scan designs, enabling participants to evaluate their effectiveness in fault detection and make
informed decisions about scan implementation strategies.

19
 ACTIVITY LOG FOR THE FIFTH WEEK

Day Person In-

Brief description of the daily
& Learning Outcome Charge
activity
Date Signature

Day – 1 Scan Golden Rules (1,2,3) Learn fundamental rules

for effective scan design.

Day - 2 Scan Golden Rules (4,5,6) Continue learning key

rules for successful scan
implementation.

Explore additional rules

Day – 3 Scan Golden Rules (7,8,9) for optimized scan
designs.

Understand advanced
Day – 4 Scan Golden Rules (10,11) rules for scan design
optimization.

Day – 5 Introduction to Scan Types Learn about different

types of scan testing.

Day –6 Full Scan Understand the concept

and implementation of
full scan testing.

20
 WEEKLY REPORT
WEEK – 5 (From Dt 29/12/2023 to Dt 03/01/2024)

Objective of the Activity Done:

Further advance knowledge of scan testing, including mastering scan design rules, exploring
various scan types, and implementing full scan testing for comprehensive fault detection in
ASICs.
Detailed Report:

The fifth week focused on advancing participants' knowledge and skills in scan testing
methodologies. Participants learned fundamental and advanced rules for effective scan design,
ensuring adherence to best practices for successful scan implementation. They also explored
different scan types and their applications, gaining insights into the benefits and limitations of
each type.

Additionally, participants gained hands-on experience in implementing full scan testing

methodologies, enabling comprehensive fault detection in ASICs. This week provided
participants with a deeper understanding of scan testing principles and techniques, empowering
them to contribute effectively to ASIC testing projects.

21
 ACTIVITY LOG FOR THE SIXTH WEEK

Day Person In-

Brief description of the daily
& Learning Outcome Charge
activity
Date Signature

Day – 1 Partial Scan Learn about partial scan

testing and its
applications.

Day - 2 Comparison Between Full Scan & Compare the advantages

Partial Scan and disadvantages of full
and partial scan.

Understand the concept

Day – 3 Partition Scan of partition scan testing.

Learn techniques for

Day – 4 How to Fix Different DRC Issues fixing various design rule
check issues.

Day – 5 Introduction to Lock Up Latches Learn about lock-up

latches and their role in
ASIC design.

Day –6 Working of Lock Up Latches and Understand how lock-up

Advantages latches work and their
benefits.

22
 WEEKLY REPORT
WEEK – 6 (From Dt 05/01/2024 to Dt 10/01/2024)

Objective of the Activity Done:

Develop expertise in advanced scan testing techniques, including partial and partition scan
implementation, resolving design rule check (DRC) issues, understanding lock-up latch
functionality, and optimizing ASIC reliability and performance through effective scan testing
methodologies.
Detailed Report:

During this week, participants delved into advanced scan testing techniques, including partial
and partition scan implementation. They learned how to efficiently detect faults in ASICs with
reduced overhead through partial scan techniques. Furthermore, participants explored strategies
for resolving various design rule check (DRC) issues, ensuring ASIC compliance with
manufacturing standards.

Additionally, participants gained insights into lock-up latch functionality and applications in
ASIC design, understanding how lock-up latches contribute to improved reliability and
performance. Overall, this week provided participants with the knowledge and skills needed to
navigate the complexities of ASIC testing and contribute effectively to ASIC projects.

23
 ACTIVITY LOG FOR THE SEVEN WEEK

Day Person
Brief description of the daily In-
& Learning Outcome
activity Charge
Date Signature
Understand the
Clock Gating concept of clock
1 gating and its
significance.
Explore the purpose
2 Why Lock Up Latches and benefits of lock-
up latches.
Learn about the
Purpose of Lock Up Latches in industrial
3 Industries applications of lock-
up latches.
Familiarize with EDA
4 Introduction to EDA Tools tools like Micro
wind, Tanner, and
Cadence.
Differentiate
5 Schematic vs. Layout between schematic
and layout diagrams.
Practice creating
6 Schematic Diagrams Using EDA Tools schematic diagrams
for different gates.

24
 WEEKLY REPORT
WEEK – 7 (From Dt 12/01/2024 to Dt 17/01/2024)

Objective of the Activity Done:

Gain a comprehensive understanding of advanced concepts such as clock gating, lock-up latches,
and EDA tools, which are crucial for efficient ASIC design and testing. Participants will explore
the significance of clock gating in power optimization, the role of lock-up latches in preventing
metastability issues, and the practical applications of EDA tools in ASIC development.
Additionally, participants will learn the differences between schematic and layout diagrams and
practice creating schematic and layout diagrams using EDA tools, enhancing their skills in
visualizing and designing digital circuits.
Detailed Report:

Throughout the week, participants engaged in activities aimed at deepening their

understanding of advanced ASIC design and testing concepts. They started by exploring the
concept of clock gating, understanding its significance in reducing power consumption in digital
circuits. This was followed by an in-depth discussion on lock-up latches, where participants
learned about their purpose and benefits in preventing metastability issues, crucial for ensuring
the reliability of digital systems.
Moreover, participants delved into the practical applications of EDA tools such as Micro wind,
Tanner, and Cadence in ASIC development. They gained hands-on experience in creating
schematic and layout diagrams using these tools, enhancing their ability to visualize and design
digital circuits accurately. Additionally, participants learned the differences between schematic
and layout diagrams, further solidifying their understanding of ASIC design principles. .

25
 ACTIVITY LOG FOR THE EIGTH WEEK

Day Person In-

Brief description of the daily
& Learning Outcome Charge
activity
Date Signature

Day – 1 Schematic Diagrams for Different Create schematic

CMOS Circuits diagrams for various
CMOS circuits.

Day - 2 Introduction to Layout Diagrams Understand the basics of

layout diagrams in ASIC
design.

Practice creating layout

Day – 3 Layout Diagrams for Different Logic diagrams for different
Gates logic gates.

Create layout diagrams

Day – 4 Layout Diagrams for Different CMOS for various CMOS circuits.
Circuits

Day – 5 Practice Session on Schematics Reinforce understanding

through schematic
diagram practice.

Day –6 Practice Session on Layouts Reinforce understanding

through layout diagram
practice.

26
 WEEKLY REPORT
WEEK – 8 (From Dt 19/01/2024 to Dt 24/01/2024)

Objective of the Activity Done:

Develop proficiency in schematic and layout design for ASICs through hands-on practice
sessions. Participants will create schematic and layout diagrams for various logic gates and
CMOS circuits, reinforcing their understanding of circuit design principles and physical
implementation. By the end of the week, participants will be equipped with the necessary skills
to accurately represent digital circuits in both schematic and layout formats, laying a strong
foundation for ASIC design and testing.
Detailed Report:

During the eighth week, participants focused on honing their skills in schematic and layout
design for ASICs. They began by creating schematic diagrams for various logic gates and CMOS
circuits, gaining a deeper understanding of circuit design principles and interconnections. This
was complemented by an introduction to layout diagrams, where participants learned about their
importance in translating schematic designs into physical layouts.

Moreover, participants practiced creating layout diagrams for different logic gates and CMOS
circuits, further reinforcing their understanding of physical implementation and interconnections.
The week concluded with hands-on practice sessions on both schematics and layouts, providing
participants with the opportunity to apply their knowledge and skills in a practical setting.

27
 ACTIVITY LOG FOR THE NINETH WEEK

Day Person In-

Brief description of the daily
& Learning Outcome Charge
activity
Date Signature

Day – 1 Introduction to Tool Command Learn about TCL scripting

Language (TCL) language and its usage.

Day - 2 TCL Scripting for Scan Insertion Practice TCL scripting for
scan insertion in ASIC
designs.

Learn methods for

Day – 3 How to Check DRC Issues detecting and resolving
DRC issues.

Understand how to create

Day – 4 Creating & Defining Different DFT and define DFT ports in
Ports ASICs.

Day – 5 How to Create Test Protocols Learn techniques for

creating test protocols in
ASIC testing.

Day –6 Auto Fixation Commands in TCL Practice TCL scripting for

Scripting auto-fixation commands.

28
 WEEKLY REPORT
WEEK – 9 (From Dt 26/01/2024 to Dt 31/01/2024)

Objective of the Activity Done:

Enhance automation and optimization capabilities in ASIC design and testing through the
utilization of scripting languages and advanced techniques. Participants will learn TCL scripting
for scan insertion, DRC issue checking, test protocol creation, and auto-fixation commands,
streamlining the design and testing processes. By mastering these techniques, participants will
be able to efficiently address design challenges, improve test coverage, and optimize ASIC
designs for enhanced performance and reliability.
Detailed Report:

The nineth week focused on advancing participants' automation and optimization capabilities
in ASIC design and testing. They started by learning TCL scripting for scan insertion, enabling
them to automate the process and improve efficiency. This was followed by sessions on checking
Design Rule Check (DRC) issues and creating test protocols using TCL scripting, streamlining
the design and testing processes.

Moreover, participants practiced auto-fixation commands in TCL scripting, further enhancing

their ability to address design challenges and optimize ASIC designs. By mastering these
techniques, participants gained valuable insights into advanced ASIC design and testing
methodologies, empowering them to tackle complex design challenges with efficiency and
precision.

29
 ACTIVITY LOG FOR THE TENTH WEEK

Day Person In-

Brief description of the daily
& Learning Outcome Charge
activity
Date Signature

Understand the concepts

Day – 1 Introduction to Compression & and applications of
Decompression compression and
decompression in ASIC
testing.

Day - 2 Test Time & Test Data Learn about test time and
test data optimization
techniques in ASIC
testing.

Practice bridging scan

Day – 3 How to Bridge Scan In, Scan Out chains for efficient scan
with More No. of Scan Chains testing.

Understand the
Day – 4 Scan Compression Blocks implementation and
benefits of scan
compression blocks.

Learn methods for

Day – 5 Calculation of Compression Ratio calculating compression
ratio in scan testing.

Review the key concepts

Day –6 Recap and Review and techniques learned
during the week.

30
 WEEKLY REPORT
WEEK – 10 (From Dt 02/02/2024 to Dt 07/02/2024)

Objective of the Activity Done:

Advance knowledge and skills in advanced ASIC testing techniques such as compression and scan
chain bridging. Participants will learn about compression and decompression techniques to reduce
test data volume and improve test efficiency, as well as scan chain bridging for testing ASICs with
multiple scan chains. By the end of the week, participants will be proficient in applying these
advanced techniques to optimize test time, test data, and overall testing efficiency in ASIC designs.
Detailed Report:

During this week, participants delved into advanced ASIC testing techniques, focusing on
compression and scan chain bridging. They learned about compression and decompression techniques
to reduce test data volume and improve efficiency, as well as scan chain bridging for testing ASICs
with multiple scan chains. Participants also learned to calculate compression ratios, enabling them to
evaluate the effectiveness of compression techniques accurately.
Overall, the week equipped participants with advanced knowledge and skills in ASIC testing, enabling
them to optimize test time, test data, and overall testing efficiency in ASIC designs.

31
 ACTIVITY LOG FOR THE ELEVENTH WEEK

Day Person In-

Brief description of the daily
& Learning Outcome Charge
activity
Date Signature

Understand the concept

Day – 1 X-Tolerance of X-tolerance in ASIC
testing.

Learn about X-
Day - 2 X-Propagation propagation issues and
their impact on ASIC
designs.

Explore techniques for

Day – 3 How to Reduce X Propagation minimizing X-propagation
effects in ASICs.

Understand fault aliasing

Day – 4 Fault Aliasing and its implications in
fault diagnosis.

Learn about scan

Day – 5 Scan Compression with Bypass compression techniques
with bypass for efficient
testing.

Explore advanced
Day –6 Advanced Compression Techniques compression techniques
for improving test
efficiency.

32
 WEEKLY REPORT
WEEK – 11 (From Dt 09/02/2024 to Dt 14/02/2024)

Objective of the Activity Done:

Gain an understanding of advanced concepts such as X-tolerance, X-propagation, fault aliasing, and
scan compression techniques. Participants will explore techniques for minimizing X-propagation
effects, improving fault diagnosis accuracy, and enhancing testing efficiency through scan
compression.
Detailed Report:

Throughout Week 11, participants delved into advanced concepts related to ASIC testing and
optimization. They started by exploring X-tolerance, understanding its significance in ensuring the
robustness of ASIC designs in the presence of unknown states ('X'). This was followed by an
examination of X-propagation issues, wherein participants learned about the challenges associated
with propagating unknown states through digital circuits and explored techniques to mitigate their
impact.
Moreover, participants delved into fault aliasing, understanding how faults can be misinterpreted
or masked during testing, potentially leading to inaccurate diagnosis or undetected faults. This
segment emphasized the importance of thorough fault analysis techniques to ensure reliable ASIC
designs. Furthermore, participants explored scan compression techniques, including the use of bypass
mechanisms, to optimize test data volume and improve testing efficiency.
Overall, Week 11 provided participants with a deeper understanding of advanced ASIC testing
concepts, equipping them with the knowledge and skills needed to tackle complex challenges in ASIC
design and testing.

33
 ACTIVITY LOG FOR THE TWELVETH WEEK

Day Person In-

Brief description of the daily
& Learning Outcome Charge
activity
Date Signature

Understand the concepts

Day – 1 Adaptive Scan and applications of
compression and
decompression in ASIC
testing.

Day - 2 Serializer & Deserializer Learn about test time and

test data optimization
techniques in ASIC
testing.

Practice bridging scan

Day – 3 At-Speed Testing chains for efficient scan
testing.

Understand the
Day – 4 TCL Scripting on Compression & implementation and
Decompression benefits of scan
compression blocks.

Learn methods for

Day – 5 TCL Scripting on Compression & calculating compression
Decompression ratio in scan testing.

Review the key concepts

Day –6 How to Form Scan Chains and techniques learned
during the week.

34
 WEEKLY REPORT
WEEK – 12 (From Dt 16/02/2024 to Dt 21/02/2024)

Objective of the Activity Done:

Deepen knowledge and skills in advanced ASIC testing techniques, including adaptive scan, serializer
and deserializer circuits, and at-speed testing. Participants will also gain proficiency in TCL scripting
for compression and decompression algorithms, and understand the process of forming scan chains
for efficient testing.
Detailed Report:

During Week 12, participants focused on advancing their expertise in ASIC testing techniques and
automation. They began by exploring adaptive scan techniques, which dynamically adjust scan chain
lengths to optimize test application time and data volume. This was followed by an examination of
serializer and deserializer circuits, essential components for transmitting data serially across ASICs.
Furthermore, participants delved into at-speed testing methodologies, learning how to test ASICs
under operational clock frequencies to detect timing-related faults. Additionally, participants honed
their scripting skills through TCL scripting exercises focused on compression and decompression
algorithms, essential for optimizing test data volume and test time in ASIC testing.
Overall, Week 12 enhanced participants' proficiency in advanced ASIC testing techniques and
scripting, preparing them to tackle complex challenges in ASIC design and testing automation.

35
 ACTIVITY LOG FOR THE THIRTEENTH WEEK

Day Person In-

Brief description of the daily
& Learning Outcome Charge
activity
Date Signature

Learn techniques for

Day – 1 Creating Test Protocols creating test protocols for
comprehensive testing
coverage.

Day - 2 Writing Test Protocols Practice writing test

protocols for ASIC testing
scenarios.

Understand methods for

Day – 3 Verifying DRC Reports verifying Design Rule
Check (DRC) reports for
ASIC compliance.

Explore strategies for

Day – 4 How to Balance the Scan Chains balancing scan chains to
optimize testing
efficiency.

Learn about on-chip clock

Day – 5 Introduction to On-Chip Clock controllers and their role
Controllers in ASIC designs.

Understand the
Day –6 Requirements for OCC requirements and
specifications for on-chip
clock controllers.

36
 WEEKLY REPORT
WEEK – 13 (From Dt 23/02/2024 to Dt 28/02/2024)

Objective of the Activity Done:

Enhance proficiency in creating and writing test protocols for comprehensive ASIC testing coverage.
Participants will learn methods for verifying DRC reports, optimizing scan chain balance, and
understanding the requirements and specifications for on-chip clock controllers.
Detailed Report:

Week 13 focused on refining participants' skills in creating comprehensive test protocols and
verifying ASIC designs for compliance. Participants learned techniques for creating detailed test
protocols that ensure thorough testing coverage and adherence to design specifications. They also
explored methods for verifying Design Rule Check (DRC) reports to identify and rectify potential
design rule violations.
Moreover, participants learned about optimizing scan chain balance to improve testing efficiency
and reduce test application time. Additionally, they gained insights into the requirements and
specifications for on-chip clock controllers, essential components for synchronizing clock signals
within ASICs.
Overall, Week 13 provided participants with the necessary skills and knowledge to create robust test
protocols, verify ASIC designs for compliance, and optimize testing efficiency through scan chain
balancing and on-chip clock controller implementation.

37
 ACTIVITY LOG FOR THE FOURTEENTH WEEK

Day Person In-

Brief description of the daily
& Learning Outcome Charge
activity
Date Signature

Practice creating block

Day – 1 Block Diagram for OCC diagrams for on-chip
clock controllers.

Day - 2 Hierarchical Scan Design Learn about hierarchical

scan design
methodologies for large
ASIC designs.

Understand the steps

Day – 3 Steps in Hierarchical Scan Design involved in hierarchical
scan design process.

Explore the top-down

Day – 4 Top-Down Scan Insertion approach for scan
insertion in hierarchical
designs.

Practice TCL scripting for

Day – 5 TCL Scripting on OCC implementing on-chip
clock controllers.

Continue practicing TCL

Day –6 TCL Scripting on OCC scripting for
implementing on-chip
clock controllers.

38
 WEEKLY REPORT
WEEK – 14 (From Dt 01/03/2024 to Dt 06/03/2024)

Objective of the Activity Done:

Advance understanding of hierarchical scan design methodologies and top-down scan insertion
approaches. Participants will practice TCL scripting for implementing on-chip clock controllers,
furthering their skills in ASIC design and testing automation.
Detailed Report:

During the final week, participants focused on advanced hierarchical scan design methodologies
and top-down scan insertion approaches. They learned about hierarchical scan design steps, including
partitioning the design hierarchy and inserting scan chains at various levels of abstraction.
Furthermore, participants practiced TCL scripting for implementing on-chip clock controllers,
essential components for managing clock signals within ASICs efficiently. This segment emphasized
automation techniques to streamline the design and testing process, improving productivity and
reliability.
Overall, Week 14 enhanced participants' proficiency in advanced hierarchical scan design
methodologies, top-down scan insertion approaches, and TCL scripting for on-chip clock controller
implementation, preparing them to tackle complex ASIC design and testing challenges with
confidence.

39
 CHAPTER 4: OUTCOMES DESCRIPTION
During my internship at BIST Technologies Pvt. Ltd., I experienced a positive and
collaborative work environment that facilitated learning and growth. The interactions with
colleagues, supervisors, and mentors were characterized by professionalism, mutual respect,
and a willingness to support one another. Team members were approachable and accessible,
fostering open communication and collaboration.
Facilities at BIST Technologies were well-maintained and conducive to productivity.
The office space was equipped with modern amenities, including ergonomic workstations,
high-speed internet, and access to industry-standard software tools. The organization
prioritized employee comfort and provided a clean and organized workspace, promoting a
sense of professionalism and focus.
Protocols, procedures, and processes were well-defined and communicated effectively
to interns. From onboarding procedures to project management workflows, there was a
structured approach to how tasks were assigned, executed, and reviewed. This clarity
promoted efficiency and accountability, allowing interns to navigate their responsibilities
with confidence.
Discipline and time management were integral aspects of the work culture at BIST
Technologies. Interns were expected to adhere to deadlines, prioritize tasks effectively, and
manage their time efficiently to meet project milestones. Supervisors provided guidance on
time management techniques and encouraged interns to maintain a disciplined approach to
their work.
Harmonious relationships and socialization were encouraged within the organization. Team-
building activities, informal gatherings, and collaborative projects provided opportunities for
interns to socialize with colleagues and build rapport. Mutual support and teamwork were
evident, with colleagues readily offering assistance, sharing knowledge, and collaborating on
projects to achieve common goals.
Motivation was fostered through a combination of intrinsic and extrinsic factors. Interns
were motivated by the opportunity to learn new skills, contribute to meaningful projects, and
receive recognition for their efforts. Additionally, the organization provided incentives such
as mentorship opportunities, professional development resources, and potential career
advancement pathways, further motivating interns to perform at their best.

40
 Space and ventilation in the office environment were adequate, promoting a comfortable and
productive work atmosphere. The layout of the workspace allowed for collaboration and
interaction among team members while also providing areas for focused individual work.

Ventilation systems ensured good air quality, contributing to the overall well-being and
productivity of employees

During my internship at BIST Technologies Pvt. Ltd., I gained specialized knowledge and
hands-on experience in VLSI Design for Testability (DFT), which is essential for ensuring the
efficient testing and diagnosis of integrated circuits (ICs) during the manufacturing process.
Through focused training sessions and practical projects in the field of DFT, I acquired the
following technical skills:
1. Scan Design Techniques:

I learned about scan design methodologies, including scan chain implementation, scan flip-
flops insertion, and scan path generation. I gained practical experience in designing and
optimizing scan chains to facilitate thorough testing of ICs for manufacturing defects and faults.

2. Built-In Self-Test (BIST) Architectures:

I gained knowledge of Built-In Self-Test (BIST) architectures and their applications in IC

testing. I learned how to design and implement BIST structures such as Linear Feedback Shift
Registers (LFSRs), pseudo-random pattern generators, and signature analysers for efficient at-
speed testing.

3. Design for Testability Guidelines:

I learned about DFT guidelines and principles for designing ICs with testability in mind. I
gained insights into techniques for enhancing controllability, observability, and fault coverage
in IC designs, ensuring comprehensive testability during the manufacturing process.

4. Fault Models and Simulation:

I acquired an understanding of various fault models, including stuck-at faults, transition

faults, and bridging faults. I learned how to simulate and analyze these fault models using
industry-standard tools such as Mentor Graphics Tessent and Synopsys DFT Compiler.

5. Automatic Test Pattern Generation (ATPG):

41
 I gained proficiency in ATPG algorithms and techniques for generating high-quality test
patterns to detect and diagnose faults in IC designs. I learned how to optimize ATPG flows to
minimize test application time and maximize fault coverage.

6. Design Verification and Validation:

I learned about design verification and validation techniques for ensuring the correctness
and robustness of DFT implementations. I gained experience in verifying DFT structures using
simulation, formal verification, and emulation techniques.

7. DFT Insertion Flows:

I acquired knowledge of DFT insertion flows and methodologies for integrating DFT
structures into IC designs. I learned how to analyse design constraints, perform DFT insertion,
and verify DFT functionality to meet design requirements.

8. Debugging and Diagnosis:

I gained experience in debugging and diagnosing test failures in IC designs. I learned

how to analyze test results, identify root causes of failures, and implement corrective actions to
improve testability and yield.

42
 Describe the real time technical skills you have acquired (in terms of the job-
related skills and hands on experience)

Real-Time Technical Skills Gained in my DFT Internship

A DFT internship equips you with valuable hands-on experience and job-related technical skills.
Here's a breakdown of what you might learn:

DFT Tools & Techniques:

 Scan Flow Automation: Gain experience using industry-standard DFT tools for automating the

Design for Testability (DFT) flow.

 Test Pattern Generation: Learn techniques for generating test patterns to identify and diagnose

potential defects in circuits.

 Fault Simulation: Practice using simulators to analyze how faults manifest in circuits and

identify effective test patterns.

 Automatic Test Pattern Generation (ATPG): Get hands-on experience with ATPG tools that

automatically generate test patterns for complex circuits.

Design for Testability (DFT) Implementation:

 Scan Chain Insertion: Learn how to insert scan chains into circuits to improve
controllability and observability for testing.
 Boundary Scan (BScan): Gain experience implementing Boundary Scan (BScan)
techniques for testing integrated circuits (ICs).
 Test Point Insertion: Practice identifying and inserting test points within a design to
facilitate easier testing.
DFT Analysis & Optimization:

 DFT Coverage Analysis: Learn how to analyze DFT coverage and identify areas of the
design that may not be thoroughly tested.

 Power Optimization for Test: Gain experience with techniques to optimize power
consumption during the testing process.

43
  Hardware/Software Co-design for Test (if applicable): In some internships, you might
get involved with exploring hardware-software co-design methodologies for DFT
implementation.
Real-World Application:

 Case Studies: Analyze real-world DFT case studies to understand how these techniques
are applied in practical scenarios.
 Project Experience: Work on practical DFT projects, applying the learned techniques to
actual circuit designs. This hands-on experience is invaluable for showcasing your skills to
potential employers.
Beyond Technical Skills:

Remember, a good internship also exposes you to the broader DFT workflow. You might gain
insights into:

 DFT Methodology: Understand the different stages of the DFT flow and how they
contribute to overall design quality.
 DFT Standards: Learn about industry-standard practices and guidelines for DFT
implementation.
 Communication & Collaboration: Collaborate with colleagues and supervisors on DFT
projects, fostering communication and teamwork skills.

44
 Describe the managerial skills you have acquired (in terms of planning, leadership, team
work, behaviour, workmanship, productive use of time, weekly improvement in competencies,
goal setting, decision making, performance analysis, etc.

Managerial Skills Developed During my DFT Internship

Your DFT internship provides a valuable platform to develop and refine your managerial skills.
Here's how you can leverage your experience:
Planning & Organization:

 Project Management: Participate in planning project timelines, milestones, and resource

allocation.
 Task Prioritization: Assist in prioritizing tasks and setting deadlines for yourself and
potentially others.
 Meeting Management: If given the opportunity, take the lead in organizing and facilitating
meetings, ensuring they stay focused and productive.
Leadership & Teamwork:

 Initiative Taking: Volunteer for challenging tasks and demonstrate proactive problem-
solving.
 Team Player: Actively participate in teamwork, listen to others' ideas, and be willing to
compromise.
 Delegation (if applicable): If managing a small team, learn to delegate tasks effectively
based on strengths and expertise.

Behaviour & Professionalism:

 Time Management: Track your time efficiently and meet deadlines consistently.
 Workmanship: Deliver high-quality work, pay attention to detail, and strive for continuous
improvement.
 Communication: Communicate clearly, concisely, and professionally with colleagues,
supervisors, and any clients you interact with.
Goal Setting & Performance Analysis:

 SMART Goals: Set Specific, Measurable, Attainable, Relevant, and Time-bound goals
for yourself during the internship.

45
  Track Progress: Regularly monitor your progress towards your goals and adjust strategies
as needed.
 Self-Evaluation: Reflect on your performance weekly. Identify areas for improvement and
discuss them with your supervisor.
Decision Making & Problem Solving:

 Critical Thinking: Approach challenges analytically and identify potential solutions.

 Information Gathering: Gather relevant information before making choices.
 Risk Assessment: Consider the potential risks and benefits of various options before
making a decision.

46
 Describe how you could improve your communication skills (in terms of improvement
in oral communication, written communication, conversational abilities, confidence levels while
communicating, anxiety management, understanding others, getting understood by others,
extempore speech, ability to articulate the key points, closing the conversation, maintaining
niceties and protocols, greeting, thanking and appreciating others, etc.,)
Communication Skills Developed During my DFT Internship

A DFT internship offers a fantastic opportunity to develop your professional communication

skills. Here's how you can leverage your training to shine:

Oral Communication & Confidence:

 Practice Presentations: Ask if I can present findings or participate in mock client

meetings.
 Seek Feedback: Request constructive criticism from trainers or supervisors on your
delivery.
 Join Discussions: Actively participate in group discussions. Ask clarifying questions and
share your insights.
 Record Yourself: Practice presentations on video and analyze areas for improvement like
pacing, body language, and vocal variety.

Written Communication & Clarity:

 Volunteer for Writing Tasks: Offer to draft reports, emails, or summaries to hone your
writing style.
 Proofread Drafts: Proofread your work and that of colleagues to build an eye for detail
and clarity.
 Use Active Voice: Strive for clear, concise writing using the active voice whenever
possible.
 Tailor Your Writing: Adapt your writing style to the audience (formal for reports,
informal for emails).

47
Conversational Skills & Understanding:

 Active Listening: Pay close attention to others, ask questions, and summarize key points
to show engagement.
 Non-verbal Cues: Maintain eye contact, use open body language, and smile appropriately
to build rapport.
 Empathy: Try to understand the other person's perspective. Ask clarifying questions if
needed.
 Networking: Mingle with colleagues and supervisors during breaks or informal gatherings.

Extempore Speech & Key Points:

 Brainstorm Key Points: Before discussions or presentations, jot down key points you want
to convey.
 Practice Impromptu Speaking: Participate in brainstorming sessions where you can speak
without extensive preparation.

Closing Conversations & Etiquette:

 Summarize Key Points: Briefly summarize the conversation's main points to ensure
understanding.
 Next Steps: If applicable, suggest next steps or action items.
 Maintain Formalities: Use greetings, thanks, and acknowledgements appropriately.
 Professionalism: Maintain a professional demeanor throughout your communication.

Anxiety Management:

 Preparation is Key: The more prepared you are, the less anxious you'll feel. Practice
presentations and rehearse conversations beforehand.
 Deep Breathing: Utilize deep breathing exercises to calm yourself before presentations or
challenging conversations.
 Positive Self-Talk: Focus on positive affirmations. Replace "I can't" with "I can do this."

Getting Understood:
48
 Clarity is King: Speak clearly and concisely, avoiding jargon or overly technical language.
 Examples & Analogies: Use examples and analogies to illustrate complex points.
 Tailor Your Message: Consider your audience's knowledge level and tailor your
communication accordingly.

49
 Describe how could you could enhance your abilities in group discussions, participation
in teams, contribution as a team member, leading a team/activity.
Enhancing My Abilities in Group Dynamics and Teamwork in DFT
Internship
Here's how I can leverage DFT training to enhance my abilities in group discussions, team
participation, contribution, and leadership:

Group Discussions:

 Technical Expertise: The knowledge gained from DFT training strengthens your
understanding of the subject matter. This allows you to contribute valuable insights and
clarifications during discussions, fostering a more informed conversation.
 Active Listening: Pay close attention to the ideas presented by others in the DFT training.
This demonstrates respect and allows you to identify areas where your expertise can
complement their points or ask relevant questions to gain a deeper understanding.

Team Participation:

 Collaboration: DFT projects often involve collaborating with engineers from different
disciplines. Use the training to share your DFT knowledge and actively seek out
opportunities to learn from others' expertise. This collaborative spirit strengthens the team.
 Problem-solving: DFT training equips you with analytical skills for test design and fault
diagnosis. Apply these skills to identify and troubleshoot challenges faced by the team
during the training. This proactive approach demonstrates your problem-solving abilities.

Contribution as a Team Member:

 Initiative: DFT training might involve practical exercises or projects. Take initiative by
proposing approaches, suggesting solutions, or volunteering for specific tasks. This
demonstrates your willingness to go the extra mile.
 Reliability: When assigned tasks during the DFT training, ensure you deliver high-quality
work on time. This builds trust and establishes you as a reliable team member.

50
Leading a Team/Activity:

 Communication Skills: DFT training can involve presenting your findings or leading
discussions. Use this as an opportunity to hone your communication skills by clearly
explaining technical concepts and actively engaging the team.
 Leadership by Example: During DFT training exercises, strive to be a role model by
demonstrating effective collaboration, problem-solving, and adherence to deadlines. This
inspires and motivates others.

Additional Tips:

 Seek Feedback: Actively seek constructive feedback from your trainers or peers during the
DFT training. This allows you to identify areas for improvement in your group work and
leadership style.
 Practice Makes Perfect: DFT training might involve role-playing or group presentations.
Use these opportunities to practice your communication and collaboration skills in a safe
environment.

By actively participating and applying the learnings from your DFT training, you can significantly
enhance your abilities in group discussions, team participation, contribution, and leadership.

51
 Describe the technological developments you have observed and relevant to the subject
area of training (focus on digital technologies relevant to your job role)
Recent Technological Advancements in DFT Internship

Here are some recent technological developments relevant to Design for Testability (DFT) what I
learnt in area of training:

1. Increased Focus on Low Power DFT:

As chip densities increase, power consumption becomes a critical concern. New DFT techniques are
being developed to ensure proper testing while minimizing power consumption during the testing
process. This might involve using specialized clock gating techniques or low-power scan chains.

2. Rise of Machine Learning for DFT:

Machine learning is being explored to automate various aspects of DFT, such as test pattern generation
and fault diagnosis. This can improve the efficiency and effectiveness of the testing process, especially
for complex circuits.

3. Hardware-assisted DFT:

There's a growing trend of incorporating DFT hardware directly into the chip design. This can include
embedded test engines or Built-In Self-Test (BIST) circuits that can perform self-testing without external
equipment.

4. Security-aware DFT:

With growing security concerns, DFT techniques are being developed to consider potential security
vulnerabilities during testing. This might involve ensuring that test data doesn't leak sensitive
information or leave the chip vulnerable to attacks.

5. Integration with Design Automation Tools:

Modern design automation tools are increasingly incorporating DFT capabilities. This allows
designers to easily implement DFT techniques during the design process itself, leading to a more holistic
and efficient approach.

52
 Student Self Evaluation of the Short-Term Internship

Student Name: Registration No:

Term of Internship: From: To :

Date of Evaluation:

Organization Name & Address:

Please rate your performance in the following areas:

Rating Scale: Letter grade of CGPA calculation to be provided

1 Oral communication 1 2 3 4 5
2 Written communication 1 2 3 4 5
3 Proactiveness 1 2 3 4 5
4 Interaction ability with community 1 2 3 4 5
5 Positive Attitude 1 2 3 4 5
6 Self-confidence 1 2 3 4 5
7 Ability to learn 1 2 3 4 5
8 Work Plan and organization 1 2 3 4 5
9 Professionalism 1 2 3 4 5
10 Creativity 1 2 3 4 5
11 Quality of work done 1 2 3 4 5
12 Time Management 1 2 3 4 5
13 Understanding the Community 1 2 3 4 5
14 Achievement of Desired Outcomes 1 2 3 4 5
15 OVERALL PERFORMANCE 1 2 3 4 5

Date: Signature of the Student

53
 Evaluation by the Supervisor of the Intern Organization

Student Name: Registration No:

Term of Internship: From: To :

Date of Evaluation:

Organization Name & Address:

Name & Address of the Supervisor

with Mobile Number

Please rate the student’s performance in the following areas:

Please note that your evaluation shall be done independent of the Student’s self-
evaluation
Rating Scale: 1 is lowest and 5 is highest rank

1 Oral communication 1 2 3 4 5
2 Written communication 1 2 3 4 5
3 Proactiveness 1 2 3 4 5
4 Interaction ability with community 1 2 3 4 5
5 Positive Attitude 1 2 3 4 5
6 Self-confidence 1 2 3 4 5
7 Ability to learn 1 2 3 4 5
8 Work Plan and organization 1 2 3 4 5
9 Professionalism 1 2 3 4 5
10 Creativity 1 2 3 4 5
11 Quality of work done 1 2 3 4 5
12 Time Management 1 2 3 4 5
13 Understanding the Community 1 2 3 4 5
14 Achievement of Desired Outcomes 1 2 3 4 5
15 OVERALL PERFORMANCE 1 2 3 4 5

Date: Signature of the Supervisor

54
 PHOTOS & VIDEO LINKS

Figure 1 Learning DFT Internship

BIST Technologies is offering a DFT internship where we're gaining practical
experience with Design for testability. We're combining classroom learning of the
theory behind DFTs with hands-on practice using industry tools. This approach equips
us with both the knowledge and the skills to apply DFTs in various engineering
applications.

Figure 2 T6682 ATE Block Diagram

As part of our DFT internship at BIST Technologies, we're delving of the T6682
ATE block diagram. Understanding how the different blocks within an Automatic Test
Equipment (ATE) interact is crucial for applying DFT knowledge effectively. By
analyzing this diagram, we're gaining insights into how DFT signals are generated,
processed, and used during the testing process. This practical application of theoretical
knowledge bridges the gap between classroom learning and real-world engineering
scenarios.

55
 Figure 3 Scan Operation

During my DFT internship at BIST Technologies, I'm diving deep into the
concept of scan operations. Through classroom guidance, I'm gaining a solid
theoretical understanding of how they function within the DFT framework. To solidify
this knowledge, I'm actively practicing with industry-standard tools. This hands-on
experience allows me to not only grasp the "what" of scan operations but also master
the "how" of implementing them effectively. This combined learning approach ensures
I can confidently apply scan operations in various practical applications.

Figure 4 Scan Compressor Blocks

At BIST Technologies, my DFT internship involves analyzing compressor
blocks. We're learning the theoretical underpinnings of Design for testability (DFTs) in
the classroom. But the exciting part is putting that knowledge to work! We're using
industry-standard DFT tools to scan compressor block diagrams. This hands-on
experience allows us to identify potential problems within the compressors by analyzing
their frequency signatures. It's a powerful way to bridge the gap between theoretical
knowledge and real-world applications of DFTs in the field of compressor diagnostics.

56