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SEM 3 DLCOA IMPORTANT QUESTIONS 💯 ( MU COMPS)

Module 1:- Computer Fundamentals

1. Convert (451.43)10 into octal, binary and hexadecimal and base 7.

2. Subtract using 1's and 2's complement method

a. (21)10-(8)10

b. (73)10-(49)10

i) 147 in to binary

ii) (23A)16 in to Decimal

iii) (135), in to decimal iv) 234 in to BCD

v) 23 in to gray code

Vi) Represent -786.25 using IEEE 754 standards (both single and double precision format

3. Explain logic gates with truth tables

a. AND

b. OR

c. NOT

d. NAND

e. NOR

f. EX-OR

4. Explain Von Neumann Model

Module 2:-Data Representation and Arithmetic algorithms

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5. Explain Booth’s Multiplication algorithm and Perform

a. (16)10 X (3) 10

b. (17)10 X (-5)10

C.Using booths algorithm perform -5 x -3

D.What is the difference between Computer organization and Computer architecture explain it
with examples

6. Explain & perform restoring division when divisor V=3 and dividend D=7.7. Explain & perform
the division using non storing division :

Dividend = 1011

Divisor = 0101

8. Represent 1259.12510 in single precision & double precision format.

Module 3:- Processor Organization and Architecture

9. Difference between multiplexer and demultiplexer with diagram.

10. Difference between encoder and decoder with diagram.

11. Explain following flip-flops

a. SR flip-flop

b. JK flip-flop

c. D flip-flop

d. T flip-flop

12. Explain Instruction cycle in detail

13. Explain any 5 addressing modes.

Module 4 :- Control Unit Design

14. Hardwired v/s Microprogammed control unit (10 points)

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15. Explain the Micro instruction format

Module 5 :- Memory Organization

16. Explain memory hierarchy with diagram.

17. Short Notes on

a. Cache coherency

b. Cache Memory

c. Amdahl’s La

D.Differentiate between SRAM & DRAM

Module 6 :- Principles of Advanced Processor and Buses

18. Explain delayed branch and branch prediction logic

19. Describe Flynn’s classification

20. Explain bus contention & arbitration.

21. Write a short note on : USB

22.Draw and explain 4 stage instruction pipelining and briefly describe the hazards associated
with it
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Digital Logic & Computer Architecture

Sem-III (Computer)
Vision:
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To become a leading department committed @engineeringnotes_mu
to nurture students
centric learning through & skill based transformative IT Education to
create Technocrats & leaders for the service of society.
Mission:
1. To shape ourselves into a learning community to flourish
leadership, team spirit, ethics, listen & respect each other.
2. To provide computer educational experience that transform
student through rigorous course work and by providing an
understanding of the need of the society and industry.
3. To educate students to be professionally IT competent for industry
and research programme by providing industry institute
interaction.
4. To strive for excellence among students by infusing a sense of
excitement in computer innovation, invention, design, creation and
entrepreneurship.
5. To contribute in the service of society by participation of faculty,
staff & students in socio-economic & socio-culture activity.
 Course Objective:
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1. To have thorough understanding of the basic structure
and operation of basic digital circuits and digital computer.
2. To discuss in detail arithmetic operations.
3. To discuss generation of control signals & different type of Buses
4. To study the hierarchical memory and principles of advanced
computing.

Course Outcome:
1. To learn different number systems and basic structure of
computer system.
2. To understand the basic concepts of digital components and to
demonstrate the arithmetic algorithms and control signals.
3. To demonstrate the memory organization and different Buses .
4. To describe the principles of parallel processing .
1. Computer Fundamentals (5Hrs)
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• Introduction to Number System and Codes:

• Number Systems: Binary, Octal, Decimal,
Hexadecimal
• Codes: Grey ,BCD, Excess-3, ASCII, Boolean Algebra.
• Logic Gates :AND,OR,NOT,NAND,NOR,EX-OR
• Basic Organization of Computer and Block Level
functional Units,
• Von Neumann Model.
2. Data Representation and Arithmetic algorithms
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• Binary Arithmetic: Addition, Subtraction, Multiplication,

Division using Sign Magnitude, 1’s and 2’s compliment,
BCD and Hex Arithmetic Operation.
• Booths Multiplication Algorithm, Restoring and Non
restoring Division Algorithm.
• IEEE-754 Floating point Representation.
3. Processor Organization and Architecture (6Hrs)
• Introduction to: Half adder, Full adder, MUX, DMUX,
Encoder, Decoder(IC level).
• Introduction to the Flip Flop: SR, JK, D, T (Truth table).
• Register Organization, Instruction Formats, Addressing
modes, Instruction Cycle, Interpretation and sequencing.
4. Control Unit Design (5Hrs)
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• Hardwired Control Unit: State Table Method, Delay
Element Methods.
• Microprogrammed Control Unit: Micro
Instruction-Format, Sequencing and execution, Micro
operations, Examples of microprograms.
5. Memory Organization (6Hrs)
• Introduction and characteristics of primary and secondary
memory, Memory Hierarchy,2- level Memory
Characteristic, Types of RAM and ROM
• Cache Memory: Concept, locality of reference, Design
problems based on mapping techniques, Cache coherence
and write policies.
• Interleaved and Associative Memory.
6. Principles of Advanced Processor
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@engineeringnotes_mu

• Basic Pipelined Data path and control, data

dependencies, data hazards, branch hazards, delayed
branch, and branch prediction, Performance
measures-CPI, Speedup, Efficiency, throughput, Amdhal’s
law, Flynn’s Classification
• Introduction to multicore architecture
• Introduction to buses: ISA, PCI, USB. Bus Contention and
Arbitration.
Module: 1
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Introduction to Number System and Codes:
Number System:-
A number system of base, or radix r is a system that uses distinct
symbols for r digit.
Numbers are represented by a string of digit symbols.
To determine quantity that number represents, it is necessary to
multiply each digit by an integer power of r and then form the sum of
all weighted digits.
Number system has two component as radix/base and digits.
If radix/base r = N, then digits are 0 to (N-1).
Ex:- If radix r = 5 then digits are 0, 1, 2, 3, and 4.
Standard Number systems are: Decimal, Binary, Octal and
Hexadecimal.
Decimal Number System:-
Base/Radix = 10 and Digits are 0, 1, 2, 3, Join
4, 5,Telegram:-
6, 7, 8, and@engineeringnotes_mu
9.
2 1 0 -1 -2
(123.45)10 = 1X10 + 2X10 + 3X10 + 4X10 + 5X10

Binary Number System:-

Base/Radix = 2 and Digits are 0 and 1.
(101.10)2 = 1X22 + 0X21 + 1X20 + 1X2-1 + 0X2-2
= 4 + 0 + 1 + 0.5 + 0 = (5.5)10
Example2: Convert following Binary numbers to the decimal numbers.
1) (1011)2 2) (1010.10)2 3) (11011.011)2 4) (10.101)2
Octal Number System:-
Base/Radix = 8 and Digits are 0, 1, 2, 3, 4, 5, 6, and 7.
(123.45)8 = 1X82 + 2X81 + 3X80 + 4X8-1 + 5X8-2
= 64 + 16 + 3 + 0.5 + 0.078 = (83.578)10
Example: Convert following Octal numbers to the decimal numbers.
1) (23)8 2) (271.12)8 3) (1234.051)8 4) (765.43)8
Hexadecimal Number System:-
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Base/Radix = 16 and Digits are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, and F.
(123.45)16 = (123.45H) = 1X162 + 2X161 + 3X160 + 4X16-1 + 5X16-2 = (291.269)10

Example: Convert following Hexadecimal numbers to the decimal numbers.

1) (253H) 2) (27A.12H) 3) (1B3F.01H) 4) (ABC.DFH)

Decimal to Binary Conversion.

Procedure for converting integer part of decimal number and fractional part of
decimal number is different.
Example: Convert (14)10 to Binary number.
Solution:-
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Chapter 1
Digital Logic Gates
1.1 Introduction
Electronic devices are of mainly two type as analog devices and digital devices and it work on
analog and digital signal respectively. The signal which changes continuously is known as
analog signal, like when vehicle starts it’s speed increases gradually means it starts with speed
0 km\hr and then reaches to required maximum say 120km\hrs and it is continuously changing.
Electric power is also continuously fluctuating 50 times in a second in India. Examples of
analog signal are electrical power supply, human speech, Thermometer etc. Because of
changing nature of this signal, processing and storage become difficult.
On starting electrical device’s using switch it performs operation as a ON or OFF, having only
two values as HIGH and LOW which is discrete in nature. This type of signals is known as
digital signal. The devices which work on digital signals are known as digital devices.
Examples of digital devices are Computer, Digital devices, Digital pen etc.

Figure 1.1 Analog and Digital waveform.

Difference between Analog Signal and Digital Circuit?

1. Analog signals are difficult to process and store as it is continuously changing while digital
signals are discrete in nature having only two values ZERO (LOW) and ONE (HIGH)
so processing and storage is easy.
2. Analog circuit result is not accurate because of noise while digital signal is more accurate
as there is less noise.
3. Analog circuits consume more power while digital circuits require less power.
4. Transmission of analog signals is difficult and inaccurate while digital signal transmission
is accurate and easy to transfer.
Because of above features digital devices are more preferable. To design digital devices basic
component are used as logic gates.

1
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1.2 Logic Gates

While designing system, number of operations have to be performed like addition,
multiplication etc, to perform such type of operations in digital system basic logic gates are
used which perform similar type of operations with minor changes. Basic logic gates are AND,
OR, NOT, etc. Logic gates work on discrete signal as HIGH (logic 1) and LOW (logic 0) only
and produces digital output only. Logic gates are as follows.
1.2.1 AND Gate
Logical AND operation is similar to the arithmetic multiplication operation where any one
input as zero will give the output as zero. In case of digital gate, input and output is only either
HIGH as Logic 1 or LOW as Logic 0. AND gate also accepts inputs as 1 or 0 and give the
output as 1 or 0.
Figure 1.2 shows symbol for an AND gate where X and Y are the input which will be either 1
or 0 and Q is output which gives output (1) only when all inputs are 1.
X Y Q
X 0 0 0
Q
Y 1 0 0
0 1 0
1 1 1

Figure 1.2 Two input AND gate Table1.1 Truth Table

Truth Table is table which gives all possible input and corresponding o utput for it. Table 1.1
is truth table for two input AND gate with corresponding output, here inputs are X and Y and
output is Q.
Q = X AND Y
=X∩Y
= X.Y
For AND gate input may be more than two but output will be one
1.2.2 OR Gate
Logical OR operation is similar to the arithmetic addition operation where all input as zero will
give the output as zero.
Figure 1.3 shows symbol for an OR gate where X and Y are the input which will be either 1 or
0 and Q is output which gives output (1) when at least one input is 1.

2
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X Y Q
X 0 0 0
Q
Y 1 0 1
0 1 1
1 1 1

Figure 1.3 Two input OR gate Table1.2 Truth Table

Table 1.2 is truth table for two input OR gate with corresponding output, here inputs are X and
Y and output is Q.
Q = X OR Y
=XUY
=X+Y
For OR gate input may be more than two.

1.2.3 NOT Gate

Logical NOT gate is like reverse operation where we perform opposite operation means if input
as 1 then output as 0 and vice versa. NOT gate is also known as Complement gate or inverter.

X Q
X 0 1
Q
1 0

Figure 1.4 NOT gate Table1.3 Truth Table

Table 1.3 is truth table for NOT gate with corresponding output, here input is X and output is
Q.
Q = NOT X
= X’
--
=X
For NOT gate input and output will be only one.

3
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1.2.4 NAND Gate

AND gate followed by NOT gate is NAND gate. Complement or inverter of AND gate output
will be NAND gate. Figure 1.5 shows symbol for the NAND gate where X and Y are input and
Q is output.

X Y Q
X
Q 0 0 1
Y 1 0 1
0 1 1
1 1 0

Figure 1.5 Two input NAND gate Table1.4 Truth Table

Table 1.4 is truth table for two input NAND gate with corresponding output, here inputs are X
and Y will be either 0 or 1 and output is Q will be 1 when at least one inputs are 0. Complement
of truth table of AND gate is the truth table of NAND gate.
-----------
Q = X AND Y
------
= X.Y
While implementation of logical expression basic logical gates used are AND, OR and NOT,
but for the same we can use NAND and NOR gate with which we implement any logical
expression that’s why it is known as universal gate. Majority of design use this concept.
Figure 1.6 shows how NAND gates can be used to implement NOT, AND, and OR gates.

X Q=X

(a) NOT Gate

X XY
Q = XY
Y

(b) NAND Gate

4
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X
X

Q = X+Y
Y
Y

(c) OR Gate

Figure 1.6: NOT, AND, and OR gate using only NAND gates.

1.2.5 NOR Gate

OR gate followed by NOT gate is NOR gate. Complement or inverter of OR gate will be NOR
gate. Figure 1.7 shows symbol for the NOR gate where X and Y are the input and Q is output.

X Y Q
X Q 0 0 1
Y
1 0 0
0 1 0
1 1 0

Figure 1.7 Two input NOR gate Table1.5 Truth Table

Table 1.5 is truth table for two input NOR gate with corresponding output, here inputs are X
and Y will be either 0 or 1 and output Q is 1 when both inputs are 0. Complement of truth table
of OR gate is the truth table of NOR gate.
--------
Q= X+Y
--------
= XVY
NOR gate is also universal gate so it is also used to implement AND, OR, and NOT gate.

5
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X Q Q
Y

Y
NOR gate using OR and NOT gate.

1.2.6 EXOR Gate

The EXOR (Exclusive OR) is another gate where X and Y are the inputs and Q is output.
Figure 1.8 shows the symbol of it.

X Y Q
X Q 0 0 0
Y 1 0 1
0 1 1
1 1 0

Figure 1.8 EXOR gate Table1.6 Truth Table

Table 1.6 is truth table for EXOR, here inputs are X and Y will be either 0 or 1 and output Q
is 1 when both inputs are different.
In digital circuit we required condition where we want output 1 when input are different as 01
or 10.

1.3 Boolean Algebra

Boolean algebra is the rules use on Boolean variable for performing manipulation on Boolean
expression which is necessity in digital systems. We know that digital logic work on digital
signals which is either logic 1 (HIGH) or logic 0 (LOW).
The number system having base 2 and digit in it as 0 and 1 is known as Binary Number System
which is used digital systems like computer, calculator, camera, mobile, etc.
We consider logical variable as X and Y having value as 0 or 1 at particular time.

Boolean Expression Law Example (If X=1, Y=0, Z=1)

X+X=X.X=X Idempotent 1+1=1 .1=1
X+1=1 Annulment 1+0=1
X .0=0 1 .0=0
X+0=X Identity 1+0=1
X .1=X 1 .1=1

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--- Complement ---

X+X =1 1+1 =1
--- ---
X .X =0 1 .1 =0

X+Y=Y+X Commutative 1+0=0+1=1

X .Y= Y.X 1 .0=0 .1=0
X.(Y . Z) = (X . Y).Z Associative 1(0 . 1) = (1 . 0)1 = 0
X.(Y + Z) = (X +Y).Z 1(0 + 1) = (1 + 0)1 = 1
X.(X + Y) = X + ( X . Y) = X Absorption 1.(1 + 0) = 1 + (1 . 0) = 1
--------- --- --- De Morgan Theorems --------- --- ---
(X + Y ) = X . Y (1 + 0 ) = 1 . 0 = 0
--------- --- --- --------- --- ---
(X . Y ) = X + Y (1 . 0 ) = 1 + 0 = 1

Table1.7 Boolean Algebra Rules

7
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Computer: Computer is a fast electronic device, which accepts DIGITISED information as input; process
it according to the PROGRAM stored in its memory, and gives the resultant output.

Computer Architecture Computer Organization

Computer Architecture is concerned with the way Computer Organization is concerned with the
hardware components are connected together to structure and behavior of a computer system as
form a computer system. seen by the user.

It acts as the interface between hardware and It deals with the components of a connection in
software. a system.

Computer Architecture helps us to understand the Computer Organization tells us how exactly all
functionalities of a system. the units in the system are arranged and
interconnected.

A programmer can view architecture in terms of Whereas Organization expresses the realization
instructions, addressing modes and registers. of architecture.

While designing a computer system architecture is An organization is done on the basis of

considered first. architecture.

Computer Architecture deals with high-level design Computer Organization deals with low-level
issues. design issues.

Architecture involves Logic (Instruction sets, Organization involves Physical Components

Addressing modes, Data types, Cache optimization) (Circuit design, Adders, Signals, Peripherals)

Basic Organization of a Computer System

Any computer can perform the four basic operations of Input, Processing, Output, and
Storage (IPOS). These operations constitute the IPOS cycle. The internal design or
structure of a computer may differ from one system to another though the basic operations
remain the same. Figure 1.1 provides a block diagram of a computer. The figure displays all
the functional units of a computer which carry out the basic computer operations. The lines
in the figure indicate the flow of instructions and data, while the Control Unit and the
Arithmetic/Logical Unit together direct the flow of control in the central processing unit.
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Input Unit

Data and instructions are entered into the computer through the input unit to get processed
into information. Input devices like the keyboard, the mouse, or the microphone are used to
enter the data. The data is entered in various forms depending on the type of input devices.
For instance, a keyboard can be used to input characters, numbers, and certain symbols; a
mouse is a device that has an on-screen pointer that enables the users to select items and
choose options; a microphone can be used if the user wishes to enter instructions by

Making a voice entry. Regardless of the ways in which the input devices receive the inputs,
the input interfaces convert them into binary codes, i.e., 0s and 1s, as the primary memory
of the computer is designed to accept data only in this format. Several advancements can
be seen in input devices with devices like cordless keyboards, optical mouse, laser mouse,
cordless mouse, etc., being introduced in the market.

Central Processing Unit (CPU)

The actual processing of the data is carried out in the Central Processing Unit (CPU), which
is the brain of computer. The CPU stores the data and instructions in the primary memory of
the computer, called the Random Access Memory (RAM) and processes them from this
location. The Arithmetic Logic Unit (ALU) and the Control Unit (CU) are the two
subcomponents of the CPU. The ALU carries out the arithmetic and logical operations while
the CU retrieves the information from the storage unit and interprets this information. The
CPU also consists of circuitry devices called cache and registers.
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Arithmetic logic unit

The data and instructions stored in the RAM are transferred to the ALU for processing. The
ALU performs the logical and the arithmetic operations on the data and the results are
temporarily stored in the RAM. After the processing, the final results are stored in the
secondary memory, i.e., the storage unit, and are released through an output device.

Control unit

The CU obtains the program instructions stored in the primary memory of the computer,
interprets them, and issues signals that result in their execution. It helps in maintaining
order and directs the operations of the entire system. It selects, interprets, and ensures the
proper execution of the program instructions.

Processors

Some computers use more than one processor for processing in order to reduce the load
on a single processor.

Output Unit

The output unit passes on the final results of computation to the users through the output
devices like the monitor, printer, etc. A monitor displays the final results of the processed
data on the screen while a printer can be used for obtaining the output in a printed format.
These output devices link the computer with the users. The output interfaces convert the
binary code produced by the computer into the human-readable form.

Storage Unit

Before the actual processing takes place, the data and instructions that enter the computer
system have to be stored internally. Also, the final results generated by the computer after
processing has to be stored before being sent to the output unit. The storage unit of a
computer system is designed to store the data generated at various stages of processing.
Storage media like hard disks, floppy disks, etc., aid in storing the data in various forms.
The hard disk is an integral part of the computer system. It is also referred to as hard drive,
disk drive, or hard disk drive. The hard disk provides a large amount of storage space for
the programs and data. Computers these days feature a hard disk that has several
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gigabytes of storage capacity. The floppy disk drives, CD-ROM/CD-RW drives, DVD drives,
and USB ports enable the user to store and exchange data with others using storage media
like floppy disks, compact discs (CDs), digital video discs (DVDs), and pen drives.

Buses
The group of wires over which signal is transfer is known as Bus. There are basic three types of buses.
Address bus, data bus, and control bus.

Address Bus: - The bus over which address is transfer is known as address bus and it is unidirectional.

Data Bus: - The bus over which data is transfer is known as data bus and it is bidirectional.

Control Bus: - The bus over which control signals are transfer is known as control bus and it is
bidirectional.
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Von-Neumann Architecture
In a Von-Neumann architecture (also known as Stored Program Computer), the same
memory and bus are used to store both data and instructions that run the program.
Since you cannot access program memory and data memory simultaneously, the Von
Neumann architecture is susceptible to bottlenecks and system performance is affected.

Harvard Architecture
The Harvard architecture stores machine instructions and data in separate memory
units that are connected by different busses. In this case, there are at least two memory
address spaces to work with, so there is a memory register for machine instructions and
another memory register for data. Computers designed with the Harvard architecture
are able to run a program and access data independently, and therefore
simultaneously. Harvard architecture has a strict separation between data and code.
Thus, Harvard architecture is more complicated but separate pipelines remove the
bottleneck that Von Neumann creates.

`
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1. Half Adder :
Half Adder is a combinational logic circuit which is designed by connecting one EX-OR gate
and one AND gate. The half adder circuit has two inputs: A and B, which add two input digits
and generates a carry and a sum.

The output obtained from the EX-OR gate is the sum of the two numbers while that obtained
by AND gate is the carry. There will be no forwarding of carry addition because there is no
logic gate to process that. Thus, this is called Half Adder circuit.

Logical Expression:
Sum = A XOR B
Carry = A AND B

Truth Table:
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2. Full Adder :

Full Adder is the circuit which consists of two EX-OR gates, two AND gates and one OR gate.
Full Adder is the adder which adds three inputs and produces two outputs which consists of
two EX-OR gates, two AND gates and one OR gate. The first two inputs are A and B and the
third input is an input carry as C-IN. The output carry is designated as C-OUT and the normal
output is designated as S which is SUM.

Equation obtained by EX-OR gate is the sum of the binary digits. While the output obtained by
AND gate is the carry obtained by addition.

Truth Table :

Logical Expression :
SUM = (A XOR B) XOR Cin = (A ⊕ B) ⊕ Cin
CARRY-OUT = A AND B OR Cin(A XOR B) = A.B + Cin(A ⊕ B)
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Difference between Half adder and full adder:

S.No. Half Adder Full Adder

Half Adder is combinational logic Full adder is combinational logical circuit that
circuit which adds two 1-bit digits. performs an addition operation on three one-bit
The half adder produces a sum of the binary numbers. The full adder produces a sum
1 two inputs. of the three inputs and carry value.

2 Previous carry is not used. Previous carry is used.

In Half adder there are two input bits In full adder there are three input bits
3 ( A, B). (A, B, C-in).

Logical Expression for half adder is : Logical Expression for Full adder is :
4 S=a⊕b ; C=a*b. S=a⊕b⊕Cin; Cout=(a*b)+(Cin*(a⊕b)).

It consists of one EX-OR gate and It consists of two EX-OR, two AND gate and
5 one AND gate. one OR gate.

It is used in Calculators, computers, It is used in Multiple bit addition, digital

6 digital measuring devices etc. processors etc.

Multiplexer and Demultiplexer

In this tutorial, we will take a brief look at two important Combinational Logic Circuits
called Multiplexer and Demultiplexer. A Multiplexer is a circuit that accept many inputs but
gives only one output. A Demultiplexer functions exactly in the reverse way of a
multiplexer i.e., a demultiplexer accepts only one input and gives many outputs. Generally,
multiplexer and demultiplexer are used together in many communication systems.

Multiplexer
Multiplexer means many into one. A multiplexer is a circuit used to select and route any
one of the several input signals to a single output. A simple example of an non-electronic
circuit of a multiplexer is a single pole multi-position switch.

Multi-position switches are widely used in many electronics circuits. However, circuits that
operate at high speed require the multiplexer to be automatically selected. A mechanical
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switch cannot perform this task efficiently. Therefore, multiplexer is used to perform high
speed switching are constructed of electronic components.

Multiplexers can handle two type of data i.e., analog and digital. For analog application,
multiplexer are built using relays and transistor switches. For digital application, they are
built from standard logic gates.

The multiplexer used for digital applications, also called digital multiplexer, is a circuit with
many input but only one output. By applying control signals (also known as Select
Signals), we can steer any input to the output. Some of the common types of multiplexer
are 2-to-1, 4-to-1, 8-to-1, 16-to-1 multiplexer.

Following figure shows the general idea of a multiplexer with n input signal, m control
signals and one output signal.

Understanding 4-to-1 Multiplexer

The 4-to-1 multiplexer has 4 input bits, 2 control or select bits, and 1 output bit. The four
input bits are D0,D1,D2 and D3. Only one of this is transmitted to the output Y. The
output depends on the values of A and B, which are the control inputs. The control input
determines which of the input data bit is transmitted to the output.
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For instance, as shown in figure, when A B = 0 0 , the upper AND gate is enabled, while
all other AND gates are disabled. Therefore, data bit D0 is transmitted to the output,
giving Y = Do.

If the control input is changed to A B = 1 1 , all gates are disabled except the bottom
AND gate. In this case, D3 is transmitted to the output and Y = D3.

 An example of 4-to-1 multiplexer is IC 74153 in which the output is same as the

input.
 Another example of 4-to-1 multiplexer is 45352 in which the output is the
compliment of the input.
 Example of 16-to-1 line multiplexer is IC 74150.
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Applications of Multiplexer
Multiplexer are used in various fields where multiple data need to be transmitted using a
single line. Following are some of the applications of multiplexers –

1. Communication System – Communication system is a set of system that enable

communication like transmission system, relay and tributary station, and
communication network. The efficiency of communication system can be increased
considerably using multiplexer. Multiplexer allow the process of transmitting
different type of data such as audio, video at the same time using a single
transmission line.
2. Telephone Network – In telephone network, multiple audio signals are integrated
on a single line for transmission with the help of multiplexers. In this way, multiple
audio signals can be isolated and eventually, the desire audio signals reach the
intended recipients.
3. Computer Memory – Multiplexers are used to implement huge amount of memory
into the computer, at the same time reduces the number of copper lines required to
connect the memory to other parts of the computer circuit.
4. Transmission from the Computer System of a Satellite – Multiplexer can be
used for the transmission of data signals from the computer system of a satellite or
spacecraft to the ground system using the GPS (Global Positioning System)
satellites.
This is just an introduction to the concept of Multiplexer. To learn more about Multiplexers,
read this Multiplexer (MUX) and Multiplexing tutorial.

Demultiplexer
Demultiplexer means one to many. A demultiplexer is a circuit with one input and many
outputs. By applying control signal, we can steer any input to the output. Few types of
demultiplexer are 1-to 2, 1-to-4, 1-to-8 and 1-to 16 demultiplexer.

Following figure illustrate the general idea of a demultiplexer with 1 input signal, m control
signals, and n output signals.
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Understanding 1-to-4 Demultiplexer

The 1-to-4 demultiplexer has 1 input bit, 2 control or select bits, and 4 output bits. An
example of 1-to-4 demultiplexer is IC 74155. The 1-to-4 demultiplexer is shown in figure
below-
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The input bit is labelled as Data D. This data bit is transmitted to the selected output lines,
which depends on the values of A and B, the control or Select Inputs.

When A B = 0 1 , the second AND gate from the top is enabled while other AND gates are
disabled. Therefore, data bit D is transmitted to the output Y1, giving Y1 = Data.

If D is LOW, Y1 is LOW. If D is HIGH, Y1 is HIGH. The value of Y1 depends upon the value
of D. All other outputs are in low state.

If the control input is changed to A B = 1 0, all the gates are disabled except the third
AND gate from the top. Then, D is transmitted only to the Y2 output, and Y2 = Data.

Example of 1-to-16 demultiplexer is IC 74154. It has 1 input bit, 4 control / select bits and
16 output bits.

Applications of Demultiplexer
1. Demultiplexer is used to connect a single source to multiple destinations. The main
application area of demultiplexer is communication system, where multiplexers are
used. Most of the communication system are bidirectional i.e., they function in both
ways (transmitting and receiving signals). Hence, for most of the applications, the
multiplexer and demultiplexer work in sync. Demultiplexer are also used for
reconstruction of parallel data and ALU circuits.
2. Communication System – Communication system use multiplexer to carry
multiple data like audio, video and other form of data using a single line for
transmission. This process make the transmission easier. The demultiplexer receive
the output signals of the multiplexer and converts them back to the original form of
the data at the receiving end. The multiplexer and demultiplexer work together to
carry out the process of transmission and reception of data in communication
system.
3. ALU (Arithmetic Logic Unit) – In an ALU circuit, the output of ALU can be stored
in multiple registers or storage units with the help of demultiplexer. The output of
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ALU is fed as the data input to the demultiplexer. Each output of demultiplexer is
connected to multiple register which can be stored in the registers.
4. Serial to Parallel Converter – A serial to parallel converter is used for
reconstructing parallel data from incoming serial data stream. In this technique,
serial data from the incoming serial data stream is given as data input to the
demultiplexer at the regular intervals. A counter is attach to the control input of the
demultiplexer. This counter directs the data signal to the output of the demultiplexer
where these data signals are stored. When all data signals have been stored, the
output of the demultiplexer can be retrieved and read out in parallel.
This is just an introduction to the concept of Demultiplexer. To learn more about
Demultiplexers, read this What is Demultiplexer (DEMUX) tutorial.

1. Multiplexer :
Multiplexer is a data selector which takes several inputs and gives a single output. In
multiplexer we have 2n input lines and 1 output lines where n is the number of selection
lines.

2. Demultiplexer :
Demultiplexer is a data distributor which takes a single input and gives several outputs. In
demultiplexer we have 1 input and 2 n output lines where n is the selection line.
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Difference between of Multiplexer and Demultiplexer :

Multiplexer Demultiplexer

Multiplexer processes the digital Demultiplexer receives digital information

information from various sources into a from a single source and converts it into
single source. several sources

It is known as Data Selector It is known as Data Distributor

Multiplexer is a digital switch Demultiplexer is a digital circuit

It follows combinational logic type It also follows combinational logic type

It has n data input It has single data input

It has a single data output It has n data outputs

It works on many to one operational

principle It works on one to many operational
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1. Encoders –
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An encoder is a combinational circuit that converts binary information in the form of a
2N input lines into N output lines, which represent N bit code for the input. For simple
encoders, it is assumed that only one input line is active at a time.
As an example, let’s consider Octal to Binary encoder. As shown in the following figure, an
octal-to-binary encoder takes 8 input lines and generates 3 output lines.

Truth Table –
Input Output

D7 D6 D5 D4 D3 D2 D1 D0 X Y Z

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1

As seen from the truth table, the output is 000 when D0 is active; 001 when D1 is active;
010 when D2 is active and so on.
Implementation –
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From the truth table, the output line Z is active when the input octal digit is 1, 3, 5 or 7.
Similarly, Y is 1 when input octal digit is 2, 3, 6 or 7 and X is 1 for input octal digits 4, 5, 6 or
7. Hence, the Boolean functions would be:
X = D4 + D5 + D6 + D7
Y = D2 +D3 + D6 + D7
Z = D1 + D3 + D5 + D7
Hence, the encoder can be realised with OR gates as follows:

One limitation of this encoder is that only one input can be active at any given time. If more
than one input is active, then the output is undefined. For example, if D6 and D3 are both
active, then, our output would be 111 which is the output for D7. To overcome this, we use
Priority Encoder
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2. Decoders –
A decoder does the opposite job of an encoder. It is a combinational circuit that converts n
lines of input into 2 n lines of output.
Let’s take an example of 3-to-8 line decoder.
Truth Table –
Input Output

X Y Z D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 1 0 0 0 0 0 0 0

0 0 1 0 1 0 0 0 0 0 0

0 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 1 0 0

1 1 0 0 0 0 0 0 0 1 0

1 1 1 0 0 0 0 0 0 0 1

Implementation –
D0 is high when X = 0, Y = 0 and Z = 0. Hence,
D0 = X’ Y’ Z’
Similarly,
D1 = X’ Y’ Z
D2 = X’ Y Z’
D3 = X’ Y Z
D4 = X Y’ Z’
D5 = X Y’ Z
D6 = X Y Z’
D7 = X Y Z
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Hence,

Flip Flops

A flip flop is an electronic circuit with two stable states that can be used to store binary data.
The stored data can be changed by applying varying inputs. Flip-flops and latches are
fundamental building blocks of digital electronics systems used in computers,
communications, and many other types of systems. Both are used as data storage elements.
It is the basic storage element in sequential logic. But first, let’s clarify the difference between
a latch and a flip-flop.

Flip flop v/s Latch

The basic difference between a latch and a flip-flop is a gating or clocking mechanism.
In Simple words. Flip Flop is edge-triggered and a latch is level triggered.
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For example, let us talk about SR latch and SR flip-flops. In this circuit when you Set S as
active the output Q would be high and Q’ will be Low. This is irrespective of anything else.
(This is an active-low circuit so active here means low, but for an active high circuit active
would mean high)

SR Latch
A flip-flop, on the other hand, is synchronous and is also known as a gated or clocked SR
latch.

SR Flip-Flop

In this circuit diagram, the output is changed (i.e. the stored data is changed) only when you
give an active clock signal. Otherwise, even if the S or R is active the data will not change.
Let’s look at the types of flip-flops to understand better.

SR Flip Flop

There are majorly 4 types of flip-flops, with the most common one being SR flip-flop. This
simple flip-flop circuit has a set input (S) and a reset input (R). In this system, when you Set
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“S” as active the output “Ǫ” would be high and “ Ǭ ” will be low. Once the outputs are
established, the wiring of the circuit is maintained until “S” or “R” go high, or power is turned
off. As shown above, it is the simplest and easiest to understand. The two outputs, as shown
above, are the inverse of each other. The truth table of SR Flip-Flop is highlighted below.

Input Output
CLK S R Qn+1
1 0 0 Qn
1 0 1 0
1 1 0 1
1 1 1 ?

JK Flip-flop

Due to the undefined state in the SR flip-flop, another flip-flop is required in electronics. The
JK flip-flop is an improvement on the SR flip-flop where S=R=1 is not a problem.

The input condition of J=K=1, gives an output inverting the output state. However, the outputs
are the same when one tests the circuit practically.

In simple words, If J and K data input are different (i.e. high and low) then the output Q takes
the value of J at the next clock edge. If J and K are both low then no change occurs. If J and
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K are both high at the clock edge then the output will toggle from one state to the other. JK
Flip-Flops can function as Set or Reset Flip-flops.

Input Output
CLK J K Qn+1
1 0 0 Qn
1 0 1 0
1 1 0 1
1 1 1 Ǭn

D Flip Flop

D flip-flop is a better alternative that is very popular with digital electronics. They are
commonly used for counters and shift-registers and input synchronization.

In this, the output can be only changed at the clock edge, and if the input changes at other
times, the output will be unaffected.

Input Output
CLK D Qn+1
1 0 0
1 1 1

The change of state of the output is dependent on the rising edge of the clock. The output (Q)
is same as the input and can only change at the rising edge of the clock.
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T Flip Flop

A T flip-flop is like a JK flip-flop. These are basically a single input version of JK flip-flops. This
modified form of JK flip-flop is obtained by connecting both inputs J and K together. It has
only one input along with the clock input.

These flip-flops are called T flip-flops because of their ability to complement its state (i.e.)
Toggle, hence the name Toggle flip-flop.

Input Output
CLK T Qn+1
1 0 Ǫn
1 1 Ǭn

Applications of Flip-Flops

These are the various types of flip-flops being used in digital electronic circuits and the
applications of Flip-flops are as specified below.

 Counters

 Frequency Dividers

 Shift Registers

 Storage Registers
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Chapter 2

Number Systems and Codes

2.1 Introduction
Number system is comprising of two components as Base and Digits. Base is also known as
Radix. Consider the number 4567. This number may be written as 4X103 + 5X102 + 6X101 +
7X100. In this number 10 is Base\Radix and 4,5,6 and 7 are digits within this number. In general
number system having base b and digits as an, an-1, an-2, ………., a1, a0 can be represented as
anbn + an-1bn-1 + an-2bn-2 + ………….. + a1b1 +a0b0. Number of digits within number system will be
0 to (b-1). Where (b-1) is value of base of the number system minus 1. Base of the number is
written as a suffix to the number. The number (122.56)10 is having base=10 so it is decimal
number. The number systems used in digital systems like computer, calculator, camera, are
Binary, Octal and Hexadecimal. These number systems are discus in details in following topics.

2.2 Decimal Number System

We are already familiar with this number system having digits as 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 and
base as 10. The number system having base 10 is Decimal number system.
(123.56)10 = 1X102 + 2X101 + 3X100 + 5X10-1 + 6X10-2 .

2.3 Binary Number System

Binary means two, the number system with base 2 is known as Binary number system. Digits
within this number is 0 and 1 only. This number system is widely used in digital gates which is
integral part of digital systems, like calculator, computer.
(10101)2 = 1X24 + 0X23 + 1X22 + 0X21 + 1X20 .

2.3.1 Binary to Decimal Conversion.

For converting number of any base to decimal number simply expanding the given number it
will give the number converted in decimal format.
Example1: Convert Binary number (10101)2 to the decimal number.
Solution: For converting the number (10101)2 into decimal expand it.

(10101)2 = 1X24 + 0X23 + 1X22 + 0X21 + 1X20

= 16 + 0 + 4 + 0 + 1
= (21)10.
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Example2: Convert following Binary numbers to the decimal numbers.

1) (1011)2 2) (1010.10)2 3) (11011.011)2 4) (10.101)2
Solution: 1) (1011)2 = 1X23 + 0X22 + 1X21 + 1X20
= 8+0+2+1
= (11)10
2) (1010.10)2 = 1X23 + 0X22 + 1X21 + 0X20 + 1X2-1 + 0X2-2
= 8 + 0 + 2 + 0 + 0.5 + 0
= (10.5)10
3) (11011.011)2 = 1X24 + 1X23 + 0X22 + 1X21 + 1X20 + 0X2-1 + 1X2-2 + 1X2-3
= 16 + 8 + 0 + 2 + 1 + 0.25 + 0.125
= (27.375)10
4) (10.101)2 = 1X21 + 0X20 + 1X2-1 + 0X2-2 + 1X2-3
= 2 + 0 + 0.5 + 0 + 0.125
= (2.625)10

2.3.2 Decimal to Binary Conversion.

Procedure for converting integer part of decimal number and fractional part of decimal
number is different. For integer part perform continuous division to the decimal number by 2
(Base of binary number) and note down the reminder. Reminder is giving the answer. While
for fractional part of decimal number perform continuous multiplication, if product of
multiplication is greater than or equal to 1 then note down 1 else 0. Following example
illustrate the conversion procedure.

Example3: Convert (14)10 to Binary number.

Solution: Steps for conversion.
i) Given decimal number is 14 divide it by 2.
14/2 => Quotient = 7 and Reminder = 0
ii) Now divide to the Quotient 7 by 2.
7/2 => Quotient = 3 and Reminder = 1
iii) Again divide to the Quotient 3 by 2.
3/2 => Quotient = 1 and Reminder = 1
iv) Lastly divide to the quotient 1 by 2.
1/2 => Quotient = 0 and Reminder = 1
For conversion result collect reminder in a sequence as start from step no iv to step no i.
(1110)2

Above procedure is shown in following diagram.

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2 14 7 3 1
0 1 1 1
↑

MSB of Binary Number

(14)10 = (1110)2
In binary number 1110 most significant bit (MSB) is 1 which is at left most side. In binary
number 0 and 1 is known as bit. Bit is minimum unit of data.
Example4: Convert (0.25)10 into binary number.
Solution: Steps for conversion.
i) Given decimal number is 0.25 multiply it by 2.
0.25X2 = 0.50
Integer part of answer = 0 and Fractional part of answer = 0.50
If product is greater than or equal to 1 then restore 1 else restore 0.
In this example product is less than 0 so restore 0
ii) Now multiply only to the Fraction of step i which is 0.50 by 2.
0.50X2 = 1.00
Integer part of answer = 1 and Fractional part of answer = 0
As product is 1 so restore 1 and fraction is 0 stop the procedure.

For conversion result collect restored bits from step no I onwards followed by decimal point.
(0.01)2
Above procedure is shown in figure 2.

SN Only Fractional Part Product Restored bit

1 0.25 X 2 0.50 0 ← MSB
2 0.50 X 2 1.00 1
(0.25)10 = (0.01)2

Example5: Convert (27.125)10 into binary number.

Solution: First convert integer part of given number which is 27 then convert fractional part
of given number which is (0.125)
Integer part conversion

2 27 13 6 3 1
1 1 0 1 1← MSB
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(27)10 = (11011)2
Fractional Part conversion

SN Only Fractional Part Product Restored bit

1 0.125 X 2 0.250 0 ← MSB
2 0.250 X 2 0.500 0
3 0.500 X 2 1.000 1
(0.125)10 = (0.001)2

(27.125)10 = (11011.001)2
Example6: Convert following number into binary number.
1) (39.325)10 2) (55.42)10 3) (170.12)10 4) (1220.065)10

Solution:
1) (39.325)10
Integer part conversion
2 39 19 9 4 2 1
1 1 1 0 0 1 ← MSB

(39)10 = (100111)2
Fractional Part conversion

SN Only Fractional Part Product Restored bit

1 0.352 X 2 0.704 0 ← MSB
2 0.704 X 2 1.408 1
3 0.408 X 2 0.816 0
4 0.816 X 2 1.632 1
5 0.632 X 2 1.264 1
6 0.264 X 2 0.528 0
7 0.528 X 2 1.056 1
8 0.056 X 2 0.112 0
9 0.112 X 2 0.224 0
10 0.224 X 2 0.448 0
(0.352)10 = (0.0101101000)2

While multiplying after getting first restoring bit as 1 continue multiplying till two consecutive
same restoring bits (00 or 11) then stop multiplying. If more precise result is expected then
continue multiplying till three or four same consecutive restoring bits depending on
requirement.

In above example you can stop multiplying after fifth step.

(39.325)10 = (100111.0101101000)2
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2) (55.42)10
Integer part conversion

2 55 27 13 6 3 1
1 1 1 0 1 1 ← MSB

Fractional part conversion

SN Only Fractional Part Product Restored bit

1 0.42 X 2 0.84 0 ← MSB
2 0.84 X 2 1.68 1
3 0.68 X 2 1.36 1
(0.42)10 = (0.011)2

(55.42)10 = (110111.011)2
3) (170.12)10
Integer part conversion

2 170 85 42 21 10 5 2 1
0 1 0 1 0 1 0 1 ← MSB

Fractional part conversion

SN Only Fractional Part Product Restored bit

1 0.12 X 2 0.24 0 ← MSB
2 0.24 X 2 0.48 0
3 0.48 X 2 0.96 0
4 0.96 X 2 1.92 1
5 0.92 X 2 1.84 1
(0.12)10 = (0.00011)2

(170.12)10 = (10101010.00011)2

4) (1220.065)10
Integer part conversion
2 1220 610 305 152 76 38 19 9 4 2 1
0 0 1 0 0 0 1 1 0 0 1 ← MSB
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Fractional part conversion

SN Only Fractional Part Product Restored bit

1 0.065 X 2 0.13 0 ← MSB
2 0.13 X 2 0.26 0
3 0.26 X 2 0.52 0
4 0.52 X 2 1.04 1
5 0.04 X 2 0.08 0
6 0.08 X 2 0. 16 0
(0.065)10 = (0.000100)2

(1220.065)10 = (10011000100.000100)2

2.3.2 Binary Number Representation

The Binary number is used to represent data within the computer. Data may be numerical,
alphanumerical or symbols. Different means are used to represent different type of data.
Numerical data may be integer or floating-point data. Integer and floating-point data may be
signed or unsigned. We have already seen how to represent unsigned integer numbers. As an
example decimal number 13 which is positive is represented in binary as 1101. (13)10 =
(1101)2. Representation of unsigned integer in binary is nothing but simply binary
representation.

To represent Signed Integer Binary Numbers following methods are used.

1. Signed Magnitude Representation.
2. Signed 1’s Complement Representation.
3. Signed 2’s Complement Representation.
1. Signed Magnitude Representation.
Signed Magnitude representation is method in which 1-bit as most significant bit
(MSB) is used to represent sign of the number and other bits are used to represent magnitude.
For positive number signed bit is 0 while for negative number it is 1. For example (+13)10 is
represented as (01101)2 and (-13)10 is represented as (11101), to represent number in sign
magnitude representation number of bits required is bits required to represent the number
plus one additional bit for sign representation. If you want to represent same number in 8-bit
format it is represented as follows.
(+13)10

0 0 0 0 1 1 0 1
↑
Sign Bit

(-13)10
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1 0 0 0 1 1 0 1
↑
Sign Bit

2. Signed 1’s Complement Representation.

Signed 1’s complement of binary number is nothing but interchange of bits means 0
is replace by 1 and 1 is replace by 0. After calculating 1’s complement of number if you
complement again, it gives original number means given number and it’s 1’s complement is
complemented of each other’s. Calculating compliment of number means changing sign of a
number, positive number become negative and negative number become positive. Note that
above method interchange of bits for calculating 1’s complement of a number is applicable
for negative numbers only. While for positive number it is simply sign magnitude
representation. For example (+13)10 in 1’s complement is represented as (01101)2 and (-13)10
as (10010)2. If you want to represent same number in 8-bit format it is represented as follows.

(+13)10

0 0 0 0 1 1 0 1
↑
Sign Bit

(-13)10

1 1 1 1 0 0 1 0
↑
Sign Bit

3. Signed 2’s Complement Representation.

2’s Complement of binary number is calculated by adding 1 in the 1’s complement of the
number. Note that above method for calculating 2’s complement of a number is applicable
for negative numbers only. While for positive number it is simply sign magnitude
representation. For example (+13)10 in 1’s complement is represented as (01101)2 & (-13)10
as (10011). If you want to represent same number in 8-bit format it is represented as follows.
(+13)10

0 0 0 0 1 1 0 1
↑
Sign Bit

(-13)10

1 1 1 1 0 0 1 1
↑
Sign Bit
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Note: - Simplified method to calculate 2’s compliment of number is as follows.

Step1: Search for first incoming 1 from least significant bit (LSB) side.
Step2: Restore as it is all the bits including first incoming 1 of LSB.
Step3: Interchange other bits 0 to 1 and 1 to 0.
Following table shows 2’s complement of binary number (01010)2 using simplified
method.

1st Incoming 1 LSB

Step 1 → ↓ ↓
Given No. → 0 1 0 1 0
Step 2 & 3 → ←-------------------Interchange-----------------→ ←------Restore as it is------→
2’s Comp. → 1 0 1 1 0

Example7: Represent following numbers in signed magnitude, 1’s Complement and 2’s
Complement format.
a) +6 and -6 b) +9 and -9 c) +21 and -21 d) +35 and -35
Solution: Following table shows representation of above numbers.

SN Number Sign 1’s 2’s

Magnitude Complement Complement
A +6 0110 0110 0110
-6 1110 1001 1010
B +9 01001 01001 01001
-9 11001 10110 10111
C +21 010101 010101 010101
-21 110101 101010 101011
D +35 0100011 0100011 0100011
-35 1100011 1011100 1011101

2.3.3 Arithmetic Operation on Binary Numbers

Basic operation perform on binary numbers are addition, subtraction, multiplication
and division.
Addition: - Rule for binary addition are as follows.
0+0=0

0+1=1
1+0=1
1 + 1 = 10 here 0 is Sum and 1 is Carry.
Example8: Perform binary addition for following numbers.
a) 101 + 110 b) 1010 and 1011 c) 11001 + 10011 + 10110
d) 110110 + 111101 + 110001 + 110011
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Solution: a)
1 0 1
+ 1 1 0
_____________________
1 0 1 1

b)
1 ← Carry
1 0 1 0
+ 1 0 1 1
__________________________
1 0 1 0 1

c)
1 0 1 1 1 1 ← Carry
1 1 0 0 1
+ 1 0 0 1 1
+ 1 0 1 1 0
________________________________
1 0 0 0 0 1 0

d)

1 0 } ← Carry
1 0 1 1 1 1
1 1 0 1 1 0
+ 1 1 1 1 0 1
+ 1 1 0 0 0 1
+ 1 1 0 0 1 1
______________________________________
1 1 0 1 0 1 1 1

Subtraction: - To perform binary subtraction operation two methods are used. First method
is using 1’s complement and second method is using 2’s complement.
1’s Complement Method: Following steps are used to perform subtraction operation.
Step1- Convert both numbers in binary format if numbers are not in binary numbers.
Step2- Take 1’s Complement of subtrahend.
Step3- Perform addition operation. (1’s complement method convert number into
negative so perform addition operation.)
Step4- After addition check for following condition
1. If carry is generated then add it into answer to get final answer.
2. If MSB of answer is 1 it indicates that answer is negative.
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Example9: Perform binary subtraction using 1’s Complement method for following numbers.
1) 1010 – 0100 2) 1001 – 1100 3) 10111 – 11001 4) 110011 – 111011
Solution: 1) 1010 – 0100 = 0110
0100 is subtrahend so take it’s 1’s complement, which is 1011 and perform
addition.

1 1 ← Carry
1 0 1 0
+ 1 0 1 1
1 0 1 0 1
In this example carry is generated so add it into the answer.

0 1 0 1
+ 1
0 1 1 0
2) 1001 – 1100 = 1100
1’ s Complement of 1100 is 0011

1 1 ← Carry
1 0 0 1
+ 0 0 1 1
1 1 0 0
MSB of answer is 1 indicate that answer is negative.

3) 10111 – 11001 = 11101

1’s Complement of 11001 is 00110

1 1
1 0 1 1 1
+ 0 0 1 1 0
1 1 1 0 1
MSB of answer is 1 indicate that answer is negative.

4) 110011 – 111011 = 110111

1’s Complement of 111011 is 000100

1 1 0 0 1 1
+ 0 0 0 1 0 0
1 1 0 1 1 1
MSB of answer is 1 indicate that answer is negative.
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2’s Complement Method: Following steps are used to perform subtraction operation.
Step1- Convert both numbers in binary format if numbers are not in binary numbers.
Step2- Take 2’s Complement of subtrahend.
Step3- Perform addition operation. (2’s complement method convert number into
negative so perform addition operation.)
Step4- After addition check for following condition
1. If carry is generated then ignore it.
2. If MSB of answer is 1 it indicates that answer is negative.

Example10: Perform binary subtraction using 2’s Complement method for following
number.
1) 1011 – 0101 2) 1000 – 1100 3) 10101 – 11101 4) 100001 – 111100

Solution: 1) 1011 – 0101 = 0110 = (6)

0101 is subtrahend so take it’s 2’s complement, which is 1011 and perform
addition.

1 1 1
1 0 1 1
+ 1 0 1 1
1 0 1 1 0
Carry is generated, ignore it.

2) 1000 – 1100 = 1100 = (-4)

1100 is subtrahend so take it’s 2’s complement, which is 0100 and perform
addition.

1 0 0 0
+ 0 1 0 0
1 1 0 0
As Sign bit of answer is 1, indicate that number is negative.

3) 10101 – 11101 = 11000 = (-8)

11101 is subtrahend so take it’s 2’s complement, which is 00011 and perform
addition.

1 1 1
1 0 1 0 1
+ 0 0 0 1 1
1 1 0 0 0
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4) 100001 – 111100 = 100101 = (-27)

111100 is subtrahend so take it’s 2’s complement, which is 000100.

1 0 0 0 0 1
+ 0 0 0 1 0 0
1 0 0 1 0 1

Multiplication: Binary Multiplication is similar to decimal multiplication in which bit by bit

Multiplication will be performed with selecting every bit of multiplier,
multiplied to every bit of multiplicand then all partial products are added
to get the final product. In binary multiplication if multiplier bit is 1 then
partial product will be same as multiplicand and if multiplier bit is 0 then
partial product will be 0.
Example: - Multiply 1010 by 1011
Solution: -

1 0 1 0 Multiplicand
X 1 0 1 1 Multiplier
1 0 1 0 Partial Product-I
+ 1 0 1 0 x Partial Product-II
+ 0 0 0 0 x x Partial Product-III
+ 1 0 1 0 x x x Partial Product-IV
1 1 0 1 1 1 0 Final Product

Division: -Binary division is also similar to decimal division in which dividend is divided by
divisor and we get answer as quotient and reminder.
Example: - Divide 11110101 by 1000
Solution: -
11110
__________
1000) 11110101
1000
1110
1000
1101
1000
1010
1000
101
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2.4 Octal Number System

Octal means eight, the number system with base 8 is known as Octal number. Digits within
this number are 0 to 7. This number system is used for specific application in digital systems.
(34)8, (236)8, (503)8, (427)8 are the octal numbers.
2.4.1 Octal to Decimal Conversion.
Similar to binary to decimal conversion expanding the given number will give the number in
decimal format.
Example11: Convert Octal number (456)8 to the decimal number.

Solution: For converting the number (456)8 into decimal expand it.
(456)8 = 4X82 + 5X81 + 6X80
= 256 + 40 + 6
= (302)10.
Example12: Convert following Octal numbers to the decimal numbers.
1) (23)8 2) (271.12)8 3) (1234.051)8 4) (765.43)8
Solution: 1) (23)8 = 2X81 + 3X80
= 16 + 3

= (19)10
2) (271.12)8 = 2X82 + 7X81 + 1X80 +1X8-1 + 2X 8-2
= 128 + 56 + 1 + 0.125 + 0.125
= (185.25)10
3) (1234.051)8 = 1X83 + 2X82 + 3X81 + 4X80 + 0X8-1 + 5X8-2 + 1X8-3
= 512+ 128 + 24 + 4 + 0.3125 + 0.00195
= (668.31445)10
4) (765.43)8 = 7X82 + 6X81 + 5X80 + 4X8-1 + 3X8-2
= 448 + 48 + 5 + 0.5 + 0.0468
= (501.5468)10

2.4.2 Decimal to Octal Conversion.

Procedure for converting decimal number to octal is same as decimal to binary
conversion. As base for octal number is 8 so for converting decimal number to octal divide by
8 and converted octal number may contain digits from 0 to 7.
Example13: Convert following number to Octal number.
1) (46)10 2) (789)10 3) (92.54)10 4) (969.8935)10
Solution: Procedure is shown in following figures
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1) (46)10
8 46 5
6 5 ← MSB
(46)10 = (56)8

2) (789)10
8 789 98 12 1
5 2 4 1 ← MSB
(789)10 = (1425)8

3) (92.54)10

First convert integer part of number that is 92.

8 92 11 1
4 3 1 ← MSB
(92)10 = (134)8
Fractional part conversion

SN Only Fractional Part Product Restored bit

1 0.54 X 8 4.32 4 ← MSB
2 0.32 X 8 2.56 2
3 0.56 X 8 4.48 4
4 0.48 X 8 3.84 3
(0.54)10 = (0.4243)8
(92.54)10 = (134.4243)8

4) (969.8935)10

First convert integer part of number that is 92.

8 969 121 15 1
1 1 7 1 ← MSB
(969)10 = (1711)8
Fractional part conversion

SN Only Fractional Part Product Restored bit

1 0.8935 X 8 7.148 7 ← MSB
2 0.148 X 8 1.184 1
3 0.184 X 8 1.472 1
4 0.472 X 8 3.776 3
(0.8935)10 = (0.7113)8

(969.8935)10 = (1711.7113)8
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2.4.3 Octal to Binary conversion

Octal to Binary conversion will be perform by representing every octal digit by 3-bit
binary irrespective of binary digits required for representing the octal number.
Example14: Convert following octal numbers to equivalent binary numbers.
1) (42)8 2) (503)8 3) (1234)8 4) (76342)8
Solution: 1) (42)8 = (100010)2 In this case 4 = (100)2 and 2 = (010)2 actually to represent 2
only 2 bits are required but as 2 is octal number so use 3 bits to represent it.
2) (503)8 = (101000011)2 0 can be represented with 1 digit while for 3 two digits
are required but here all digits are represented in 3 bits.

3) (1234)8 = (001010011100)2
4) (76342)8 = (111110011100010)2

2.4.4 Binary to Octal conversion

Binary to octal conversion is perform by grouping binary in the size of 3 from LSB and
moving towards MSB for integer number or integer part of floating-point number.
While for fractional number or fractional part of floating number perform group of 3
from MSB toward MSB After grouping each group has to be replace by octal number.

Example15: Convert following binary numbers to the equivalent octal numbers.

1) (1101)2 2) (10001011)2 3) (1000.10001)2 4) (1010101.1101)2
Solution: 1) (1101)2 = ( 1 101 )2 = ( 001 101 )2
= (15)8

2) (10001011)2 = (10 001 011)2 = (010 001 011)2

= (213)8

3) (1000.10001)2 = ( 1 000 .100 01)2 = ( 001 000 .100 011)2

= ( 10.43)8

4) (1010101.1101)2 = (1 010 101 .110 1)2 ( 001 010 101 .110 100 )2
= (125.64)8

2.4.4 Arithmetic Operation on Octal

Arithmetic operations rules are similar with binary numbers arithmetic. As octal
number digits are 0, 1, 2, 3, 4, 5, 6, and 7, same bits will be the output digit after performing
arithmetic operations. The octal number system is not used in computer to perform
arithmetic operations so only addition and subtraction operation are discussed below.
Arithmetic operations on octal numbers are perform after converting number into binary
number.
Example16: Perform addition operation on following numbers.
1) (64)8 + (53)8 2) (435)8 + (317)8 3) (3415)8 + (1234)8 4) (7653)8 + (2354)8
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Solution: Perform following steps to perform arithmetic operation.

A) Convert octal number into binary.
B) Perform corresponding arithmetic operation.
C) Convert binary number into octal number.

1) (64)8 + (53)8 = (137)8

110 100
+ 101 011
____________
1 011 111
1 3 7

2) (435)8 + (317)8 = (754)8

111 11 ←Carry
100 011 101
+ 011 001 111
______________
111 101 100
7 5 4

3) (3415)8 + (1234)8 = (4651)8

11 111 ←Carry
011 100 001 101
+ 001 010 011 100
____________________
100 110 101 001
4 6 5 1

4) (7653)8 + (2354)8 = (12227)8

1 111 111 01 ←Carry

111 110 101 011
+ 010 011 101 100
___________________
010 010 010 111
1 2 2 2 7
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Example17: Perform subtraction operation on following numbers.

1) (64)8 - (53)8 2) (317)8 - (435)8 3) (3415)8 - (1234)8
Solution: For performing subtraction operation subtrahend will be negative which is
represented in 2’s complement form. As subtrahend is represented in 2’
complement form operation perform will be addition.
1) (64)8 - (53)8 = (11)8
(64)8 = (110100)2 and (53)8 = (101011)2 Binary representation of
numbers. (53)8 is subtrahend represent (101011)2 in 2’s Complement.
2’s Complement of (101011)2 is (010101)2

101 ←Carry
110 100
+ 010 101
____________
Carry→ 1 001 001

After performing operation carry is generated which is ignore in 2’

complement operation.

2) (317)8 - (435)8 = (-116)8

Binary representation
(317)8 = (011001111)2 & (435)8 = (100011101)2
2’s Complement of (435)8 = (100011101)2 is (011100011)2

1 1 1 1 ←Carry
011001111
+ 011100011
______________
110110010

As MSB of answer is 1 means it is negative to get original answer take 2’s complement
and attached minus sign.
(110110010)2 2’s Complement is (001 001 110)2 = (-116)8

3) (3415)8 - (1234)8 = (2161)8

Binary representation
(3415)8 = (011100001101)2 & (1234)8 = (001010011100)2
2’s Complement of (1234)8 = (001010011100)2 is (110101100100)2
1 1 1 1 11 ←Carry
0 1 1 1 0 0 0 0 1 1 0 1
+ 1 1 0 1 0 1 1 0 0 1 0 0
________________________________________
1 0 1 0 0 0 1 1 1 0 0 0 1
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2.5 Hexadecimal Number System

The number system with base 16 is known as hexadecimal number system. Digits within this
number system are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, and F . In this number system A=(10)10,
B=(11)10, C=(12)10, D=(13)10, E=(14)10, F=(15)10. This number system is used in digital systems
like computer. (34)16, (2A36)16, (D03)16, (ACF)16 are the hexadecimal numbers. Hexadecimal
numbers are represented by base 16 or with H.
2.5.1 Hexadecimal to Decimal Conversion.
Similar to binary to decimal conversion expanding the given number will give the number in
decimal format.
Example18: Convert Hexadecimal number (45)16 to the decimal number.
Solution: For converting the number (56H) into decimal expand it.
(56)16 = 5X161 + 6X160

= 80 + 6
= (86)10.
Example19: Convert following Hexadecimal numbers to the decimal numbers.
1) (253H) 2) (27A.12H) 3) (1B3F.01) 4) (ABC.DF)
Solution: 1) (253H) = 2X162 + 5X161 3X160
= 512 + 80 + 3
= (595)10

2) (27A.12H) = 2X162 + 7X161 + 10X160 +1X16-1 + 2X 16-2

= 512 + 112 + 10 + 0.0625 + 0.00781
= (634.0703)10

3) (1B3F.01H) = 1X163 + 11X162 + 3X161 + 15X160 + 0X16-1 + 1X16-2

= 4096+ 2816 + 48 + 15 + 0.0625 + 0.0039
= (6975.0664)10

4) (ABC.DFH) = 10X162 + 11X161 + 12X160 + 13X16-1 + 15X16-2

= 2560 + 176 + 12 + 0.8125 + 0.0585
= (2748.871)10
2.5.2 Decimal to Hexadecimal Conversion.

Procedure for converting decimal number to hexadecimal is same as decimal to binary

conversion. As base for hexadecimal number is 16 so for converting decimal number to
hexadecimal divide by 16 and converted hexadecimal number may contain digits from 0 to 9
and A, B, C, D, E, F.
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Example20: Convert following number to Hexadecimal number.

1) (16)10 2) (759)10 3) (262.64)10 4) (918.12)10
Solution: Procedure is shown in following figures
1) (16)10

16 16 1
0 1 ← MSB
(16)10 = (10H)

2) (759)10
16 759 47 2
7 F 2 ← MSB
(759)10 = (2F7H)

3) (262.64)10

First convert integer part of number that is 92.

16 262 16 1
6 0 1 ← MSB
(92)10 = (106H)
Fractional part conversion

SN Only Fractional Part Product Restored bit

1 0.64 X 16 10.24 (A.24) A ← MSB
2 0.24 X 16 3.84 3
3 0.84 X 16 13.44 (D.44) D
4 0.44 X 16 7.04 7
(0.64)10 = (0.A3D7)
(262.64)10 = (106.A3D7H)

4) (918.12)10
First convert integer part of number that is 918.
16 918 57 3
6 9 3 ← MSB
(918)10 = (396H)
Fractional part conversion

SN Only Fractional Part Product Restored bit

1 0.12 X 16 1.92 1 ← MSB
2 0.92 X 16 14.72 (E.72) E
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3 0.72 X 16 11.52 (B.52) B

4 0.52 X 16 8.32 8
(0.12)10 = (0.1EB8)8
(918.12)10 = (396.1EB8H)

2.5.3 Hexadecimal to Binary conversion

Hexadecimal to Binary conversion will be perform by representing every hexadecimal digit

by 4-bit binary irrespective of binary digits required for representing the hexadecimal
number.
Example21: Convert following Hexadecimal numbers to equivalent binary numbers.
1) (37H) 2) (5D3H) 3) (ABCDH) 4) (1B3E4FH)
Solution: 1) (37H) = (01100111)2 In this case 3 = (0011)2 and 7 = (0111)2 . Actual bits
required for 3 and 7 are 2 and 3 respectively but represent both
numbers in 4-bits as it is in hexadecimal.
2) (5D3H) = (0101 1101 0011)2
3) (ABCD)8 = (1010101111001101)2
4) (1B3E4FH) = (0001 1011 0011 1110 0100 1111)2
= (1 1011 0011 1110 0100 1111)2
2.5.4 Binary to Hexadecimal conversion
Binary to Hexadecimal conversion is perform by grouping binary in the size of 4 from LSB
and moving towards MSB for integer number or integer part of floating-point number.
While for fractional number or fractional part of floating number perform group of 4
from MSB toward LSB, after grouping each group has to be replace by hexadecimal
digit.

Example22: Convert following binary numbers to the equivalent hexadecimal numbers.

1) (11011)2 2) (100101011)2 3) (1001010.10001)2 4) (10101001.1101)2
Solution: 1) (111011)2 = ( 11 1011 )2 = ( 0011 1011 )2
= (3BH)

2) (100101011)2 = (1 0010 1011)2 = (0001 0010 1011)2

= (12BH)

3) (1001010.10001)2 = ( 100 1010 .1000 1)2 = ( 0100 1010 .1000 0001)2

= ( 2A.81H)

4) (10101001.1101)2 = (1010 1001 .1101)2 ( 1010 1001 .1101 )2

= (A9.DH)

2.5.4 Arithmetic Operation on Hexadecimal Numbers

Arithmetic operation on hexadecimal will same as other number system like decimal,
octal, binary. First number is converted into the 4-bits equivalent binary and perform
operation like binary number.
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Example23: - Perform following operation.

1) (2DH) + (C1H) 2) (4BCH) – (2DEH) 3) (ABH) x (CDH) 4) (D8H) / (12H)
Solution: - For above operation first convert number into binary perform operation and
convert result into hexadecimal.
1) (2DH) + (C1H)

(2DH) = 0010 1101

+ (C1H) = + 1100 0001
(EEH) = 1110 1110

2) (4BCH) – (2DEH)
For subtraction operation take 2’s complement of subtrahend and perform
addition operation.
(2DEH) = (1011011110)2
2’s Complement of (0010 1101 1110)2 is (1101 0010 0010)

(4BCH) = 0100 1011 1100

+ (2DEH) = + 1101 0010 0010
(1DEH) = 0001 1101 1110
3) (ABH) x (CDH)

AB = 10101011
X CD = X 11001101
88EF = 10101011
00000000x
10101011xx
10101011xxx
00000000xxxx
00000000xxxxx
10101011xxxxxx
10101011xxxxxxx
1000 1000 1110 1111

2.6 Codes
Codes are used to represent information, information may be numbers, alphabets, symbols.
Within digital systems like computer information required for processing and storage
in binary for that various binary codes are available. Example of binary codes are BCD code,
ASCII code, Excess-3 code, Gray code, EBCDIC etc. Information store in one particular code
may have different meaning in another code.
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2.6.1 BCD Codes

Binary Coded Decimal BCD) code is binary code used to represent decimal numbers. Decimal
numbers 0 to 9 is represented in 4-bits binary numbers, irrespective of actual bits required to
represent that digit. To represent decimal 1 only 1 bit is required but in BCD it 0001, similarly
for 2 and 3 2-bits are required but is represented in 4-bits as 0010 and 0011 respectively.
Following table give decimal digits with equivalents BCD.
Decimal Numbers BCD Codes
0 0000
1 0001
2 0010
3 0011
4 0100
5 0101
6 0110
7 0111
8 1000
9 1001
10 0001 0000
11 0001 0001
12 0001 0010
13 0001 0011
14 0001 0100
15 0001 0101

BCD Arithmetic: - BCD code is the method to represent decimal numbers in binary means
when decimal input is given to computer in accept in BCD format but if performing
processing on it, gives the invalid/incorrect BCD number so for converting it into correct BCD
some rules are used which are as follow.
BCD Addition: - BCD addition is performed for two 1-bit number, if answer is greater than 9
or carry is generated then it is invalid BCD to correct it into correct BCD, ADD 6.
Example24: - Add following BCD numbers.
1) 5 + 3 2) 6 + 7 3) 9 + 8
Solution: - 1) 5 + 3
0101 (5 in BCD)
+ 0011 (3 in BCD)
1000 (8 in BCD ) < 9, Correct BCD

2) 6 + 7
0110 (6 in BCD)
+ 0111 (7 in BCD)
1101 (13 in Binary) > 9, Invalid BCD
+ 0110 Add 6, To get Correct BCD
10011 (13 in BCD)
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3) 9 + 8
1001 (9 in BCD)
+ 1000 (8 in BCD)
1 0001 (1 in BCD) < 9, but carry is generated, invalid BCD
+ 0110 Add 6, to get Correct BCD
1 0111 (17 in BCD)

BCD Subtraction: - BCD subtraction is performed by converting subtrahend into it’s negative
format like for binary number in 1’s or 2’s complement format. Similar to this for decimal
number 9’s complement method is used. For calculating 9’s complement of number subtracts
the number from 9. The 9’s complement of number 5 is 9 – 4 = 5 and number 6 is 9 – 6 = 3.
Procedure for BCD subtraction: -
1 Take 9’s complement of subtrahend.
2. Perform of addition minuend and subtrahend.
3. Result of subtraction will be either invalid BCD then add 6 with carry of this addition or
valid BCD then take 9’s complement of answer.
Example: - Perform BCD subtraction for following numbers.
1) 7 – 2 2) 9 – 3 3) 2 – 7 4) 7 – 9
Solution: - 1) 7 – 2
0 1 1 1 (7 in BCD)
+ 0111 9’s Complement of 2.
1 1 1 0 (14 in Binary) > 9, invalid BCD
+ 0110 Add 6
1 0100 Carry is generated
+ 1 Add carry
0101 (5 in BCD)

2) 9 – 3
1001 (9 in BCD)
+ 0110 9’s Complement of 3,
1111 (15 in Binary) > 9, invalid BCD
+ 0110 Add 6
1 0101 Carry is generated
+ 1 Add carry
0110 (6 in BCD)

3) 2 – 7
0010 (2 in BCD)
+ 0010 9’ Complement of 7
0100 (4) < 9, Valid BCD
0101 9 ‘s Complement of 4
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4) 7 – 9
0111 (7 in BCD)
+ 0000 9’s Complement of 9
0111 (7) < 9, Valid BCD
0010 9’s Complement of 7
Excess-3 Code: -
Excess-3 code is generated by adding 3 to each decimal digit. This code is not weighed code
like BCD code. BCD code is weighted because every digit is having values either of 8, 4, 2, 1.
For example Excess-3 code for 4 will be 0100 + 0011 = 0111. This code is self-complementing
code. For example Excess-3 code of 4 is 0100 + 0011 = 0111 and it’s 1’s complement is 1000
which is Excess-3 code of 9’s complement of 4 i.e. 5(1000).
Following table gives Excess-3 codes for the decimal numbers.
Decimal Numbers Excess-3 Codes
0 0011
1 0100
2 0101
3 0110
4 0111
5 1000
6 1001
7 1010
8 1011
9 1100

Gray Codes: -
Gray code is differing by only one bit from its preceding and succeeding numbers so also
known as unit distance code. For example, BCD code for 3 is 0011 and for 4 is 0100, these two
succeeding number differ at 3-digit places except MSB digit all other digit are differing, which
is not expected in Gray code. Gray code is useful in error detection code. Gray code is non-
weighted code. If we consider 4-bit binary number as B (B3B2B1B0) and Gray code G (G3G2G1G0)
then G3 = B3, G2 = B3 ExOR B2, G1 = B2 ExOR B1 and G0 = B1 ExOR B0.
Following table gives Gray code for 4-bit binary numbers
Binary Numbers Gray Codes
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
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1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

ASCII Code: - American Standard Code for Information Interchange (ASCII) code is 7-digit code
used to represent numbers, alphabets (Uppercase and Lowercase), special symbols, etc.
7-digits unique code is assigned to every character represented in ASCII code, as length of
each code is 7-bit so 27 = 128 total characters are represented in ASCII code.
Following table represent ASCII codes.
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Registers in Computer Architecture
Register is a very fast computer memory, used to store data/instruction in-execution.

A Register is a group of flip-flops with each flip-flop capable of storing one bit of information.
An n-bit register has a group of n flip-flops and is capable of storing binary information of n-bits.

A register consists of a group of flip-flops and gates. The flip-flops hold the binary information and
gates control when and how new information is transferred into a register. Various types of
registers are available commercially. The simplest register is one that consists of only flip-flops
with no external gates.

These days registers are also implemented as a register file.

Loading the Registers

The transfer of new information into a register is referred to as loading the register. If all the bits of
register are loaded simultaneously with a common clock pulse than the loading is said to be done
in parallel.

Following are some commonly used registers:

1. Accumulator: This is the most common register, used to store data taken out from the
memory.

2. General Purpose Registers: This is used to store data intermediate results during
program execution. It can be accessed via assembly programming.

3. Special Purpose Registers: Users do not access these registers. These registers are for
Computer system,

o MAR: Memory Address Register are those registers that holds the address for
memory unit.

o MBR: Memory Buffer Register stores instruction and data received from the memory
and sent from the memory.

o PC: Program Counter points to the next instruction to be executed.

o IR: Instruction Register holds the instruction to be executed.

Register Transfer
Information transferred from one register to another is designated in symbolic form by means of
replacement operator.

R2 ← R1

It denotes the transfer of the data from register R1 into R2.

Normally we want the transfer to occur only in predetermined control condition. This can be shown
by following if-then statement: if (P=1) then (R2 ← R1)

Here P is a control signal generated in the control section.

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Control Function
A control function is a Boolean variable that is equal to 1 or 0. The control function is shown as:

P: R2 ← R1

The control condition is terminated with a colon. It shows that transfer operation can be executed
only if P=1.

Micro-Operations
The operations executed on data stored in registers are called micro-operations. A micro-
operation is an elementary operation performed on the information stored in one or more registers.

Example: Shift, count, clear and load.

Types of Micro-Operations

The micro-operations in digital computers are of 4 types:

1. Register transfer micro-operations transfer binary information from one register to another.

2. Arithmetic micro-operations perform arithmetic operations on numeric data stored in

registers.

3. Logic micro-operations perform bit manipulation operation on non-numeric data stored in

registers.

4. Shift micro-operations perform shift micro-operations performed on data.

Arithmetic Micro-Operations

Some of the basic micro-operations are addition, subtraction, increment and decrement.

Add Micro-Operation

It is defined by the following statement:

R3  R1 + R2

The above statement instructs the data or contents of register R1 to be added to data or content of
register R2 and the sum should be transferred to register R3.

Subtract Micro-Operation

Let us again take an example:

R3  R1 + R2' + 1

In subtract micro-operation, instead of using minus operator we take 1's compliment and add 1 to
the register which gets subtracted, i.e R1 - R2 is equivalent to R3 → R1 + R2' + 1
Increment/Decrement Micro-Operation
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Increment and decrement micro-operations are generally performed by adding and subtracting 1
to and from the register respectively.

R1  R1 + 1

R1  R1 – 1

Symbolic Designation Description

R3 ← R1 + R2 Contents of R1+R2 transferred to R3.
R3 ← R1 - R2 Contents of R1-R2 transferred to R3.
R2 ← (R2)' Compliment the contents of R2.
R2 ← (R2)' + 1 2's compliment the contents of R2.
R3 ← R1 + (R2)' + 1 R1 + the 2's compliment of R2 (subtraction).
R1 ← R1 + 1 Increment the contents of R1 by 1.
R1 ← R1 – 1 Decrement the contents of R1 by 1.

Logic Micro-Operations

These are binary micro-operations performed on the bits stored in the registers. These operations
consider each bit separately and treat them as binary variables.

X-OR micro-operation

Consider the X-OR micro-operation with the contents of two registers R1 and R2.

R1 ← R1 X-OR R2

Shift Micro-Operations

These are used for serial transfer of data. That means we can shift the contents of the register to
the left or right. In the shift left operation the serial input transfers a bit to the right most position
and in shift right operation the serial input transfers a bit to the left most position.

There are three types of shifts as follows:

a) Logical Shift

It transfers 0 through the serial input. The symbol "shl" is used for logical shift left and "shr" is
used for logical shift right.

R1 ← shl R1

R1 ← shr R1

The register symbol must be same on both sides of arrows.

b) Rotate (Circular Shift)
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This circulates or rotates the bits of register around the two ends without any loss of data or
contents. In this, the serial output of the shift register is connected to its serial
input. "ROL" and "ROR" is used for rotate (circular shift) left and right respectively.

c) Arithmetic Shift

This shifts a signed binary number to left or right. An arithmetic shift left multiplies a signed
binary number by 2 and shift left divides the number by 2. Arithmetic shift micro-operation leaves
the sign bit unchanged because the signed number remains same when it is multiplied or divided
by 2.

Computer Instructions
Computer instructions are a set of machine language instructions that a particular processor
understands and executes (Instruction is a command given to Computer to perform specific task.).
A computer performs tasks on the basis of the instruction provided.

An instruction comprises of groups called fields. These fields include:

o The Operation code (Opcode) field which specifies the operation to be performed.
o The Address field which contains the location of the operand, i.e., register or memory
location.
o Operand may be 3, 2, 1, and 0; accordingly different Instructions formats are available.
o The Mode field which specifies how the operand will be located.

Instruction Format

Depending on number of operands different instruction formats are

1) 3 – Address machine
2) 2 – Address machine
3) 1 – Address machine
4) 0 – Address machine

1) 3 – Address machine
The instruction having three operands is known as 3-address machine.

OPCODE OPERAND1 OPERAND2 OPERAND3

In this type of instruction operand2 and operand3 perform specified operation which are
source register and result is store in operand3 register, which is destination register.

Example:- ADD R1, R2, R3 (R1)  (R2) + (R3)

In this type of instruction operand2 and operand3 perform specified operation and store the
result in separate register R1.

2) 2 – Address machine
The instruction having two operands is known as 2-address machine.
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OPCODE OPERAND1 OPERAND2

In this type of instruction operand1 and operand2 perform specified operation which are
source register and result is store in operand1 register, which is destination register.

Example:- ADD R1, R2 (R1)  (R1) + (R2)

In this type of instruction operand1 and operand2 perform specified operation and store the
result in register R1.

3) 1 – Address machine
The instruction having only one operand is known as 1-address machine.

OPCODE OPERAND

In this type of instruction one operand is in accumulator register and another operand is
instruction it perform specified operation which are source register and result is store in
accumulator register, which is destination register.

Example: - ADD R1 (R1)  (ACC) + (R1)

In this type of instruction one operand will be in accumulator register and another operand
in instruction and after performing specified operation result is stored the accumulator
register
This type of instruction is also called as accumulator-based instruction.

4) 0 – Address machine
The instruction having no operand is known as 0- address machine or Stack Machine.

OPCODE

This type of instructions performs operations with stack. One Operands is on top of the
stack and another operand on top of stack minus one and result is stored on top of the
stack.

Example: - ADD (TOS)  (TOS) + (TOS-1)

In this type of instruction both operands are stored on to the stack and result is also stored
onto the stack. Where TOS is top of the stack.

A basic computer has three instruction code formats which are:

1. Memory - reference instruction
2. Register - reference instruction
3. Input-Output instruction

1. Memory - reference instruction.3M165Java Try Catch

In Memory-reference instruction, 12 bits of memory is used to specify an address and one bit to
specify the addressing mode 'I'.
Example:- MOV R, M (R) ← (M)
MOV M, R (M) ← (R)
2. Register - reference instruction
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The Register-reference instructions are represented by the Opcode 111 with a 0 in the leftmost bit
(bit 15) of the instruction.

Note: The Operation code (Opcode) of an instruction refers to a group of bits that define arithmetic and
logic operations such as add, subtract, multiply, shift, and compliment.

A Register-reference instruction specifies an operation on or a test of the AC (Accumulator)

register.

Example:- MOV R1, R2 (R1) ← (R2)

3. Input-Output instruction

Just like the Register-reference instruction, an Input-Output instruction does not need a reference
to memory and is recognized by the operation code 111 with a 1 in the leftmost bit of the
instruction. The remaining 12 bits are used to specify the type of the input-output operation or test
performed.

Example:- IN A, 45H (A) ← (45H)

OUT 45H, A (45H) ← (A)

Note

o The three operation code bits in positions 12 through 14 should be equal to 111. Otherwise,
the instruction is a memory-reference type, and the bit in position 15 is taken as the
addressing mode I.
o When the three operation code bits are equal to 111, control unit inspects the bit in position
15. If the bit is 0, the instruction is a register-reference type. Otherwise, the instruction is an
input-output type having bit 1 at position 15.

Instruction Set Completeness

A set of instructions is said to be complete if the computer includes a sufficient number of
instructions in each of the following categories:
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o Arithmetic, logical and shift instructions
o A set of instructions for moving information to and from memory and processor registers.
o Instructions which control the program together with instructions that check status
conditions.
o Input and Output instructions

Arithmetic, logic and shift instructions provide computational capabilities for processing the type of
data the user may wish to employ.

A huge amount of binary information is stored in the memory unit, but all computations are done in
processor registers. Therefore, one must possess the capability of moving information between
these two units.

Program control instructions such as branch instructions are used change the sequence in which
the program is executed.

Input and Output instructions act as an interface between the computer and the user. Programs
and data must be transferred into memory, and the results of computations must be transferred
back to the user.

Addressing Modes:

The operation field of an instruction specifies the operation to be performed. And this operation
must be performed on some data. So, each instruction needs to specify data on which the
operation is to be performed. But the operand(data) may be in accumulator, general purpose
register or at some specified memory location. So, appropriate location (address) of data is need
to be specified, and in computer, there are various ways of specifying the address of data. These
various ways of specifying the address of data are known as “Addressing Modes”

Addressing Modes can be defined as-

“The technique for specifying the address of the operands “

Types Of Addressing Modes:

Various types of addressing modes are:
1. Implied Addressing Mode
2. Immediate Addressing Mode
3. Register Addressing Mode
4. Memory Addressing Mode

1 Implied Addressing Mode:

Implied Addressing Mode also known as "Implicit" or "Inherent" addressing mode is the
addressing mode in which, no operand (register or memory location or data) is specified in the
instruction. As in this mode the operands are specified implicit in the definition of instruction.

As an example: The instruction DAA:

DAA stand for “Decimal Adjust after Addition” is an Implied Mode instruction because the
operand in the accumulator register is implied in the definition of instruction.
DAA: After performing BCD addition, this instruction correct answer in correct BCD format.
 2. Immediate Addressing Mode:
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In Immediate Addressing Mode operand is specified in the instruction itself. In other words, an
immediate mode instruction has an operand field rather than an address field, which contain actual
operand to be used in conjunction with the operand specified in the instruction.

As an example: The Instruction:

MOV AH, 06H Move 06H to the higher byte of accumulator register
ADD AL, 05H ADD 05H to the lower byte of accumulator register

This mode is very useful for initialising the register to a constant value.

3.Register Addressing Mode:

In Register Addressing Mode, both operands are specified in registers This is fastest addressing
mode.

Example of such instructions are:

MOV AX, BX Move contents of Register BX to AX

ADD DX, CX Add the contents of register CX to DX

Here, AX, BX, CX, DX are used as register names which is of 16-bit register.

4.Memory Addressing Modes:

The Memory addressing modes are of two types. Direct addressing mode and indirect addressing
mode is shown below:

Direct Addressing Mode:

Direct Addressing Mode is also known as “Absolute Addressing Mode”. In this mode the address
of data(operand) is specified in the instruction itself. That is, in this type of mode, the operand
resides in memory and its address is mention directly within instruction.

As an example: Consider the instruction:

ADD AX, [1000H] (AX)  (AX) + [1000H]

In this instruction add contents of memory location 1000H to the AX (accumulator) and result is
stored in AX (accumulator). In this instruction 1000H is memory address not a data.

Indirect Addressing Mode:

Indirect Addressing Mode, the operand is stored in memory, but within instruction register is used
to store memory address. That’s why also known as register indirect addressing mode.

Example of such instructions are:

MOV BX, [CX] (BX)  (CX), where (CX) = 7000H & (7000H) = 1234H

In above instruction memory address 7000H is stored in register CX and memory location 7000H
having data 1234H, which is transfer to the BX register.
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Other examples of indirect addressing mode are, Base Addressing mode, Index Addressing mode,
Base Index addressing mode.

In case of base addressing mode base registers and for index addressing mode index registers
and concern registers are used to give operand address.

In base index addressing mode, base register, index registers and concern registers are used to
give operand address.

Instruction Cycle Definition

The processing involved in the execution of a single instruction is termed as Instruction
Cycle. This processing is done in two steps i.e. fetch and execute. To execute an
instruction the processor first reads an instruction from the memory which is
called fetching and then the fetched instruction is executed.

 Fetch cycle: In this cycle, the processor reads the instruction that is to be
executed from the memory.
 Execute cycle: In this cycle, the processor interprets the opcode of the fetched
instruction and performs the operations accordingly.

In the basic computer, each instruction cycle includes the following procedures −

 It can fetch instruction from memory.

 It is used to decode the instruction.
 It can read the effective address from memory if the instruction has an indirect address.
 It can execute the instruction.
After the following four procedures are done, the control switches back to the first step and repeats
the similar process for the next instruction. Therefore, the cycle continues until a Halt condition is
met. The figure shows the phases contained in the instruction cycle.

As shown in the figure, the halt condition appears when the device receive turned off, on the
circumstance of unrecoverable errors, etc.

Fetch Cycle
The address instruction to be implemented is held at the program counter. The processor fetches
the instruction from the memory that is pointed by the PC.
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Next, the PC is incremented to display the address of the next instruction. This instruction is
loaded onto the instruction register. The processor reads the instruction and executes the
important procedures.

Execute Cycle
The data transfer for implementation takes place in two methods are as follows −

 Processor-memory − The data sent from the processor to memory or from memory to
processor.
 Processor-Input/Output − The data can be transferred to or from a peripheral device by
the transfer between a processor and an I/O device.
In the execute cycle, the processor implements the important operations on the information, and
consistently the control calls for the modification in the sequence of data implementation. These
two methods associate and complete the execute cycle.

State Diagram for Instruction Cycle

The figure provides a large aspect of the instruction cycle of a basic computer, which is in the
design of a state diagram. For an instruction cycle, various states can be null, while others can be
visited more than once.

 Instruction Address Calculation − The address of the next instruction is computed. A

permanent number is inserted to the address of the earlier instruction.
 Instruction Fetch − The instruction is read from its specific memory location to the
processor.
 Instruction Operation Decoding − The instruction is interpreted and the type of operation
to be implemented and the operand(s) to be used are decided.
 Operand Address Calculation − The address of the operand is evaluated if it has a
reference to an operand in memory or is applicable through the Input/Output.
 Operand Fetch − The operand is read from the memory or the I/O.
 Data Operation − The actual operation that the instruction contains is executed.
 Store Operands − It can store the result acquired in the memory or transfer it to the I/O.

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Microprogramming provides an alternative method of designing program control units. A microprogrammed control
unit has the structure shown in the Figure1. It is built around a storage unit called control memory, where all the control
signals are stored in a program like format resembling. The control memory stores a set of microprograms designed to
implements the behavior of the given instruction set. Each instruction causes the corresponding program to be fetched
and its control information extracted in a manner that resembles the fetching and execution of program from the
computer’s maim memory.

Figure1: General structure of (a) a hardwired and (b) microprogrammed control unit.

Basic Concepts:

An instruction is implemented by a sequence of one or more sets of concurrent microinstructions. Each microoperation
is associated with a group of control lines that can be activated in a prescribe sequence to trigger the microoperations.
As the number of instructions and control lines can be in the hundreds, a hardwired control unit is difficult to design and
verify. Furthermore, such control design is inherently inflexible in the sense that changes, for example, to correct design
errors or update the instruction set, required that the control unit be redesigned.
Microprogramming is a method of control-unit design in which the control signal selection and sequencing
information is stored in a ROM or RAM called a control memory (CM). the control signals can be activated at any time
are specified by a microinstruction, which is fetched from CM in much the same way an instruction is fetched from main
memory. Each microinstruction also explicitly or implicitly specifies the next microinstruction to be used, thereby
providing the necessary information for microoperation sequencing. A set of related microinstructions forms a
microprogram. Microprograms can be changed relatively easily by changing the content of CM.

Control Unit organization:

In its simplest form a microinstruction has two parts: a set of control fields that specify the control signals to be
activated and an address field that contains the address in CM of the next microinstruction to be executed.
Microprogramming is invented by Maurice V. Wilkes, so microprogramming also known as Wilkes Design.
In microprogramming, each bit ki of a control field correspond to a distinct control lines ci . when ki = 1 in the current
microinstruction, ci is activated; otherwise ci remain inactive. Figure2 shows a microprogrammed control unit designed
in this style.
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Figure2: Basic structure of microprogrammed control unit.

The control memory CM is implemented by ROM, left part (AND plane) of the ROM decodes an address obtain from the
control memory address register (CMAR). Each address selects a particular row in the right part (OR plane) of the ROM
that contains a microinstruction composed (in this small example) of a 6-bits control field and a 3-microinstruction with
address 000, is selected, the control signals c0, c2, and c4 are activated by the xs in the control field. At the same time, the
contents of the address field a2a1a0 = 001 are sent to the CMAR, where they are stored and used to address the next
microinstruction to be executed.
As Figure2 indicates, the CMAR can be loaded from an external source as well as from address field of a
microinstruction. The external source typically provides the starting address of microprogram in the CM. a specific
microprogram prestored in CM executes each instruction of a microprogrammed CPU. The instruction’s opcode, after
encoding, provides the starting address for its microprogram.
Every program control unit should be able to respond to external signal or conditions. We can satisfy this
requirement by introducing some sort of switch S controlled by an external condition that allows the current
microinstruction to select one of two possible address fields. Thus, in Figure2, the third microinstruction may be
followed by the microinstruction with address 100 or 101. as determined by the external condition. This feature makes
conditional branches within a microprogram possible.
Many modifications to the preceding design have been proposed over the year. A major of concern is the
microinstruction’s word length, since it greatly influences the size and cost of the CM. microinstruction length is
determined by three factors:
 
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The maximum number of simultaneous microoperation that must be specified, that is, the degree of parallelism
required at the microoperation level.
 The way in which the control information is represented or encoded.
 The way in which the next microinstruction address is specified.
The control memory is generally ROMs, so their content cannot be altered online. Normally there is no need to change
CM except to correct design or to make minor enhancement to the system. It was recognized from beginning however,
that the CM could be read-write memory (RAM). Wilkes observed that such device, called a writable control memory
(WCM), would have the number of “fascinating possibilities,” but doubled the cost. The most interesting feature of
WCM is that it allows us to change a processor instruction set by changing the microprogram that interpret the
instruction set.

Parallelism in microinstructions:

Microprogrammed processors are frequently characterized by the maximum number of microoperations that a single
microinstruction can specify. This number range from one to hundred.
Microinstructions that specify a single microoperation are similar to the conventional machine instructions. They
are relatively short, due to lack of parallelism, more microinstructions are needed to perform a given operation. The
short microinstruction format is shown in Figure3. It consists of 4 bytes (32 bits). The left most byte (shaded) is an
opcode that specifies the microoperation has to be performed. The next 2 bytes specify the operands, which, in most
cases, are the address of CPU registers. The right most byte contains information used to construct the address of the
next microinstruction.

Figure3: Vertical microinstruction format

Horizontal microinstruction format takes advantage of the fact that, at the microprogramming level, many operations
can be performed in parallel. If all the useful combinations of parallel microoperation were specified by the single
opcode, the number of opcodes would, in most cases. Be enormous. Furthermore, an opcode decoder of considerable
complexity would be needed. To avoid these difficulties, it is usual to divide the microoperation specification part of a
microinstruction into k disjoint control fields. Each control field handles a limited set of microinstructions, any one of
which can be performed simultaneously with the microoperations specified by the remaining control field.
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Figure4: Horizontal microinstruction format

Figure4 shows horizontal microinstruction format, which is 90 bits. It is partitioned into separate fields for
various purposes. There are 21 fields, shown shaded in Figure4, which constitute the control fields. The remaining fields
are used to generate the next microinstruction address and to detect errors by means of parity bits. For example, the 3
bits control fields consisting of bits 65:67 controls the right input to the main adder of the CPU in question. This field
indicate which of several possible registers should be connected to the adder’s right input. Bits 68:71 identify the
function to be performed by the adder; the possibilities include binary addition and decimal addition with various ways
of handling input and carry bits.

Comparison of Horizontal and vertical Microinstruction:

Horizontal Microinstructions Vertical Microinstructions

Long format Short format
Ability to express a high degree of parallelism Limited ability to express parallel microoperation.
Little encoding of the control information. Considerable encoding of the control information.

.
Comparison between hardwired and Micro-programmed Control:
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Attribute Hardwired Control Micro-programmed Control

Speed Fast Slow
Cost of implementation More Cheaper
Implementing approach Sequential circuit Programming
Flexibility Not flexible, difficult to Flexible, new machine instructions
modify for new instruction. can easily be added.
Ability to handle Complex instructions Difficult Easier
Design process Complicated Systematic
Decoding and Sequencing logic Complex Easy
Applications RISC microprocessor CISC microprocessor
Instruction set size Small Large
Control memory Absent Present
Chip area required Less More

Example:- Write micro-program for following instructions.

1) ADD R1, R2
2) ADD R1, 50
3) ADD R1, M
4) SUB (R3), R4
5) JN L1 ; JN means jump if negative, its conditional jump instruction.
6) JMP L1 ; JMP means jump , its unconditional jump instruction.
In above instructions R1, R2, R3, R4 are registers, M is memory location and L1 is label.

Solution:- All the instructions has 3 phases of execution

1) Instruction fetch
2) Operand fetch
3) Execution cycle
Instruction fetch phase is for fetching the instruction from memory and it is compulsory operation. For all the
instructions code for fetching instruction is same.

Operand fetch phase is use to fetch operand from memory. It is applicable whenever operand is in memory, if
operand is in instruction or in registers then this operation is not required.

Execution cycle is for performing predefines operation by op-code (mnemonic) and it is compulsory.

Micro-Instructions for Instruction fetch (applicable for all instruction)

Micro-Instructions Descriptions
MAR  PC The next instruction address is transferred from PD to MAR.
MDR  M(MAR) The content of memory address is transferred to the MDR register.
PC  PC + 1 The PC is incremented by 1 (assuming length of instruction as a 1.)
IR  MDR (Opcode) Opcode is stored into IR register.
Figure: 4.2

1) ADD R1, R2
 Instruction fetch Phase: Figure 4.2
 Operand fetch: Not applicable as both operands are in registers.
 Execution cycle: As follows
Micro-Instructions Descriptions
Y R1 R1 Register content is transferred to the temporary register Y.
Z  Y + R2 R2 Register content is added with Y register result is stored in
temporary register Z.
R1  Z Z content is transferred to destination register R1.

2) ADD R1, 50
  Instruction fetch Phase: Figure 4.2
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 Operand fetch: Not applicable as operand is within instruction as a constant(50).
 Execution cycle: As follows
Micro-Instructions Descriptions
R1 R1 + 50 Constant 50 is added with content of R1 and result is stored in
register R1.

3) ADD R1, M
 Instruction fetch Phase: Figure 4.2
 Operand fetch: As follows
Micro-Instructions Descriptions
MAR M Operand M (which is in memory) address is transferred to the
MAR.
MDR M(MAR) The content of memory address is transferred to the MDR register.

 Execution cycle: As follows

Micro-Instructions Descriptions
Y  MDR Memory operand is transferred to the temporary register Y.
Z  Y + R1 R1 Register content is added with Y register result is stored in
temporary register Z.
R1  Z Z content is transferred to destination register R1.

4) SUB (R3), R4
 Instruction fetch Phase: Figure 4.2
 Operand fetch: As follows
Micro-Instructions Descriptions
MAR R3 Memory Operand whose address is in register R3 is transferred to
the MAR.
MDR M(MAR) The content of memory address is transferred to the MDR register.

 Execution cycle: As follows

Micro-Instructions Descriptions
Y  MDR Memory operand is transferred to the temporary register Y.
Z  R4 - Y From R4 Register Y register content is subtracted and result is
stored in temporary register Z.
R4  Z Z content is transferred to destination register R4.

5) JN L1
 Instruction fetch Phase: Figure 4.2
 Operand fetch: Not applicable as operands is label, which is memory location pointed by PC
whenever condition is true means negative.
 Execution cycle: As follows
Micro-Instructions Descriptions
If negative flag is set then If the flag bit indicates that the result of execution of the
PC  MDR (operand) previous instruction had been negative then control will be
transferred to the label L1. L1 will appear as an operand in
the current instruction.

6) JMP L1
 Instruction fetch Phase: Figure 4.2
 Operand fetch: Not applicable as operands is label, which is memory location pointed by PC

 Execution cycle: As follows

Micro-Instructions Descriptions
control will be transferred to the instruction with label L1. L1
PC  MDR (operand) will appear as an operand in the current instruction.
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5. Memory Organization
A memory unit is the collection of storage units or devices together. The
memory unit stores the binary information in the form of bits. Generally,
memory/storage is classified into 2 categories:

Memory Characteristics: -

1. Memory Types:
The information storage components of a computer can be stored in four
groups, as shown below.

CPU Registers: These high-speed registers in the CPU serve as the working
memory for temporary storage of information and data. They usually general-
purpose registers. This is also known as internal processor memory.

Main (primary) Memory: This large, fairly fast external memory stores
programs and data that are in active use, storage locations in main memory
are addressed directly by the CPU’s load and store instructions. Main memory
is made up of RAM and ROM.

RAM: Random Access Memory

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DRAM: Dynamic RAM, is made of capacitors and transistors, and must be

refreshed every 10~100 ms. It is slower and cheaper than SRAM.

SRAM: Static RAM, has a six-transistor circuit in each cell and retains
data, until powered off.

NVRAM: Non-Volatile RAM, retains its data, even when turned off.
Example: Flash memory.

ROM: Read Only Memory, is non-volatile and is more like a permanent

storage for information. It also stores the bootstrap loader program, to
load and start the operating system when computer is turned on. PROM
(Programmable ROM), EPROM (Erasable PROM) and EEPROM(Electrically
Erasable PROM) are some commonly used ROMs.

Secondary Memory: This memory type is much large in capacity but also much
slower than main memory. Secondary memory stores system programs, large
data files, and the like that are not continually required by the main memory is
executed.

Cache Memory: Cache memory is fast and small in size connected between
CPU registers and main memory.

2. Access Modes:
A fundamental characteristic of a memory is the order or sequence in
which information can be accessed.

Random Access: Main memories are random access memories, in which

each memory location has a unique address. Using this unique address
any memory location can be reached in the same amount of time in any
order.

Sequential Access: This method allows memory access in a sequence or

in order.
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3. Memory Retention: The methods of writing information into a

memory can be permanent or irreversible in that information has been
written, it cannot be altered while the memory is in use or on-line.

Volatile Memory: This loses its data, when power is switched off.

Non-Volatile Memory: This is a permanent storage and does not lose any
data when power is switched off.

Types of RAM
RAM (Random Access Memory) is a part of computer’s Main Memory which is
directly accessible by CPU. RAM is used to Read and Write data into it which is
accessed by CPU randomly. RAM is volatile in nature, it means if the power goes
off, the stored information is lost. RAM is used to store the data that is currently
processed by the CPU. Most of the programs and data that are modifiable are
stored in RAM.
Integrated RAM chips are available in two form:
1. SRAM(Static RAM)
2. DRAM(Dynamic RAM)

1. Static RAM (SRAM):

Static memories (SRAM) are memories that consist of circuits capable of retaining
their state as long as power is on. Thus this type of memories is called volatile
memories. The below figure shows a cell diagram of SRAM. A latch is formed by
two inverters connected as shown in the figure. Two transistors T1 and T2 are used
for connecting the latch with two bit lines. The purpose of these transistors is to act
as switches that can be opened or closed under the control of the word line, which
is controlled by the address decoder. When the word line is at 0-level, the
transistors are turned off and the latch remains its information. For example, the
cell is at state 1 if the logic value at point A is 1 and at point B is 0. This state is
retained as long as the word line is not activated.
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For Read operation, the word line is activated by the address input to the address
decoder. The activated word line closes both the transistors (switches) T1 and T2.
Then the bit values at points A and B can transmit to their respective bit lines. The
sense/write circuit at the end of the bit lines sends the output to the processor.
For Write operation, the address provided to the decoder activates the word line
to close both the switches. Then the bit value that to be written into the cell is
provided through the sense/write circuit and the signals in bit lines are then stored
in the cell.

2. Dynamic RAM (DRAM):

DRAM stores the binary information in the form of electric charges that applied to
capacitors. The stored information on the capacitors tend to lose over a period of
time and thus the capacitors must be periodically recharged to retain their usage.
The main memory is generally made up of DRAM chips.

DRAM Memory Cell: Though SRAM is very fast, but it is expensive because of its
every cell requires several transistors. Relatively less expensive RAM is DRAM, due
to the use of one transistor and one capacitor in each cell, as shown in the below
figure., where C is the capacitor and T is the transistor. Information is stored in a
DRAM cell in the form of a charge on a capacitor and this charge needs to be
periodically recharged.

For storing information in this cell, transistor T is turned on and an appropriate

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voltage is applied to the bit line. This causes a known amount of charge to be
stored in the capacitor. After the transistor is turned off, due to the property of the
capacitor, it starts to discharge. Hence, the information stored in the cell can be
read correctly only if it is read before the charge on the capacitors drops below
some threshold value.

Types of DRAM:
There are mainly 5 types of DRAM:

1. Asynchronous DRAM (ADRAM): The DRAM described above is the asynchronous

type DRAM. The timing of the memory device is controlled asynchronously. A
specialized memory controller circuit generates the necessary control signals to
control the timing. The CPU must take into account the delay in the response of the
memory.

2. Synchronous DRAM (SDRAM): These RAM chips’ access speed is directly

synchronized with the CPU’s clock. For this, the memory chips remain ready for
operation when the CPU expects them to be ready. These memories operate at the
CPU-memory bus without imposing wait states. SDRAM is commercially available as
modules incorporating multiple SDRAM chips and forming the required capacity for
the modules.

3. Double-Data-Rate SDRAM (DDR SDRAM): This faster version of SDRAM performs

its operations on both edges of the clock signal; whereas a standard SDRAM
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performs its operations on the rising edge of the clock signal. Since they transfer
data on both edges of the clock, the data transfer rate is doubled. To access the
data at high rate, the memory cells are organized into two groups. Each group is
accessed separately.

4. Rambus DRAM (RDRAM): The RDRAM provides a very high data transfer rate
over a narrow CPU-memory bus. It uses various speedup mechanisms, like
synchronous memory interface, caching inside the DRAM chips and very fast signal
timing. The Rambus data bus width is 8 or 9 bits.

5. Cache DRAM (CDRAM): This memory is a special type DRAM memory with an on-
chip cache memory (SRAM) that acts as a high-speed buffer for the main DRAM.

Difference between SRAM and DRAM

Below table lists some of the differences between SRAM and DRAM:
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2- Level Memory Characteristics:

Consider following 2-level memory hierarchy where level 1 memory is cache
memory and level 2 memory is main memory, another 2-level memory
hierarchy combination is level 1 memory as main memory and level 2 memory
will be secondary memory.

Cache Main
CPU Memory Memory
(M1) (M2)

The following relations normally hold between adjacent memory M1 and M2 in

a memory hierarchy.

Cost per bit C1 > C2

Access time tA1 < tA2

Storage Capacity S 1 < S2

2-level memory hierarchy denoted by (M1, M2), which can be interpreted as

(cache, main memory) or (main memory, secondary memory).

The average cost per bit of memory is given by

C=

Where c1 denotes cost per bit of M1 and S1 denotes the storage capacity in
bits of M1 and c2 denotes cost per bit of M2 and S2 denotes the storage
capacity in bits of M2.

The performance of a 2-level memory is often measured in terms of the hit

ratio H, which is defined as the probability that a virtual address generated by
the CPU refer to the information currently stored in the faster memory M1.
Whenever required information is available in level 1 memory it is known as
HIT and if not available in level 1 memory (available in level 2 memory) is
known as MISS.
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H=

The number of address reference satisfied by M1 and M2 denoted by N1 and

N2 respectively.

(1 – H) is called as Miss ratio.

Let tA1 and tA2 be the access times of M1 and M2, respectively, relative to the
CPU. The average time tA for the CPU to access a word in the 2-level memory
is given by

tA = H.tA1 + (1- H)tA2

in the most 2-level memory hierarchies, a request for a word not in the fast
level M1 causes a block of information containing the requested word to be
transferred to M1 from M2. When block transfer has been completed, the
requested word is available in M1. The time tB required for the block transfer
is called the block-access or blocked transfer time. Hence we can write
tA2 = tB + tA1 submitting into the above expression, we get

tA = tA1 + (1-H) tB

In many cases tA2 > > tA1 therefore, tA2 = tB. For example, a block transfer
from secondary to main memory requires a relatively slow IO operation,
making tA2 and tB much greater than tA1

Let r = tA2/tA1, denotes access time ratio for 2- level memory. Let access
efficiency e = tA1/tA

e= = ( )

= ( )

where r = tA2/tA1
( )
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Example1:- A 2-level memory hierarchy (M1,M2) has the access time tA1 =
10 sec and tA2 = 10-3 sec. What must be the hit ratio H be in order for the
-8

access efficiency to be at least 65 percent of its maximum value?

Solution:- Access time tA1 = 10-8 sec and tA2 = 10-3 sec.

Efficiency e = 65% = 0.65

r = tA2/tA1 = 10-3/10-8 = 105

e= ( )

0.65 < 1/{1 + (1-h) 105}

1 + (1-h) * 105 < 1/0.65

(1-h) * 105 < (1/0.65 ) – 1 = (100/65) – 1 = 35/65 = 0.53

(1-h) < 0.53/ 105

-h < 0.0000053 -1

h > 0.9999947

Example2: Suppose a cache is 10 times faster than maim memory and suppose
that the cache can be used 90% of the time. How much speedup do we gain by
using the cache?

Solution:- t2 = 10 t1 and h = 0.9

Average access time tA = t1 + (1-h)t2

= t2/10 + (1+ 0.9)t2

= t2/10 + 0.1t2 = 0.2t2

Speed Up = t2/ Average access time = t2/0.2t2 = 5

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Cache Memory
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Cache Mapping
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Problems Solved in class.

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Cache Coherence
In one CPU system, two copies of same data, one in cache memory and another in
main memory may become different (inconsistent) is known as cache coherency
or cache inconsistency.

The content of cache and main memory can be altered by more than one device
e.g. CPU can write to cache and input\output module or DMA (Direct Memory
Access) can directly write to main memory. This can result in inconsistencies in
the values of cache and main memories.

Techniques for resolve cache coherence in single CPU system:

Write Through Policy:

Write data in cache as well as main memory. This will always keep the two copy of
data (one in cache and another in main memory) consistent. The disadvantage of
this technique is that a bottleneck is created due to large number of access to the
main memory.

Write Back Policy:

Write back policy, it writes data in cache memory and not to main memory.
Consequently, data in cache memory and main memory may contain different
data. The cache line holds the most recent data, and main memory contains older
data, which has not been updated.

Caches configured as write back caches must use one or more of the dirty bits in
the cache line status information block. When a cache controller in write back
writes a value to cache memory, it sets the dirty bit true. If the core accesses the
cache line at a later time, it knows by the state of the dirty bit that the cache line
contains data not in main memory. If the cache controller evicts a dirty cache line,
it is automatically written out to main memory. The controller does this to
prevent the loss of vital information held in cache memory and not in main
memory.
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Interleaved Memory:
Interleaved memory implement the concept of accepting more words in a single
memory access cycle. Memory can be partitioned into N seprate memory
modules. Thus N acesses can be carried out
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Associative Memory
An associative memory can be considered as a memory unit whose stored data can be
identified for access by the content of the data itself rather than by an address or
memory location.

Associative memory is often referred to as Content Addressable Memory (CAM).

When a write operation is performed on associative memory, no address or memory

location is given to the word. The memory itself is capable of finding an empty unused
location to store the word.

On the other hand, when the word is to be read from an associative memory, the
content of the word, or part of the word, is specified. The words which match the
specified content are located by the memory and are marked for reading.

The following diagram shows the block representation of an Associative memory.

From the block diagram, we can say that an associative memory consists of a memory
array and logic for 'm' words with 'n' bits per word.

The functional registers like the argument register A and key register K each have n bits,
one for each bit of a word. The match register M consists of m bits, one for each
memory word.
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The words which are kept in the memory are compared in parallel with the content of
the argument register.

The key register (K) provides a mask for choosing a particular field or key in the
argument word. If the key register contains a binary value of all 1's, then the entire
argument is compared with each memory word. Otherwise, only those bits in the
argument that have 1's in their corresponding position of the key register are compared.
Thus, the key provides a mask for identifying a piece of information which specifies how
the reference to memory is made.

The following diagram can represent the relation between the memory array and the
external registers in an associative memory.

The cells present inside the memory array are marked by the letter C with two
subscripts. The first subscript gives the word number and the second specifies the bit
position in the word. For instance, the cell Cij is the cell for bit j in word i.

A bit Aj in the argument register is compared with all the bits in column j of the array
provided that Kj = 1. This process is done for all columns j = 1, 2, 3......, n.

If a match occurs between all the unmasked bits of the argument and the bits in word i,
the corresponding bit Mi in the match register is set to 1. If one or more unmasked bits
of the argument and the word do not match, Mi is cleared to 0.
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Pipeline
Pipelining is the process of accumulating instruction from the
processor through a pipeline. It allows storing and executing
instructions in an orderly process. It is also known as pipeline
processing.

Instruction Pipelining
Instruction pipelining is a technique of organizing the instructions for execution
in such a way that the execution of the current instruction is overlapped by the
execution of its subsequent instruction. Instruction pipelining improves the
performance of the processor by increasing its throughput i.e. number of
instructions per unit time.

What is Instruction Pipelining?

Consider that we have a set of instructions to get executed, let us see how it
begins? The processor fetches an instruction from the memory, decode the
instruction and determine the kind of operation that has to be performed. If the
operation requires operands then the processor fetches the operands from the
memory and then performs the required operation. Finally, the processor
stores the result to the specified memory location.

In this way, the processor processes each instruction from the start till it
finishes execution and then it fetches the next instruction for instruction. Now
if we divide the instruction execution into stages then it could be divided into:

 Instruction fetches: Fetch the instruction from the main memory or cache.
 Instruction decoding: The processor interprets instruction and determines
the operation that has to be performed.
 Operand fetch: If the execution of the instruction requires operand then the
processor fetches operand from the main memory or cache.
 Instruction Execution: The processor performs the desired operation.
 Operand Store: The result of execution is stored.
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 Now each stage is handled by the different sections of the hardware.

So, once the instruction is fetched by the fetching unit of the hardware
and is forwarded to other hardware section for decoding, operand
fetches, execution and operand store; the fetching unit of hardware has
to sit idle till the operand store stage is completed.
 The figure below shows you the sequential execution (non pipeline) of
the instruction processing one stage in one clock cycle.

This reduces the efficiency of the system. Thus to improve the systems
efficiency instruction pipelining can be implemented. Instruction
pipelining lets different hardware sections to process different instructions
simultaneously.

The figure below shows you how the pipelined instruction reduces the
processing time of several instructions and improves the efficiency of the
system. Notice that the instruction decodes stage of instruction 1 is
overlapped with the instruction fetch stage of instruction 2.
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It is noticeable how the instruction pipelining speed up the processing time of

the processor. Like when the instructions are executed sequentially only two
instruction are executed in 10 clock cycles where when the instructions are
pipelined five instructions are executed in 9 clock cycles.

Instruction Pipelining Hazards

The instruction pipelining hazards is a condition where the execution of the
pipelined instructions is stopped or delayed; it is also called a pipeline bubble.
There are three kinds of instruction pipeline hazards.

Resource Hazards

When two pipelined instructions or even more, want to access the same
resource it results in resource hazards. It is also termed structural hazards. A
solution to this hazard is that these instructions must be executed serially up
to some portion of the pipeline.
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Let us understand this with the help of an example. Consider the main
memory you have has a single port that restricts the processor to perform
instruction fetch, read data and write data one at a time. This means you
cannot perform the operand read & write operation, from memory in parallel
with instruction fetch.

Now consider that there are three instructions in the pipeline. So in the normal
conditions, the operand fetch of instruction 1 must-have overlapped the
instruction fetch of instruction 3. But there is a case that source operand of
instruction 1 is present in main memory instead of register and the rest of all
the operands are in register. So we would halt the instruction fetch of
instruction 3 for one clock cycle. Because instruction 1 will fetch its source
operand from memory so in the same clock cycle instruction 3 cannot perform
instruction fetch in parallel to operand fetch of instruction 1.

Data Hazards

The data hazard is a condition when accessing an operand location creates

conflict. Consider that you have two instructions:

ADD R1, R2

SUB A, R1

Observe the instructions above the result of add instruction is stored in

register R1 after the execution. This R1 act as an operand for subtract
instruction. Now in the figure below notice that the register R1 is updated with
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the add result in clock cycle t 4. But the subtract instruction need its operand
R1 at the t3 clock cycle. But if subtract instruction fetches the operand R1 in
the t3 clock cycle then it will generate an incorrect result.

So the subtract instruction must stall or halt for two clock cycles because for
the correct result the subtract instruction is dependent on the result of add
instruction. This dependency is also called data dependency.

Control Hazards

Control hazards occur when instruction pipelining fails in predicting branches

in the instruction. Let us understand this with the help of an example.
Consider the first instruction I1 in the pipeline is a branch instruction that
targets instruction I6.

The instruction I1 is fetched in cycle t0, decoded in cycle t1, fetch operands in
cycle t2 and perform execution in cycle t3 where the target address is
computed. But till then three instructions I2, I3 and I4 are pipelined in cycle t1,
t2 and t3 which must be discarded as instruction I1 is branch instruction which
will compel the processor to execute the instruction I9 after instruction I1.

This is how control hazards lead to delay of three cycles t 1, t2 and t3 between
I1 and I 6 which is also termed as branch delay.
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This branch delay could be minimized if the branches in the instruction could
be predicted at the decoding stage only.

Advantages of Instruction Pipelining

1. Instruction pipelining increases instruction throughput.
2. Instruction pipelining let all the stages i.e. instruction fetch, instruction decode,
operand fetch, execute and operand store to be performed parallel.
3. In every clock cycle, an instruction completes its execution.
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Performance Measurements
Performance metrics are a measure to evaluate computer design. First of all, it is imperative to know
the metrics. The most likely parameters of Real-world performance metrics are Speed, Capacity, Cost
and Energy consumption. The world evaluates these four factors with relevance to a target
application or the requirement and chooses the computer. The trade-off is amongst these four factors.
Of these four, Speed is the performance of CPU.

Most computers run synchronously utilizing a CPU clock running at a constant clock rate: Or clock
frequency: f

where: Clock rate = 1 / clock

f = 1/c

• The CPU clock rate depends on the specific CPU organization (design) and hardware
implementation technology (VLSI) used.

• A computer machine (ISA) instruction is comprised of a number of elementary or micro operations

which vary in number and complexity depending on the instruction and the exact CPU organization
(Design).

– A micro operation is an elementary hardware operation that can be performed during one CPU
clock cycle.

– This corresponds to one micro-instruction in microprogrammed CPUs.

– Examples: register operations: shift, load, clear, increment, ALU operations: add , subtract, etc.

• Thus: A single machine instruction may take one or more CPU cycles to complete termed as the
Cycles Per Instruction (CPI).

Instruction Per Cycle = IPC = 1/CPI

• Average (or effective) CPI of a program: The average CPI of all instructions executed in the program on a given CPU
design.

k-stage pipeline processes n tasks in k + (n-1) clock cycles:

k cycles for the first task and n-1 cycles
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for the remaining n-1 tasks

Total time to process n tasks

Tk = [ k + (n-1)] 

For the non-pipelined processor

T1 = nk

Speedup factor

T
_______
1
nk
___________________ nk
________________
Sk = =
Tk [ k + (n-1)]  = k + (n-1)

Efficiency of the k-stages pipeline:

S k n
Ek =
________
= _____________
k k + (n-1)
Pipeline throughput (the number of tasks per unit time) :

note equivalence to IPC

n
___________________ nf
________________
Hk = [ k + (n-1)]  =
k + (n-1)

Amdahl’s Law
Suppose, Moni have to attend an invitation. Moni’s another two friend Diya and Hena are also invited.
There are conditions that all three friends have to go there separately and all of them have to be
present at door to get into the hall. Now Moni is coming by car, Diya by bus and Hena is coming by
foot. Now, how fast Moni and Diya can reach there it doesn’t matter, they have to wait for Hena. So to
speed up the overall process, we need to concentrate on the performance of Hena other than Moni or
Diya.
This is actually happening in Amdahl’s Law. It relates the improvement of the system’s performance
with the parts that didn’t perform well, like we need to take care of the performance of that parts of the
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systems. This law often used in parallel computing to predict the theoretical speedup when using
multiple processors.

Formula
Amdahl’s Law can be expressed in mathematically as follows −
SpeedupMAX = 1/((1-p)+(p/s))
SpeedupMAX = maximum performance gain
s = performance gain factor of p after implement the enhancements.
p = the part which performance needs to be improved.
Let’s take an example, if the part that can be improved is 30% of the overall system and its
performance can be doubled for a system, then −
SpeedupMAX = 1/((1-0.30)+(0.30/2))
= 1.18
Now, in another example, if the part that can be improved is 70% of the overall system and its
performance can be doubled for a system, then −
SpeedupMAX= 1/((1-0.70)+(0.70/2))
= 1.54
So, we can see, if 1-p can’t be improved, the overall performance of the system cannot be improved
so much. So, if 1-p is 1/2, then speed cannot go beyond that, no matter how many processors are
used.
Multicore programming is most commonly used in signal processing and plant-control systems. In
signal processing, one can have a concurrent system that processes multiple frames in parallel. the
controller and the plant can execute as two separate tasks, in plant-control systems.
Multicore programming helps to split the system into multiple parallel tasks, which run simultaneously,
speeding up the overall execution time.

Flynn’s Classification:
 Multiprocessing can be defined using Flynn’s classification, it is based on multiplicity of
instruction stream and data streams in a computer system.
 An instruction stream is a sequence of instruction executed by computer.
 A data stream in a sequence of data which includes input data or temporary results.

They are classified into 4 types:

1) SISD (Single Instruction Single Data Stream)

Single instruction: Only one instruction stream is being acted or executed by CPU during one clock
cycle.

Single data stream: Only one data stream is used as input during one clock cycle.
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A SISD computing system is a uniprocessor machine that is capable of executing a single instruction
operating on a single data stream. Most conventional computers have SISD architecture where all the
instruction and data to be processed have to be stored in primary memory.

2) SIMD (Single Instruction Multiple Data Stream)

A SIMD system is a multiprocessor machine, capable of executing the same instruction on all the
CPUs but operating on the different data stream.
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3) MISD (Multiple Instruction Single Data stream)

An MISD computing is a multiprocessor machine capable of executing different instructions on

processing elements but all of them operating on the same data set.

4) MIMD (Multiple Instruction Multiple Data Stream)

A MIMD system is a multiprocessor machine that is capable of executing multiple instructions over
multiple data streams. Each processing element has a separate instruction stream and data stream.
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Expansion Buses
The expansion bus allows the CPU to communicate with peripheral devices. Expansion
bus and associated slots are required because basic PC system cannot satisfy all
needs of users. Expansion bus slots or I/O bus designs in general, provide the
opportunity to add more devices to PC. We can plug sound cards, video cards, SCSI
controller cards, network interface cards, etc. Into expansion bus slots provided on PC
motherboard.

Block diagram is shown below :

Functions of Expansion Bus :

1. Expansion bus slots are long thin connectors provided on motherboard near
backside of computer and these are used to connect all add-on cards in a computer
system.
2. They provide direct electrical connection with PC’s main logical circuitry. Therefore,
its purpose is to enable user to add expansion boards to computer system that plays
a Crucial role in enhancing power and capabilities of a PC.
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3. Expansion bus determines what exactly can be added to system – how many add-
on cards, how much memory on expansion cards, what other system components
and how easy it will be to setup system.
4. It provide a common pathway for data, address and control signals that links various
components of PC.
5. Bus design also has to assure that data actually goes to place where it is meant to
go, i.e. through bus circuits computer sends definite patterns of digital bits in a
definite sequence from one point to another.
6. Expansion bus provides special signals to synchronize working of add-on cards with
the rest of the computer.
In modern PCs, a number of basic peripheral devices are built into motherboard. As a
result, it may happen that expansion slots may remain unused, but that doesn’t mean
that expansion buses remain unused in that system. All built-in controllers and ports still
use I/O bus to communicate with CPU, i.e. They operate in such a way as it they are
add-on cards plugged into the system’s expansion bus slots.
Since introduction of first PC till, a number of expansion bus types have appeared on
PC platform with basic objective of providing faster I/O speeds for better system
performance. The need for better performance arises mainly due to improvements in
three main areas :
 Faster processors
 Increasing application software requirements
 Faster multimedia requirements in audio and video
 Faster peripherals.

ISA (Industry Standard Architecture)

ISA (Industry Standard Architecture) is a standard bus (computer interconnection)

architecture that was associated with the IBM AT motherboard. The first IBM personal
computers (PCs) introduced in 1981 included the 8-bit subset of the ISA bus, and the
PC AT, which IBM launched in 1984, was the first full 16-bit implementation of the ISA
bus. It allowed 16 bits at a time to flow between the motherboard circuitry and an
expansion slot card and its associated device(s).

It is also called as "AT bus", ISA was one of the first expansion buses for PCs.
Providing the hardware interface for connecting peripheral devices in PCs, ISA
accepted cards for sound, display, hard drives and other devices. ISA allowed for
additional expansion cards to be attached to a computer's motherboard and was
capable of direct memory access (DMA), with multiple expansion cards on a memory
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channel and separate interrupt request (IRQ) assignment for each card. The
development and use of ISA led to several later technologies.

 8-bit ISA Connector:

 16-bit ISA Connector:

Features:-

8 bit ISA bus/card (XT – Bus):

1. 8-bit data interface.
2. 4.77 MHz bus.
3. 62 pin connector.

16 bit ISA bus (AT – Bus Card):

1. 16 bit data interface.
2. 8 MHz bus.
3. 62 pin connector.
4. 36 pin AT extension connection.

Peripheral Component Interconnect (PCI)

It could be a standard information transport that was common in computers from 1993
to 2007 or so. It was for a long time the standard transport for extension cards in
computers, like sound cards, network cards, etc. It was a parallel transport, that, in its
most common shape, had a clock speed of 66 MHz, and can either be 32 or 64 bits
wide. It has since been replaced by PCI Express, which could be a serial transport as
contradicted to PCI. A PCI port, or, more precisely, PCI opening, is essentially the
connector that’s utilized to put through the card to the transport. When purge, it basically
sits there and does nothing.
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Types of PCI :
These are various types of PCI:

 PCI 32 bits have a transport speed of 33 MHz and work at 132 MBps.
 PCI 64 bits have a transport speed of 33 MHz and work at 264 MBps.
 PCI 64 bits have a transport speed of 66 MHz and work at 512 MBps.
 PCI 64 bits have a transport speed of 66 MHz and work at 1 GBps.

Function of PCI :

PCI slots are utilized to install sound cards, Ethernet and remote cards and presently
strong state drives utilizing NVMe (Nonvolatile Memory express) innovation to supply
SSD (Solid State Drive) drive speeds that are numerous times speedier than SATA
(Serial Advanced Technology Attachment) SSD speeds. PCI openings too permit
discrete design cards to be included to a computer as well.
PCI openings (and their variations) permit you to include expansion cards to a
motherboard. The extension cards increment the machines capabilities past what the
motherboard may create alone, such as: upgraded illustrations, extended sound,
expanded USB and difficult drive controller, and extra arrange interface options, to title
a couple of.

Advantage of PCI :

 You’ll interface a greatest of five components to the PCI and you’ll be able
moreover supplant each of them by settled gadgets on the motherboard.
 You have different PCI buses on the same computer.
 The PCI transport will improve the speed of the exchanges from 33MHz to
133 MHz with a transfer rate of 1 gigabyte per second.
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 The PCI can handle gadgets employing a greatest of 5 volts and the pins
utilized can exchange more that one flag through one stick.

Disadvantage of PCI :

 PCI Graphics Card cannot get to system memory.

 PCI does not support pipeline.

Universal Serial Bus (USB)

Universal Serial Bus (USB) is an industry-standard that establishes

specifications for connectors, cables, and protocols for communication,
connection, and power supply between personal computers and their peripheral
devices. There have been 3 generations of USB specifications:

1. USB 1.x
2. USB 2.0
3. USB 3.x
USB 2.0 has multiple updates and additions. The USB Implementer Forum (USB
IF) currently maintains the USB standard and it was released in 1996.
USB was designed to standardize the connection of peripherals like pointing
devices, keyboards, digital still, and video cameras. But soon devices such as
printers, portable media players, disk drives, and network adaptors to personal
computers used USB to communicate and to supply electric power. It is
commonplace to many devices and has largely replaced interfaces such as serial
ports and parallel ports. USB connectors have replaced other types of battery
chargers of portable devices with themselves.

Advantages of USB –

The Universal Serial Bus was designed to simplify and improve the interface between
personal computers and peripheral devices when compared with previously existing
standard or ad-hoc proprietary interfaces.
1. The USB interface is self-configuring. This means that the user need not adjust
settings on the device and interface for speed or data format, or configure
interrupts, input/output addresses, or direct memory access channels.
2. USB connectors are standardized at the host, so any peripheral can use any
available receptacle. USB takes full advantage of the additional processing power
that can be economically put into peripheral devices so that they can manage
themselves. USB devices mostly do not have user-adjustable interface settings.
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3. The USB interface is hot pluggable or plug and plays, meaning devices can be
exchanged without rebooting the host computer. Small devices can be powered
directly from the USB interface thus removing extra power supply cables.
4. The USB interface defines protocols for improving reliability over previous
interfaces and recovery from common errors.
5. Installation of a device relying on the USB standard minimal operator action is
required.

Disadvantages of USB –
1. USB cables are limited in length.
2. USB has a strict “tree” topology and “master-slave” protocol for addressing
peripheral devices. Peripheral devices cannot interact with one another except via
the host, and two hosts cannot communicate over their USB ports directly.
3. Some very high-speed peripheral devices require sustained speeds not available in
the USB standard.
4. For a product developer, the use of USB requires the implementation of a complex
protocol and implies an intelligent controller in the peripheral device.
5. Use of the USB logos on the product requires annual fees and membership in the
organization.

Bus Contention:

Bus contention, in computer design, is an undesirable state of the bus in which more
than one device on the bus attempts to place values on the bus at the same time. Most
bus architectures require their devices follow an arbitration protocol carefully designed
to make the likelihood of contention negligible.

Bus contention can be resolved by Bus arbitration method.

BUS Arbitration
Bus Arbitration refers to the process by which the current bus master accesses and
then leaves the control of the bus and passes it to another bus requesting processor
unit. The controller that has access to a bus at an instance is known as a Bus master.
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A conflict may arise if the number of DMA controllers or other controllers or processors
try to access the common bus at the same time, but access can be given to only one of
those. Only one processor or controller can be Bus master at the same point in time. To
resolve these conflicts, the Bus Arbitration procedure is implemented to coordinate the
activities of all devices requesting memory transfers. The selection of the bus master
must take into account the needs of various devices by establishing a priority system for
gaining access to the bus. The Bus Arbiter decides who would become the current bus
master.

There are two approaches to bus arbitration:

1. Centralized bus arbitration –

A single bus arbiter performs the required arbitration.

2. Distributed bus arbitration –

All devices participating in the selection of the next bus master.

Methods of Centralized BUS Arbitration –

There are three bus arbitration methods:

(i) Daisy Chaining method –
It is a simple and cheaper method where all the bus masters use the same line
for making bus requests. The bus grant signal serially propagates through each
master until it encounters the first one that is requesting access to the bus. This
master blocks the propagation of the bus grant signal, therefore any other
requesting module will not receive the grant signal and hence cannot access the
bus.
During any bus cycle, the bus master may be any device – the processor or any
DMA controller unit, connected to the bus.
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Advantages –
 Simplicity and Scalability.
 The user can add more devices anywhere along the chain, up to a certain
maximum value.

Disadvantages –
 The value of priority assigned to a device depends on the position of the
master bus.
 Propagation delay arises in this method.
 If one device fails then the entire system will stop working.

(ii) Polling or Rotating Priority method –

In this, the controller is used to generate the address for the master (unique
priority), the number of address lines required depends on the number of masters
connected in the system. The controller generates a sequence of master
addresses. When the requesting master recognizes its address, it activates the
busy line and begins to use the bus.

Advantages –
 This method does not favor any particular device and processor.
 The method is also quite simple.
 If one device fails then the entire system will not stop working.

Disadvantages –
 Adding bus masters is difficult as increases the number of address lines of the
circuit.
(iii) Fixed priority or Independent Request method –
In this, each master has a separate pair of bus request and bus grant lines and
each pair has a priority assigned to it.
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The built-in priority decoder within the controller selects the highest priority
request and asserts the corresponding bus grant signal.

Advantages –
 This method generates a fast response.
Disadvantages –
 Hardware cost is high as a large no. of control lines is required.

Distributed BUS Arbitration :

In this, all devices participate in the selection of the next bus master. Each device
on the bus is assigned a 4bit identification number. The priority of the device will
be determined by the generated ID.
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Explain flynns classification in detail.

Flynn's classification is a way of categorizing computer architectures

based on the number of instruction streams and data streams that can be
executed simultaneously. It was proposed by Michael J. Flynn in 1966 and
has since become a fundamental concept in computer architecture. Flynn's
classification defines four categories, known as Flynn's taxonomy:

1. SISD (Single Instruction, Single Data):

o In SISD architecture, there is only one instruction stream being
processed at a time, and it operates on a single data stream.
o This architecture resembles the traditional Von Neumann
architecture, where instructions are fetched sequentially and
executed one at a time.
o SISD computers are uniprocessors, meaning they have a single
central processing unit (CPU) that executes instructions.
o Examples of SISD computers include early mainframes and
personal computers.
2. SIMD (Single Instruction, Multiple Data):
o In SIMD architecture, a single instruction stream controls
multiple processing units, each of which operates on different
data streams simultaneously.
o SIMD computers are designed to perform the same operation
on multiple pieces of data in parallel.
o This architecture is particularly useful for tasks such as
multimedia processing, scientific computing, and parallel
processing.
o Examples of SIMD architectures include graphics processing
units (GPUs) and vector processors.
3. MISD (Multiple Instruction, Single Data):
o In MISD architecture, multiple instruction streams operate on
a single data stream simultaneously.
o While theoretically possible, MISD architectures are not
commonly found in practical computing systems.
o MISD architectures are often discussed in theoretical contexts,
such as fault-tolerant systems or in some parallel processing
models.
4. MIMD (Multiple Instruction, Multiple Data):
o In MIMD architecture, multiple instruction streams operate on
multiple data streams independently.

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o MIMD computers typically consist of multiple processors,
each with its own control unit and memory.
o This architecture is highly parallel and allows different
processors to execute different programs on different sets of
data simultaneously.
o MIMD systems are widely used in parallel computing
environments, such as clusters, supercomputers, and
distributed systems.

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Draw and explain 4 stage instruction pipelining and briefly describe the hazards associate with it.

4-Stage Instruction Pipelining Diagram:

Copy code
IF | ID | EX | WB
---------|----------|----------|----------
Fetch | Decode | Execute | Write Back
| | |
| | |

1. Fetch (IF - Instruction Fetch): Fetches the instruction from

memory.
2. Decode (ID - Instruction Decode): Decodes the instruction and
reads operand values from registers.
3. Execute (EX - Execution): Executes the instruction (e.g.,
arithmetic, logical, or branch operations).
4. Write Back (WB): Writes the result back to the appropriate register.

Hazards Associated with 4-Stage Instruction Pipelining:

1. Data Hazards:
o Read After Write (RAW): Occurs when an instruction
depends on the result of a previous instruction that has not yet
written its result to the register file. This hazard can stall the
pipeline until the dependent instruction's result is available.
o Write After Read (WAR): Occurs when an instruction writes
to a register that a later instruction is reading from. This can
lead to incorrect results if not handled properly.
2. Control Hazards:
o Branch Hazards: Occur when there is a conditional branch
instruction in the pipeline, and the branch target is not yet
known. The pipeline needs to stall until the branch outcome is
resolved.
3. Structural Hazards:
o Resource Conflict: Occurs when two or more instructions
need access to the same hardware resource at the same time.
For example, if two instructions require access to the same
functional unit in the Execute stage simultaneously, a
structural hazard occurs.
4. Pipeline Flush:

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o In some cases, it may be necessary to flush the pipeline,
discarding instructions that are in progress, due to exceptions
or mispredicted branches. This can lead to performance
penalties as the pipeline needs to be refilled with instructions.

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What is bus aarbitration ? describe various bus arbition methods or techniquis

Bus arbitration is the process of determining which device on a shared

bus gets to use the bus at any given time when multiple devices are
competing for access. It's crucial in systems where multiple devices need
to communicate over a shared bus to ensure efficient and fair access to
the bus resources.
1. **Centralized Arbitration**:
- In centralized arbitration, there is a single arbiter responsible for
granting access to the bus.
- The arbiter typically uses a predetermined priority scheme or a round-
robin approach to determine which device gets access to the bus next.
- This method is relatively simple to implement but can become a
bottleneck if the arbiter becomes overloaded with requests.
2. **Distributed Arbitration**:
- In distributed arbitration, each device has its own logic for
determining when to request access to the bus.
- Devices communicate with each other to negotiate bus access using
protocols such as token passing or contention-based protocols.
- Token passing: Devices pass a token to indicate that they have the right
to use the bus. When a device is finished, it passes the token to the next
device in the sequence.
- Contention-based protocols: Devices contend for the bus by asserting
their request signals. A priority scheme or collision resolution mechanism
determines which device gets access when multiple devices request the
bus simultaneously.
- Distributed arbitration can be more scalable and efficient than
centralized arbitration but may require more complex communication
protocols.
3. **Priority-based Arbitration**:

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 - Priority-based arbitration assigns different priority levels to devices
based on predefined criteria.
- Devices with higher priority levels are granted access to the bus before
devices with lower priority levels.
- Priority levels can be statically assigned or dynamically adjusted based
on the system's requirements.
- Priority-based arbitration ensures that critical devices, such as system
controllers or memory units, receive timely access to the bus.
4. **Time Division Multiplexing (TDM)**:
- Time Division Multiplexing divides the bus access time into fixed time
slots.
- Each device is assigned one or more time slots during which it can
access the bus exclusively.
- TDM is often used in synchronous systems where devices require
periodic access to the bus at predictable intervals.
- While TDM ensures fair access to the bus, it may lead to inefficient use
of bandwidth if some devices do not fully utilize their allocated time slots.

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Explain different types of addressing modes
Addressing modes are techniques used by CPUs to specify the operand(s)
of an instruction. They determine how the CPU accesses data from
memory or registers to perform operations. Here are some common
addressing modes:
1. **Immediate Addressing**:
- The operand is directly specified within the instruction.
- Example: `MOV R1, #10` (Move immediate value 10 into register R1).
- Advantages: Simple and fast for small constant values.
- Limitations: Not suitable for large data or variable operands.
2. **Register Addressing**:
- The operand is specified by a register or a register pair.
- Example: `ADD R1, R2` (Add the contents of registers R1 and R2).
- Advantages: Fast access to data stored in registers.
- Limitations: Limited number of registers available.
3. **Direct Addressing**:
- The operand's memory address is directly specified within the
instruction.
- Example: `LOAD R1, 1000` (Load the contents of memory address 1000
into register R1).
- Advantages: Simple and straightforward.
- Limitations: Not suitable for programs with dynamic memory
allocation.
4. **Indirect Addressing**:
- The instruction specifies a memory address that contains the address
of the operand.
- Example: `LOAD R1, (R2)` (Load the contents of memory address stored
in register R2 into register R1).
- Advantages: Allows for flexibility in memory addressing.
- Limitations: Requires an additional memory access to fetch the
operand's address.
5. **Indexed Addressing**:
- An index register holds an offset that is added to a base address to
determine the operand's location.

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 - Example: `LOAD R1, (R2 + offset)` (Load the contents of memory
address calculated by adding the contents of register R2 and an offset into
register R1).
- Advantages: Useful for accessing elements of arrays or data structures.
- Limitations: Limited range of offset values.
6. **Relative Addressing**:
- The operand's memory address is calculated relative to the current
instruction's address.
- Example: `JMP label` (Jump to the memory address specified by the
label relative to the current instruction's address).
- Advantages: Facilitates position-independent code and code
relocation.
- Limitations: Limited range of relative addresses.
7. **Base or Displacement Addressing**:
- A base register holds a base address, and the operand's address is
calculated by adding a displacement value to the base address.
- Example: `LOAD R1, (base + displacement)` (Load the contents of
memory address calculated by adding the contents of a base register and
a displacement into register R1).
- Advantages: Useful for accessing data structures with fixed
displacements.
- Limitations: Requires careful management of base registers and
displacements.

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List and explain characteristics of memory.

• Volatility:

• Definition: Volatility refers to whether the memory retains data

when power is turned off.
• Explanation: Volatile memory loses its stored information when the
power supply is removed or interrupted. RAM (Random Access
Memory) is a primary example of volatile memory. Non-volatile
memory, on the other hand, retains data even when the power is off,
such as ROM (Read-Only Memory) or flash memory.

• Capacity:

• Definition: Capacity denotes the amount of data that a memory

device can store.
• Explanation: Memory capacity is typically measured in bytes, with
units such as kilobytes (KB), megabytes (MB), gigabytes (GB), and
terabytes (TB). Different types of memory have varying capacities,
ranging from small amounts in cache memory to large capacities in
hard disk drives or solid-state drives.

• Speed:

• Definition: Speed, also known as access time, represents how

quickly data can be read from or written to memory.
• Explanation: Faster memory allows for quicker access to data and
instructions, which can significantly impact overall system
performance. Memory speed is measured in nanoseconds (ns) or
megahertz (MHz), with lower values indicating faster access times.

• Access Method:

• Definition: Access method refers to how data is retrieved from or

stored into memory.
• Explanation: Memory can support various access methods,
including random access and sequential access. Random Access
Memory (RAM) allows for direct access to any memory location,
while sequential access memory requires data to be accessed in a
specific order.

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• Accessibility:

• Definition: Accessibility indicates how readily memory can be

accessed by the CPU or other components.
• Explanation: Some memory types, such as cache memory, are
located closer to the CPU, enabling faster access to frequently used
data. Other types of memory, like secondary storage devices (e.g.,
hard disk drives, solid-state drives), require additional processing or
intermediary steps for access.

• Cost:

• Definition: Cost reflects the financial expense associated with

acquiring or implementing memory technology.
• Explanation: Memory cost is a significant consideration in
computer design and purchasing decisions. Faster and higher-
capacity memory often comes at a higher cost. Advances in
technology may lead to reductions in memory cost over time.

• Error Handling:

• Definition: Error handling refers to the memory's ability to detect

and correct errors that occur during data storage or retrieval.
• Explanation: Some memory technologies incorporate error
detection and correction mechanisms, such as ECC (Error-
Correcting Code) memory. These mechanisms help ensure data
integrity and reliability, particularly in mission-critical applications.

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Draw and explain the concept of microprogrammed control unit with
their advantage and disadvantage.

A microprogrammed control unit is a type of control unit that uses

microcode to implement the control logic of the CPU. Microcode is a low-
level code that defines the sequence of microoperations to be executed to
perform various CPU functions. Here's a simplified diagram:
+------------------+
| Microcode |
+------------------+
|
V
+--------------------------+
| Control Unit Logic |
+--------------------------+
| |
V V
+--------------+------------+
| ALU | Registers |
+--------------+------------+

• Microcode: Contains a sequence of microinstructions that control

the operation of the CPU. Each microinstruction specifies the
microoperations to be performed during one clock cycle.
• Control Unit Logic: Decodes the current instruction and generates
the corresponding microinstructions from the microcode memory.
• ALU (Arithmetic Logic Unit): Performs arithmetic and logical
operations.
• Registers: Store data and control signals.

Advantages of Microprogrammed Control Unit:

1. Simplified Hardware Design:

o Microprogramming allows complex control logic to be
implemented using simpler hardware components.
o It reduces the complexity of the control unit circuitry, making
it easier to design and debug.

Easier Debugging and Testing:

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 • Since microcode is stored in memory, it can be easily modified and
tested without making changes to the hardware.
• Debugging and testing of the control unit can be done at the
microcode level, which simplifies the development process.

Disadvantages of Microprogrammed Control Unit:

1. Slower Execution:
o Microinstructions are executed sequentially, which can
introduce additional overhead and slow down the CPU's
performance compared to hardwired control units.
o Each instruction requires multiple microinstructions to be
executed, leading to increased latency.

Higher Hardware Cost:

• While microprogramming simplifies the design of the control unit, it

may require additional hardware components such as microcode
memory, increasing the overall cost of the CPU.

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Design hardware control unit using state table and delay-element
method with their advantage and disadvantage.
Designing a hardware control unit using a state table and the delay-
element method involves defining the control signals and their transitions
between different states in a table format. The delay-element method
introduces delays to synchronize the timing of control signals.
ChatGPT

Hardware Control Unit Design Using State Table and Delay-Element

Method:

1. Define States and Control Signals:

o Identify the states the control unit can be in based on the
CPU's operation and the control signals needed for each state
transition.
2. Create a State Table:
o Construct a state table that represents the control unit's
behavior. The table should list the current state, inputs, next
state, and control signals for each state transition.
3. Implement Delay Elements:
o Introduce delay elements (flip-flops or other timing circuits) to
synchronize the timing of control signals and ensure proper
sequencing of operations.
4. Design Combinational Logic:
o Use combinational logic (e.g., logic gates, multiplexers) to
generate control signals based on the current state and
inputs.
5. Implement the Control Unit:
o Implement the control unit circuitry based on the state table
and delay-element method, integrating the delay elements
and combinational logic.
6. Test and Debug:
o Test the control unit to ensure proper functionality and debug
any issues in the design.

Advantages

Modularity:

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 • State tables provide a structured and modular approach to designing
control units, making it easier to understand and modify the control
unit's behavior.

Flexibility:

• State tables allow for flexibility in defining the control unit's

operation and behavior, enabling support for various instruction sets
and architectures.

Disadvantages

• Complexity:

• Designing a control unit using state tables and the delay-element

method can be complex, especially for CPUs with large instruction
sets or complex architectures.

• Timing Constraints:

• Introducing delay elements to synchronize control signals adds

complexity and may introduce timing constraints that need to be
carefully managed.

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Draw and explain microoinstruction sequencing

Microinstruction sequencing involves the process of executing a sequence

of microinstructions to perform a specific operation within a CPU's control
unit. These microinstructions are stored in microcode memory and are
executed sequentially to carry out tasks such as fetching instructions,
decoding them, and executing operations. Let's illustrate microinstruction
sequencing and discuss its components:
lua
Copy code
+-----------------------------------+
| Microinstruction |
+-----------------------------------+
| | |
V V V
+----------------------+----------------------+
| Control Signals | Next Address |
+----------------------+----------------------+

1. Microinstruction:
o A microinstruction contains control signals that control the
operation of the CPU during a clock cycle.
o Control signals specify actions such as enabling registers,
selecting multiplexer inputs, and controlling the ALU (Arithmetic
Logic Unit).
2. Control Signals:
o Control signals determine the behavior of the CPU during the
current clock cycle.
o Examples of control signals include:

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 ▪ Read/Write Enable: Controls the read or write operation to
memory or registers.
▪ ALU Control: Specifies the operation to be performed by
the ALU.
▪ Register Select: Determines which register is being
accessed.
▪ Clock Enable: Controls the clock signal to trigger the next
clock cycle.
3. Next Address:
o Indicates the address of the next microinstruction to be
executed.
o It specifies the sequence in which microinstructions are executed
to perform a task.
o Next address generation may involve incrementing the current
address, branching to a different address based on conditions, or
jumping to a specific address.

Microinstruction Sequencing Process:

1. Fetch Microinstruction:
o The control unit retrieves the microinstruction from the
microcode memory based on the current address.
2. Execute Microinstruction:
o The control unit interprets the control signals within the
microinstruction and performs the corresponding actions,
such as setting control lines, accessing registers or memory,
and activating the ALU.
3. Update Address:
o The control unit determines the address of the next
microinstruction based on the current microinstruction's next
address field.
o Address generation may involve simple incrementation,
branching based on conditions (e.g., branch if zero), or
jumping to specific addresses (e.g., subroutine call).
4. Repeat Process:
o The process repeats for each clock cycle, with the control unit
fetching, executing, and updating the address of the next
microinstruction.

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Explain with suitable diagram, why DRAM cell required refreshing in
computer system

Dynamic Random Access Memory (DRAM) cells require refreshing in

computer systems due to the inherent characteristics of the memory
technology. DRAM cells store data in the form of electrical charges on
capacitors, which tend to leak over time. Refreshing is necessary to
maintain the integrity of the stored data. Let's break down the process with
a suitable diagram:
+-----------------+ +-------------+
| | | |
| Control | | |
| Logic | | |
| | | |
+--------+--------+ +--------+----+
| |
| Memory |
| Array |
| |
+--------v--------+ +--------v----+
| | | |
| Row | | |
| Decoder | | |
| | | |
+-----------------+ +-------------+
| |
| |
+---------v---------+ +-------v------+
| | | |
| Sense | | |
| Amplifiers | | |
| | | |
+-------------------+ +--------------+

1. Memory Array:
o The memory array consists of rows and columns of DRAM
cells. Each cell contains a capacitor to store data.
2. Control Logic:
o The control logic generates signals to read from or write to
specific rows and columns within the memory array.
3. Row Decoder:
o The row decoder selects a specific row in the memory array
based on the memory address provided by the control logic.
4. Sense Amplifiers:
o The sense amplifiers detect and amplify the tiny voltage
signals from the selected row of memory cells to distinguish
between stored 0s and 1s.

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1. Capacitor Leakage:
o DRAM cells store data in the form of electrical charges on
capacitors. However, capacitors tend to leak charge over time
due to their inherent characteristics.
2. Data Loss:
o As charge leaks from the capacitors, the stored data gradually
fades away. If not refreshed periodically, the charge on the
capacitors can diminish to the point where the stored data
becomes unreadable.
3. Refreshing Process:
o To prevent data loss, DRAM cells need to be refreshed
periodically. During the refresh operation, the control logic
reads the data from each row of memory cells and rewrites it
back, effectively restoring the charge on the capacitors and
refreshing the data.
4. Refresh Interval:
o The refresh interval, typically measured in milliseconds,
determines how often the DRAM cells need to be refreshed.
The refresh rate is controlled by the system's memory
controller or memory management unit.

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what is pipeline hazards ? give the types of pipeline hazards

Pipeline hazards are situations that arise in pipelined processors that can
stall or disrupt the smooth flow of instructions through the pipeline,
leading to reduced performance or incorrect results. There are several
types of pipeline hazards:

Structural Hazards:

• Structural hazards occur when the hardware resources required to

execute multiple instructions simultaneously are not available.
• Examples include conflicts for accessing the same hardware
component, such as the instruction fetch unit, instruction decode
unit, or execution units.

Data Hazards:

• Data hazards arise when a pipeline stage depends on the result of a

previous instruction that has not yet been computed or written back
to the register file.
• There are three types of data hazards:
o Read After Write (RAW): Also known as data dependency
hazard, occurs when an instruction tries to read data before a
previous instruction writing to the same location completes.
o Write After Read (WAR): Occurs when an instruction tries
to write data before a previous instruction reading from the
same location completes.
o Write After Write (WAW): Occurs when two instructions try
to write to the same location simultaneously, leading to
incorrect results if not properly handled.

Control Hazards:

• Control hazards arise due to changes in the flow of control caused by

branch instructions or other control flow instructions.
• The pipeline needs to predict the outcome of branch instructions and
fetch subsequent instructions accordingly.
• If the prediction is incorrect, a branch misprediction occurs, and the
pipeline needs to be flushed, leading to wasted clock cycles.

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explain different memory mapping techniques

Memory mapping techniques refer to methods used to map logical

addresses to physical addresses in a computer system. These techniques
are crucial for managing memory efficiently and facilitating the interaction
between the CPU and memory subsystem. Here are some common
memory mapping techniques:

1. Direct Mapping:
o In direct mapping, each memory block in the main memory is
mapped to a specific cache line in the cache memory.
o A portion of the logical address (e.g., the middle bits) is used
to index into the cache.

Fully Associative Mapping:

• In fully associative mapping, each memory block can be placed in

any cache line in the cache memory.
• The entire logical address is used as a tag to search for the desired
memory block in the cache.

Set Associative Mapping:

• Set associative mapping combines aspects of direct mapping and

fully associative mapping.
• The cache is divided into multiple sets, each containing a fixed
number of cache lines.

Segmentation:

• Segmentation divides the logical address space into segments of

variable lengths.
• Each segment represents a logical unit of the program, such as code,
data, or stack.

Paging:

• Paging divides the logical address space and physical memory into
fixed-size pages.
• The memory management unit (MMU) translates logical addresses
to physical addresses using a page table, which maps each page

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 explain in detail cache coherence

Cache coherence is a fundamental concept in computer

architecture and multiprocessing systems, particularly in systems
with multiple CPU cores or processors sharing a common memory.
It ensures that all cached copies of a shared memory location are
kept consistent across different caches. In simpler terms, cache
coherence ensures that if one processor updates a memory
location, all other processors accessing the same location see the
update.

Cache coherence is typically implemented using cache coherence

protocols. These protocols define rules and mechanisms for
maintaining cache coherence in a multiprocessor system.

MESI Protocol:

• MESI (Modified, Exclusive, Shared, Invalid) is one of the most

widely used cache coherence protocols.
•

MOESI Protocol:

• MOESI (Modified, Owned, Exclusive, Shared, Invalid) is an

extension of the MESI protocol.

MESIF Protocol:

• MESIF (Modified, Exclusive, Shared, Invalid, Forward) is another

extension of the MESI protocol.

Cache coherence protocols are implemented using various mechanisms,

including:

1. Invalidation-Based Coherence:
o In invalidation-based coherence, when one cache updates a
memory location, it sends an invalidation message to all other
caches holding copies of the same memory location.

Update-Based Coherence:

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• In update-based coherence, when one cache updates a memory
location, it sends an update message to all other caches holding
copies of the same memory location.

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 design a full adder using half adder and additinal gates gives its truth table

A full adder is a combinational logic circuit that adds three input bits (A, B, and Cin) and
produces two output bits (Sum and Cout). It can be implemented using two half adders and
additional logic gates.

Here's the truth table for a full adder:

A B Cin Sum Cout

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Half Adder:

A half adder adds two input bits (A and B) and produces two output bits (Sum and Cout).

Truth table for a half adder:

A B Sum Cout
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Full Adder:

A full adder adds three input bits (A, B, and Cin) and produces two output bits (Sum and
Cout).

Implementation:

1. Use the first half adder to add A and B, producing a partial sum (PS) and a partial carry (PC).
2. Use the second half adder to add PS and Cin, producing the final sum (Sum) and the final
carry out (Cout).
3. • HA1: First half adder (adds A and B)
4. • HA2: Second half adder (adds PS and Cin)
5. • OR: OR gate (combines PC and Cout)

Truth Table for Full Adder:

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A B Cin Sum Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

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Draw basic organization of computer and explain its block level diagram functional
units

The basic organization of a computer typically consists of several

functional units interconnected to perform various tasks involved in
executing instructions and processing data. Here's a simplified block-level
diagram of a computer and explanations of its functional units:

CPU (Central Processing Unit):

The CPU is the core component responsible for executing instructions and
performing data processing operations.

• Control Unit: Controls the operation of the CPU by decoding

instructions fetched from memory and generating control signals to
coordinate the activities of other units.
• Arithmetic Logic Unit (ALU): Performs arithmetic and logical
operations, such as addition, subtraction, AND, OR, etc., on data
fetched from registers.
• Registers: Stores temporary data and control information used by
the CPU during instruction execution. Common types of registers
include:
o Program Counter (PC): Holds the memory address of the next
instruction to be fetched.
o Instruction Register (IR): Holds the current instruction being
executed.

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2. Memory:

Memory stores instructions and data needed for program execution. It is

typically organized into different levels, such as cache, main memory
(RAM), and secondary storage (e.g., hard disk).

3. Input/Output (I/O):

The I/O subsystem facilitates communication between the computer and

external devices, such as keyboards, mice, displays, printers, and network
interfaces.

Functional Units in Detail:

• Control Unit:
o Fetches instructions from memory.
o Decodes instructions to determine their operations.
o Generates control signals to coordinate the activities of other
units.
o Manages the flow of data and instructions between different
units.
• ALU:
o Performs arithmetic operations (e.g., addition, subtraction)
and logical operations (e.g., AND, OR, NOT) on data operands.
o Executes instructions that involve mathematical calculations
or logical comparisons.
• Registers:
o Program Counter (PC): Holds the memory address of the next
instruction to be fetched.
o Instruction Register (IR): Holds the current instruction being
executed.
o General-Purpose Registers: Hold data operands and
intermediate results during computation.
o Accumulator: Stores results of arithmetic operations.
o Index Registers: Hold memory addresses or offsets for data
access.
o Stack Pointer: Points to the top of the stack used for
subroutine calls and local variables storage.

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draw logic circuit diagram for master slave J-K flip-flop with preset and clear inputs using
NAND gates give its truth table and logic symbol diagram

A master-slave J-K flip-flop with preset (PR) and clear (CLR) inputs can be
constructed using NAND gates. Here's the logic circuit diagram, truth
table, and logic symbol diagram:
• J and K are the data inputs.
• PR (preset) and CLR (clear) are the control inputs.

• Q and Q' are the complementary outputs.

X denotes "don't care" state.

This circuit functions as a master-slave J-K flip-flop with preset (PR) and
clear (CLR) inputs. It stores a single bit of information and can be used in
sequential logic circuits for various applications like counters, shift
registers, and memory elements.

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Explain how NAND gate can be used universal logic gates give
appropriate example for how it can be used to implement other logic
gates.
NAND gates are considered universal logic gates because they can be used to implement any other
logic gate, including AND, OR, NOT, and XOR gates. This property is known as functional
completeness. Here's how NAND gates can be used to implement other logic gates:

NOR Gate
A NOR gate is a combination of an OR gate followed by a NOT gate. It
outputs a 1 only when all its inputs are 0; otherwise, it outputs 0.

NOT Gate (Inverter)

Circuit: Connect both inputs of a NAND gate to the same input signal.

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AND Gate
Circuit: Connect the outputs of two NAND gates to the inputs of a third
NAND gate.

A B Z
0 0 0
0 1 0
1 0 0
1 1 1

OR Gate
Circuit: Connect each input to a NAND gate and then connect the
outputs of these gates to the inputs of another NAND gate.

A B Output (A OR B)
0 0 0
1 0 1
0 1 1
1 1 1

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XOR Gate
Circuit: Utilize a combination of five NOR gates.

A B OUTPUT(A XOR B)
0 0 0
0 1 1
1 0 1
1 1 0

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 MUMBAI UNIVERSITY
SEMESTER 3
Digital Logic Design And Analysis
DECEMBER 2017-CBCS

Q.1(a) Convert (1762.46)10 into octal,binary and hexadecimal. [3]

Ans :
(i) (1762.46)10 = (X)8 i.e Decimal to octal

Remainder
8 1762 2
220 4 ∴ (1762)10 = (3342)8
27 3
3 3

Fractional part :
0. 46
8
3 68 ∴ (0.42)10 = (0.353)8
8
5 44 ∴ (1762.46)10 = (3342.353)8
8
3 52

(ii) (1762.46)10 = (Y)2 i.e Decimal to binary

2 1762 0
881 1 ∴ (1762)10 = (11011100010)8
440 0
220 0
110 0
55 1
27 1
13 1
6 0
3 1
1 1
 Fractional part :
0. 46
2
0 92 ∴ (0.42)10 = (0.011)2
2
1 84 ∴ (1762.46)10 = (11011100010.011)2
2
1 68

(iii) (1762.46)10 = (Z)16 i.e Decimal to hexadecimal

Remainder
16 1762 2
110 E ∴ (1762)10 = (6E2)16
6 6

Fractional part :

0. 46
16
7 36 ∴ (0.42)10 = (0.75C)2
16
5 76 ∴ (1762.46)10 = (6E2.75C)2
16
C 16

(b) Prove OR-AND configuration is equivalent to NOR-NOR configuration.

[3]
Ans :
The expression for OR gate output is y=A+B.
The expression for AND gate output is y=A.B
The expression for NOR gate output is y=̅̅̅̅̅̅̅̅
𝑨+𝑩
From this we can prove that OR-AND configuration is same as NOR-NOR
Configurations.

(c) Perform substration using 16’s complement. [4]

(i)(𝐂𝐁10)16 − (971)16
(ii) (426)16 − (𝐃𝐁𝐀)16
Ans : (i) (971)16 15’s complement is :
(𝐂𝐁10)16 − (971)16 = (𝐂𝐁10)16 + (971)16 = 𝐶19𝐹

(𝐂𝐁10)16 − (971)16 = C19F

(ii) (𝐃𝐁𝐀)16 15’s complement is : 245

426 + 245 = −994 IN HEXA DECIMAL

(426)16 − (𝐃𝐁𝐀)16= -994

(d) Find 8’s complement of following numbers.

(i) (𝟐𝟕)8 (i) (3𝟐𝟏)8 [2]
Ans : 8’s complement is 1 + 7’s complement of number.
To calculate 7’s complement substract each digit of
number from 7
(i) (𝟐𝟕)8 = (77-27) + 1 = 50 + 1 =51
∴ (𝟐𝟕)8 = (𝟓𝟏)8

(ii) ∴ (𝟑𝟐𝟏)8 = 777 − 321 = 456 + 1 = 457

∴ (𝟑𝟐𝟏)8 = (𝟒𝟓𝟕)8
(e) Perform following substraction (52)10 − (65)10 using 2’s complement
Method. [2]
Ans : (52)10 = (110100)2
(65)10 = (1000001)2
2’s complement of (65)10 is (0111110)+1=0111111
∴ (52)10 − (65)10 = (110100)2 − (0111111)2 = −1101

We can represent -1101 in decimal as -13 .

∴ (52)10 − (65)10 = (−13)10

(f) Write hamming code for 1010. [2]

Ans : Given code W=(1 0 1 0)
Hamming code is given by ,
X=W.G
1 0 00 1 10
X=( 1 0 1 0 1 00 1 01 ]
0 ) . [0 0 10 0 1 1
0 0 01 1 1 1

X=(1010001)

(g) Implement the following Boolean equation using NAND gates only.
Y= AB+CDE+F [2]
Ans : In this y can be implemented using 3 input nand and 2 input nand
gates.
(h) Explain the term prime implicant. [2]
Ans :
i) A group of related 1's (implicant) on a Karnaugh map which is not subsumed by
any other implicant in the same map. Equivalently (in terms of Boolean algebra), a
product term which is a "minimal" implicant in the sense that removing any of its
literals will yield a product term which is not an implicant (on a Karnaugh map it
would appear "maximal").

ii) A group of related 0's (implicant) on a Karnaugh map which is not subsumed by
any other implicant (of 0's) in the same map.

Q.2(a) Design a 4-bit ripple adder. [10]

Ans :
(i) Multiple full adder circuits can be cascaded in parallel to add an N-bit number. For
an N- bit A parallel A adder, there must be N number of full adder circuits.

(ii) A ripple carry adder is a logic circuit in which the carry-out of each full adder is
the carry in of the succeeding next most significant full adder. It is called a ripple carry
adder because each carry bit gets rippled into the next  stage.

(iii)In a ripple carry adder the sum and carry out bits of any half adder stage is not
valid until the carry in of that stage occurs.

(iv)Propagation delays inside the logic circuitry is the reason behind this. Propagation
delay is time elapsed between the application of an input and occurance of the
corresponding output.

(v)Consider a NOT gate, When the input is “0” the output will be “1” and vice versa.
The time taken for the NOT gate’s output to become “0” after the application of logic
“1” to the NOT gate’s input is the propagation delay here.

(v)Similarly the carry propagation delay is the time elapsed between the application of
the carry in signal and the occurance of the carry out (Cout) signal.
 (vi) Sum out S0 and carry out Cout of the Full Adder 1 is valid only after the
propagation delay of Full Adder 1.

(vii) In the same way, Sum out S3 of the Full Adder 4 is valid only after the joint
propagation delays of Full Adder 1 to Full Adder 4. In simple words, the final
result of the ripple carry adder is valid only after the joint propogation delays of
all full adder circuits inside it.

(b) Obtain the minimal expression using QuineMc-Cluskey method.

F(A,B,C,D)=∑𝐦(1,5,6,12,13,14) + 𝐝(2,4) [10]
Ans :
Step 1: Write down the binary equivalent of the given expressions (including
the don't care):

A B C D
1 0 0 0 1
2 0 0 1 0
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
Step 2:
Create the following table in which the binary number with equal number of
1's are grouped together. For e.g. the first group contains binary numbers with
only one number of 1's, second group contains binary numbers with two 1's
and so on.

GROUP MINTERM BINARY REPRESENTATION

A B C D
1 m1 0 0 0 1 √
d2 0 0 1 0 √
d4 0 1 0 0 √
2 m5 0 1 0 1 √
m6 0 1 1 0 √
m12 1 1 0 0 √
3 m13 1 1 0 1 √
m14 1 1 1 0 √

Step 3: In the next step compare every element of group 1 with elements in
group 2, elements of group 2 with 3, etc. In general compare elements of nth
group with elements of n+1th group. If only 1 element is changing in the
comparison the mark it with an underscore. Put a tick mark against both the
elements if the elements are present in the comparison. For e.g. in m1 and m5
the A, C, D bits are same but only B bit changes, so an underscore is put
against it.

GROUP MATCHED BINARY REPRESENTATION

PAIRS A B C D
1 m1 m5 0 _ 0 1
d2 m6 0 _ 1 0
d4 m5 0 1 0 _ √
 d4 m6 0 1 _ 0 √
d4 m12 _ 1 0 0 √
2 m5 m13 _ 1 0 1 √
m6 m14 _ 1 1 0 √
m12 m13 1 1 0 _ √
m12 m14 1 1 _ 0 √

Step 4: In this step again match the values of nth group with n+1th group and
mark tick against the ones that gets matched, followed by underscore to the
single bits that change. Since m1 m5, d2 m6 are not getting matched with any
other no tick marks is put against them.

GROUP MATCHED BINARY REPRESENTATION

PAIRS A B C D
1 d4 m5 m12 m13 _ 1 0 _
d4 m6 m12 m13 _ 1 _ 0

Step 5: Now make the last table which contains the prime implicant and the
min terms involved (Prime implicants are the ones that do not get matched).
Write them in their alphabet form with 0 bit represented as bars. In this step
write all the numbers which were given in the question (not the don't care
ones). Put a cross below the numbers which contain the minterms.

Prime Minterms 1 5 6 12 13 14
Implicant Involved
BC 4, 5, 12, 13 ˟ ˟ ˟
BD 4, 6, 12, 14 ˟ ˟ ˟
ACD 1, 5 ˟ ˟
ACD 2, 6 ˟
 If the column of the numbers contain only one cross then the prime implicant
belonging to the single cross belonging row is considered. In this case the
columns of 1, 13 and 14 contain only 1 crosses so the row belonging to them is
considered which are BC, BD, ACD. These are the reduced answer.

Therefore the final answer is:

Y = BC + BD + ACD

∴ F(A,B,C,D) = BC + BD + ACD

Q.3(a) Implement full adder using 8:1 multiplexer. [10]

Ans :
3 bit binary adder is adder circuit which performs bit by bit addition and
gives output as sum and carry .The truth table for a full adder :

A B C SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

We will require two 8:1 multiplexer to implement a full adder. One for sum
and one for carry.
In 8:1 MUX we have 3 selection lines, assigning them A, B, C.For sum :

For carry :
(b) Implement the following functions using demultiplexer.
F1(A,B,C)=∑𝐦(0,3,7) F2(A,B,C)=∑𝐦(1,2,5) [5]
Ans :
(1) F1 (A, B, C) = 𝛴m(0, 3, 7)
Number of variables = 3
Number of select lines = 3
Number of lines = 23 = 8

(2) F2 (A, B, C) = 𝛴m(1, 2, 5)

Number of Variables = 3
Number of Select Lines = 3
Number of Lines = 23 = 8
(c) Simplify F(A,B,C,D)=∏𝐌(3,4,5,6,7,10,11,15) and implement
using minimum number of gates. [5]
Ans :
We can write same function using sum of product way ,

F(A,B,C,D)=∏m(0,1,2,8,9,12,13,14)

K-map is given by

The expression after grouping :

F(A,B,C,D)= A.𝐶̅ + 𝐵̅.𝐶̅ + 𝐶̅ .( 𝐴̅𝐵̅ + A. 𝐵)

Circuit Diagram :
Q.4(a) Compare TTL and CMOS logic withn respect to fan in,fan out
Propogation delay,power consumption,noise margin,current and
Voltage parametes. [5]
Ans :
Parameter TTL CMOS
Propagation Delay 1 to 200nsec 1.5 to 33nsec
Power consumption Relatively High Depends on Vcc
Noise Margin 0.3-0.5 0.3Vcc
Current High (0.2-2mA) Low (1uA)
Voltage 5V 3-18V
Fan in High fan in Low fan in
Fan out Approx. 10 >50
Transistor used BJT FET
Type Current controlled Voltage controlled
Current devices current device

(b) Draw the circuit of SR flip flop using two NOR gates and write the
Architecture body for the same using structural modelling. [5]
Ans :

SR flip flop using two NOR gate :

SR FLIP FLOP
Architectural Body :

begin

PROCESS(CLOCK)

variable tmp: std_logic;

begin

if(CLOCK='1' and CLOCK'EVENT) then

if(S='0' and R='0')then

tmp:=tmp;

elsif(S='1' and R='1')then

tmp:='Z';

elsif(S='0' and R='1')then

tmp:='0';

else

tmp:='1';

end if;

end if;

Q <= tmp;

QBAR <= not tmp;

end PROCESS;
end behavioral;
(c) Explain 1-digit BCD adder. [10]
Ans :

i) BCD adder adds two BCD digits and produces output as a BCD digit. A
BCD or Binary Coded Decimal digit cannot be greater than 9.

ii)The two BCD digits are to be added using the rules of binary addition. If
sum is less than or equal to 9 and carry is 0, then no correction is needed. The
sum is correct and in true BCD form.

iii)But if sum is greater than 9 or carry =1, the result is wrong and correction
must be done.

iv)The wrong result can be corrected adding six (0110) to it.

v)For implementing a BCD adder using a binary adder circuit IC 7483,

additional combinational circuit will be required, where the Sum
output S3−S0S3−S0 is checked for invalid values from 10 to 15.

vi) Truth Table :

S3 S2 S1 S0 Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
vi) The Boolean expression is, Y=S3S2+S3S1Y=S3S2+S3S1

vii)The BCD adder is shown below. The output of the combinational circuit
should be 1 if Cout of adder-1 is high. Therefore Y is ORed with Cout of adder
1.
viii)The output of combinational circuit is connected to B1B2 inputs of adder-2
and B3=B1+0B3=B1+0 as they are connected to ground permanently. This
makes B3B2B1B0B3B2B1B0 = 0110 if Y' = 1.

ix)The sum outputs of adder-1 are applied to A3A2A1A0A3A2A1A0 of adder-

2.

x)The output of combinational circuit is to be used as final output carry and

the carry output of adder-2 is to be ignored.
Q.5 (a) Convert JK flip flop to SR flip flop and D filp flop. [10]

Ans: (A) JK Flip flop to SR flip flop :

1.Truth table of SR FF:

S R Q 𝑄̅
0 0 X X
0 1 0 1
1 0 1 0
1 1 - -

2.Excitation Table of JK FF:

Qn 𝑄𝑛+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

3.Conversion Table:

S R 𝑄𝑛 𝑄𝑛+1 J K
0 0 0 0 0 X
0 1 1 1 X 0
0 0 0 0 0 X
0 1 1 0 X 1
1 0 0 1 1 X
1 1 1 1 X 0
1 0 - - X X
1 1 - - X X
4. Logical expressions for the inputs :

Simplify the logical expressions for the inputs of the given flip-flop (J and K) in terms
of the inputs of the desired flip-flop (S and R) and the flip-flop's present-state, Qn.This

can be done by following any logical simplification technique like that of the
K-map.

5. Circuit Diagram :

S J 𝑄𝑛

CLK JK FF

R K 𝑄𝑛+1

(B) JK TO D FF :

1.Truth Table of D flip flop :

D Q 𝑄̅
0 0 0
0 1 0
1 0 1
1 1 1
 2.Excitation Table of JK FF:

Qn 𝑄𝑛+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

3.Conversion Table :

D 𝑄𝑛 𝑄𝑛+1 J K
0 0 0 0 X
0 1 1 0 1
1 0 0 1 X
1 1 0 1 0

4.Use a K-map to obtain the logical expressions for the inputs J and K
in terms of D and Qn.

5. Circuit Diagram:

D J 𝑄𝑛

CLK JK FF

K
𝑄𝑛+1
(b) Design 3 bit synchronous counter using T flip flops. [10]

Ans : (i) A synchronous counter, in contrast to an asynchronous counter, is one

whose output bits change state simultaneously, with no ripple.

(ii)The only way we can build such a counter circuit from T flip-flops is to
connect all the clock inputs together, so that each and every flip-flop receives the
exact same clock pulse at the exact same time.

(iii) For an up counter that means it will count from value 0 to 7 for interval
difference of 1.

(iv) Truth table for up counter is given by ,

Present State Next State T2 T1 T0

000 001 0 0 1
001 010 0 1 1
010 011 0 0 1
011 100 1 1 1
100 101 0 0 1
101 110 0 1 1
110 111 0 0 1
111 000 1 1 1

(v) From this truth table :

(vii)The 3-bit Synchronous binary up counter contains three T flip-flops & one
2-input AND gate. All these flip-flops are negative edge triggered and the
outputs of flip-flops change (affect) synchronously. The T inputs of first,
second and third flip-flops are 1, Q0Q0 & Q1Q0Q1Q0 respectively.

(viii)The output of first T flip-flop toggles for every negative edge of clock
signal.

(ix)The output of second T flip-flop toggles for every negative edge of clock
signal if Q0Q0 is 1.

(x)The output of third T flip-flop toggles for every negative edge of clock signal
if both Q0Q0 & Q1Q1 are 1.
(Here we can write Q3Q2Q1=Q2Q1Q0).
Q.6 Write short note on (any four) [20]

(a) State table :

Ans :
i) The state table representation of a sequential circuit consists of three
sections labeled present state, next state and output.

Ii)The present state designates the state of flip-flops before the

occurrence of a clock pulse.

iii) The next state shows the states of flip-flops after the clock pulse, and
the output section lists the value of the output variables during the
present state.

iv) In addition to graphical symbols, tables or equations, flip-flops can

also be represented graphically by a state diagram.
v) In this diagram, a state is represented by a circle, and the transition
between states is indicated by directed lines (or arcs) connecting the
circles.

(b) ALU IC 74181

Ans :
i)The 74181 is a bit slice arithmetic logic unit (ALU), implemented as
a 7400 series TTL integrated circuit.

ii)The first complete ALU on a single chip, it was used as the

arithmetic/logic core in the CPUs.
iii) The 74181 is a 7400 series medium-scale integration
(MSI) TTL integrated circuit, containing the equivalent of 75 logic
gates and most commonly packaged as a 24-pin DIP.

iv) The 4-bit wide ALU can perform all the traditional add / subtract /
decrement operations with or without carry, as well as AND /
NAND, OR / NOR, XOR, and shift.

v) Many variations of these basic functions are available, for a total of

16 arithmetic and 16 logical operations on two four-bit words. Multiply
and divide functions are not provided but can be performed in multiple
steps using the shift and add or subtract functions.

vi)Shift is not an explicit function but can be derived from several

available functions; e.g., selecting function "A plus A" with carry (M=0)
will give an arithemetic left shift of the A input.

(c) Sequence generator :

Ans :

i)There are counters which pass through a definite number of states in a

pre-determined order. For example, a 3-bit up-counter counts from 0 to
7 while the same order is reversed in the case of 3-bit down counter.

ii) These circuits when suitably manipulated can be made to count till
an intermediate level also. This means that instead of counting till 7, we
can terminate the process by resetting the counter just at, say, 5. Such
counters are then known as mod-N counters.

iii)We can design sequence generator using some D flip flops.

It will generate sequence from some given input binary digit.

iv) Sequence generator :

 𝑄1 𝑄0 𝑄1 ∗ 𝑄0 ∗ 𝐷1 𝐷0
0 0 0 1 0 1
0 1 1 1 1 1
1 1 1 0 1 0
1 0 0 0 0 0

D1 Q1 D0 Q0

Clk Q1’ Clk Q0’

CLK

Sequence Generator

(d) Data flow modelling

Ans :

i)The process of identifying, modeling and documenting how data

moves around an information system. Data flow modeling
examines processes (activities that transform data from one form to
another), data stores (the holding areas for data), external
entities (what sends data into a system or receives data from a
system, and data flows (routes by which data can flow).

ii)Data flow modeling is one of the foundations of the Structured

Systems Analysis and Design Method.

iii)Data flow modeling also is called data flow diagramming.

(e) 4 bit ring counter
Ans :
i) A ring counter is a Shift Register (a cascade connection of flip-
flops) with the output of the last flip flop connected to the input of
the first.
ii)It is initialised such that only one of the flip flop output is 1 while
the remander is 0.
iii)The 1 bit is circulated so the state repeats every n clock cycles if n
flip-flops are used. The MOD of a counter is the number of unique
states. The MOD of the n flip flop ring counter is n.
iv)It can be implemented using D-type flip-flops (or JK-type flip-
flops).
v) 4-bit Ring Counter :

Truth Table :
CLK 𝑄3 𝑄2 𝑄1 𝑄0

1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
 DLDA
(CBCGS MAY 2018)

Q1] a) Write the entity declaration in VHDL for NOR gate.

(02)

Solution :-
NOR Gate:
A logic gate whose output logic is ‘1’ if and only if all of its inputs are logic ‘0’.
Entity declaration of NOR gate

Library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity nor_df is
Port (a: in STD_LOGIC;
b: in STD_LOGIC;
c: out STD_LOGIC);
end nor_df;
architecture Behavioral of nand_df
is
begin
c<=a nor b;

Q1] b) Add (22)10 to (56)10 in BCD.

(02)
Solution :-
BCD of (22)10 is 00100010
BCD of (56)10 is 01010110

00100010
+ 01010110

01111000
(22)10 + (56)10 = 01111000
Q1] c) Convert decimal 57 into binary, base 7 and hexadecimal.
(02)

Solution :-
Decimal 57 to binary

Decimal 57 to base 7

Decimal 57 to hexadecimal

Q1] d) Construct hamming code for 1010.

(02)
Solution :-
7 bit Hamming code is given as
D7 D6 D5 P4 D3 P2 P1

Given 4 bit is 1010 therefore it can be written as

1 0 1 P4 0 P2 P1

P1: For P1 consider P1, D3, D5, D7

D3, D5, D7 = 011
For even parity set P1 = 0
P1: For P2 consider P2, D3, D6, D7
D3, D6, D7 = 001
For even parity set P2 = 1
P1: For P1 consider P4, D5, D6, D7
D5, D6, D7 = 011
For even parity set P4 = 0

1 0 1 0 0 1 0
Therefore, hamming code for 1010 is given as 1010010.

Q1] e) Perform subtraction using 2’s complement for (10)10 - (7)10.

(02)

Solution :-
Binary representation of 7 is 0111
1’s complement of 7 is 1000
2’s complement of 7 is 1’s complement + 1

1000

+ 1

1001

Now adding 10 and 2’s complement of 7

1010

+ 1001

10011

Discard carry 1
Therefore (10)10 - (7)10 = 0011 = (3)10.

Q1] f) State and prove De Morgan’s law.

(02)

Solution :-
Theorem 1:
Statement: The complement of the product of two or more variables is equal to the sum of the
components of the variables.
Logical expression: ̅̅̅̅̅ ̅+B
A. B = A ̅
NAND is equal to BUBBLED OR.

A B A.B ̅̅̅̅̅
A. B ̅
A ̅
B ̅+B
A ̅

0 0 0 1 1 1 1

0 1 0 1 1 0 1

1 0 0 1 0 1 1

1 1 1 0 0 0 0

From the above truth table we can see that ̅̅̅̅̅ ̅+B
A. B = A ̅ Hence proved.

Theorem 2 :-

Statement: The complement of the sum of two or more variables is equal to the product of the
complement of the variables
Logical expression: ̅̅̅̅̅̅̅̅
𝐴 + 𝐵 = 𝐴̅. 𝐵̅
NOR is equal to BUBBLED AND.

A B A+B ̅̅̅̅̅̅̅
A+B ̅
A ̅
B ̅. B
A ̅

0 0 0 1 1 1 1

0 1 1 0 1 0 0

1 0 1 0 0 1 0

1 1 1 0 0 0 0

From the above truth table we can see that ̅̅̅̅̅̅̅̅

𝐴 + 𝐵 = 𝐴̅. 𝐵̅ Hence proved.

Q1] g) Convert (77)10 into Excess 3 code.

(02)

Solution :-
Excess 3 code is 3 added to BCD.
BCD of 77 is 0111 0111 and 0f 3 is 0011

01110111

+ 00110011

10101010
Excess 3 code of 77 is 10101010

Q1] h) Perform addition of (34)8 and (62)8.

(02)

Solution :-
(34)8 + (62)8

34

+ 62

116

In the above sum 6 + 3 is greater than 7 hence can’t be represented as octal therefore we need to
divide it with 8

Remainder is the sum and the quotient is carry.

Therefore, we get (34)8 + (62)8 = (116)8.

Q1] i) Find 8’s complement of the number (37)8 and (301)8.

(02)

Solution :-
To find 8’s complement we first need to find 7’s complement and then add 1 to it.
7’s complement of 37 is obtain by subtracting 37 from 77
i) 77

+ 37

40 7’s complement
+ 1

41 8’s complement
ii) 777
+ 301

476 7’s complement

+ 1

477 8’s complement

Q1] j) Explain ASCII code in brief.

(02)

Solution :-
ASCII was developed by the American National Standards Institute (ANSI). Pronounced ask-ee, ASCII
is the acronym for the American Standard Code for Information Interchange.
It is a code for representing 128 English characters as numbers.
Technically, ASCII is 7-bit representing only 128 characters (0-127). The range 0-31 are control
characters, with 32-127 representing alphabetical characters from A to Z, numerals from 0 to 9 and
punctuation marks (though not in that order).
For example, the ASCII code for uppercase M is 77.
Most computers use ASCII codes to represent text, which makes it possible to transfer data from one
computer to another.
Text files stored in ASCII format are sometimes called ASCII files. Text editors and word
processors are usually capable of storing data in ASCII format, although ASCII format is not always
the default storage format.

Q2] a) Simplify the following equation using K map to obtain SOP equation and realize the
minimum equation using only NAND gates.

F(A,B,C,D) = 𝜮m(1,2,4,6,9,10,12,14) + d(3,7,13)

(10)
Solution :-

Step 1: Draw K map

Step 2: SOP Equation
Y = B𝐶̅ 𝐷
̅ + 𝐵̅ 𝐶̅ 𝐷 + C 𝐷
̅

Step 3: NAND gate realization

Take double inversion
𝑌 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
B𝐶̅ 𝐷
̅ + 𝐵̅ 𝐶̅ 𝐷 + C 𝐷̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
Y = ̅̅̅̅̅̅̅
̅ ̅̅̅̅̅̅
𝐵 𝐶̅ 𝐷 𝐵̅ 𝐶̅ 𝐷 ̅̅̅̅
𝐶𝐷̅
Q2] b) Implement full adder using 8:1 mux.

(10)
Solution :-

Truth table of full adder

A B Cin S Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

In full adder there are 3 input A, B and Cin and they are added and generates two output S and Cout.
S is the sum of A, B and Cin and Cout is the carry generated by adding 3 input’s.

Full Adder Implementation using 8:1 MUX

An 8:1 multiplexer consists of eight data inputs I0 to I7, three input select lines A, B and C and a single
output line Y. Depending on the select lines combinations, multiplexer decodes the inputs.
Since the number of input data bits given to the MUX are eight therefore 3 bits (23=8) are needed to
select one of the eight data bits. That is there is 3 select lines in 8:1 MUX.
Since in full adder there are 2 output, we need two 8:1 multiplexer. Output of 1st multiplexer is sum
of adder and output of 2nd multiplexer is carry generated of full adder.
 Fig. Full Adder using 8:1 MUX
As we can see in the above diagram there are 3 select lines A, B and C. there are 7 input I0 to I7.
The input is connected to 0 or 1 depending upon the value given in truth table.
The select lines of both multiplexer is connected to same input.

Q3] a) Obtain the minimal expression using Quine Mc-Cluskey method

F(A,B,C,D) = 𝜮m(1,2,3,5,6,10.11,13,14) + d(4,7)

(10)
Solution :-
Table 1
Group Minterm Binary Representation
A B C D
0 M1 0 0 0 1
M2 0 0 1 0
M4* 0 1 0 0
1 m3 0 0 1 1
m5 0 1 0 1
 m6 0 1 1 0
m10 1 0 1 0
2 m13 1 1 0 1
m14 1 1 1 0
m7* 0 1 1 1

Table 2

Group Minterm Binary Representation

A B C D
0 m1-m3 0 0 _ 1
m1-m5 0 _ 0 1
m2-m3 0 0 1 _
m2-m6 0 _ 1 0
m2-m10 _ 0 1 0
m4-m5* 0 1 0 _
m4-m6* 0 1 _ 0
1 m3-m7* 0 _ 1
M5-m13 _ 1 0 1
m5-m7* 0 1 _ 1
m6-m14 _ 1 1 0
m6-m7* 0 1 1 _
m10-m14 1 _ 1 0

Table 3
Group Minterm Binary Representation
A B C D
0 m1-m3-m5-m7 0 _ _ 1
M1-m5-m3-m7 0 _ _ 1
M1-m5-m10-m14 _ _ _ _
M2-m3-m6-m7 0 _ 1 _
M2-m6-m3-m7 0 _ 1 _
M2-m6-m10-m14 _ _ 1 0
M2-m10-m5=m13 _ _ _ _
M2-m10-m6-m14 _ _ 1 0
M4-m5-m6-m7 0 1 _ _
M4-m6-m5-m7 0 1 _ _

PI Decimal of PI 1 2 3 5 6 10 13 14 4 7

𝐴̅𝐷 M1 m3 m5 m7 ⊗ X X X

𝐴̅𝐶 M2 m3 m6 m7 X X X X
̅
𝐶𝐷 M2-m6-m10-m14 X X ⊗ ⊗

𝐴̅𝐵 M4-m5-m6=m7 X X ⊗ X
Y=𝐀 ̅̅̅̅ + 𝐀
̅ 𝐃 + 𝐂𝐃 ̅B

Q3] b) What is race around condition? How to overcome it?

(10)
Solution:-
The race around condition occurs in JK flipflop when both the inputs are high that is J=K=1 normally
in level triggered JK flipflop.

Fig.3.1 Race around condition

The above figure shows the race around condition in JK Flipflop when J=K=1.
This may lead to unpredictable output when clock disables and it is called as race around condition.
This can be avoided by
1. Using edge triggered JK flipflop
2. Using Master Slave JK flipflop
In edge triggered JK flipflop, race condition is avoided as the enable input of the clock remains active
only for a short time.

In master slave flipflop master and slave are inverted clock so that only one will be active at a time.
During the high of the clock, output will be toggled and will remain at the output of master but could
not be followed by slave as it is disabled. So, output of slave remains same as earlier and toggled
output remains at master. When clock is low master is deactivated and slave is enabled which only
follows the output of master. So at the end of one complete clock we just have one toggled output
and race around condition is avoided.
Q4] a) Design 3 bit asynchronous counter and draw the timing diagram.

(10)
Solution :-

A ripple counter is an asynchronous counter where only the first flip-flop is clocked by an external
clock. All subsequent (next occurring) flip-flops are clocked by the output of the preceding flip-flop.
In asynchronous counter, a clock pulse drives FF0. Output of FF0 drives FF1 which then drives the
FF2 flip flop. All J and K inputs are connected to Logic 1. Therefore, each flip flop will toggle with
negative transition at its clock input.

Fig. 4.1 bit Asynchronous counter

The 3 bit MOD-8 asynchronous counter consists of 3 JK flip flops. Overall propagation delay time is
the sum of individual delays. Initially all flip flops are reset to produce 0. The output conditions is Q2
Q1 Q0 = 000.
When the first clock pulse is applied, the FF0 changes state on its negative edge. Therefore, Q2Q1Q0
= 001. On the negative edge of second clock pulse flip flop FF0 toggles. Its output changes from 1 to
0. This being negative change, FF1 changes state. Therefore, Q2 Q1 Q0 = 010. Similarly, the output of
flipflop FF2 changes only when there is negative transition at its input when fourth clock pulse is
applied.

Fig. 4.2 Timing diagram

The output of the flip flops is a binary number equivalent to the number of clock pulses received.
The output conditions are as shown in the truth table.
 Counter Q2 Q1 Qo
State
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1

On the negative edge of eighth pulse, counter is reset. The counter acts as a frequency divider. FF0
divides clock frequency by 2, FF1 divides clock frequency by 4, FF2 divides clock frequency by 8. If n
flip flops are cascaded, we get 2n output conditions. The largest binary number counted by n
cascaded flip flops has a decimal equivalent of 2n −1. MOD-8 counter has count of the largest binary
number 111 which has decimal equivalent of 23−1=7.

Q4] b) Convert JK flipflop to SR flipflop and D flipflop.

(10)
Solution :-
JK to SR
a) Excitation Table
Input’s Present State Next State Flip Flop Input

S R Qn Qn+1 J K
0 0 0 0 0 X
0 0 1 1 X 0
0 1 0 0 X X
0 1 1 0 X 1
1 0 0 1 1 X
1 0 1 1 X 0
1 1 0 X X X
1 1 1 X X X

b) K- map simplification

For J
For K

c) Logic diagram

JK to D
a) Excitation Table

Input Present State Next State Flip Flop Input

D Qn Qn+1 J K
0 0 0 0 X
0 1 0 X 1
1 0 1 1 X
1 1 1 X 0

b) K-map simplification
For J

J=D
For K
c) Logic diagram

Q5] a) Compare TTL and CMOS with respect to different parameters.

(10)
Solution :-

PARAMETER TTL CMOS

Basic gate NAND INVERTER
Circuit Transistor- transistor Complementary MOS
Speed of More Less
operation
Propagation 4- 12 ns 50 ns
delay per rate
Power supply 5V 3 to 15V
voltage
Power PD = 10 Mw PD = 0.1 mW
dissipation
Wired collector With passive pull up With tristate output
capability
Fan-out 10 50
Noise Immunity Good Very good to excellent
Speed power 100 pJ 10.5 pJ
product
Available Very high High
functions
Compatibility With DTL No, but compatible with TTL for 5V
with other supply
families
Switching speed Faster than CMOS Less than TTL
Circuits It uses BJT’s It uses FET’s
Noise immunity Less than CMOS Better than TTL
Power It consumes lot more power than CMOS Consumes less power than TTL
consumption chips. chips.
Q5 b) Explain the features of VHDL and its modeling styles.

(10)
Solution:-
VHDL stands for very high-speed integrated circuit hardware description language. This language was
first introduced in 1981 for the department of Defense (DoD) under the VHSIC program.
Features of VHDL are as follows:
1) Designs are organized hierarchically.
2) Each design element has:
i) A well-defined interface.
ii) A precise behavioral specification using either algorithmic description or hardware
structural description.
3) Models concurrency, timing, and clocking:
i) Handles asynchronous and synchronous circuits
ii) Designs can be simulated.
4) Language is not case sensitive.
5) A formal language for specifying the behavior and structure digital circuit.

Modeling styles: Modeling Style means, that how we Design our Digital IC's in Electronics. With the
help of modeling style we describe the Design of our Electronics.
Normally we use Three type of Modeling Style in VHDL -
• Data Flow Modeling Style.
• Behavior Modeling Style.
• Structural Modeling Style.
Data Flow Modeling Style – Dataflow system describes a system in terms of how data flows through
the system. Data dependencies in the description match those in atypical hardware implementation.
A dataflow description directly implies a corresponding gate level implementation.
Dataflow descriptions consist of one or more concurrent signal assignment situation
Behavior Modeling Style – A behavioral description describes a system’s behavior or function in an
algorithmic fashion.
Behavioral style is the most abstract style. The description is abstract in the sense that it does not
directly imply a particular gate-level implementation.
Behavioral style consists of one or more process statements. Each process statement is a single
concurrent statement that itself contains one or more sequential statements.
Sequential statements are executed sequentially statements by a simulator, the same as the execution
of sequential statements in a conventional programming language.
Structural Modeling Style – In structural style of modelling, an entity is described as a set of
interconnected components.
The top-level design entity’s architecture describes the interconnection of lower level design entities.
Each lower level entity can, in turn, be described as an interconnection of design entities at the next-
lower level, and so on.
Structural style is most useful and efficient when a complex system is described as an interconnection
of moderately complex design entities. This approach allows each design entity to be independently
designed and verified before being used in the higher-level description.

Q6] a) Moore and Mealy machine.

(05)
Solution :-
Moore Machines: Moore machines are finite state machines with output value and
its output depends only on present state. It can be defined as (Q, q0, ∑, O, δ, λ) where:
• Q is finite set of states.
• q0 is the initial state.
• ∑ is the input alphabet.
• O is the output alphabet.
• δ is transition function which maps Q×∑ → Q.
• λ is the output function which maps Q → O.

Figure 1
In the moore machine shown in Figure 1, the output is represented with each input state separated
by /. The length of output for a moore machine is greater than input by 1.
• Input: 11
• Transition: δ (q0,11)=> δ(q2,1)=>q2
• Output: 000 (0 for q0, 0 for q2 and again 0 for q2)
Mealy Machines: Mealy machines are also finite state machines with output value and its output
depends on present state and current input symbol. It can be defined as (Q, q0, ∑, O, δ, λ’) where:
• Q is finite set of states.
• q0 is the initial state.
• ∑ is the input alphabet.
• O is the output alphabet.
• δ is transition function which maps Q×∑ → Q.
• ‘λ’ is the output function which maps Q×∑→ O.
 Figure 2
In the mealy machine shown in Figure 1, the output is represented with each input symbol for each
state separated by /. The length of output for a mealy machine is equal to the length of input.
• Input:11
• Transition: δ (q0,11)=> δ(q2,1)=>q2
• Output: 00 (q0 to q2 transition has Output 0 and q2 to q2 transition also has Output 0)

Q6] b) Sequence generator.

(05)
Solution :-
the sequence generators are nothing but a set of digital circuits which are designed to result in a
specific bit sequence at their output. There are several ways in which these circuits can be designed
including those which are based on multiplexers and flip-flops.

A circuit which generates a prescribed sequence of bits, in synchronization with a clock, is referred
to as a sequence generator such generator can be used as:

1] counters.

2] Random bit generators.

3] Prescribed period and sequence generators.

4] Code generator.
 The basic structure of a sequence generator is shown in diagram below:

The output Y of the next state decoder is function of QN-2, QN-1 …….. Q1, Q0. This system is similar
to a ring counter or twisted ring counter which are special case of sequence generator, the design of
the decoder will be clear.

Q6] c) Universal shift register.

(05)
Solution:-
A Universal shift register is a register which has both the right shift and left shift with parallel load
capabilities. Universal shift registers are used as memory elements in computers. A Unidirectional
shift register is capable of shifting in only one direction. A bidirectional shift register is capable of
shifting in both the directions. The Universal shift register is a combination design
of bidirectional shift register and a unidirectional shift register with parallel load provision.
n-bit universal shift register –
A n-bit universal shift register consists of n flip-flops and n 4×1 multiplexers. All the n multiplexers
share the same select lines(S1 and S0)to select the mode in which the shift register operates. The
select inputs select the suitable input for the flip-flops.
The working of the Universal shift register depends on the inputs given to the select lines.
The register operations performed for the various inputs of select lines are as follows:

S1 S0 REGISTER OPERATION

0 0 No changes
0 1 Shift Right

1 0 Shift Left
 1 1 Parallel Load

Q6] d) Priority Encoder.

(05)
Solution :-
The priority encoders output corresponds to the currently active input which has the highest priority.
So, when an input with a higher priority is present, all other inputs with a lower priority will be ignored.

A priority encoder provides n bits of binary coded output representing the position of the highest
order active input of 2ninputs. If two or more inputs are high at the same time, the input having the
highest priority will take precedence.

Fig.6.d Priority Encoder

A 4-to-2 priority encoder takes 4 input bits and produces 2 output bits as shown in figure 6.4. In this
truth table, for all the non-explicitly defined input combinations (i.e. inputs containing 2, 3, or 4 high
bits) the lower priority bits are shown as don't cares (X). Similarly, when the inputs are 0000, the
outputs are not valid and therefore they are XX.

Truth table for 4 bit input to priority encoder:

I3 I2 I1 I0 Y1 Y0

0 0 0 0 X X

0 0 0 1 0 0

0 0 1 X 0 1

0 1 X X 1 0

0 1 X X 1 0
 1 X X X 1 1

From this truth table, we use the Karnaugh Map to minimize the logic to the following Boolean
expressions:

Y1 = I2 + I3

Y0 = I3 + I2 X I1

Q6] e) Carry look ahead adder.

(05)

Solution :-
In ripple carry adders, for each adder block, the two bits that are to be added are available instantly.
However, each adder block waits for the carry to arrive from its previous block. So, it is not possible
to generate the sum and carry of any block until the input carry is known. This disadvantage is
overcomed in carry look ahead adder.

Carry Look-ahead Adder:

A carry look-ahead adder reduces the propagation delay by introducing more complex hardware. In
this design, the ripple carry design is suitably transformed such that the carry logic over fixed groups
of bits of the adder is reduced to two-level logic.

Fig 6.e Carry look ahead adder

We define two variables as ‘carry generate’ Gi and ‘carry propagate’ Pi then,

Pi = Ai ⊕ Bi

Gi = Ai x Bi
 DIGITAL LOGIC DESIGN AND ANALYSIS (DLDA)

NOVEMBER--2018

Q1 (a) Convert decimal number 576.24 into binary, base-9, octal, hexadecimal
system. (04)

Solution:
(i)Conversion to Binary

2 576

2 288 0

2 144 0

2 72 0

2 36 0

2 18 0

2 9 0

2 4 1

2 2 0

2 1 0

0 1
The binary equivalent of 576 is 1001000000.
0.24 x 2 = 0.48 ~ 0
0.48 x 2 = 0.96 ~ 0
0.96 x 2 = 1.92 ~ 1-
0.92 x 2 = 1.84 ~ 1
0.84 x 2 = 1.68 ~ 1
(576.24) = (1001000000.00111)
10 2

(ii)Conversion to Base-9

9 576

9 64 0

9 7 1

0 7

1
The base-9 equivalent of 576 is (710).
0.24 x 9 = 2.16 ~ 2
0.16 x 9 = 1.44 ~ 1
0.44 x 9 = 3.96 ~ 3
0.96 x 9 = 8.64 ~ 8
(576.24) =(710.2138)
10 9

(iii)Conversion to Octal

8 576

8 72 0

8 9 0

8 1 1

0 1
The octal equivalent of 576 is (1100).
0.24 x 8 = 1.92 ~ 1
0.92 x 8 = 7.36 ~ 7
0.36 x 8 = 2.88 ~ 2
0.88 x 8 = 7.04 ~ 7
(576.24) = (1100.1727)
10 8

(iv)Conversion to Hexadecimal

16 576

16 36 0

16 2 4

0 2
The Hexadecimal equivalent of 576 is (240).
0.24 x 16 = 3.84 ~ 3
0.84 x 16 = 13.44 ~ D
0.44 x 16 = 7.04 ~ 7
0.04 x 16 = 0.64 ~ 0
(576.24) = (240.3D70)
10 16

---------------------------------------------------------------------------------------------------------------------------

(b) Construct hamming code for 1010 using odd parity. (04)

Solution:
The given code is 1010 i.e. 4-bits.
∴ 3 Parity bits are required.

2
1 2 3 4 5 6 7

P1 P2 1 P3 0 1 0

Using Odd - parity,

P1 = (3, 5, 7) = (1, 0, 0) = 0
P2 = (3, 6, 7) = (1, 1, 0) = 1
P3 = (5, 6, 7) = (0, 1, 0) = 0
∴ Hamming code is as follows:

1 2 3 4 5 6 7

0 1 1 0 0 1 0

The Hamming code for the given code is 1010 is 0110010.

---------------------------------------------------------------------------------------------------------------------------

(c)Convert (-89) to its equivalent sign magnitude, 1’s Complement and 2’s
10

Complement Form. (04)

Solution:
The sign magnitude equivalent of (-89) is as follows: 10

Sign bit
1 1 0 1 1 0 0 1
MSB magnitude

(-89) = (11011001)
10 2

The binary equivalent of (-89) is (11011001) . 10 2

So, 1`s complement of (-89) is (00100110) 10 2

2’s complement of (-89) is : 10

0 0 1 0 0 1 1 0
+ 1
___________________________________________________
0 0 1 0 0 1 1 1

So, 2’s complement of (-89) is (00100111) . 10 2

--------------------------------------------------------------------------------------------------------------------------

(d)Perform (BC5) - (A2B) without converting to any other base.

H H (04)

Solution:
B C 5B 1

- A 2 B
__________________________________

3
 1 9 A
Here, as 5 < B, so we borrow 16 from the previous value as the given values are in
Hexadecimal format. 16 is then added to 5 ,thus it becomes 21 and 21 is subtracted from B.
So, we get answer as A.
Since, we have borrowed from the previous value i.e C ,the value of C decreases by 1.So, it
becomes B.

Thus, (BC5) - (A2B) = (19A)

H H H

---------------------------------------------------------------------------------------------------------------------------

(e) Prove De Morgan's theorem. (04)

Solution:
The two theorems suggested by De-Morgan and which are extremely useful in Boolean
algebra are stated as follows:
___ __ __
Theorem 1: AB = A + B
NAND = Bubbled OR:
This theorem states that the complement of a product is equal to the sum of individual
complements.

This theorem can be verified using truth table as follows:

___ __ __ __ __
A B AB A B A + B

0 0 1 1 1 1

0 1 1 1 0 1

1 0 1 0 1 1

1 1 0 0 0 0

4
 ___ __ __
Thus we can see that AB = A + B .

Theorem 2 : A + B = A ・ B
NOR = Bubbled AND:
This theorem states that the complement of a sum is equal to the product of individual
complements.

This theorem can be verified using truth table as follows:

______ __ __ __ __
A B A+B A B A ・ B

0 0 1 1 1 1

0 1 0 1 0 0

1 0 0 0 1 0

1 1 0 0 0 0

_____ __ __
Thus we can say that A + B = A ・ B .

5
 _ _ _
Q.2(a)Given the logic expression A + B C + A B D + A B C D (10)
1. Express it in standard SOP form.
2. Draw K-map and simplify
3. Draw logic diagram using NOR gates only.

Solution:

The given expression is :

_ _ _
A+B C+ABD+ABCD
(i)Expressing the given expression in standard SOP form:
_ _ _
A+B C+ABD+ABCD
_ _ _ _ _ _ _ _ _
∴ A (B + B) (C + C) (D + D ) + B C (A + A) (D + D) + A B D (C + C) + A B C D
_ _ _ _ _ _ _ _ _ _ _ _ _ _
∴ (A B + A B)(C D + C D + C D + C D ) + B C (A D + A D + A D + A D ) + A B C D + A B C D
+ABCD
_ _ _ _ _ _ _ _ _ _ __
∴ABCD+ABCD+ABCD+ABCD+ABCD+ABCD+ABCD+ABCD+

_ _ _ __ _ _ _ _ __ _ _ _ _
+A B C D + A B C D + A B C D + A B C D + A B C D + A B C D + A B C D

The standard SOP form of the given expression is :

_ ___ _ __ __ _ __ _ _ _ _ _ _
∴ABCD+ABCD+ABCD+ABCD+ABCD+ABCD+ABCD+ABCD+
_
ABCD+ABCD

(ii)Using K-map to simplify the given expression :

From standard SOP form we get,

F(A, B, C, D) = Σ m (0, 1, 8, 9, 10, 11, 12, 13, 14, 15)

6
Q.2(b)Reduce using Quine McCluskey method and realize the operation using only
NAND gates. (10)
F(A, B, C, D)= π M(0, 2, 3, 6, 7, 8, 9, 12, 13)

Solution:

F(A, B, C, D)= π M(0, 2, 3, 6, 7, 8, 9, 12, 13)

F(A, B, C, D)= Σm (1, 4, 5, 10, 11, 14, 15)

Step 1: Grouping the minterms according to the number of 1’s

7
Group Minterm Binary representation
A B C D

1 1 0 0 0 1

4 0 1 0 0

2 5 0 1 0 1

10 1 0 1 0

3 11 1 0 1 1

14 1 1 1 0

4 15 1 1 1 1

Step 2: Grouping the minterms that form pairs

Group Minterm Binary representation

A B C D

1 1-5 0 - 0 1

4-5 0 1 0 -

2 10-11 1 0 1 -

10-14 1 - 1 0

3 11-15 1 - 1 1

14-15 1 1 1 -

Step 3: Grouping the minterms to form quad

Group Minterm Binary representation

A B C D

1 10-11-14- 1 - 1 -
15

10-14-11- 1 - 1 -
15

8
Step 4: Collecting all Prime Implicants

_ _ _ _
From Step 2, the prime implicants are A C D and A B C .
From Step 3, we get the prime implicants as A C.
_ _ _ _
F(A, B, C, D)= A C D + A B C + A C

Step 5: Preparing the Prime Implicants Table

Prime Implicant Decimal numbers Given Minterms

(PI) (minterms)

1 4 5 10 11 14 15

_ _
ACD 1,5 X X

_ _
ABC 4,5 X X

AC 10,11,14,15 X X
X X
_ _ _ _
∴ F(A, B, C, D)= A C D + A B C + A C

9
Q.3(a)Design a 4-bit binary to gray code converter. (10)

Solution:
The truth table showing binary inputs being converted to gray outputs is as follows:

The K-maps for each gray output is as shown below.

K-map for g :
0 K-map for g :
1

__ __ __ __
∴ g = b1 b0 + b1 b0
0 ∴ g = b2 b3 + b2 b3
1

10
K-map for g : 2 K-map for g : 3

__ __
∴ g = b1 b2 + b1 b2
2 ∴ g = b3
3

The logic diagram of 4-bit Binary to Gray code converter is as shown below.

---------------------------------------------------------------------------------------------------------------------------

Q.3(b)Design a 4 bit BCD adder using IC 7483 and necessary gates. (10)

Solution:
1. A BCD adder adds two BCD digits and produces a BCD digit. BCD number cannot be
greater than 9.
2. The two given BCD numbers are to be added using the rules of binary addition.
3. If sum is less than or equal to 9 and carry=0 then correction is necessary. The sum is
correct and in the true BCD form.
4. But if sum is invalid BCD or carry=1, then the result is wrong and needs correction.
5. The wrong result can be corrected by adding six (0110) to it.
6. The 4 bit binary adder IC 7483 can be used to perform addition of BCD numbers.

11
 7. In this, if the four-bit sum output is not a valid digit, or if a carry C3 is generated then
decimal 6 (0110 binary) is to be added to the sum to get the correct result.
8. Fig1 shows a 1-digit BCD adders can be cascaded to add numbers several digits long
by connecting the carry-out of a stage to the carry-in of the next stage.
9. The output of combinational circuit should be 1 if the sum produced by adder 1 is
greater than 9 i.e. 1001. The truth table is as follows:

I/P O/P

S3 S2 S1 S0 Y

0 0 0 0 0

0 0 0 1 0

0 0 1 0 0

0 0 1 1 0

0 1 0 0 0

0 1 0 1 0

0 1 1 0 0

0 1 1 1 0

1 0 0 0 0

1 0 0 1 0

1 0 1 0 1

1 0 1 1 1

1 1 0 0 1

1 1 0 1 1

1 1 1 0 1

1 1 1 1 1
Truth table for BCD numbers
Y=1 since the sum obtained is an invalid BCD number.

12
 The BCD adder is shown below. The output of the combinational circuit should be 1 if
Cout of adder-1 is high. Therefore Y is 0 with Cout of adder 1.
 The output of combinational circuit is connected to B B inputs of adder-2 and B = B +
1 2 3 1

0 as they are connected to ground permanently. This makes B B B B = 0110 if Y' = 1. 3 2 1 0

 The sum outputs of adder-1 are applied to A A A A of adder-2. The output of

3 2 1 0

combinational circuit is to be used as final output carry and the carry output of adder-
2 is to be ignored.

BLOCK DIAGRAM OF BCD ADDER

Operation of BCD Adder is as follows:

Case1: Sum ≤ 9 and carry = 0
 The output of combinational circuit Y’ = 0. Hence B B B B = 0 0 0 0 for adder-2.
3 2 1 0

13
  Hence output of adder-2 is same as that of adder-2
Case 2: Sum >9 and carry = 0
 If S3S2S1S0 of adder -1 is greater than 9, then output Y’ of combinational circuits
becomes 1.
 Therefore B B B B = 0 1 1 0 (of adder-2).
3 2 1 0

 Hence six (0 1 1 0) will be added to the sum output of adder-1.

 We get the corrected BCD result at the output of adder-2.

Case 3: Sum ≤ 9 but carry = 1

 As carry output of addere-1 is high, Y’ = 1.
 Therefore B B B B = 0 1 1 0 (of adder-2).
3 2 1 0

 Hence six (0 1 1 0) will be added to the sum output of adder-1.

 We get the corrected BCD result at the output of adder-2. Thus the Four bit BCD
addition can be carried out using the binary adder.

14
Q.4(a)Implement the following logic function using all 4 : 1 multiplexers with the select
inputs as ‘B’, ‘C’, ‘D’, ‘E’ only.
F(A, B, C, D, E) = Σ(0,1,2,3,6,8,9,10,13,15,17,20,24,30) (10)

Solution:

D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 8 D 9 D 10 D 11 D 12 D 13 D 14 D 15

_
A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

A 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

_ _ _ _ _ _ _ _
A 1 A A A 0 A 0 1 A A 0 0 A A A

15
Q.4(b)Convert a SR flip flop to JK flip flop. (10)

Solution:

16
Q.5(a)Design a mod-6 synchronous counter using T flip flop. (10)

Solution:
(i)State Diagram :

(ii)State Table :

Present State Next State Flip-flop inputs

Q C Q B Q A Q C+1 Q B+1 Q A+1 T c T B T A

0 0 0 0 0 1 0 0 1

0 0 1 0 1 0 0 1 1

0 1 0 0 1 1 0 0 1

0 1 1 1 0 0 1 1 1

1 0 0 1 0 1 0 1 1

1 0 1 0 0 0 1 0 1

1 1 0 0 0 0 1 1 0

1 1 1 0 0 0 1 1 1

(iii)K map and simplification :

17
 T =QQ +QQ +QQ
C A B B C A C

__ __
TB = QAQC + QBQC + QCQA

__ __
T =Q +Q +Q
A C B A

(iv)Logic Diagram:

18
---------------------------------------------------------------------------------------------------------------------------

Q.5(b)Explain the operation of a 4-bit universal shift register. (10)

Solution:
A shift register which can shift the data in only one direction is called as a unidirectional shift
register. A shift register which can shift the data in both directions is called as bi-directional
shift register. Similarly, a shift register which can shift data in both directions i.e shift left or
right as well as load it parallelly, is called as a universal shift register.
The figure below shows the logic diagram of a 4-bit universal shift register.

This shift register is capable of performing the following operations:

1.Parallel loading (parallel input parallel output)
2.Left shifting

19
3.Right shifting
The mode control input is connected to Logic 1 for parallel loading operation whereas
it is connected to 0 for serial shifting.When mode pin is connected to ground, the universal
shift register acts as a bi-directional register.For serial left operation, the input is applied to
serial input which goes into AND gate-1 of the above figure.For serial right operation, the
serial input is applied to D input (input of AND gate-8).The well known example of universal
shift register is in the form of IC 7495.
Universal Shift Register IC 7495:
It is a 4 bit shift register with serial and parallel synchronous operating modes.Because of its
capability to operate in all possible modes, it is called a universal shift register.
Some features of this chip are:
1.Synchronous shift left capacity.
2.Synchronous parallel loading is possible.
3.It has separate clock inputs,one for shift operation and the other for load operation.
4.The cascading of two or more 7495 ICs for more than 4-bits is possible.

The figure below shows the pin configuration of IC 7495

A,B,C,D are the inputs to four internal flip flops with A acting as LSB and D as MSB. QA
through QD are the corresponding outputs.
IC 7495 is capable of performing the following operations:
1.Parallel loading (parallel input parallel output)
2.Left shifting
3.Right shifting

20
 INTERNAL LOGIC DIAGRAM OF IC 7495
1.Parallel loading:
The connection diagram for IC 7495 in parallel input parallel output mode is as shown in the
figure below.The mode control (M) is connected to logic 1. This will enable the AND gates 2,
4, 6, 8 as shown in internal logic diagram. The AND gates 1, 3, 5, 7 are disabled.This allows
data transfer from the inputs A, B, C, D to the flip flops and disable
s the serial transfer of data. The 4-bit binary number which is to be loaded parallely is applied
to the A, B, C, D inputs.
The clock applied at clock-2 input only will be paused through the flip flops because with M=1
and AND gate-10 is enabled and gate-9 is disabled. As soon as a falling edge of clock is
applied, all flip-flops will change their status simultaneously and binary number applied to
ABCD inputs will be loaded into the shift register. The unused inputs such as serial input and
clock-1 can be left open or connected to ground because they are the don’t care options for
this mode.

21
2.Serial Shift Right Operation:
The connection for serial shift right mode is as shown in the figure below. Make mode control
= 0, therefore AND gates 1, 3, 5, 7 will be enabled and AND gate 2, 4, 6, 8 will get
disabled.Hence, the inputs ABCD become don’t care.

3.Serial Shift Left Operation:

The connection diagram of 7495 for the shift left operation is as shown in the figure. Q is
D

connected to C, Q to B and Q to A and the serial data is applied at input D.Mode control is
C B

connected to 1. Hence, the AND gates 2, 4, 6, 8 are enabled whereas 1, 3, 5, 7 are disabled.
This will make the serial input (pin no. 1) a don’t care input. The serial data is applied to D
which will be routed through the enabled AND gates 2, 4, 6, 8 to facilitate the right shifting
operation. As M = 1, AND gate - 10 is enabled and gate - 9 is disabled. So clock - 1 becomes
a don’t care input. Apply clock pulses to CLK - 2(shift left).Each high to low transition of clock
will transfer data from D to Q , Q to Q , Q to Q ,Q to Q .Thus the shift left operation is
D D C C B B A.

performed.

22
Q.6 Write Short notes on (any 2) (20)
(a)VHDL

Solution:
The long form of VHDL is Very High Speed Integrated Circuit (VHSIC) hardware description
language.
VHDL is used to form a digital system at many levels of ideas ranging from algorithmic level
to the gate level.
This language defines the syntax as well as simulation semantics for each language. It is a
strong typed language which contains too many words to write.
VHDL is difficult to understand because it provides wide ranging of modelling capabilities but
without learning the more complex features it is possible to incorporate a core subset of
language which is simple and easy to understand.
Some Features of VHDL are:
1. Strongly typed language: Only LHS and RHS operators of the same type are allowed
in VHDL.
2. Support hierarchies: Using VHDL, hierarchy can be represented. For example, full
adder.In this case it is composed of half adder and OR gate.
3. VHDL supports for test and simulation of programs.
4. Concurrency: VHDL is a concurrent language which executes statements
simultaneously in parallel.
5. VHDL supports different types of data modelling
(i)Structural
(ii)Data flow
(iii)Behavioural
(iv)Mixed
6. Supports sequential statement: VHDL can execute only one statement at a time in
sequence only.
7. VHDL supports synchronous and asynchronous models.
8. VHDL can be used as a communication model between different CAD and CAE
models.
Structure of VHDL module:
Design units of VHDL code are independent components which are separately combined and
stored in the library.
VHDL program is composed of the following design units:
1. Package (optional)
2. Entity
3. Architecture
4. Configuration (optional)
The diagram below shows the design units of VHDL.

23
Advantages of VHDL
1. VHDL allows designers to quickly develop designs requiring tens of thousands of
logic gates.
2. VHDL supports multiple level of hierarchy and modular design methods.
3. VHDL allows user to pick any synthesis tool.
4. VHDL is multipurpose i.e. once calculation block is created then it can be used in
many other projects.
5. For describing complex logic, VHDL provides powerful high level constructs.

Disadvantages of VHDL
VHDL is not a low level language i.e. gate level program. It is not suitable for
verification of basic objects like gates. Because in VHDL these objects are readily available.
Applications of VHDL
1. It is used in electronic design automation to describe mixed signal system such as
FPGA (Field Programmable Gate Arrays) and Integrated circuits.
2. VHDL can be used as a general purpose parallel programming language.
3. VHDL can also be used for design and simulation purposes.

(b)TTL and CMOS logic families:

TTL family:
The long form of TTL is Transistor Transistor Logic. It is a logic family
consisting completely of transistors. It employs transistors with multiple emitters. The digital
ICs in the TTL family use only transistors as their basic building block. TTL ICs were first
developed in 1965 and they were known as “Standard TTL”. This version of TTL is not
practically used now due to availability of advanced versions. Some characteristics of TTL
family are as follows:
1. TTL is made up of BJTs (Bipolar Junction Transistor).
2. It has a high level noise margin of 0.4 V i.e. V = 0.4 V.
NH

3. It has a low level noise margin of 0.4 V i.e. V = 0.4 V.

NL

4. TTL family has less noise immunity than CMOS family.

5. The propagation delay of a standard TTL is 10nS.
6. It has a comparatively faster switching speed as compared to CMOS family.
7. It has a power dissipation of 10mW per gate i.e. P = 10mW.
D

24
 8. TTL family has a speed power product of 100 pJ.
9. P of TTL does not depend on frequency.
D

10. TTL has a Fan Out capacity of 10.

11. In TTL, inputs can remain floating. The floating inputs are treated as logic 1s.
12. Since BJTs require more space, TTLs have a comparatively low component density.
13. Transistors are operated in saturated or cut off regions.
14. Power supply voltage of TTL is fixed which is equal to 5V.

CMOS family:
Complementary Metal Oxide Semiconductor (CMOS) is a technology for constructing
integrated circuits, employing MOSFET transistors. CMOS technology is used in
microprocessors, microcontrollers, static RAM, and other digital logic circuits. CMOS
technology is also used for several analog circuits such as image sensors (CMOS sensor),
data converters, and highly integrated transceivers for many types of communication. Some
characteristics of CMOS logic family are as follows:
1. CMOS devices are made up of N-channel MOSFET and P-channel MOSFET.
2. It has a high level noise margin of 1.45 V i.e. V = 1.45 V.
NH

3. It has a low level noise margin of 1.45 V i.e. V = 1.45 V.

NL

4. CMOS family has better noise immunity than TTL family.

5. The propagation delay of a metal gate CMOS is 105nS.
6. It has a comparatively slower switching speed as compared to TTL family.
7. It has a power dissipation of 0.1 mW per gate i.e. P = 0.1 mW. Hence, it is used for
D

battery backup applications.

8. CMOS family has a speed power product of 10.5 pJ.
9. P of CMOS depends on frequency.
D

10. CMOS has a Fan Out capacity of 50.

11. The unused inputs should be returned to GND or V .They should never be left
DD

floating.
12. CMOS usually have a high component density than TTL as MOSFETs need less
space while fabricating an IC.
13. MOSFETs are operated as switches i.e. in the ohmic region or cut off regions.
14. Power supply voltage of CMOS is flexible ranging from 3V to 15V.

(c)4-bit magnitude comparator

Solution:
A 4-bit comparator is used to compare two 4-bit words A (A - A ) and B (B - B ). IC 7485 is a
3 0 3 0

four bit comparator in the integrated circuit form. It is possible to cascade more than one IC
7485 to compare words of almost any size.The figure below shows the pin configuration and
the logic symbol of IC 7485.

25
The Pin names and their functions are as shown in the table below:

Pin Pin number Function

name

A to A
0 3 10,12,13,15 Binary input (opearand 1) Active high

B to B
0 3 9,11,14,1 Binary input (opearand 2) Active high

I (A < B) 2 These lines are used for cascading a number of IC 7485 outputs of
I (A = B) 3 the previous stage are fed as inputs to this stage.
I (A > B) 4

A<B 7 These are the outputs. When ICs 7485 are cascaded, these outputs
A=B 6 are applied to cascading inputs of the next stage.
A>B 5

26
Comparing inputs Cascading inputs Outputs

A3,B3 A2,B2 A1,B1 A0,B0 A>B A<B A=B A>B A<B A=B

A3>B3 X X X X X X H L L

A3<B3 X X X X X X L H L

A3=B3 A2>B2 X X X X X H L L

A3=B3 A2<B2 X X X X X L H L

A3=B3 A2=B2 A1>B1 X X X X H L L

A3=B3 A2=B2 A1<B1 X X X X L H L

A3=B3 A2=B2 A1=B1 A0>B0 X X X H L L

A3=B3 A2=B2 A1=B1 A0<B0 X X X L H L

A3=B3 A2=B2 A1=B1 A0=B0 H L L H L L

A3=B3 A2=B2 A1=B1 A0=B0 L H L L H L

A3=B3 A2=B2 A1=B1 A0=B0 L L H L L H

A3=B3 A2=B2 A1=B1 A0=B0 X X H L L H

A3=B3 A2=B2 A1=B1 A0=B0 H H L L L L

A3=B3 A2=B2 A1=B1 A0=B0 L L L H H L

27
 DLDA
(CBCGS MAY 2019)

Q1] a) Convert (451.43)10 into octal, binary and hexadecimal and base 7.

(04)

Solution :-
Decimal to octal

451 = 703

0.43 x 8 = 3.44 3
0.44 x 8 = 3.52 3
0.52 x 8 = 4.16 4
0.43 = (0.334)
(451.43)10 = (703.334)8

Decimal to binary

451 = 111000011
0.43 x 2 = 0.86 0
0.86 x 2 = 1.72 1
0.43 = 0.01
(451.43)10 = (111000011.01)2

Decimal to hexadecimal

451 = (1 12 3)
0.43 x 16 = 6.88 6
0.88 x 16 = 14.08 14
0.08 x 16 = 1.28 1
0.43 = (0.6 14 1)
(451.43)10 = (1 12 3.6 14 1)16

Decimal to base 7

451 = (1 2 1 3)
0.43 x 7 = 3.01 3
0.01 x 7 = 0.07 0
0.43 = (0.30)
(451.43)10 = (1213.30)7

Q1] b) Subtract using 1’s and 2’s complement method (73)10 – (49)10.
(04)
Solution :-
1’s complement method
Binary representation of 49 is 0110001
1’s complement of 49 is 1001110
 1001110

+ 1001001

10010111

+ 1

10011000

Therefore (73)10 - (49)10 = 11000 = (24)10.

2’s complement method.
Binary representation of 49 is 0110001
1’s complement of 49 is 1001110
2’s complement of 49 is 1’s complement + 1

1001110

+ 1

1001111

Now adding 73 and 2’s complement of 7

1001001

+ 1001111

1 00 11000
Discard carry 1
Therefore (73)10 - (49)10 = 11000 = (24)10.

Q1] c) Perform (52)10 - (68)10 in BCD using 9’s complement.

(04)
Solution :-

First subtract 68 from 99 that is find 9’s complement of 68

99

- 68

31

We then add 52 and 9’s complement of 68

52
 + 31

83
(52)10 - (68)10 = (83)

Q1] d) State De Morgan’s theorem. Prove OR-AND configuration is equivalent to

NOR-NOR configuration.
(04)
Solution :-
Theorem 1:

Statement: The complement of the product of two or more variables is equal to the sum of the
components of the variables.
Logical expression: ̅̅̅̅̅ ̅+B
A. B = A ̅
NAND is equal to BUBBLED OR.

A B A.B ̅̅̅̅̅
A. B ̅
A ̅
B ̅+B
A ̅

0 0 0 1 1 1 1

0 1 0 1 1 0 1

1 0 0 1 0 1 1

1 1 1 0 0 0 0

From the above truth table we can see that ̅̅̅̅̅ ̅+B
A. B = A ̅ Hence proved.

Theorem 2 :-

Statement: The complement of the sum of two or more variables is equal to the product of the
complement of the variables
Logical expression: ̅̅̅̅̅̅̅̅
𝐴 + 𝐵 = 𝐴̅. 𝐵̅
NOR is equal to BUBBLED AND.

A B A+B ̅̅̅̅̅̅̅
A+B ̅
A ̅
B ̅. B
A ̅

0 0 0 1 1 1 1

0 1 1 0 1 0 0

1 0 1 0 0 1 0

1 1 1 0 0 0 0

From the above truth table we can see that ̅̅̅̅̅̅̅̅

𝐴 + 𝐵 = 𝐴̅. 𝐵̅ Hence proved.
Q1] e) Encode the data bits 111010001 using Hamming code.

(04)

Solution :-
For given data of 9 bit, hamming code is given as
D13 D12 D11 D10 D9 P8 D7 D6 D5 P4 D3 P2 P1

Given 9 bit is 111010001 therefore it can be written as

1 1 1 0 1 P8 0 0 0 P4 1 P2 P1

P1: For P1 consider P1, D3, D5, D7, D9, D11, D13
D3, D5, D7, D9, D11, D13 = 100111
For even parity set P1 = 0
P2: For P2 consider P2, D3, D6, D7, D10, D11
D3, D6, D7, D10, D11 = 10001
For even parity set P2 = 0
P4: For P1 consider P4, D5, D6, D7, D12, D13
D5, D6, D7 = 00011
For even parity set P4 = 0
P8: For P1 consider P8, D9, D10, D11, D12, D13
D9, D10, D11, D12, D13= 10111
For even parity set P4 = 0
1 1 1 0 1 0 0 0 0 0 1 0 0

Therefore, hamming code for 111010001 is given as 1110100000100.

Q1] f) Explain SOP and POS and solve the following using K-Map
F(A,B,C,D)=πM(1,3,5,6,7,10,11)+d(2,4)

(04)

Solution :-
The sum-of-products (SOP) form is a method (or form) of simplifying the Boolean expressions of
logic gates. In this SOP form of Boolean function representation, the variables are operated by AND
(product) to form a product term and all these product terms are ORed (summed or added) together
to get the final function.

The product of sums form is a method (or form) of simplifying the Boolean expressions of logic
gates. In this POS form, all the variables are ORed, i.e. written as sums to form sum terms.

F(A,B,C,D)=πM(1,3,5,6,7,10,11)+d(2,4)
 Fig.1.1 K map representation.

Equation form is
̅ + B) (A
Y = (A ̅ +D) (C+B
̅)

Q1] g) Explain lockout condition. How can it be avoided?

(04)

Solution :-
In counters, Lockout condition is that condition wherein a counter gets onto a forbidden state and
rather than coming out of it to another acceptable state or initial state, the counter switches to
another forbidden state and gets stuck up in the cycle of forbidden states only.
If by chance, the counter happens to find itself in any one of the unused states, its next state would
not be known. It may just be possible that the counter might go from one unused state to another
and never arrive at a used state. A counter whose unused states have this feature is said to suffer
from LOCK OUT.

To avoid lock out and make sure that at the starting point the counter is in its initial state or it comes
to its initial state within few clock cycles, external logic circuitry is to be provided and so we design
the counter assuming the next state to be the initial state, from each unused states.
In order to prevent lock out condition, use PRESET option and clear option in a flip flop and hence
the registers will be cleared and we can go for the smooth functioning of counter circuits.

Q2] a) Reduce equation using Quine McCluskey method and realize circuit using (10)
basic gates.
-F(A,B,C,D) = Σm (1,5,6,12,13,14) + d(2,4)

(10)
Solution :-
Table 1
Group Minterm Binary Representation
A B C D
0 m1 0 0 0 1
m2* 0 0 1 0
m4* 0 1 0 0
1 m5 0 1 0 1
m6 0 1 0 1
m12 0 1 1 0
2 m13 1 1 0 1
m14 1 1 1 0

Table 2

Group Minterm Binary Representation

A B C D
0 m1-m5 0 _ 0 1
m2-m6* 0 _ 1 0
m4-m5* 0 1 0 _
m4-m12* _ 1 0 0
1 M5-m13 _ 1 0 1
M6-m14 _ 1 1 0
M12-m13 1 1 0 _
M12-m14 1 1 _ 0

Table 3
Group Minterm Binary Representation
A B C D
0 M4-m5-m12-m13* _ 1 0 _
M4-m12-m5-m13* _ 1 0 _
M4-m12-m6-m14* _ 1 _ 0

PI Decimal of PI 1 5 6 12 13 14 2 4

BC̅ M4 m5 m12 m13 ⊗ X ⊗ X

̅
BD M4 m6 m12 m14 ⊗ X ⊗ X

Y = B𝐂̅ + 𝐁
̅D

Q2] b) Design 4-bit BCD subtractor using IC 7483.

(10)
Solution :-
4 Bit BCD subtractor

IC 7483 performs the addition of two 4-bit BCD numbers A3 A2 A1 A0 and B3 B2 B1 B0 and carry input
to give the output S3 S2 S1 S0 and carry out. So for adding the two numbers A3 A2 A1 A0 and B3 B2
B1 B0, the two numbers are given to input terminals 1,3,8,10 and 16,4,7,11 of the IC 7483 and carry
in the terminal 13 is set to zero. To subtract two numbers by two’s complement method, we are adding
the 2’s complement of the second number to each of the four bits of the first numbers. The final carry
is neglected and the difference is taken from S3 S2 S1 S0.
In the circuit we set mode control such that when the mode control is zero, addition is performed and
subtraction is performed when the mode control is one. We use XOR gates to feed the input so that
when control is one, the complement of each of the four bits are fed and mode control is zero, the
input as such is fed.
In 1’s complement subtraction, the complement of the subtraction is taken and added with the other
number. The final carry is then added to LSB of the result. In case there is no carry, the complement
of the result is taken and this will be a negative number. This indicates that, subtraction is performed
from a smaller number.

Fig 2 - 4 bit BCD subtractor using IC 7483

Q3] a) Implement the following using only one 8:1 Mux.

F(A,B,C,D) = Σm (0,2,4,6,8,10,12,14)

(05)
Solution :-
Step 1: Draw a table

If both the values in the column are included than it is connected to 1. If both the values of the column
are not included than it is connected to input 0. So, for the given question the mux drawn is given
below.

Step 2: MUX implementation

Fig. 3a 8:1 MUX

Q3] b) Design a Full Subtractor using only NAND gates.

(05)
Solution:-
Truth table of full subtractor

X Y Z D B

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0
 1 0 1 0 0

1 1 0 0 0

1 1 1 1 1

D=X ⊕Y⊕Z

B=̅ ̅̅
XY +X Y Z + XYZ

Representation of full subtractor using NAND gates.

Q3] c) Design a logic circuit to convert 4-bit gray code to its corresponding BCD code.

(10)
Solution:-
Step1: Write the truth table of Gray code and its equivalent binary code is as shown in table:
Step2: Write K – map for each binary output and get simplified expression The K – map for various
binary outputs and the corresponding simplified expression are given below:
For output B3

Fig.3.1 K map for B3

Simplified expression B3=G3
For output B2

Fig 3.2 K map for B2

̅̅̅̅) + G(2)(G3
B2 = G(3)( G2 ̅̅̅̅)
=G3 ⨁ G2
 Fig 3.3 K map for B1
B1 = G1 ̅̅̅̅̅̅̅̅
G2 G3 + G2 ̅̅̅̅̅̅̅̅
G3 G2 + G3 G2 G1 + G3 ̅̅̅̅̅̅̅̅
G1 G2
̅̅̅̅
= G1 (G2⊕G3) + G1 (G2⊕G3)
= ̅̅̅̅
G1𝑋 + ̅̅̅̅
G1𝑋 Where X = G2 ⊕ G3
= G1 ⊕ G2 ⊕ G3
For output B0

Fig 3.4 K map for B0

B0 = G0 ̅̅̅̅̅̅̅̅̅̅̅̅
G1 G2 G3 + G2 ̅̅̅̅̅̅̅̅̅̅̅̅
G3 G1 G0 + G1 ̅̅̅̅̅̅̅̅̅̅̅̅
G3 G2 G0 + G1 ̅̅̅̅̅̅̅̅̅̅̅̅
G3 G2 G0 + G2 ̅̅̅̅
G3 G1 G0 + G2 ̅̅̅̅
G1 G3 G0 +
̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅
G2 G0 G3 G1 + G3 G1 G2 G0 + G0 G2 G3 G1 ̅̅̅̅
= ̅̅̅̅̅̅̅̅̅
G0 G1 (G2⊕G3) + G0 G1 ̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅ (G3 ⊕ G2 ) + G0 G1 ̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅ (G3 ̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅ (G3
⊕ G2 ) + G1 G0 ⊕ G2 )
= (G2⊕G3) + (G1 ̅̅̅̅̅̅̅̅̅̅̅̅
⊕ G0 ) +(G1⊕G0) + (G3 ̅̅̅̅̅̅̅̅̅̅̅̅
⊕ G2 )
= Y̅ X + Y X̅
Where X = (G2⊕G3) and Y=(G1⊕G0)
= (G2⊕G3) ⊕ (G1⊕G0)
= G2⊕G3⊕G1⊕G0
Step3: Realization
The Gray to Binary code converter is as shown in figure given below
 Fig. 3.5 Gray code to binary converter

Q4] a) Compare different logic families with respect to fan in, fan out, speed,
Propogation delay and power dissipation.

(05)
Solution :-
Parameter ECL DTL TTL IIL CMOS
Fan in - - 12-14 - Greater than
10
Fan out 25 Medium (8) High (10) 8-11 50
Speed X Power 100 300 100 Less than 1 70
Propagation 1-2 30 10 25-2500 70
Delay (ns)
Power 40-45 8-12 10 5-25 01
Dissipation (mW)

Q4] b) Implement 3 bit binary to gray code converter using Decoder.

(05)
Solution :-

Truth table:-
 A B C X Y Z
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 1
0 1 1 0 1 0
1 0 0 1 1 0
1 0 1 1 1 1
1 1 0 1 0 1
1 1 1 1 0 0

Formulae:-
Let b2 b1 b0 be the 3-bit binary number and g2 g1 g0 be its equivalent gray code.
Then,
g2 = b2
g1 = b2 ⊕ b1
g0 = b1 ⊕ b0

Fig. 4.1 Binary to gray code converter.

Q4] c) Explain 4 bit bidirectional shift register.

(10)
Solution :-

• The binary information (data) in a register can be moved from stage to stage within the
register or in or out of the register upon applications of clock pulses.
• This type of bit movement or shifting is essential for certain application like arithmetic and
logic operations used in Microprocessors.
 • This group of registers are called as ‘Shift Register’

4 –bit Bidirectional Shift Register:

• Bidirectional shift register allows shifting of data either to left or to the right side.
• It can be implemented using logic gates circuitry that enables the transfer of data from one
stage to the next stage to the right or to the left, depend on the level of control line.
• The RIGHT/LEFT is the control input signal which allows data shifting either towards right or
towards left.
• A high on this line enables the shifting of data towards right and low enables it towards left.
• When RIGHT/LEFT is high, gates G1, G2, G3 and G4 are enabled.
• The state of Q output of each flip flop is passed through the D input of the following flip flop.
• When the pulse arrives, the data are shifted one place to the right.
• When the RIGHT/LEFT signal is low, gates G5, G6, G7 are enabled.
• The Q output of each flip-flop is passed through the D input of the preceding flip-flop.

Fig.4.s2 - 4 bit Bidirectional Shift Register

Q5] a) Design mod 13 synchronous counter using T flipflop.

(10)
Solution :-
A synchronous counter is one which has the same clock input for all its flip flops. A MOD 13
synchronous counter counts from 0000 to 1101. Hence it will require four T flip flops. Synchronous
counters are designed by using excitation table to determine the combinational logic of inputs to
each flip flop. The excitation table for all the four T flip flops is shown:
 Present state Next state T Flipflop
QD QC QB QA QD + QC+ QB + QA + TD TC TB TA
0 0 0 0 0 0 0 1 0 0 0 1
0 0 0 1 0 0 1 0 0 0 1 1
0 0 1 0 0 0 1 1 0 0 0 1
0 0 1 1 0 1 0 0 0 1 1 1
0 1 0 0 0 1 0 1 0 0 0 1
0 1 0 1 0 1 1 0 0 0 1 1
0 1 1 0 0 1 1 1 0 0 0 1
0 1 1 1 1 0 0 0 1 1 1 1
1 0 0 0 1 0 0 1 0 0 0 1
1 0 0 1 1 0 1 0 0 0 1 1
1 0 1 0 0 0 0 0 1 0 1 0
1 0 1 1 X X X X X X X X
1 1 0 0 X X X X X X X X
1 1 0 1 X X X X X X X X
1 1 1 0 X X X X X X X X
1 1 1 1 X X X X X X X X
Fig 5.a Excitation table for MOD 13 synchronous counter

From the above excitation table, we can draw k maps to determine input to every flipflop

Four equations for four T flipflop are obtained. Using them, the MOD 13 synchronous counter is
designed as follows:
 Fig 5.2 MOD 13 synchronous counter using T flipflop

Q5 b) Convert SR flipflop to JK flipflop and D flipflop.

(10)
Solution:-
SR to JK
a) Excitation Table
Input’s Present State Next State Flip Flop Input

J K Qn Qn+1 S R
0 0 0 0 0 X
0 1 0 0 0 X
1 0 0 1 1 0
1 1 0 1 1 0
0 0 1 0 0 1
0 1 1 0 0 1
1 0 1 1 X 0
1 1 1 1 X 0

b) K- map simplification
c) Logic diagram

SR to D
a) Excitation Table

Input Present State Next State Flip Flop Input

D Qn Qn+1 S R
0 0 0 0 X
1 0 1 1 0
0 1 0 0 1
1 1 1 X 0

b) K-map simplification

c) Logic diagram
Q6] a) ALU

(05)
Solution :-
The arithmetic logic unit is that part of the CPU that handles all the calculations the CPU may need.
Most of these operations are logical in nature. Depending on how the ALU is designed, it can make
the CPU more powerful, but it also consumes more energy and creates more heat. Therefore, there
must be a balance between how powerful and complex the ALU is and how expensive the whole unit
becomes. This is why faster CPUs are more expensive, consume more power and dissipate more
heat.
The main functions of the ALU are to do arithmetic and logic operations, including bit shifting
operations. These are essential processes that need to be done on almost any data that is being
processed by the CPU.
ALUs routinely perform the following operations:
Logical Operations: These include AND, OR, NOT, XOR, NOR, NAND, etc.
Bit-Shifting Operations: This pertains to shifting the positions of the bits by a certain number of
places to the right or left, which is considered a multiplication operation.
Arithmetic Operations: This refers to bit addition and subtraction. Although multiplication and
division are sometimes used, these operations are more expensive to make. Addition can be used to
substitute for multiplication and subtraction for division.

Q6] b) 3 bit Up/Down Asynchronous Counter

(05)
Solution :-
Asynchronous counters are those whose output is free from the clock signal. Because the flip flops in
asynchronous counters are supplied with different clock signals, there may be delay in producing
output.
By adding up the ideas of UP counter and DOWN counters, we can design asynchronous up /down
counter. The 3 bit asynchronous up/ down counter is shown below.
It can count in either ways, up to down or down to up, based on the clock signal input.
UP Counting
If the UP input and down inputs are 1 and 0 respectively, then the NAND gates between first flip flop
to third flip flop will pass the non-inverted output of FF 0 to the clock input of FF 1. Similarly, Q
output of FF 1 will pass to the clock input of FF 2. Thus, the UP /down counter performs up counting.
DOWN Counting
If the DOWN input and up inputs are 1 and 0 respectively, then the NAND gates between first flip
flop to third flip flop will pass the inverted output of FF 0 to the clock input of FF 1. Similarly, Q
output of FF 1 will pass to the clock input of FF 2. Thus, the UP /down counter performs down
counting.
The up/ down counter is slower than up counter or a down counter, because the addition
propagation delay will be added to the NAND gate network.

Q6] c) Octal to Binary Encoder

(05)
Solution:-
An encoder has 2n or fewer input lines, only one of which is in the “1” state at a particular time and
an n-bit code is generated on “n” output lines depending upon which of the input is excited. In
other words, an encoder is a circuit in which output lines generate the binary code corresponding to
the input value.
An octal to binary encoder has 23 = 8 input lines D0 to D7 and 3 output lines Y0to Y2. Below is
the truth table for an octal to binary encoder.
 Fig.6.c Truth Table of octal to binary encoder.

From the truth table, the outputs can be expressed by following Boolean Function.
Y0 = D1 + D3 + D5 + D7
Y1 = D2 + D3 + D6 + D7
Y2 = D4 + D5 + D6 + D7
Above boolean functions are formed by ORing all the input lines for which output is 1. For instance
Y0 is 1 for D1, D3, D5, D7 input lines. The encoder can therefore be implemented with OR gates
whose inputs are determined directly from truth table.

Q6] d) 4-bit Universal shift register

(05)
Solution :-
A Universal shift register is a register which has both the right shift and left shift with parallel load
capabilities. Universal shift registers are used as memory elements in computers. A Unidirectional
shift register is capable of shifting in only one direction. A bidirectional shift register is capable of
shifting in both the directions. The Universal shift register is a combination design
of bidirectional shift register and a unidirectional shift register with parallel load provision.
The register operations performed for the various inputs of select lines are as follows:
S1 S0 REGISTER OPERATION

0 0 No changes
0 1 Shift Right

1 0 Shift Left

1 1 Parallel Load

4-bit universal shift register is built with four blocks each constituted of a 4X1 mux and a D-flipflop.
All the blocks are essentially identical. Because all the multiplexers in the register are wired similarly,

The L inputs come through port 11, which is why the L inputs are readable only when S1S0 = 11. The
feedback Q wires are connected at port 00, so that when S1S0 = 00 the output Q of the D-flipflops
feed back into the flipflops’ inputs resulting in no total change in the register content. Port 01 is
wired to facilitate right-shifts. In mode S1S0 = 01 only port 01 is active and it takes its value from the
previous more significant flipflop and passes it down to the flipflop wired to its mux output. Lastly
port 10 is wired to conduce to left-shifts. Being the only active port when S1S0 = 10, it remits the
output of the less significant flipflop sourcing into it to the flipflop wired to its mux output. As a
consequence of this wiring pattern where each block of the register is an exact replica of any other
block, the selector switches are able to align the behavior of all the multiplexers simultaneously. This
coincidence of behavior is what we refer to as mode behavior of the universal register.

Q6] e) VHDL

(05)

Solution :-
VHDL stands for very high-speed integrated circuit hardware description language. This language was
first introduced in 1981 for the department of Defense (DoD) under the VHSIC program.
VHDL is a hardware description language that can be used a model a digital system at many levels of
abstraction, ranging from the algorithmic level to the gate levels.
Structure of VHDL Module:
The Main component of VHDL module consist of following declaration.
1) Package
2) Entity
3) Architecture
4) Configuration
The following fig. shows the relationship of these basic blocks of VHDL program.
A design may include any number of packages, entity, and Architecture and configuration
declaration.
The entity and architecture blocks are compulsory but packages and configuration blocks are
optional.

Fig 6.e Relationship of VHDL Design units

Features of VHDL are as follows:
1) Designs are organized hierarchically.
2) Each design element has:
i) A well-defined interface.
ii) A precise behavioral specification using either algorithmic description or hardware
structural description.
3) Models concurrency, timing, and clocking:
i) Handles asynchronous and synchronous circuits
ii) Designs can be simulated.
4) Language is not case sensitive.
5) A formal language for specifying the behavior and structure digital circuit.
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MUMBAI UNIVERSITY
DIGITAL LOGIC DESIGN & ANALYSIS
SEMESTER 3 – CBCGS – DECEMBER 2019

Q.1 a) What are Universal gates? Why they are called so ?Explain with suitable
Example . [4M]

Ans : i) A universal gate is a gate which can implement any Boolean function without
use any other gate type.
ii) The NAND and NOR gates are universal gates.
iii) AND and NOR are called universal gates because all the other gates like
and,or,not,xor and xnor can be derived from it.
iv) NAND GATE :

A B Y
0 0 1
0 1 1
1 0 1
1 1 0
NOR GATE :

A B Y
0 0 1
0 1 0
1 0 0
1 1 0

v) Example : OR gate using universal gate i.e NAND gate .

OR gate can be implemented using three NAND gate .

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OR GATE USING NAND

b) Perform following substractions using 7’s complement method.

a) (𝟐𝟎)𝟓 - (𝟏𝟒)𝟓
b) (𝟐𝟎)𝟏𝟎 - (𝟏𝟓)𝟏𝟎 [4M]
Ans : a) The given numbers are of base 5 .We should convert it into octal for
Substraction process.
Using conversion table ,
(20)5 = (12)8 & (14)5 = (11)8
Here A = 12, B = 11.
Find A - B = ? using 7's complement
First find 7's complement of B = 11

Note : 7's complement of a number is obtained by subtracting all bits from 77.
7's complement of 11 is 77-11 = 66
Add it in A i.e in 12 ,
12 + 66 = 100
Here in 7s complement substraction we add carry in LSB
∴ 00 + 1 = 01
∴ (20)5 − (14)5 = (01)8

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b) let A = 20 and B = 15 are decimal value .

We need octal numbers for the 7s complement of any number.
∴ (20)10 = (24)8 & (15)10 = (17)8
Applying 7’s complement method on B ,
77 – 17 = 60 in octal
Add this number in A
∴ (24)8 + (60)8 = (104)8 Here carry is 1 . Add carry to LSB

∴ (20)10 - (15)10 = (5)10

c) Perform (𝟑𝟒)𝟏𝟎 − (𝟏𝟐)𝟏𝟎 in BCD using 10’s complement method . [4M]

Ans :
Here A = 34, B = 10.
Find A - B = ? using 10's complement
First find 10's complement of B = 10

Note : 10's complement of a number is 1 added to it's 9's complement number.

9's complement of 10 is

9 9

- 1 0

8 9

Now add 1 : 89 + 1 = 90

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Now Add this 10's complement of B to A

3 4

+ 9 0

1 2 4

Here carry is 1 ; carry is ignored .,

(34)10 − (12)10 = (24)10

d) Explain lockout condition.How can it be avoided ? [4M]

Ans : i) Sometimes a counter may find itself in some unused states, this happen when
if next state of some unused state is again some unused one and if by chance the
counter happens to find itself in some unused state and never arrives at in used state
then this condition is called “Lock Out”.
ii) To avoid lock out condition the unused states are introduced in front of used states
1,4,5,6 and 7.
iii) An additional circuit is require to ensure that “lock out” does not occur. The
counter should be designed using the next state to be initial state from the unused
state.
iii)An additional circuit is require to ensure that “lock out” does not occur. The
counter should be designed using the next state to be initial state from the unused
state.
iv) To avoid lock out condition the unused states are introduced in front of used states
from the above state diagram the 1,4,5,6 and 7 is the sequence and unused states are
0,3 and 6 the states are introduced in front of us States 1,4,5 and 7 respectively.

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e) If the 7 bit hamming code word received by receiver is 1011011,assuming

the even parity,state whether the received code word is correct or not.
If wrong locate the bit having error and extract corrected data. [4M]
Ans : The received data is 1101101
2𝑘 -1 >= m+k ,
23 – 1 >= 4+3 ,
7=7
Odd C1=1011
Even C2 = 1001
Odd C4 =1101
Bit error = 1+4 = 5

The correct data 1001011

Q.2 a) Reduce using Quine McClusky Method & realize the operation using
NOR gates only.
F = ∑ 𝒎(𝟎, 𝟏, 𝟐, 𝟖, 𝟏𝟎, 𝟏𝟏, 𝟏𝟒, 𝟏𝟓) [10M]
Ans : The given function contains min terms and truth table and Quine
McClusky method is given

Quine McClusky Method :

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Finding all prime implicants of the function.Use those prime implicants in a prime
implicant chart to find the essential prime implicants of the function, as well as other
prime implicants that are necessary to cover the function

A B C D Y
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 0
1 1 0 1 0
1 1 1 0 1
1 1 1 1 1

∴ y = B'D' + AC + A'B'C'

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Implementation :

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b) Explain one digit BCD Adder . [10]

Ans : I)A BCD adder adds two BCD digits and produces output as a BCD digit. A BCD or Binary
Coded Decimal digit cannot be greater than 9.

II)The two BCD digits are to be added using the rules of binary addition.
III) If sum is less than or equal to 9 and carry is 0, then no correction is needed. The sum is
correct and in true BCD form.
IV) But if sum is greater than 9 or carry =1, the result is wrong and correction must be done.
The wrong result can be corrected adding six (0110) to it.

V) For implementing a BCD adder using a binary adder circuit IC 7483, additional
combinational circuit will be required, where the Sum output S3−S0S3−S0 is checked
for invalid values from 10 to 15. The truth table and K-map for the same is as shown:

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VI)The Boolean expression is, Y=S3S2+S3S1Y=S3S2+S3S1

VII)The BCD adder is shown below. The output of the combinational circuit should be
1 if Cout of adder-1 is high. Therefore Y is ORed with Cout of adder 1.
VIII)The output of combinational circuit is connected to B1B2 inputs of adder-2
and B3=B1+0B3=B1+0 as they are connected to ground permanently. This
makes B3B2B1B0B3B2B1B0 = 0110 if Y' = 1.
IX) The sum outputs of adder-1 are applied to A3A2A1A0A3A2A1A0 of adder-2. The
output of combinational circuit is to be used as final output carry and the carry output
of adder-2 is to be ignored.

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Example :

Thus,
Cout = 1
S3S2S1S0=0000 S3S2S1S0=0000
Hence, for adder, inputs will be
A3A2A1A0=0000 A3A2A1A0=0000
B3B2B1B0=0110 B3B2B1B0=0110
This will give final output as
Cout S3S2S1S0=10110 S3S2S1S0=10110.

Q.3 (a) Construct 32:1 MUX using 8:1 MUX only.Also comment about select lines used
[10M]
Ans :

i) In electronics, a multiplexer (or mux), also known as a data selector, is a device that
selects between several analog or digital input signals and forwards it to a single output
line.

ii) The multiplexer is a combinational logic circuit designed to switch one of several
input lines to a single common output line.

iii) Multiplexer are of different types .Example 2:1 MUX , 4:1 MUX , 8:1 MUX , 16:1
MUX ,32:1 MUX ,etc.

iv) We can implement a MUX using different types of MUX .For example , we can
Construct 32:1 MUX using 8:1 MUX only.

V) Truth table and implementation of 32:1 MUX :

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Comment on select lines : i) From circuit diagram , we can see that S0 S1 S2 select
lines are used to select MUX which are connected to the main data lines.
ii)There are select lines such as S5 S4 S3 used to select this multiple MUXes .

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b) Solve the following using Kmap

F(A,B,C,D) = 𝝅𝑴(𝟑, 𝟒, 𝟓, 𝟔, 𝟕, 𝟏𝟎, 𝟏𝟏, 𝟏𝟓) [5M]
Ans : The given function contains max terms .
Truth table :

A B C D Y
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0

KMAP :

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Circuit Diagram :

y = B'C' + AC' + A'B'D' + ABD'

c) Design full adder using half adders and few gates. [5M]
Ans : Half Adder : The addition of 2bits is called Half adder the input variebles are
augent and addent bits and output variebles are sum&carry bits.
Full Adder : Full Adder is the adder which adds three inputs and produces two
outputs. The first two inputs are A and B and the third input is an input carry as C-
IN. The output carry is designated as C-OUT and the normal output is designated
as S which is SUM.
A B C Y(SUM) Y(CARRY)
0 0 0 0 0
0 0 1 1 0 A B Y(SUM) Y(CAR
0 1 0 1 0 RY)
0 1 1 0 1 0 0 0 0
1 0 0 1 0 0 1 1 0
1 0 1 0 1 1 0 1 0
1 1 0 0 1 1 1 0 1
1 1 1 1 1
HALF ADDER

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Full adder using half adder circuit :

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Q.4 a) Convert SR flip flop to JK flip flop and T flip flop. [10M]
Ans : A) SR flip flop to JK flip flop :
I) The truth tables for the flip flop conversion are given below. The present state is
represented by Qp and Qp+1 is the next state to be obtained when the J and K
inputs are applied.
II)For two inputs J and K, there will be eight possible combinations. For each
combination of J, K and Qp, the corresponding Qp+1 states are found. Qp+1
simply suggests the future values to be obtained by the JK flip flop after the value
of Qp. The table is then completed by writing the values of S and R required to get
each Qp+1 from the corresponding Qp. That is, the values of S and R that are
required to change the state of the flip flop from Qp to Qp+1 are written.

Truth Table :
J K 𝑄𝑃 𝑄𝑃+1 S R
0 0 0 0 0 X
0 0 0 1 X 0
0 0 1 0 0 X
0 0 1 0 0 1
0 1 0 1 1 0
0 1 0 1 X 0
0 1 1 1 1 0
0 1 1 0 0 1

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Circuit :

B) SR Flip flop to T flip flop :

Truth table of T flip flop :
T INPUT PRESENT STATE NEXT STATE
0 0 0
0 1 1
1 0 1
1 1 0

Excitation table of SR flip flop :

Present State Next state S R
0 0 0 X
0 1 1 0
1 0 0 1
1 1 x 0

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Combined table for conversion :

T Present Next state S R
0 0 0 0 x
0 1 1 x 0
1 0 1 1 0
1 1 0 0 1

1. Connect the S input to the output of a two-input AND gate which is driven
by the user-provided input, T, and the negation of the flip-flop's present-
state, Q̅n
2. Connect the R input to the output of a two-input AND gate which is
driven by the user-defined input, T, and the present-state of the flip-flop,
Qn

Circuit :

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b) Design 3-bit asynchronous up-down counter. [10M]

Ans :
i) As we know that in the up-counter each flip-flop is triggered by the normal
output of the preceding flip-flop (from output Q of first flip-flop to clock of next
flip-flop); whereas in a down-counter,
each flip-flop is triggered by the complement output of the preceding flip-flop
(from output Q^ of first flip-flop to clock of next flip-flop).

Truth table :
State Qc Qb Qa State Qc Qb Qa
0 0 0 0 7 1 1 1
1 0 0 1 6 1 1 0
2 0 1 0 5 1 0 1
3 0 1 1 4 1 0 0
4 1 0 0 3 0 1 1
5 1 0 1 2 0 1 0
6 1 1 0 1 0 0 1
7 1 1 1 0 0 0 0

i)For up down counting operation preceding flip-flop sometime it need input from
output from output Q of first flip-flop to clock of next flip-flop for up-counting and
sometimes from output Q^ of first flip-flop to clock of next flip-flop for down-
counting. So in above circuit diagram it is shown clearly.
ii) As we know a flip-flop can hold single bit so for 3 bit operation it need three
flip-flops.
iii)An inverter has been inserted in between the count-up control line and the
count-down control line to ensure that the count-up and count-down cannot be
simultaneously in the HIGH state.
iv)When the count-up/down line is held HIGH, the lower AND gates will be
disabled and their outputs will be zero.

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v) So they will not affect the outputs of the OR gates. At the same time the upper
AND gates will be enabled. Hence, QA will pass through the OR gate and into the
clock input of the B flip-flop.
vi)Similarly, QB will be gated into the clock input of the C flip-flop. Thus, as the
input pulses are applied, the counter will count up and follow a natural binary
counting sequence from 000 to 111.
vii)Similarly, with count-up/down line being logic 0, the upper AND gates will
become disabled and the lower AND gates are enabled, allowing Q′A and Q′B to
pass through the clock inputs of the following flip-flops.
viii)Hence, in this condition the counter will count in down mode, as the input
pulses are applied.

Designed Circuit :

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Q.5 a) Design 4-bit Binary to Gray Code Convertor. [10M]

Ans :
i) The logical circuit which converts the binary code to equivalent gray code is
known as binary to gray code converter.
ii) The gray code is a non-weighted code. The successive gray code differs in one-
bit position only that means it is a unit distance code.
iii)It is also referred as a cyclic code. It is not suitable for arithmetic operations. It
is the most popular of the unit distance codes. It is also a reflective code.
iv) An n-bit Gray code can be obtained by reflecting an n-1 bit code about an axis
after 2n-1 rows and putting the MSB of 0 above the axis and the MSB of 1 below
the axis. Reflection of the 4 bits binary to gray code conversion table is given
below:

A B C D GRAY CODE
0 0 0 0 0000
0 0 0 1 0001
0 0 1 0 0011
0 0 1 1 0010
0 1 0 0 0110
0 1 0 1 0111
0 1 1 0 0101
0 1 1 1 0100
1 0 0 0 1100
1 0 0 1 1101
1 0 1 0 1111
1 0 1 1 1110
1 1 0 0 1010
1 1 0 1 1011
1 1 1 0 1001
1 1 1 1 1000

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G4=∑m(8,9,10,11,12,13,14,15), G3=∑m(4,5,6,7,8,9,10,11)

G2=∑m(2,3,4,5,10,11,12,13), G1=∑m(1,2,5,6,9,10,13,14)

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b) What is race around condition?How it is overcome in Master slave JK

Flip flop? [5M]
Ans : Race around condition :
i) In jk flip flop there occurs a condition called race around when we put both
j and k as 1.In race around Condition till the clock is high the output varies
continuously from 0 to 1 &1 to 0.
ii) This condition is undesirable as it is of no use because the change in output
is uncontrolled.
iii) In JK flip flop as long as clock is high for the input conditions J&K equals to
the output changes or complements its output from 1–>0 and 0–>1.
iv) This is called toggling output or uncontrolled changing or racing condition.
Consider above J&K circuit diagram as long as clock is high and J&K=11
then two upper and lower AND gates are only triggered by the
complementary outputs Q and Q(bar). I.e. in any condition according to
the propagation delay one gate will be enabled and another gate is
disabled.
v) If upper gate is disabled then it sets the output and in the next lower gate
will be enabled which resets the flip flop output.
vi) If the Clock On or High time is less than the propagation delay of the flip
flop then racing can be avoided. This is done by using edge triggering
rather than level triggering.
vii) If the flip flop is made to toggle over one clock period then racing can be
avoided. This introduced the concept of Master Slave JK flip flop.

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c) Design 1-Bit Magnitude comparator using logic gates. [5M]

Ans : i) A comparator used to compare two bits is called a single bit comparator.
ii) It consists of two inputs each for two single bit numbers and three outputs to
generate less than, equal to and greater than between two binary numbers.

A B A>B A<B A==B

0 0 0 0 1
0 1 0 1 0
1 0 1 0 0
1 1 0 0 1

iii) A magnitude digital Comparator is a combinational circuit that compares two digital
or binary numbers in order to find out whether one binary number is equal, less than
or greater than the other binary number.
iv) We logically design a circuit for which we will have two inputs one for A and other
for B and have three output terminals, one for A > B condition, one for A = B condition
and one for A < B condition.
A A>B

B COMPARATOR A<B
A==B
Logical expression :
A>B : AB'
A<B : A'B
A=B : A'B' + AB

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Q. 6 Write a short note on any four [20M]

a) VHDL Modelling Styles
b) TTL and CMOS Logic Families.
c) SISO and PISO Shift Register
d) ALU
e) Twisted ring counter
Ans : A) VHDL Modelling Styles :
1] Structural modelling: in this type of modelling an entity is explained as a set of
inter connected component’s.
• It shows graphical representation of modules component’s, with their inter
connection.
• Structural modelling can be used to generate very high level or low level
description in ckt.
2] Data flow modelling: In data flow modelling the data flow through the entity is
expressed using con current signal assignment statements.
• Concurrent signal assignment statements are those in which appear outside
of a process, there are event triggered.
• In signal assignment for assignment of a value to a signal symbol < = is used.

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3] Behavioral style of modelling:

• The behavioral level of abstraction is the level of abstraction supported in
VHDL.
• Process body must be included in every behavioral description.
• The behavioral style of modelling denotes the entity behavior as a set of
statements which executes sequentially.
4] Mixed style of modelling: in a single structure body, we can mix the three
modelling style is within an architecture body to represent structure we can use
components installation statements, to represent data flow we can use
concurrent signal assignment statements and to represent behavior, we can use
process statements

B) TTL and CMOS Logic Families :

i) The transistor-transistor-logic (TTL) family was developed in the use of
transistor switches for logical operations and defines the binary values as
0 V to 0.8 V = logic 0
2 V to 5 V = logic 1
ii) TTL is the largest family of digital ICs, but the CMOS family is growing rapidly.
They are inexpensive, but draw a lot of power and must be supplied with +5 volts.
Individual gates may draw 3 to 4 mA.
iii) The low power Schottky versions of TTL chips draw only 20% of the power, but
are more expensive. Part numbers for these chips have LS in the middle of them.

iv) The complementary metal oxide semiconductor family (CMOS) has equivalents
to most of the TTL chips.
v) CMOS chips are much lower in power requirements (drawing about 1 mA) and
operate with a wide range of supply voltages (typically 3 to 18 volts).
vi) The CMOS model number will have a C in the middle of it, e.g., the 74C04 is the
CMOS equivalent to the TTL 7404.

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vii) A high drawback is extreme sensitivity to static electricity - they must be

carefully protected from static discharges.

C) SISO and PISO Shift Register :

i) The Shift Register is another type of sequential logic circuit that can be used for
the storage or the transfer of binary data
ii) Shift Registers are used for data storage or for the movement of data and are
therefore commonly used inside calculators or computers to store data such as
two binary numbers before they are added together, or to convert the data from
either a serial to parallel or parallel to serial format.
iii) Serial-in to Serial-out (SISO) - the data is shifted serially “IN” and “OUT” of the
register, one bit at a time in either a left or right direction under clock control.
The SISO shift register is one of the simplest of the four configurations as it has
only three connections, the serial input (SI) which determines what enters the left
hand flip-flop, the serial output (SO) which is taken from the output of the right
hand flip-flop and the sequencing clock signal (Clk).
iv) Parallel-in to Serial-out (PISO) - the parallel data is loaded into the register
simultaneously and is shifted out of the register serially one bit at a time under
clock control.
The Parallel-in to Serial-out shift register acts in the opposite way to the serial-in
to parallel-out one above. The data is loaded into the register in a parallel format
in which all the data bits enter their inputs simultaneously, to the parallel input
pins PA to PD of the register. The data is then read out sequentially in the normal
shift-right mode from the register at Q representing the data present at PA to PD.

D) ALU :
i) An arithmetic logic unit (ALU) is a digital circuit used to perform arithmetic and
logic operations.

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ii) It represents the fundamental building block of the central processing unit
(CPU) of a computer. Modern CPUs contain very powerful and complex ALUs. In
addition to ALUs, modern CPUs contain a control unit (CU).
iii) Most of the operations of a CPU are performed by one or more ALUs, which
load data from input registers. A register is a small amount of storage available as
part of a CPU.
iv) The control unit tells the ALU what operation to perform on that data, and the
ALU stores the result in an output register. The control unit moves the data
between these registers, the ALU, and memory.
v) An ALU performs basic arithmetic and logic operations. Examples of arithmetic
operations are addition, subtraction, multiplication, and division. Examples of
logic operations are comparisons of values such as NOT, AND, and OR.
vi) All information in a computer is stored and manipulated in the form of binary
numbers, i.e. 0 and 1. Transistor switches are used to manipulate binary numbers
since there are only two possible states of a switch: open or closed.
vii) An open transistor, through which there is no current, represents a 0. A
closed transistor, through which there is a current, represents a 1.

E) Twisted Ring counter :

i) A twisted ring counter, also called switch-tail ring counter, walking ring
counter, Johnson counter, or Möbius counter, connects the complement of the
output of the last shift register to the input of the first register and circulates a
stream of ones followed by zeros around the ring.
ii)Ring counters are often used in hardware design (e.g. ASIC and FPGA design) to
create finite-state machines .
iii) A binary counter would require an adder circuit which is substantially more
complex than a ring counter and has higher propagation delay as the number of
bits increases, whereas the propagation delay of a ring counter will be nearly
constant regardless of the number of bits in the code.

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