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Final Project

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36 views4 pages

Final Project

Uploaded by

Tuấn Nguyễn
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Digital Design Using VHDL

FINAL PROJECT

Each group chooses one of the following topics


A. Implement CNN on FPGA.
1. Description:
- Research simple Neural network in image processing, recognize
handwritten digits by using Verilog language and upload design to FPGA
kit.
2. Documents:
- Roman A. Solovyev, Alexandr A. Kalinin, Alexander G. Kustov, Dmitry
V. Telpukhov, and Vladimir S. Ruhlov, “FPGA Implementation of
Convolutional Neural Networks with Fixed-Point Calculations”
- Link paper: https://ieeexplore.ieee.org/document/8656778
3. Source code: https://github.com/ZFTurbo/Verilog-Generator-of-Neural-
Net-Digit-Detector-for-FPGA.
4. Requirement:
4.1. Learn about CNN theory, simulate, evaluate design results when
implementing on software (Python)
4.2. Design, verify modules when switching to Verilog code.
4.3. Implement your design on hardware: FPGA kit, camera, monitor.

B. Design I2C controller core:


1. Description:
- I2C protocol was invented by Philips semiconductors in the 1980s, to
provide easy onboard communications between a CPU and various
peripheral chips. I²C stands for Inter-Integrated Circuit. It is used for
attaching lower-speed peripheral ICs to microcontrollers in short-distance
communication. Low-speed peripherals include external EEPROMs,
digital sensors, I2C LCD, and temperature sensors.
Digital Design Using VHDL

FINAL PROJECT

- Design I2C Master Core: provides an interface between a Wishbone


Master and an I2C bus, compatible with Philips I2C bus standard and
Wishbone bus.
2. Documents:
- I2C Bus Specification, Philips Semiconductor, version 2.1, January 2000
Link: https://vdocument.in/bus-i2c-philips.html?page=1
- Bollam Eswari, N.Ponmagal, K.Preethi, S.G.Sreejeesh,
“Implementation of I2C Master Bus Controller on FPGA”
Link paper: https://ieeexplore.ieee.org/document/6577141
I2C – Master Core Specification:
Source code: https://github.com/trondd/oc-i2c
3. Requirements:
3.1. Build Specification of the design based on the documentations
provided: I2C bus standard, Wishbone bus.
 System modeling / design by using diagram, FSM, ASM, FSMD,
ASMD,..
 Describe the input / output signals of each module / block.
3.2. Design I2C Master Core: provides an interface between a
Wishbone Master and an I2C bus.
 Compatible with Philips I2C bus standard.
 Compatible with Wishbone bus.
3.3. Verify your design.
3.4. Evaluate the results of the device when deployed on FPGA: by
simulation, FPGA board, evaluate resource consumption.
Digital Design Using VHDL

FINAL PROJECT

C. Design FFT/IFFT 128 points IP core


1. Description:
- FFT is an algorithm for the effective Discrete Fourier Transform
calculation.
2. Documents:
- Pipelined FFT/IFFT 128 points (Fast Fourier Transform) IP Core User
Manual
Link: FFT/IFFT 128 points
- Source code: https://github.com/freecores/pipelined_fft_128
3. Requirement.
3.1. Build Specification of the design
- System modeling / design by using diagram, FSM, ASM, FSMD,
ASMD,..
- Describe the input / output signals of each module / block.
3.2. Implement Algorithm on C++ / Python
3.3. Verify your RTL design.
3.4. Evaluate the results of the device when deployed on FPGA: by
simulation, FPGA board, evaluate resource consumption.

D. Design a RISC Stored – Program Machine.


1. Description:
- Follow the steps in Section 7.3 Design and Synthesis of a RISC Stored
Program Machine – Chapter 7. Design and Synthesis of Datapath
Controller – Advanced Digital Design with Verilog HDL.
- Documents: Michael D. Ciletti, Advanced Digital Design with the
Verilog HDL book.
2. Requirements:
Digital Design Using VHDL

FINAL PROJECT

- Implement the design according to the instructions in the document.


2.1. Build Specification of the design based on the documentations provided.
- System modeling/design by diagram, FSM, ASM, ASMD, FSMD,..
- Describe the input/output signals of each module.
2.2. Verify your design.
2.3. Evaluate the results of the device when deployed on FPGA: by
simulation, FPGA kit, evaluate resource consumption.

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