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Problem 1: Number Representations.: Problem 5: Design Sequential Circuit

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19 views2 pages

Problem 1: Number Representations.: Problem 5: Design Sequential Circuit

Uploaded by

Tuấn Nguyễn
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Problem 1: Number representations.

1. Convert to hexadecimal and binary


a. 0.62510
b. 123.1710
2. Convert to hexadecimal and decimal:
a. 11000012
b. 110101101.101012
3. Convert to decimal and binary
a. 0x26AE
b. 0xBC10, E1
4. Add the following numbers in binary using 2’s complement to represent negative
numbers. Use a word length of 6 bits (including sign).
a. 21 + 11
b. (−25 + 18)
c. (−12) + 13
d. (−11) + (−21)
Repeat, using 1’s complement to represent negative numbers
Problem 2. Boolean algebra:
Prove using boolean algebra
a. 𝐴 + 𝐵 + (𝐴 + 𝐵)𝐶 = 𝐴 + 𝐵
b. 𝐵 ′ (𝐴 + 𝐵 + 𝐶) = 𝐵′(𝐴 + 𝐶)
c. (𝐴′ + 𝐵 ′ + 𝐶′) . (𝐵′ + 𝐶)(𝐴 + 𝐵′) = 𝐵′
Problem 3. K-Map minimization.
Simplify the following functions using Karnaugh Maps, draw the circuit.
1. F (W, X, Y, Z) = 𝛴 m (0, 2,3,8,9,10,11,12,13,14,15)
2. F (W, X, Y, Z) = 𝛴 m (3,9,11,12,13,14,15) + 𝛴d(1,4,6) // d : don’t care
3. F (A, B, C, D) = 𝛱 𝑀(4,6,8,9,11,12,15)
Determine the minimum sum of products and minimum product of sums for:
1. 𝑓 = 𝑏 ′ 𝑐 ′ 𝑑 ′ + 𝑏𝑐𝑑 + 𝑎𝑐𝑑 ′ + 𝑎′ 𝑏 ′ 𝑐 + 𝑎′ 𝑏𝑐′𝑑
2. F (A, B, C, D) = AC’D’ + A’C + ABC + AB’C + A’C’D’
3. F (A ,B, C, D) = A’B’C’D + CD + AC’D
Problem 5: Design Sequential Circuit
1. Design the circuit for FSM using JK flip – flop.
Current State (S) Next State (S’) Output Z
X=0 X=1
A F B 0
B A F 1
C A D 1
D F E 0
E D B 1
F D E 0

2. Design state strasition diagram for electronic combination lock using Moore
machines. The combination should be 01011
Problem 6: Simulation in Modelsim
1. Install ModelSim:
Link
2. Read ModelSim Tutorial book: Chapter 1: Introduction, Chapter 2: Conceptual
Overview.
3. Step by step do Chapter 3: Basic Simulation, Chapter 4: Projects in ModelSim
Tutorial book
4. Take a screenshot of the result screen after you are simulated successfully

Q Q next J K J K Q next
0 0 0 X 0 0 Q
0 1 1 X 0 1 0
1 0 X 1 1 0 1
1 1 X 0 1 1 Q’

• Quartus for Cyclone II: VD DE2, DE1


Intel® Quartus® II Web Edition Design Software Version 13.0sp1 for Windows

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