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Module 2_VLSI

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12 views

Module 2_VLSI

Uploaded by

rashmi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Module 2: MOS circuit Design Processes and

Circuit Characterization and performance Estimation

MOS LAYERS
MOS design is aimed at turning a specification into a set of masks for processing silicon to
meet the specification. MOS circuits are formed on four basic layers,
• N-diffusion
• P-diffusion
• Poly Silicon
• Metal
which are isolated from one another by thick or thin (thinox) silicon dioxide insulating
layers. The thin oxide (thinox) mask region includes n-diffusion, p-diffusion, and transistor
channels. Polysilicon and diffusion regions interact so that a transistor is formed where they
cross one another.

STICK DIAGRAMS

Stick diagrams convey layer information through the use of a color code for example, in the
case of nMOS design, green for n-diffusion, red for polysilicon, blue for metal, yellow for
implant, and black for contact areas. Sometimes the color code is complemented by
monochrome encoding of the lines so that black and white copies of stick diagrams do not
lose the layer information. The encodings chosen are shown in monochrome form in Figures
3.l(a)-(b).
Stick diagrams of inverter circuits are presented in Figure 3.1 (d).

The transistor stick diagrams of Figure 3.2 stressing the ready translation into mask layout
form.

nMOS Design Style:


Single metal, single polysilicon nMOS technology is shown in Figure 3.1(a).
The layout of nMOS involves:
A transistor is formed wherever poly. crosses n-diff. (red over green) and all diffusion wires
(interconnections) are n-type (green).

When starting a layout, the first step normally taken is to draw the metal (blue) VDD and GND
rails in parallel allowing enough space between them for the other circuit elements which will
be required. Next, thinox (green) paths may be drawn between the rails for inverters and
inverter-based logic as shown in Figure 3.3(a), not forgetting to make contacts as appropriate.
Inverters and inverter-based logic comprise a pull-up structure, usually a depletion mode
transistor, connected from the output point to VDD and a pull-down structure of enhancement
mode transistors suitably interconnected between the output point and GND. This step in the
process is illustrated in Figure 3.3(b), remembering that poly. (red) crosses diffusion (green)
wherever transistors are required. Write the implants (yellow) for depletion mode transistors
and the length to width (L: W) ratio for each transistor. Ratios are important, particularly in
nMOS and nMOS-Iike circuits. Signal paths may also be switched by pass transistors, and long
signal paths may often require metal buses (blue).
CMOS Design Style:
The two types of transistor used, 'n' and 'p', are separated in the stick layout by the demarcation
line (representing the p-well boundary) above which all p-type devices are placed (transistors
and wires). The n-devices (green) are consequently placed below the demarcation line and are
thus located in the p-well. These factors are emphasized by Figure 3.4.

Diffusion paths must not cross the demarcation line and n-diffusion and p-diffusion wires must
not join. The 'n' and 'p' features are normally joined by metal where a connection is needed.
Their geometry will appear when the stick diagram is translated to a mask layout. Place crosses
on VDD and Vss rails to represent the substrate and p-well connection respectively. The design
begins with the drawing of the VDD and Vss rails in parallel and in metal and the creation of an
(imaginary) demarcation line in between, as in Figure 3.5(a). The n-transistors are then placed
below this line and thus close to VSS, while p-transistors are placed above the line and below
VDD. In both cases, the transistors are placed with their diffusion paths parallel to the rails
(horizontal in the diagram) as shown in Figure 3.5(b). A similar approach can be taken with
transistors in symbolic form.

Interconnect the n- with the p-transistors as required, using metal and connect to the rails as
shown in Figure 3.5(c). Only metal and polysilicon can cross the demarcation line but with that
restriction, wires can run in diffusion also. Finally, the remaining interconnections are made as
appropriate and the control signals and data inputs are added. These steps are illustrated in
Figure 3.5(d).

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