3 UNIT

Dynamic CMOS Design

CONTENTS
Part-1: Dynamic CMOS Design : .**..... 3-2F to 3-7F
Steady-State of
Dynamic Gate Circuits
Part-2 : Noise Consideration in 3-7F to 3-10F
Dynamic Design, Charge
Sharing, Cascading
Dynamic Gates
Part-3 : Domino Logic 3-11F to 3-13F
Part-4: NP-CMOS Logic 3-14F to 3-16F
Part-5: Problems in Single-Phase 3-16F to 3-17F
Clocking
Part-6: Two-Phase Non-overlapping 3-17F to 3-20F
Clocking
Part-7: Sequential CMOS Logic 3-20F to 3-24F
Circuits, Layout Design

3-1 F (EC-Sem-7)
3-2F (EC-Sem-7) DynamicCMOS Design

PART-1

Dynamic CMOS Design : Steady-State of Dynamic Gate Circuits.

Questions-Answers

Long Answer Type and Medium Answer Type Questions

Que 3.1. Explain the dynamie CMOS design.

Answer
A. Dynamic CMOS design :
1 Dynamic circuit, which relies on temporary storage of signal values on
the capacitance of high impedance circuit nodes.
2 In this, an alternate logicstyle called dynamic logic is presented that
obtains a similar result, while avoiding static power consumption.
3 With the addition of a clock input, it uses a sequence of precharge and
conditional evaluation phases.
B. Construction and working :
1 The basic construction of an (n-type) dynamic logic gate is shown in
Fig. 3.1.1. The PDN (pull-down network) is constructed exactly as in
complementary CMOS.

Vpp VpD
CLKM, Out

In
CLK-LM, -Out

Ing PDN
Ing

CLKH[M CLK M

(a) n-type network (b) Example

Fig. 3.1.1. Basic concepts of dynamic gate.

VLSI Design 3-3F (EC-Sem-7)
2. The operation of this circuit is divided into twomajor phases:
a.
Precharge:
When CLK= 0, the output node, Out is precharged to Vpn bythe pMOS
transistor M,. During that time, the evaluate nMOS transistor M, is
OFF, so that the pull-down path is disabled.
i. The evaluation FET eliminates any static power that would be consumed
during the precharge period (this is, static current would flow between
the supplies if both the pull down and the precharge device were turned
ON simultaneously ).
b. Evaluation :
i. For CLK= 1, the precharge transistor M, is OFF, and the evaluation
transistor M, is turned ON.
i. The output is conditionally discharged based on the input values and the
pull-down topology.
If the inputs are such that the PDN conducts, then a low resistance path
exists between Out and GND and the output is discharged toGND.
Que 3.2. What are the properties of dynamic circuit ?

Answer
The properties of dynamic circuit are:
1. Dynamic logic has higher speed than equivalent static family.
2 It occupies less area. The number of transistors is lower than in the
static case.
3 It is non-ratioed. The noise margin does not depend on transistor ratios,
as is the case in the pseudo-nMOS family.
4 It has low power dissipation. It only consumes dymamic power. No static
current path ever existsbetween V,nn and GND.
5. Dynamic logic always require clock.
Que 3.3. Explain the behavior of pass transistor in dynamic

CMOS logicimplementation. AKTU2020-21, Marks 07

OR
Explain the working of pass transistor circuit. Also explain how the
charge stored affects the transfer of logic '1' and logic 0' in nMOS
pass transistor circuits.
Answer
1. The fundamental building block of nMOS dynamic logic circuits
consisting
of a nMOS pass transistor driving the gate of another nMOS as shown
in Fig. 3.3.1.
34F (EC-Sem-7) Dynamic CMOS Design
2 The pass transistor M, is controlled by periodic clock pulse and acts as a
switch to charge up or charge down the parasitic capacitance C,.

Vi,
Mp

CK
Fig. 3.3.1.
3 There are two possible operation when CK= 1, they are logic 'l' transfer
ie., charging up the capacitance C, and logic ®transfer ie., charging
down the capacitance C,.
4 The pass transistor Mp provides the only current path to the capacitive
node (soft node) V,.
5. When CK - 0,the pass transistor M, ceases the path and charge stored
in parasitic capacitor C, is used to determine the output of the inverter.
A. Logic »1' transfer :
1 Assume that the soft node voltage is equal to 0 initially, i.e.,
V(t = 0) = 0 V. A logic 1' level is applied to the input terminal which
corresponds toV,, = VoH =VDD
2 Now the clock signal at the gate of the pass transistor goes from 0 to
Vpn at t=0.
3. The pass transistor Mp starts to conduct as soon as the clock signal
becomes active. With Vns =Veg. the M, will operate in saturation region
throughout this cycle, since V,Ds>Ves-VTn'
B. Logic 0' transfer :
1. Assume that the scft node voltage V, is at logic 1' level initially i.e.,
V(t= 0) = V. =(Vpp-V). Alogic 0' level is applied to the input
max

terminal, which corresponds to V,, =0V.

2 Now the clock signal at the gate of the pass transistor goes from 0to VpD
at t = 0.
3 The pass transistor M, starts to conduct as soon as the clock signal
becomes active. I¬ this case, the direction of drain current flowing
through M, will be opposite to that in the logic'1' transfer.
4. With Ves= Vnn and Vng =Vmny) the pass transistor operates in the linear
region throughout this cycle, since Vps < Ves-Va'
Que 3.4.Estimate the equation for the charge storage and charge
leakage at the soft node capacitance C,.
VLSI Design 3-5F (EC-Sem-7)

Answer
1. The
preservation of correct logic at soft node during inactive clock pulse
depends on sufficient amount of charge in C,.
2. Let us assume that high logic has been transferred to the soft
node
during active clock pulse, and both the input voltage V and clock are
equal to 0V as shown in Fig. 3.4.1.

Vin = 0

Iieakage "Bate 0

CK= 0
Fig. 3.4.1.
3. The charge in C, will gradually leak away due to leakage currents
associated with pass transistor Mp. The gate current of inverter transistor
is negligible.
4 The leakage current responsible for draining the soft node capacitance
over time has two responsible components. They are subthreshold
channel current and reverse conduction current.
Ileakage
subthreshold(MP) reverse (MP) ...(3.4.1)
Other component of C,, like oxide related parasitic can be considered
constants, and represented by Cin
5 The sum of two main components are used to express the total charge
stored in the soft node
Q=QV) +Qun
where .(3.4.2)
Ci =Cgb +Cpoly +Cmetal
6. The time derivation of the total soft node charge Qwill give the total
leakage current as
dQ
dt
dQ,V,) dQin
dt dt
dQ, (V,) VCin ...(3.4.3)
dV, dt dt

Que 3.5. Explain the term voltage bootstrapping in CMOS logie

with suitable example. AKTU 2018-19, Marks 05

Answer
1. Voltage b0otstrapping is a very useful dynamic circuit technique for
overcoming threshold voltage drops in digital circuits.
3-6F (EC-Sem-7) Dynamic CMOS Design
2 Dynamic voltage bootstrapping techniques offer a simple yet effective
way to overcome threshold voltage drops which occurs in most situations.
Vpp

M,

V
M,
Cs Choot Vout

VnM, out

Fig. 3.5.1. Dynamic bootstrapping arrangement to

boost V, during switching.
3. When input voltage Vim is low, maximum value of output voltage can be
attain, is limited by
...3.5.1)
Vt (max) = V,-V, (Vout)
level
4. To overcome threshold voltage drop and to obtain full logic high
(Vpn)at output node, the voltage V, must be increased.
C
5. As shown in figure M, is added to circuit. The two capacitors C, and boot
represent capacitances which dynamically couple voltage V, to ground
and to output respectively.
voltage
6 This circuit produces a high V, during switching, so that threshold
drop is overcome at output.
...3.5.2)
V,2 Vpp +V,Vou
According to equation,
d(Vout - V,)
cs lChoot ’Cg Choot dt
dt
dV, Choot dVout ...(3.5.3)
dt Cg + Choot dt
voltage V. during this
7 It is seen from equation that increase in output Integrating
switching event will proportionally increase voltage level V,.
eq. (3.5.3) on both sides, we get
VpD
Choot dVout
Vpp-VT3 Cg +Cboot VoL
V,= (Vpp-V) t CgChoot
+Choot
(Vpp-Vo) ..3.5.4)
 VLSI Design 3-7F (EC-Sem-7)

8. If capacitor Choot >> Cg, maximum value of V, is

V,(max) = 2Vpp-VT3-VoL ...(3.5.4)
which proves that voltage bootstrapping can significantly boost the
voltage level V,.
Que 3.6. Differentiate between dynamic CMOS logic circuit and
static CMOS logic circuit.
Answer

S. No. Parameter Static CMOS Dynamic CMOS

logic circuit |logic circuit
1. Glitches 30 % energy increase Intrinsically does not
have this problem
2 Switching Depends on previous Does not depend on
activity state previous state.
3 Power down Effectively used Generally, higher
models activity factor.
4. Clock Power No clock Not well suited
due to gate capacitance
of precharge MOS
transistor

PART-2

Noise Consideration in Dynamic Design, Charge Sharing.

Questions-Answers

Long Answer Type and Medium Answer Type Questions

Que 3.7. What are the noise considerations in dynamie design ?

Answer
Noise considerations in dynamic design are:
i. Charge leakage :
1. The operation of the dynamic logic depends on the principles of
dynamically storinga charge on the output node (capacitor).
2 Due to leakage currents, this charge gradually leaks away, resulting
eventually in malfunctioning of the gate.
3-8F (EC-Sem-7) Dynamic CMOS Design
3 Charge leakage causes degradation in the logic high level.
Vpp

Out

t
A
Vout4 Precharge Evaluate

M.
t
(b) Effect on waveforms
(a) Leakage source
Fig. 3.7.1. Charge leakage.
4. Dynamic circuits require a minimal clock rate which is typically between
250 Hz and 1 kHz.
ii. Charge sharing :
1. During the precharge phase, the output node is precharged to Vpn
Vpp

|M, Out

BM,

"M,
Fig. 3.7.2.
capacitances ofthe internal
2. Capacitors C, and C, represent the parasitic
nodes of the circuit.
and the capacitance
3 Assume now that during precharge all inputs are set 0
C is discharged.
during evaluation, while
4. Assume further that input B remains at 0
input Amakes a to 1 transition.
VLSI Design
3-9F (EC-Sem-7)
5. Turning transistor M, ON, the charge stored originally on
is redistrilbuted over C, and C. This
causesa drop in the
capacitor C,
which cannot be output
recovered to the dynamic nature of the circuit.
due voltage,
6. One way of alleviating the problem of charge
pMOS transistor in parallel with the prechargesharing is to asadd a small
Fig. 3.7.3 to supply the extra current transistor shown in
needed.
VDD

CLK (0)

oOutput
A

CLK (0)

Fig. 3.7.3. Addition of level restoring transistor.

iüi. Clock feed-through :
1 The clock signal is coupled to the
storage node by the gate-source
capacitance and the gate-overlap capacitance ofthe precharge device as
shown in Fig. 3.7.4.
VpD

TM, Out

C
5V

Overshoot
BM I Out

Fig.3.7.4, Clock feed through.

2. The fast rising and falling edges of the clock couple into the signal node.
3. The disadvantage of clock feed-through is that it causes the signal level
torise sufficiently above the supply voltage as to forward bias the junction
diode.
3-10 F (EC-Sem-7) Dynamic CMOS Design
4 This causes electron injection into the substrate and eventually resulting
in faulty operation.
5. This can be avoided by providing a sufficient number of well contacts
close to the precharge device tocollect the injected current.
iv. Cascading dynamic gate :
1 Cascade dynamic gate is a combination oftwo simple inverters connected
in series,as shown in Fig. 3.7.5.

Vpo VpD
-M,
Out 1 Out 2

Out 1
In
Vn
M
Out 2

(a) (b)
Fig. 3.7.5. Cascading dynamic gates.

2. The problem is that during precharge all outputs are being precharged
to1.
3. The PDN of the second gate is thus in a conducting state at the onset of
the evaluation phase.
4. Suppose now that "In" makes a 0to 1 transition. At the onset of the
evaluation period (¢ =1), output "Out 1" starts to discharge.
5 When "0ut 1" exceeds the switching threshold of the second gate, a
conducting path exists between "Out 2" and GND. "Out 2" therefore
discharges as well, and the correct output of the gate equals 1.
6. This conducting path is only turned OFF when "Out 1" reaches Vy, and
shuts OFF the nMOS pull-down transistor. This leaves "Out 2" at an
intermediate voltage level. The charge loss leads to reduce noise margins
and eventual malfunction.
7. It is obvious that the cascading problem arise because the output is
precharged to "1", so correct operation is guaranteed as long as the
inputs can only make a signal 0 to 1 transition during the evaluation
period.
VLSI Design 3-11 F EC-Sem-7)

PART-3

Domino Logic.

Questions-Answers
Long Answer Type and Medium Answer Type
Questions

Que 3.8.
Explain the domino CMOS logic. Also discuss the
cascaded domino CMOS logic structures.
OR
Explain CMOS domino circuit along with its features. How it can be
cascaded in VLSI circuits ?
|AKTU2017-18, Marks 10
Answer
1 The generalized circuit diagrams of domino CMOS logic gate is
Fig. 3.8.1. The additional inverter allows us to operate a shown in
structures in cascade. number of such
2 During precharge phase (CK =0), the output node of dynamic CMOS is
at logic high, and output of CMOS inverter become low.

VpD Vpp

Vout

nMOS
logic

Fig. 3.8.1.
3 When (CK = 1), at the beginning of evaluation phase there are
possibilities : two
The output node of dynamic CMOS stage either
remains high. discharge to low or
3-12 F (EC-Sem-7) Dynamic CMOS Design
b. Similarly inverter output voltage can also make one transition, from 0
to 1.
4.
Now regardless of input voltages applied to dynamic CMOS stage, it is
not possible for buffer output to make 1to Otransitions during evaluation
phase.
5 Now consider the case for cascading domino CMOS logic gates as shown
in Fig. 3.8.2.

o
nMOS nMOS
logic logic

Fig. 3.8.2.
6. Allinput transistors will be OFF during the precharge phase, since all
buffer output is equal to 0'.
7. During evaluation phase each buffer output can make 0 to 1 transition
and thus each input of all subsequent logic stages can also make Oto 1
transition.
8 In cascade structure consisting of several such stages, the evaluation of
each stage ripples the next stage evaluation, similar to a chain of dominos
falling one after the other. The structure is hence called domino CMOS
logic.
Que 3.9. Implement the Boolean function Y= AB + (C+ D)(F +E)
+ GH using domino CMOS logic. AKTU2018-19, Marks 05
OR
Implement the Boolean function Z =AB +(C+ D)(E+F) +GH using
standard CMOS and domino CMOS logic.
AKTU2019-20, Marks 07
Answer
1 Fig. 3.9.1 and Fig. 3.9.2 show the realization of the logic by using
conventional CMOS and domino logic styles.
2 From implementation, it is clear that the number of transistors used in
domino logic is less than the number of transistors in conventional
CMOS logic.
VLSI Design 3-13 F (EC-Sem-7)

VDD

A LB

VpD

Fig. 3.9.1. Conventional CMOS logic gate.

Vpp

out

Fig. 3.9.2. Domino CMOS logic style.

Que 3.10. Write the properties of dominoCMOS logic.

Answer
The properties of domino CMOS logie are:
1. Each gate requires N+ 4 transistors.
2. Logic evaluation propagates as falling dominoes hence minimum
evaluation period is determined by the logic depth.
3. The nodes must be precharged during the precharge period. Total
precharge time depends on size of pMOS.
4. Inputs must be stable during the evaluation period.
5. Gates are ratioless and non-inverting.
3-14F (EC-Sem-7) Dynamic CMOS Design

PART-4

NP.CMOS logic.

Questions-Answers

Long Answer Type and Medium Answer Type Questions

Que 3.11. Explain NORA CMOS (NP-Domino) logic circuit. Also

write its advantages and disadvantages.
OR
Explain Domino and NORA CMOS logic circuit with suitable

example. AKTU2019-20, Marks 07

OR
Enlist the advantages of dynamic logic circuit over static logic circuit.
Explain NORA CMOS logic circuit with suitable example.
AKTU 2018-19, Marks 10

Answer
A. Domino CMOS logic: Refer Q. 3.8, Page 3-11F, Unit-3.
B. Advantages of dynamic logic circuit over static logic circuit :
The dynamic logic implementation of complex functions generally
requires a smaller silicon area than does the static logic implementation.
C. NORA CMOS logic circuit :
1 This design alternative to domino CMOS logic eliminates the output
buffer without causing race problems between clock and data that arise
when cascading dynamic gates.
2 NORA CMOS (No-Race CMOS) avoids these race problems by cascading
alternate nMOS and pMoS blocks for logic evaluation. The cost is routing
two complemented clock signals.
3 The cascaded NORA gate structure is shown in Fig. 3.11.1.
VLSIDesign 3-15 F (EC-Sem-7)

GC GO GC

nMOS pMOS nMOS

logic logic logic
block block block

Fig. 3.11.1. NORA CMOS cascaded gates.

4. When the global clock (GC) is low (GC high), the nMOS logic block
output nodes are precharged high, while outputs of gates with pMOS
logic blocks are precharged low. When the clock changes, gates are in
the evaluate state.
D. Advantages of NORA CMOS logic circuit :
1 Static CMOS inverter is not required at the output of every dynamic
logic state.
2. Compatible with domino CMOS logic.
3 It allows pipelined system architecture.
E. Disadvantage of NORA CMOS logic circuit : NORA CMOS also
suffers from charge sharing and leakage. To overcome dynamic charge
sharing and soft node leakage problem a circuit technique called Zipper
CMOS can be used.

Que 3.12.Write the difference between dynamic CMOS logie circuit

and static CMOS logic circuit. Explain the classification of dynamic
CMOS logic circuit and design a 2 input EXOR logic gate using domino
logic. AKTU2019-20, Marks 07
Answer
A. Difference : Refer Q. 3.6, Page 3-7F, Unit-3.
B. Classification of dynamic CMOS logic circuit :
i. Domino logic : Refer Q. 3.8, Page 3-11F, Unit-3.
ii. NORA logic: Refer Q.3.11, Page 3-14F, Unit-3.
C. 2 input EXOR logic gate using domino logic gate: The 2 input
EXOR logicgate is shown in Fig. 3.12.1.
3-16 F (EC-Sem-7) DynamicCMOS Design

CLK
Vpp Vpp

B4

Fig. 3.12.1.

PART-5

Problems in Single-Phase Clocking.

Questions-Answers

Long Answer Type and Medium Answer Type Questions

Que 3.13. Explain single-phase clock. What are the problems in

single-phase clock ?
Answer
A Single-phase clock :

Clk
High W
CIk Low IN Q, Next
stage
(a) Single-phase clock (b) Single-phase n-type MOS inverter
Fig. 3.13.1.

1. Single-phase clock consists ofa sequence of pulses having high and low
levels with width Wand time period T' as shown in Fig.3.13.1(a).
2. A single-phase clock has two states (low and high) and two edges per
period.
3. The schematic diagram of a single-phase dynamic nM0S inverter is
shown in Fig. 3.13.1(b).
VLSI Design
3-17 F (EC-Sem-7)
4. When the clock is in the high state,
5
Depending on the input, Q, is eitherboth transistors Q, and Q, are ON.
ON or OFF.
Ifthe input voltage is low, Q, is OFF and
VDp through Q, and Qg: the output capacitor charges to
6
When the input voltage is high, Q, is ON and
through it to alow level. the output is discharged
7. When the clock is in the low state, the
transistors Q, andQ, are OFF,
isolating the output capacitor. This voltage is maintained
period is not too long. during the
OFF period of the clock,provided the
8. During the period, the power
flow through the circuit. As supply is also disconnected and no current
current flows only when the clock is high,
the power consumption is small, and it depends on the duty cycle.
9. It may be noted that the output of the
low output voltage depends on the circuit is also ratioed, because the
that of Q, ratio of the ON resistance of Q, to
(ratio of high time to the time period T).
10. As we know that, this ratio is
Q, (Low ratio) and is often related the physical dimensions of Q,to
to
referred to as the inverter ratio.
B. Problems in single-phase clock:
1. The circuits realized using the
disadvantages single-phase clocking scheme has the
that the output voltage level is dependent
ratio and the number of transistors in the on the inverter
current path of GND.
2 In other words, single-phase dymamic
the circuit dissipates power when the circuits are ratioed logic. Moreover,
output is low and the clock is high.
3. Another problem arising out of single-phase clocked logic is
clock skew problem. known as
4. This is due to a delay in a clock signal
number of circuit stages. This results in during its journey through a
hazards, etc. Some of the problems can beundesired
overcome
signals like glitch,
clocking scheme. using two-phase

PART-6
Two-Phase Non-Overlapping Clocking.

Questions-Answers
Long Answer Type and Medium Answer Type
Questions
3-18 F EC-Sem-7) Dynamic CMOS Design

Que 3.14. Briefly discuss about two-phase non-overlapping clock.

Answer
1. A two-phase non-overlapping clock is shown in Fig. 3.14.1(a). As the
two-phases ($, and ,) are never high simultaneously, the clock has
three states and four edges and satisfies the property !, o', =0.
2 There is a dead time, A, between transitions of the clock signals as
shown in Fig. 3.14.1a).
3. The schematic diagram of a circuit that generates two-phase clock is
shown in Fig. 3.14. 1(b).

(a) Two-phase clock

Clk

(b) Two-phase clock generator circuit

Fig. 3.14.1.

4 An inverter based on two-phase clock generator is shown in Fig. 3.14.2.

5 When the clock , is high, the intrinsic capacitor charges to Vpp through
Q. And clock ¢, which comes after o, performs the evaluation. IfV..
high, Q, is turned ON and Q, is ON, the capacitor discharges to the GND
level and the output V, attains low logical level.
6 IV, is low the Q, is OFF and there is no path for the capacitor to
in

discharge. Therefore, the output V, remains at high logic level.

7. It may be noted that the pull-up and pull-down transistors are never
simultaneously ON. The circuit has no DC circuit path regardless of the
state of the clocks or the information stored on the parasitic capacitors.
8 Moreover, the output is not ratioed, i.e., the low-Bevel output is
independent of the relativevalue of the aspect ratio of the transistors.
9. That is why the circuits based on two-plhase clocking are often termed
as ratioless and powerless.
VLSI Design 3-19 F (EC-Sem-7)

DD

Vo

Fig. 3.14.2. Two-phase n-type MOS (nMOS) inverter.

Que 3.15. Describe the working of threestage pseudo nMOS dynamic

shift register driven with two-phase ciocking giving its circuit.
AKTU2019-20, Marks 07
Answer
1. In depletion load dynamic shift register cireuits, the input data are inverted
once and transferred or shifted into the next stage during each clock
pulse as shown in Fig. 3.15.1.

VDD Vpp VDD

Vin out

Cinl Cin2
Cout Cout2 C;ns
Fig.3.15.1.
2 The operation of three stage dynamic shift register circuit is as follows.
3. When ¢, is active, input V,, is transferred into capacitance C, and the
output appe ars at Coutl*
4. When o, becomes active during next phase, the Ca is transferred as
input to second stage Cng and output of second stage is determined.
3-20 F (EC-Sem-7) Dynamic CMOS Design
5. During the first stage Cn continues to retain its previous level via
charge storage.
6. When , becomes active again, the original data written into register
i.e., into third stage and the first stage can now accept the next data bit.
7. The maximum clock frequency is determined by the signal propagation
delay through one inverter stage.
8. One-half period of clock signal is long enough to allow Cn to charge up
or down and to propagate the logic to C The logic high of each inverter
stage is one threshold voltage lower than the power supply voltage.

PART-7

Sequential CMOS Logic Circuits, Layout Design.

Questions-Answers
Long Answer Type and Medium Answer Type Questions

Que 3.16. Explain sequential CMOS circuit.

Answer
1 Fig. 3.16.1 shows a sequential circuit consisting of acombinational circuit
and a memory block in the feedback loop.

A -0UT 1

B Combination al -OUT 2
logic
C

Memory

Fig. 3.16.1.

2 In most cases, the regenerative behavior of sequential circuits is due to

either a direct or an indirect feedback connection between the output
and the input.
VLSI Design 3-21 F (EC-Sem-7)
3.
Regenerative operation can, under certain conditions, also be interpreted
as a simple memory function.
4. The critical components of sequential systems are the basic
circuits, which can be classified into three main groups : regenerative
i. Bistable: Bistable circuits have, as their name implies, two table states
or operation modes, each of which can be attained under
and output conditions.
certain input
ii. Monostable: Monostable circuits, on the other hand, have only one
stable operating point. Even if the circuit experiences an external
perturbation, the output eventually returns to the single stable state
after a certain time period.
iüi. Astable: In astable circuits, there is no stable
which the circuit can preserve for a certain timeoperating
period.
point or state
Consequently,
the output of an astable circuit must oscillate without setting
into a
stable operating mode.
Que 3.17. Explain SR latch based on NOR gate.

Answer
1. The gate-level schematic of the SR latch consisting of two
NOR gates
are shown in Fig. 3.17.1.

-Q
Fig. 3.17.1.
2. If the set input (S) is equal to logic 1 and the reset input is equal to logic
0 then the output Qwillbe forced to logic 1. While Qis forced to logic 0.
This means the SR latch will be set, irrespective of its previous state.
3. Similarly, ifS is equal to 0 and R is equal to 1 then the output Qwill be
forced to0 while Q is forced to 1. This means the latch is reset, regardless
of its previously held state.
4 Finally, if both of the inputs S and R are equal to logic 1then both output
will be forced to logic 0 which conflicts with the
complementarity of Q
and .
3-22 F (EC-Sem-7) Dynamic CMOS Design
5. Therefore, this input combination is not allowed during normal operation.
6 Truth table of NOR based SR Latch is given in Table 3.17.1.
Table 3.17.1.

S R Operation

Hold

1 1 Set
0 1 1 Reset
1 1 0 Not allowed

7 CMOSSR latch based on NOR gate is shown in Fig. 3.17.2.

VpD VDD

H[M, M, H[M, M,R

Fig. 3.17.2. CMOS SR latch circuit based on NOR2 gates.

8. Ifthe S is equal to Vw and the Ris equalto Vors both of the parallel
connected transistors M, and M, will be ON. The volt age on node will
assume a logic-low level of Vo =0.
9. At the same time, both M, and M, are turned OFF, which results in a
logic-high voltage Vou at node @. If the Ris equal to Vop and the S is
equal to Vo,, M, and M, turned OFF and M, and M, turned ON.
Que 3.18. Discuss NOR-based SR latch with a clock.
Answer
1 Fig. 3.18.1 shows a NOR-based SR latch with a clock added. The latch is
responsive to inputs S and R only when CLK is high.
 3-23 F (EC-Sem-7)
VLSI Design

Fig. 3.18.1.

2 When CLK is low, the latch retains its current state. Observe that Q
changes state:
When S goes high during positive CLK.
On leading CLK edge after changes in S and R during CLK low time.
iüi. Apositive glitch in S while CLK is high.
iv. When R goes high during positive CLK.
3. CMOS AO1 implementation of clockedNOR based SRlatch is shown in
Fig. 3.18.2.
4. When clock is high, the circuit becomes simply a NOR based CMOS
latch which will respond to input S and R.

VpD Vpp
CK

CKL

Fig. 3.18.2.

Que 3.19. Write a short note on clocked JK flip-flop.

3-24 F (EC-Sem-7)
Dynamic CMOS Design

Answer
1. Fig. 3.19.1 shows a clocked JK latch, based on NAND gates.

CLK

Fig. 3.19.1.
2 The disadvantage of an SR latch is that when both S andR are high, its
output state becomes indeterminant.
3. The JKlatch eliminates this problem by using feedback from output to
input, such that all input states of the truth table are allowable. If
J=K=0, the latch will hold its present state.
4. IfJ= land K= 0, the latch will set on the next positive-going clock edge,
i.e., Q= 1, Q =0.
5. IfJ= 0and K= 1, the latch will reset on the next positive-going clock
edge, i.e., Q = l and Q =0.
6. IfJ= K= 1, the latch willtoggle on the next positive-going clock edge.
7. The operation of the clocked JK latch is given in the Table 3.19. 1.
Table 3.19.1.

J K Q R QOperation
0 1 1 1 0 1
0 Hold
1 0 1 1 1

0 1 1 1
1 Reset
1 1 0

1 0 1 1
1 Set
1 0 1 1 1 0

1 1 1
1 1
1
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1 1