Industrial Training Report VLSI Design

TABLE OF CONTENTS

CHAPTER TOPIC Pg-No

1 INTRODUCTION (VLSI) 1-4
2 HISTORY 5-6
3 DIGITAL DESIGN LOGIC 7-10
4 HARDWARE DESCRIPTION LANGUAGE 11
5 VERILOG 12
6 DESIGN UNITS AND DATATYPES 13-15

7 VERILOG MODELLING STYLES 16-19

8 SIMULATION USING TESTBENCHES 20-21
9 SUMMER INTERNSHIP PROJECT 22-28

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 Industrial Training Report VLSI Design

INTRODUCTION

Gone are the days when huge computers made of vacuum tubes sat humming in entire dedicated
rooms and could do about 360 multiplications of 10 digit numbers in a second. Though they
were heralded as the fastest computing machines of that time, they surely don’t stand a chance
when compared to the modern day machines. Modern progressing second. But what drove this
change? The whole domain of computing ushered into a new dawn of electronic miniaturization
with the advent of semiconductor transistor by Bardeen (1947-48) and then the Bipolar
Transistor by Shockley (1949) in the Bell Laboratory.
Since the invention of the first IC (Integrated Circuit) in the form of a Flip Flop by Jack Kilby in
1958, our ability to pack more and more transistors onto a single chip has doubled roughly every
18 months, in accordance with the Moore’s Law. Such exponential development had never been
seen in any other field and it still continues to be a major area of research work.

VLSI chiefly comprises of Front End Design and Back End design these days. While front end
design includes digital design using HDL, design verification through simulation and other
verification techniques, the design from gates and design for testability, backend design
comprises of CMOS library design and its characterization. It also covers the physical design and
fault simulation.

While Simple logic gates might be considered as SSI devices and multiplexers and parity
encoders as MSI, the world of VLSI is much more diverse. Generally, the entire design
procedure follows a step by step approach in which each design step is followed by simulation
before actually being put onto the hardware or moving on to the next step. The major design
steps are different levels of abstractions of the device as a whole:

1. Problem Specification: It is more of a high level representation of the system. The major
parameters considered at this level are performance, functionality, physical dimensions,

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fabrication technology and design techniques. It has to be a tradeoff between market

requirements, the available technology and the economical viability of the design. The end
specifications include the size, speed, power and functionality of the VLSI system.

2. Architecture Definition: Basic specifications like Floating point units, which system to
use, like RISC (Reduced Instruction Set Computer) or CISC (Complex Instruction Set
Computer), number of ALU’s cache size etc.

3. Functional Design: Defines the major functional units of the system and hence facilitates the
identification of interconnect requirements between units, the physical and electrical
specifications of each unit. A sort of block diagram is decided upon with the number of inputs,
outputs and timing decided upon without any details of the internal structure.

4. Logic Design: The actual logic is developed at this level. Boolean expressions, control
flow, word width, register allocation etc. are developed and the outcome is called a Register
Transfer Level (RTL) description. This part is implemented either with Hardware Descriptive
Languages like VHDL and/or Verilog. Gate minimization techniques are employed to find the
simplest, or rather the smallest most effective implementation of the logic.

5. Circuit Design: While the logic design gives the simplified implementation of the logic,
the realization of the circuit in the form of a netlist is done in this step. Gates, transistors and
interconnects are put in place to make a netlist. This again is a software step and the outcome is
checked via simulation.

6. Physical Design: The conversion of the netlist into its geometrical representation is done in
this step and the result is called a layout. This step follows some predefined fixed rules like the
lambda rules which provide the exact details of the size, ratio and spacing between components.
This step is further divided into sub-steps which are:

6.1 Circuit Partitioning: Because of the huge number of transistors involved, it is not
possible to handle the entire circuit all at once due to limitations on computational
capabilities and memory requirements. Hence the whole circuit is broken down into
blocks which are interconnected.

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Figure 1 VLSI Design Flow

6.2 Floor Planning and Placement: Choosing the best layout for each block from
partitioning step and the overall chip, considering the interconnect area between the
blocks, the exact positioning on the chip in order to minimize the area arrangement while

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meeting the performance constraints through iterative approach are the major design
steps taken care of in this step.

6.3 Routing: The quality of placement becomes evident only after this step is completed.
Routing involves the completion of the interconnections between modules. This is
completed in two steps. First connections are completed between blocks without taking
into consideration the exact geometric details of each wire and pin. Then, a detailed
routing step completes point to point connections between pins on the blocks.

6.4 Layout Compaction: The smaller the chip size can get, the better it is. The
compression of the layout from all directions to minimize the chip area thereby reducing
wire lengths, signal delays and overall cost takes place in this design step.

6.5 Extraction and Verification: The circuit is extracted from the layout for comparison
with the original netlist, performance verification, and reliability verification and to check
the correctness of the layout is done before the final step of packaging.

7. Packaging: The chips are put together on a Printed Circuit Board or a Multi Chip Module
to obtain the final finished product.

Initially, design can be done with three different methodologies which provide different levels of
freedom of customization to the programmers. The design methods, in increasing order of
customization support, which also means increased amount of overhead on the part of the
programmer, are FPGA and PLDs, Standard Cell (Semi Custom) and Full Custom Design.

While FPGAs have inbuilt libraries and a board already built with interconnections and blocks
already in place; Semi Custom design can allow the placement of blocks in user defined custom
fashion with some independence, while most libraries are still available for program
development. Full Custom Design adopts a start from scratch approach where the programmer is
required to write the whole set of libraries and has full control over the block development,
placement, and routing. This also is the same sequence from entry level designing to professional
designing.

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HISTORY

In 1920s when several inventors attempted devices that were intended to control current in solid-
state diodes and convert them into triodes. After World War II, when the use of silicon and
germanium crystals as radar detectors led to improvements in fabrication and theory. Scientists
who had worked on radar returned to solid-state device development. The invention of the
first transistor was at Bell Labs in 1947, the field of electronics shifted from vacuum tubes
to solid-state devices.

With the small transistor at their hands, electrical engineers of the 1950s saw the possibilities of
constructing far more advanced circuits. However, as the complexity of circuits grew, problems
arose.[1] One problem was the size of the circuit. A complex circuit like a computer was
dependent on speed. If the components were large, the wires interconnecting them must be long.
The electric signals took time to go through the circuit, thus slowing the computer.

The invention of the integrated circuit by Jack Kilby and Robert Noyce solved this problem by
making all the components and the chip out of the same block (monolith) of semiconductor
material. The circuits could be made smaller, and the manufacturing process could be automated.
This led to the idea of integrating all components on a single-crystal silicon wafer, which led to
small-scale integration (SSI) in the early 1960s, and then medium-scale integration (MSI) in the
late 1960s.

Very large-scale integration was made possible with the wide adoption of the MOS transistor,
originally invented by Mohamed M. Atalla and Dawon Kahng at Bell Labs in 1959. Atalla first
proposed the concept of the MOS integrated circuit chip in 1960, followed by Kahng in 1961,
both noting that the MOS transistor's ease of fabrication made it useful for integrated
circuits. General Microelectronics introduced the first commercial MOS integrated circuit in
1964. In the early 1970s, MOS integrated circuit technology allowed the integration of more than
10,000 transistors in a single chip. This paved the way for VLSI in the 1970s and 1980s, with
tens of thousands of MOS transistors on a single chip (later hundreds of thousands, then millions,
and now billions).

The first semiconductor chips held two transistors each. Subsequent advances added more
transistors, and as a consequence, more individual functions or systems were integrated over

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time. The first integrated circuits held only a few devices, perhaps as many as
ten diodes, transistors, resistors and capacitors, making it possible to fabricate one or more logic
gates on a single device. Now known retrospectively as small-scale integration (SSI),
improvements in technique led to devices with hundreds of logic gates, known as medium-scale
integration (MSI). Further improvements led to large-scale integration (LSI), i.e. systems with at
least a thousand logic gates. Current technology has moved far past this mark and
today's microprocessors have many millions of gates and billions of individual transistors.

At one time, there was an effort to name and calibrate various levels of large-scale integration
above VLSI. Terms like ultra-large-scale integration (ULSI) were used. But the huge number of
gates and transistors available on common devices has rendered such fine distinctions moot.
Terms suggesting greater than VLSI levels of integration are no longer in widespread use.

In 2008, billion-transistor processors became commercially available. This became more

commonplace as semiconductor fabrication advanced from the then-current generation
of 65 nm processes. Current designs, unlike the earliest devices, use extensive design
automation and automated logic synthesis to lay out the transistors, enabling higher levels of
complexity in the resulting logic functionality. Certain high-performance logic blocks like the
SRAM (static random-access memory) cell, are still designed by hand to ensure the highest
efficiency.

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Digital Logic Design

Digital logic design is the basis of electronic systems, such as computers and cell phones. Digital
logic is rooted in binary code, which renders information through zeroes and ones, giving each
number in the binary code an opposite value. This system facilitates the design of electronic
circuits that convey information, including logic gates with functions that include AND, OR, and
NOT commands. The value system translates input signals into specific outputs. These functions
facilitate computing, robotics, and other electronic applications.
Digital logic design forms the foundation of electrical engineering and computer engineering.
Digital logic designers build complex electronic components that use both electrical and
computational characteristics such as power, current, logical function, protocol, and user input.
Digital logic design is used to develop hardware, such as circuit boards and microchip
processors. This hardware processes user input, system protocol, and other data in navigational
systems, cell phones, or other high-tech systems.
Everything that works on batteries and everything that can have a circuit board, is built by using
principles of Digital electronics and Digital Logic Design. Digital electronics deals with the
circuits that operate on digital inputs and outputs. In the provided course above a detailed
discussion starting from the bottom of what it means to be digital, how digital values are
manipulated by circuits. Further we moved to the discussion of the memory aspect of digital
aspect of digital electronics.
Digital Number Systems
When we design digital Systems, we frequently deal with number system apart from binary. In
digital electronics, the number system is used for representing the information. The number
system has different bases and the most common of them are the decimal, binary, octal, and
hexadecimal. The base or radix of the number system is the total number of the digit used in the
number system.
The number system that we use in our day-to-day life is the decimal number system. Decimal
number system has base 10 as it uses 10 digits from 0 to 9. In decimal number system, the
successive positions to the left of the decimal point represents units, tens, hundreds, thousands
and so on.
Octal has eight values 0 to 7. If larger values than 7 are needed, extra columns are added to the
left. Each column value is now 8 times the value of the column to its right.
Hexadecimal numbers are used extensively in microprocessor work. The hexadecimal number
system has a base of 16, and hence it consists of the following sixteen number of digits.
Boolean Algebra
Binary is a language in its own way, it is governed by some laws. These laws fall under Boolean
Algebra. These are the rules needed to perform operations on binary data. Boolean algebra
differs from the mathematical algebraic system with respect to the operations done on its
variables. Boolean algebra is used to simplify the complex logic expressions of a digital circuit.
Thereby allowing us to reduce complex circuits into simpler ones. It goes something like this:

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Binary Arithmetic
In the binary number system, there are only two digits 0 and 1, and any number can be
represented by these two digits. The arithmetic of binary numbers means the
operation of binary addition, binary subtraction, binary multiplication and binary
division.
Logic Circuits
There are two main types of digital logic circuits in digital electronics combinational
and sequential logic circuits.
Combinational Circuit
The combinational logic circuits are the circuits that contain different types of logic gates.
Simply, a circuit in which different types of logic gates are combined is known as
a combinational logic circuit. The output of the combinational circuit is determined from the
present combination of inputs, regardless of the previous input. The input variables, logic gates,
and output variables are the basic components of the combinational logic circuit. There are
different types of combinational logic circuits, such as Adder, Subtractor, Decoder, Encoder,
Multiplexer, and De-multiplexer.
There are the following characteristics of the combinational logic circuit:

o At any instant of time, the output of the combinational circuits depends only on
the present input terminals.
o The combinational circuit doesn't have any backup or previous memory. The present
state of the circuit is not affected by the previous state of the input.
o The n number of inputs and m number of outputs are possible in combinational
logic circuits.

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Sequential Circuit

The sequential circuit is a special type of circuit that has a series of inputs and outputs. The
outputs of the sequential circuits depend on both the combination of present inputs and previous
outputs. The previous output is treated as the present state. So, the sequential circuit contains the
combinational circuit and its memory storage elements. A sequential circuit doesn't need to
always contain a combinational circuit. So, the sequential circuit can contain only the memory
element.

Types of Sequential Circuits – There are two types of sequential circuit:

Asynchronous sequential circuit – These circuit do not use a clock signal but uses the
pulses of the inputs. These circuits are faster than synchronous sequential circuits
because there is clock pulse and change their state immediately when there is a change in
the input signal. We use asynchronous sequential circuits when speed of operation is
important and independent of internal clock pulse.
Synchronous sequential circuit – These circuit uses clock signal and level inputs (or
pulsed) (with restrictions on pulse width and circuit propagation). The output pulse is the
same duration as the clock pulse for the clocked sequential circuits. Since they wait for
the next clock pulse to arrive to perform the next operation, so these circuits are
bit slower compared to asynchronous. Level output changes state at the start of an input
pulse and remains in that until the next input or clock pulse.

Finite State Machines

The finite state machines (FSMs) are significant for understanding the decision making logic as
well as control the digital systems. In the FSM, the outputs, as well as the next state, are a
present state and the input function. This means that the selection of the next state mainly
depends on the input value and strength lead to more compound system performance. As in
sequential logic, we require the past inputs history for deciding the output. Therefore, FSM
proves very cooperative in understanding sequential logic roles. Basically, there are two methods
for arranging a sequential logic design namely mealy machine as well as more machine. This

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article discusses the theory and implementation of a finite state machine or FSM, types, finite
state machine examples, advantages, and disadvantages.

FSMs are used in games; they are most recognized for being utilized in artificial intelligence, and
however, they are also frequent in executions of navigating parsing text, input handling of the
customer, as well as network protocols.
These are restricted in computational power; they have the good quality of being comparatively
simple to recognize. So, they are frequently used by software developers as well as system
designers for summarizing the performance of a difficult system.
The finite state machines are applicable in vending machines, video games, traffic
lights, controllers in CPU, text parsing, analysis of protocol, recognition of speech, language
processing, etc.
FSMs are used in games; they are most recognized for being utilized in artificial intelligence, and
however, they are also frequent in executions of navigating parsing text, input handling of the
customer, as well as network protocols.
These are restricted in computational power; they have the good quality of being comparatively
simple to recognize. So, they are frequently used by software developers as well as system
designers for summarizing the performance of a difficult system.
The finite state machines are applicable in vending machines, video games, traffic
lights, controllers in CPU, text parsing, analysis of protocol, recognition of speech, language
processing, etc.
Applications of Finite State Machine:
 UART-Transmitter-Design
 UART-Receiver-Design
 Traffic-Light-Controller
 Simple-Traffic-Controller
 Serial-Adder
 Sequential-Counters-JKFF
 Sequential-Counters-DFF
 Sequential-Counters
 Sequence-Generator
 Sequence-Detector
 Lift-Controller

The advantages of Finite State Machine include the following.

 Finite state machines are flexible
 Easy to move from a significant abstract to a code execution
 Low processor overhead
 Easy determination of reachability of a state

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Hardware Description Language

In the early days of Integrated Circuits, engineers had to sit down and physically draw transistors
and their connections on paper to design them such that it can be fabricated on silicon. Bigger
and complex circuits demanded more engineers, time and other resources and soon enough there
was a need to have a better way of designing integrated circuits.
Hardware description language (HDL) is a specialized computer language used to program
electronic and digital logic circuits. The structure, operation and design of the circuits are
programmable using HDL. HDL includes a textual description consisting of operators,
expressions, statements, inputs and outputs. Instead of generating a computer executable file, the
HDL compilers provide a gate map. The gate map obtained is then downloaded to the
programming device to check the operations of the desired circuit. The language helps to
describe any digital circuit in the form of structural, behavioural and gate level and it is found to
be an excellent programming language for FPGAs and CPLDs.
The three common HDLs are Verilog, VHDL, and SystemC. Of these, SystemC is the
newest. The HDLs will allow fast design and better verification. In most of the industries,
Verilog and VHDL are common. Verilog, one of the main Hardware Description Language
standardized as IEEE 1364 is used for designing all types of circuits. It consists of modules and
the language allows Behavioral, Dataflow and Structural Description. VHDL (Very High Speed
Integrated Circuit Hardware Description Language) is standardized by IEEE1164. The design is
composed of entities consisting of multiple architectures. SystemC is a language that consist a
set of C++classes and macros. It allows electronic system level and transaction modeling.

Need for Hardware Description Language

The Moore’s Law in the year 1970 has brought a drastic change in the field of IC technology.
This change has made the developers to bring out complex digital and electronic circuits. But the
problem was the absence of a better programming language allowing hardware and software
codesign. Complex digital circuit designs require more time for development, synthesis,
simulation and debugging. The arrival of HDLs has helped to solve this problem by allowing
each module to be worked by a separate team.
All the goals like power, throughput, latency (delay), test coverage, functionality and area
consumption required for a design can be known by using HDL. As a result, the designer can
make the necessary engineering tradeoffs and can develop the design in a better and efficient
way. Simple syntax, expressions, statements, concurrent and sequential programming is also
necessary while describing the electronics circuits. All these features can be obtained by using a

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hardware description language. Now while comparing HDL and C languages, the major
difference is that HDL provides the timing information of a design.

Verilog
Verilog was developed to simplify the process and make the Hardware description
language(HDL) more robust and flexible. Today, Verilog is the most popular HDL used and
practiced throughout the semiconductor industry.

Why Verilog?

Verilog consist a level of abstraction that helps hide away the details of its implementation and
technology.

For example, the design of D-flip flop would require the knowledge of how the transistors need
to be arranged to achieve a positive edge triggered FF and what the rise, fall and clk-Q times
required to latch the values onto a flop among many other technology oriented details. Power
dissipation, timing and the ability to drive nets and other flops would also require a more
thorough understanding of the physical characteristic of a transistor.

Verilog helps on the behaviour and leave the rest to be sorted out later.

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DESIGN UNITS AND DATATYPES

Verilog introduces several new data types. These data types make RTL descriptions easier to
write and understand.

The data storage and transmission elements found in digital hardware are represented using a set
of Verilog Hardware Description Language (HDL) data types.

In Verilog, data types are divided into NETS and Registers. These data types differ in the way
that they are assigned and hold values, and also they represent different hardware structures.

Integer and Real Data Types

Many data types will be familiar to C programmers. The idea is that algorithms modelled in C
can be converted to Verilog if the two languages have the same data types.

Verilog introduces new two-state data types, where each bit is 0 or 1 only. Using two-
state variables in RTL models may enable simulators to be more efficient. And they are not
affecting the synthesis results.

The data types include bit, byte, shortint, int, longint, reg, logic,

time. Non-Integer Data Types

Arrays
In Verilog, we can define scalar and vector nets and variables. We can also define memory
arrays, which are one-dimensional arrays of a variable type.

Verilog allowed multi-dimensioned arrays of both nets and variables and removed some of the
restrictions on memory array usage.

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Verilog takes this a stage further and refines the concept of arrays and permits more operations
on arrays.

In Verilog, arrays may have either packed or unpacked dimensions, or both.

Packed dimensions

 Are guaranteed to be laid out contiguously in memory.

 It can be copied on to any other packed object.
 Can be sliced ("part-selects").
 Are restricted to the "bit" types (bit, logic, int, etc.), some of which (e.g., int) have a fixed
size.

Nets
Nets are used to connect between hardware entities like logic gates and hence do not store any
value.

The net variables represent the physical connection between structural entities such as logic
gates. These variables do not store values except trireg. These variables have the value of their
drivers, which changes continuously by the driving circuit.

Some net data types are wire, tri, wor, trior, wand, triand, tri0, tri1, supply0, supply1, and trireg.
A net data type must be used when a signal is:

o The output of some devices drives it.

o It is declared as an input or in-out port.
o On the left-hand side of a continuous assignment.

1. Wire
A wire represents a physical wire in a circuit and is used to connect gates or modules. The value
of a wire can be read, but not assigned to, in a function or block. A wire does not store its value
but must be driven by a continuous assignment statement or by connecting it to the output of a
gate or module.
2. Wand(wired-AND)
The value of a wand depends on logical AND of all the drivers connected to it.

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3. Wor (wired-OR)
The value of wor depends on the logical OR of all the drivers connected to it.
4. Tri (three-state)
All drivers connected to a tri must be z, except one that determines the tri's value.
5. Supply0 and Supply1
Supply0 and supply1 define wires tied to logic 0 (ground) and logic 1 (power).

Registers
A register is a data object that stores its value from one procedural assignment to the next. They
are used only in functions and procedural blocks.
An assignment statement in a procedure acts as a trigger that changes the value of the data
storage element.
Reg is a Verilog variable type and does not necessarily imply a physical register. In multi-bit
registers, data is stored as unsigned numbers, and no sign extension is done for what the user
might have thought were two's complement numbers.
Some register data types are reg, integer, time, and real.reg is the most frequently used type.
 Reg is used for describing logic.
 An integer is general-purpose variables. They are used mainly loops-indices, parameters,
and constants. They store data as signed numbers, whereas explicitly declared reg types
store them as unsigned. If they hold numbers that are not defined at compile-time, their
size will default to 32-bits. If they hold constants, the synthesizer adjusts them to the
minimum width needed at compilation.
 Real in system modules.
 Time and realtime for storing simulation times in test benches. Time is a 64-bit quantity
that can be used in conjunction with the $time system task to hold simulation time.

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Verilog Modelling Styles

Verilog Design has the capability of designing a module in several coding styles. Depending on
the needs of a design, internals of each module can be defined at four level of abstractions.
Irrespective of the internal abstraction level, the module would behave exactly in the similar way
to the external environment. Following are the four different levels of abstraction which can be
described by the four different coding styles of Verilog language:

Behavioral or Algorithmic level

This is the highest level of abstraction provided by Verilog HDL.

1) A module can be implemented in terms of the desired design algorithm

without concern for the hardware implementation details.

2) It specifies the circuit in terms of its expected behavior.

3) It is the closest to a natural language description of the circuit

functionality, but also the most difficult to synthesize.

Program for implementation of 4:1 MUX using Behavioural Modelling

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module Mux_4to1( input [3:0] i, input [1:0] s, output reg o);

always @(s or
i) begin
case (s)
2'b00 : o = i[0];
2'b01 : o = i[1];
2'b10 : o = i[2];
2'b11 : o = i[3];
default : o = 1'bx;
endcase
end
endmodule
Simulation Result of 4:1 Mux Behavioral level model:

Dataflow level

1) At this level,the module is designed by specifying the data flow.

2) Looking towards the design, one can realize how data flows between hardware registers
and how the data is processed in the design.

3) This style is similar to logical equation. The specification is comprised of expressions

made of input signals and assigned to outputs.

Program for implementation of 4:1 MUX using Dataflow Modelling

module Mux_4to1_df(input [3:0] i, input [1:0] s,output o);

assign o = (~s[1] & ~s[0] & i[0]) | (~s[1] & s[0] & i[1]) | (s[1] & ~s[0] & i[2]) | (s[1] &
s[0] & i[3]);
endmodule

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Simulation Result of 4:1 Mux Dataflow model:

Gate or Structural level :

1) The module is implemented in terms of logic and implementation between

these gates.

2) It resembles a schematic drawing with components connected with

signals.

3) A change in the value of any input signal of a component activates the

component. If two or more components concurrently, they will perform
their actions concurrently as well.

4) A Structural level representation is closer to the physical implementation

than behavioural one but it is involved because of large number of details.
Since logic gate is most popular component, Verilog has a predefined set
of logic gates known as primitives. Any digital circuit can be built from
these primitives.

Program for implementation of 4:1 MUX using Gate level Modelling

module Mux_4to1_gate(input [3:0] i, input [1:0] s, output
o); wire NS0, NS1;

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wire Y0, Y1, Y2, Y3;

not N1(NS0, s[0]);
not N2(NS1, s[1]);
and A1(Y0, i[0], NS1, NS0);
and A2(Y1, i[1], NS1, s[0]);
and A3(Y2, i[2], s[1], NS0);
and A4(Y3, i[3], s[1], s[0]);
or O1(o, Y0, Y1, Y2, Y3);
endmodule
Simulation Result of 4:1 Mux Gate level modelling:

Switch Level Modelling

The switch level of modelling provides a level of abstraction between the logic and analog-
transistor levels of abstraction. It describes the interconnection of transmission gates, which are
abstractions of individual MOS and CMOS transistors.

The switch level transistors are modelled as being either on or off, conducting or not conducting.
The values carried by the interconnections are abstracted from the whole range of analog
voltages or currents to a small number of discrete values. These values are referred to as
signal strengths.

Verilog also provides support for transistor level modelling. However, designers rarely use these
days as the complexity of circuits has required them to move to higher levels of abstractions
rather than use switch level modelling.

Simulation is a technique of applying different input stimulus to design at different times to

check if the RTL code behaves the intended way. Essentially, simulation is well-followed
technique to verify the robustness of the design. It is also similar to how a fabricated chip will be
used in the real world and how it reacts to different inputs.

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Simulation Using Testbench

Simulations are controlled using testbenches. A testbench is an additional Verilog module (not
part of the actual system design) used to generate the appropriate waveforms on the input ports
of the module under test, in order to exercise the functionality of that module. Optionally, the
testbench also monitors the outputs of the module under test, and generates warnings if they
deviate from the expected output values. A testbench is simply a Verilog module. But it is
different from the Verilog code we write for a DUT. Since the DUT’s Verilog code is what we
use for planning our hardware, it must be synthesizable. Whereas, a testbench module need not
be synthesizable. We just need to simulate it to check the functionality of our DUT.

Verilog code for the half adder which is tested using different stimulus in testbench:

module half_adder
(
input wire a, b,
output wire sum, carry
);

assign sum = a ^ b;
assign carry = a & b;

endmodule
Above program illustrates the functioning of half adder. Testbenches are written in separate
Verilog files.Simplest way to write a testbench, is to invoke the ‘design for testing’ in the
testbench and provide all the input values inside the ‘initial block’.
A testbench with name ‘half_adder_tb’ is defined below.in tesbenches port is always empty, i.e.
no inputs or outputs are defined in the definition. Then 4 signals are defined i.e. a, b, sum and
carry. these signals are then connected to actual half adder design using structural modelling.
Lastly, different values are assigned to input signals.

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‘always’ statement is used in the testbench; which includes the input values along with the
corresponding output values. If the specified outputs are not matched with the output generated
by half-adder, then errors will be displayed.
// half_adder_tb.v

`timescale 1 ns/10 ps // time-unit = 1 ns, precision = 10 ps

module half_adder_tb;

reg a, b;
wire sum, carry;
// duration for each bit = 20 * timescale = 20 * 1 ns = 20ns
localparam period = 20;

half_adder UUT (.a(a), .b(b), .sum(sum), .carry(carry));

initial // initial block executes only once

begin
// values for a and
b a = 0;
b = 0;
#period; // wait for period

a = 0;
b = 1;
#period;

a = 1;
b = 0;
#period;

a = 1;
b = 1;
#period;
end
endmodule

Testbench waveform observation:

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Summer Internship Project

Topic: Implementation of 8 x8 asynchronous FIFO memory for efficient
reading and writing operations in two different clock domains.

Theory: Design and Verification of Asynchronous FIFO using Verilog/UVM FIFOs are often
used to safely pass data from one clock domain to another asynchronous clock domain. Using a
FIFO to pass data from one clock domain to another clock domain requires multi-asynchronous
clock design techniques. There are many ways to design a FIFO wrong. There are many ways to
design a FIFO right but still make it difficult to properly synthesize and analyze the design. This
project will detail one method that is used to design, synthesize and analyze a safe FIFO between
different clock domains without using Gray code pointers that are synchronized into a different
clock domain before testing for "FIFO full" or "FIFO empty" conditions.

PROGRAM:
/*Write Enable=wr_en
Write data=wr_data
Write pointer=wr_ptr
wr_clk= clk for wrinting
rd_clk= clock for reading

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wr_rst=reset the memory elements by initiallising all to zero

rd_rst=reset the memory elemets
full= status to show full
empty=status to show empty
rd_data= the data needed to be read out
*/

module fifo(wr_en,wr_data,wr_ptr,wr_clk,wr_rst,rd_en,rd_clk,rd_rst,rd_data,rd_ptr,full,empty);
//INPUT GIVEN FROM TESTBENCHES
parameter RAM_DEPTH=7;
input wr_en;
input rd_en;
input [7:0]wr_data;
input rd_rst,wr_rst;
input wr_clk;
input rd_clk;
integer i;
//OUTPUT
output reg[2:0]wr_ptr=3'b000;
output reg [2:0]rd_ptr=3'b000;
output reg [7:0]rd_data;
output reg full=1'b0;
output reg empty=1'b0;
reg [7:0]mem[RAM_DEPTH:0];
//CLK WHICH IS USED FOR WRITING OPERATION
always @(posedge wr_clk)
begin
if(wr_en)
begin
if(wr_rst)
begin
wr_ptr=3'b000;
rd_ptr=3'b000;
full=1'b0;
for(i=0;i<RAM_DEPTH+1;i=i+1)
begin
mem[i]<=8'h0;
en
end d
else
begin
if((wr_ptr!=3'b111)&&(!full)) // this will check till 110
begin
//$display("data before assign in mem=%h",mem[wr_ptr]);
mem[wr_ptr]<=wr_data;
//$display("data after assign in mem=%h",mem[wr_ptr]);

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 Industrial Training Report VLSI Design

//$display("mem[%b]=%h,full=%b,wr_ptr=%b,data=%h",wr_ptr,mem[wr
_ptr],full,wr_ptr,wr_data);
wr_ptr<=wr_ptr+3'b001;
//$display("Worked full= %b mem[wr_ptr]=%h",full,mem[wr_ptr]);

end
else
if(!full)
begin
$display("i also worked");
mem[wr_ptr]<=wr_data; //this will work for wr_ptr=3'b111
full<=1'b1; //now when full goes one then none of them
work
//wr_en=1'b0;
end

end
end
end

//CLK USED FOR READING OPERATION

always @(posedge rd_clk)
begin
if(rd_en)
begin
if(rd_rst)
begin
wr_ptr=3'b000;
rd_ptr=3'b000;
empty=1'b0;
for(i=0;i<RAM_DEPTH+1;i=i+1)
begin
mem[i]<=0;
en
end d
else
begin
if(rd_ptr!=3'b111&&!empty)
begin
rd_data<=mem[rd_ptr];
rd_ptr<=rd_ptr+3'b001;

end
else
begin
rd_data<=mem[rd_ptr];

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 Industrial Training Report VLSI Design

empty<=1'b1;
//rd_en=1'b0;

end
end
end
end

endmodule

//TESTBENCH
module tb_fifo;
reg rd_en;
reg wr_en;
reg [7:0]wr_data;
wire [7:0]rd_data;
reg rd_clk;
reg wr_clk;
wire [2:0]rd_ptr;
wire [2:0]wr_ptr;
reg rd_rst;
reg wr_rst;
wire full;
wire empty;
//wire [7:0]mem[2:0];
fifo a0(.rd_en(rd_en),
.wr_en(wr_en),
.wr_data(wr_data),
.rd_data(rd_data),
.rd_clk(rd_clk),
.wr_clk(wr_clk),
.rd_ptr(rd_ptr),
.wr_ptr(wr_ptr),
.rd_rst(rd_rst),
.wr_rst(wr_rst),
.full(full),
.empty(empty)
//.mem(mem)
);
always #20 rd_clk=~rd_clk;
always #5 wr_clk=~wr_clk;
initial
begin
{rd_en,wr_en,rd_clk,wr_clk,wr_data,wr_rst,rd_rst}=0;

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Industrial Training Report VLSI Design

#5
wr_en=1'b1;
wr_data=8'hff;
#9
wr_en=1'b1;
wr_data=8'h1f;
#9
wr_en=1'b1;
wr_data=8'h2f;
#9
wr_en=1'b1;
wr_data=8'h3f;
#9
wr_en=1'b1;
wr_data=8'h4f;
#9
wr_en=1'b1;
wr_data=8'h5f;
#9
wr_en=1'b1;
wr_data=8'h6f;
#9
wr_en=1'b1;
wr_data=8'h7f;
#9
wr_en=1'b1;
wr_data=8'h8f;
#9
wr_en=1'b1;
wr_data=8'h9f;
#9
wr_en=1'b1;
wr_data=8'haf;
#9
rd_en=1'b1;
wr_en=1'b0;

end
endmodule

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Industrial Training Report VLSI Design

RESULT:

Plot from 0ns to 100ns

Plot from 100ns to 220ns

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Industrial Training Report VLSI Design

Plot from 220ns to 300ns

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 Industrial Training Report VLSI Design

CONCLUSION
This project has really been faithful and informative. It has made us learn and understand the
many trivial concepts of Hardware Description Language. I have used Mentor Graphics tool
Model PE student edition. It helped me to watch the wave patterns after providing multiple
stimulus, and also this version is free for students. The fast growing VLSI Technology provides
good future and scope of the proposed project. Finally, it has taught us a valuable lifelong lesson
about the improvements and working and interacting in a group. I have received criticism and
advice from engineers and technician when mistakes were made. Throughout the industrial
training, I found that several things are important such as Time management, Goal management,
Critical and Analytical thinking, Keen observation of technical concepts etc.

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