I NV E N TI V E

Universal Verification Methodology

(UVM)

September 2011 – UVM1.1

 UVM Agenda

Introduction to UVM and Coverage Driven Verification

UVM:
• The UVM Library
• Stimulus Generation
• Building Reusable Verification Components
• Testbench Creation Using Reusable Components
UVM Multi-Language and UVM Acceleration
Summary

2
 What is UVM?

UVM is the Universal Verification Methodology

– A methodology and a library that codifies the best practices for
efficient and exhaustive verification.
• A complete, proven solution
– Proven solution, with a success record and large community of users
with methodology knowledge and commitment
– Well-thought-out solution for a wide variety of verification challenges
• Open
– A key motivation for moving to SystemVerilog
– An Accellera standard, supported by Cadence, Mentor and Synopsys
• Enables reuse of verification environments
– Verification IP can dramatically speed-up delivery and improve quality
– A common methodology that also works for other languages
(SystemVerilog, e, SystemC)

3 © 2011 Cadence Design Systems, Inc. All rights reserved.

 UVM is Production Ready
Cadence Verification Methodology Leadership from the Beginning…

2000 eRM Jan

2006URM
2008 OVM Feb 2011 UVM

eVC OVC UVC

Configuration DUT I/F Configuration DUT I/F Configuration DUT I/F

Passive Agent Active Agent Passive Agent Active Agent Passive Agent Active Agent

Sequence_driver Sequencer Sequencer

Monitor Monitor Monitor
Seqs. Seqs. Seqs.
Checks Checks Checks

Coverage BFM Coverage Driver Coverage Driver

OVM 2.1.1
Included: Added: Added:
• Architecture • SystemVerilog support • SV callback enhancements
• Sequences • Architecture • Report catching callback
• Messaging/logging • Sequences • SV end of test enhancements
• Reset/clocking • Factory • Closer to eRM capability
• Common test interface • Configuration mechanism • Register support
• Packaging & code structure • Field automation • Enhanced phasing
Added: • Message macros • Partial TLM2 support
• Module to system reuse • Register pkg (contribution) • Improved configuration and
• Register package (vr_ad) • Integration of AVM base classes command line support
• HW/SW co-verification •TLM Communication Channel • Script for “o” to “u” migration for
• Multi-language interoperability OVM users
4 © 2011 Cadence Design Systems, Inc. All rights reserved.
 UVM and Coverage Driven Verification

• Coverage-driven verification(CDV) combines the

following aspects to significantly reduce the time spent
verifying a design:
– Automatic stimulus generation
– Self-checking testbenches
– Coverage metrics

• Why CDV?
– Eliminate the effort and time to write hundreds of tests
– Ensure thorough verification using upfront goal setting

• UVM provides the framework to achieve CDV

5
 Coverage Driven Verification
• Components of a coverage driven verification
environment
Coverage
– Automated Stimulus Generation
– Independent Checking
– Coverage Collection
Scoreboard
Data Checking

seed
Coverage Monitor Monitor
23098432
38748932
23432239
17821961
10932893
20395483
Random
18902904
23843298 Generation
23432432
24324322
55252255
09273822 Random DUT
Stimulus
13814791
Tests Sequence Driver
4098e092
Tests Generator UART APB
23432424 Generator
24242355
25262622
26452454
24524522

6
 Coverage Driven Verification Flow
Verification • Create a verification plan
Plan
Verification – Based on specification requirements
vPlan
Environment
– Decide what to test and how
Verification • Create smart testbench that:
Architecture
– Generates random legal stimulus
Adjust and Add Assertions,
– Includes assertions and coverage to
Constraints Constraints measure progress against the goals
and Stimulus & Coverage
Sequences – Checks for undesired behavior (BUGS!)
• Implement coverage model based on
Simulation, the verification plan, in place early on
Acceleration,
Emulation • Iteratively run simulations and analyze
coverage
• Adjust constraints and add new
Refine Coverage
Model scenarios targeting coverage holes
Review Coverage
• Refine and enhance the coverage
model
7
 Agenda

Introduction to UVM and Coverage Driven Verification

UVM:
• The UVM Library
• Stimulus Generation
• Building Reusable Verification Components
• Testbench Creation Using Reusable Components
UVM Multi-Language and UVM Acceleration
Summary

8
 The UVM Library
Using inheritance and encapsulation in class libraries

• Three layers of elements

Existing TLM standard for
TLM class communication

Structural Elements
Classes common to most
Methodology methodologies: components,
messages, simulation
phases, etc.

The main user interface that enables

reuse including classes that capture
the high-level methodology and wrap
the low-level classes
9
 UVM Class Hierarchy
(UVM 1.1)
uvm_object
Base class for all UVM name
copy(),
data and hierarchical clone()
uvm_transaction
components …
print()
uvm_sequence_item

uvm_sequence
uvm_report_object
body()
uvm_report_*()

uvm_report_handler uvm_port_base #(IF) TLM

uvm_component uvm_*_export uvm_*_port uvm_*_imp

parent
children
uvm_tlm_fifo uvm_tlm_req_rsp_channel
get/set_config_*(), create ()
uvm_subscriber
build_phase(), uvm_tlm_transport_channel
uvm_tlm_analysis_fifo
connect_phase(),
end_of_elaboration_phase();
uvm_env start_of_simulation_phase();
run_phase(), …… uvm_sequencer
uvm_test
uvm_monitor uvm_agent
uvm_driver
uvm_scoreboard
10
 Using the UVM Class Library

Deriving an environment from the class library allows:

• Exploiting built-in automation
– Sequences … standard & powerful test writer interface
– Built-in factory for rapid reuse
– Transaction manipulation (packing, deep copying etc)
– Flexible automatic test phase interface
– Messaging utilities
• Adhering to a proven methodology
– Modular topology (monitors, drivers, agents)
– Out-of-the box or partial reuse
– TLM communication for language independent modularity
– A powerful component configuration scheme

11
 Where Do I Get UVM?

Download the UVM library from

Option 1
www.uvmworld.org
You will be redirected to
http://www.accellera.org/activities/vip

Option 2 Included in Incisive Release

– Located at: `ncroot`/tools/uvm
– Will contain bug fixes not on UVM world
– Contains Cadence additions to UVM
• Tcl commands
• Transaction recording
• Register generator
• Templates for verification component generation
12
 What the release looks like?
uvm/
UVM_Reference.html UVM Reference Manual
uvm_release-notes.txt UVM Release information
uvm/bin/
ovm2uvm.pl OVM to UVM migration script
uvm/doc/ User Guide and Reference
uvm/src/ UVM source files
base/ low-level library components
comps/ methodology layer (agent, env)
reg/ register package
macros/ macro definitions
seq/ sequence-related code
tlm1, tlm2/ TLM layer components
uvm_pkg.sv `include file required for UVM
uvm.sv
uvm_macros.svh
13
 What the release looks like? (cont.)

uvm/sv/cdns_additions Cadence-specific additions (only

found in the IUS version of UVM)
uvm/examples/ Directories of examples that run on
multiple simulators
simple/ Includes: basic_examples, callbacks,
…… configuration, factory, phases, etc
integ/ more complex UVM examples
xbus/ UVM equivalent of the xbus
examples/ To run on IES: irun –f compile_ius.f
sv/
codec/
apb/

14
 Agenda

Introduction to UVM and Coverage Driven Verification

UVM:
• The UVM Library
• Stimulus Generation
– Modeling Data Items
– Reusable Sequences
• Building Reusable Verification Components
• Testbench Creation Using Reusable Components
UVM Multi-Language and UVM Acceleration
Summary

15
 Modeling Data Items

• Data items
– Represent the main transaction input to the DUT
– Adhering to a protocol, consistent values are generated and sent
– Examples include packets, transactions, instructions, and so on
• Test environment randomizes data items (transactions)
– A default distribution should be generated
– Tests further steer generation by layering constraints or
selecting from pre-defined scenarios
– This makes test short, readable, easier to write and maintain
Test 3
Test 2
Test 1

UVM
Smart Testbench
16
 SystemVerilog Data Item: A UART Frame

class uart_frame;
rand int transmit_delay; Fields to be randomized
rand bit start_bit;
rand bit [7:0] payload;
rand bit [1:0] stop_bits;
rand bit [3:0] error_bits; How will the test-writer
bit parity; request a bad parity frame?

// utility functions parity is calculated using a function

extern function bit calc_parity( );
extern function void print( );
extern function bit compare(uart_frame rhs);
…
endclass: uart_frame

17
 Design for Test-writing using Knobs
typedef enum bit {BAD_PARITY, GOOD_PARITY} parity_e;
class uart_frame;
Can you
Define an find another to
enumeration possible
make it
rand int transmit_delay; easy to describe parity type
rand bit start_bit;
control field in the frame?
rand bit [7:0] payload; Can have zero, short, medium
rand bit [1:0] stop_bits; and long delays
rand bit [3:0] error_bits;
bit parity; Knobs are control fields that
// control fields allow easy user interface
rand parity_e parity_type;
Test writers can specify the
// utility functions
distribution of GOOD vs. BAD
extern function bit calc_parity( );
parity
…
endclass: uart_frame
Extra logic can set the parity based
on the generated parity_type
Recommendation: Think of the desired scenarios and make sure you have the
18
needed control knobs to achieve them
 Data Item Example

class uart_frame;
rand int transmit_delay;
rand bit start_bit;
rand bit [7:0] payload;
bit parity;
rand bit [1:0] stop_bits;
rand bit [3:0] error_bits; User defined function

// Utility functions
extern function bit calc_parity( ); Required for most
transactions!
extern function void print();
extern function bit compare(uart_frame rhs);
…
endclass: uart_frame

19
 Where SV Language Stops and UVM Begins
Example: Data Items
class uart_frame;
bitrand bitstart_bit;start_bit;
[7:0]bitpayload;
bitrand [7:0] payload;
bitrand bitparity; parity;
parity_e
rand parity_e
parity_type;
parity_type;
intrand inttransmit_delay;
transmit_delay;
endclass: uart_frame
Does language alone support all the necessary customization operations?
• Randomization No! Only randomization is defined
• Printing in the SystemVerilog LRM
• Cloning
• Comparing
• Copying UVM provides the rest!
• Packing
• Transaction Recording
20
 Enabling Data Item Automation

class uart_frame extends uvm_sequence_item;

rand bit start_bit;
rand bit [7:0] payload; UVM data items are derived
bit parity; from uvm_sequence_item
rand parity_e parity_type;
rand int xmit_delay; Enables all automation for
uart_frame fields
// *optional* field declarations and automation flags
`uvm_object_utils_begin(uart_frame)
`uvm_field_int( start_bit, UVM_ALL_ON)
`uvm_field_int( payload, UVM_ALL_ON)
`uvm_field_int( parity, UVM_ALL_ON)
`uvm_field_enum( parity_e, parity_type, UVM_ALL_ON + UVM_NOCOMPARE)
`uvm_field_int( xmit_delay, UVM_ALL_ON + UVM_DEC + UVM_NOCOMPARE)
`uvm_object_utils_end
endclass: uart_frame Specify field level flags:
UVM_NOCOMPARE,
21
UVM_NOPRINT, etc.
 Example: Data Type Automation

---------------------------------------
Name Type Size Value
---------------------------------------
my_frame uart_frame - @607
uart_frame frame1, frame2; start_bit integral 1 ’h1
initial payload integral 8 ’hfc
begin parity integral 1 ’h0
frame1 = new(“my_frame”); parity_type parity_e 32 BAD_PARITY
assert(frame1.randomize()); xmit_delay integral 32 ’d382
---------------------------------------
frame1.print();
$cast(frame2, frame1.clone()); Create a new uart_frame
frame2.set_name(“my_frame2”) and copy frame1 to frame2
frame2.print(tree_printer);
end my_frame2: (uart_frame@788) {
start_bit: ’h1
payload: ’hfc
Three built-in printers parity: ’h0
can be used parity_type: BAD_PARITY
xmit_delay: ’d382
}
22
 Transaction Recording in IES
// inside driver or monitor code
uart_frame frame1;
int handle;
...
handle = begin_tr(frame1); // start recording
… // body including timing
end_tr(frame1)); // end recording

SimVision: Automatic
transaction recording.

23
Automatic recording methods built into UVM items
 Messages for Debug & Error Reporting

• Messages
– While developing or using environments, users need to print messages
– $display does not allow non-intrusive filtering and control
– User may want to get trace messages from a suspect component
– Critical to large environment with many verification components
• Error reporting
– The testbench must produce clear and descriptive error messages to
communicate a checker mismatch
– Should affect simulation based on severity
• Error – stop
• Warning – record and proceed
• Allow customization of above

24
 UVM Messaging Facility

Messages print trace information with advantages over $display:

• Aware of its hierarchy/scope in testbench
• Allows filtering based on hierarchy, verbosity, and time

uvm_report_info("PKT", "Packet Sent");

Output time id message body
UVM_INFO @10 uvm_test_top.test.generator [PKT]: Packet Sent
severity scope
• Simple Messaging:
– uvm_report_*(string id, string message);
• Where * (severity) is one of fatal, error, warning, info
• Tips:
– Use get_type_name() to give an id of the class type
– Use $sformatf() to create message string using $display syntax
25
 Messages and Verbosity

uvm_report_info(get_type_name(), $sformatf("addr %h",addr), UVM_LOW);

• Additional argument to uvm_report* defines verbosity

UVM_NONE, UVM_LOW, UVM_MEDIUM, UVM_HIGH, UVM_FULL

• By changing the verbosity maximum, messages can be filtered

– For example, if the verbosity is set to UVM_LOW, all messages coded with
UVM_MEDIUM and higher will not print

Ways to change verbosity without recompiling!

1. Command-line: % irun …. +UVM_VERBOSITY=UVM_NONE
2. Procedural (test): set_report_verbosity_level_hier(UVM_MEDIUM);

26
 Using the UVM Library with Incisive Simulators

• irun allows users to run the simulator by specifying all input files and
command-line options on a single command line.
– Each file is compiled using the appropriate compiler based on the file
extension used.
• Verilog, SystemVerilog, VHDL, e, C and C++
– Command-line options are also recognized and passed to the compiler,
the elaborator and the simulator
% irun -access +r -gui test.sv verify.e top.v sub.vhd
• irun supports UVM-specific options:
-uvm Searches <install_dir>/tools/uvm/src and
sets command-line options to compile the lib
-uvmhome $UVM_HOME Optionally specifies a different directory for
the UVM installation
+UVM_TESTNAME Passes the default test name for run_test()
+UVM_VERBOSITY Sets the verbosity level for UVM messages

27
 Constraint Layering Using the Factory

typedef enum {SHORT, MEDIUM, LONG} delay_t;

// extended class uses control knob for transmit_delay
class delay_frame extends uart_frame; Add control knob to
rand delay_t delay_knob;
constrain transmit_delay
constraint delay_type_c { transmit_delay > 0;
delay_knob == SHORT -> transmit_delay < 10;
delay_knob == MEDIUM -> transmit_delay < 40
delay_knob == LONG -> transmit_delay > 100; }
`uvm_object_utils_begin(delay_frame)
`uvm_field_enum(delay_t, delay_knob, UVM_ALL_ON|UVM_NOCOMPARE)
`uvm_object_utils_end
function new (string name=“delay_frame”); … Registers delay_frame with
endclass: delay_frame the factory

// In the generator class: Replace frame=new();

uart_frame frame; // data item declaration with create (…)
...
frame
frame == uart_frame::type_id::create(“frame”));
new(“frame”); // create a new data item
28
 What is the UVM Factory?

type and instance override list

• Central location to create
from to
class instances on demand uart_frame delay_frame
– Each type is registered with the ... ...
factory
– Instances created via factory Factory
call Class Hierarchy
• Not via class constructor uart_frame
Create uart_frame ? +create

Factory allocates instance delay_frame ? registered types

of required type
uart_frame
delay_frame
– Apply override instructions to factory delay_frame
+create
• Make all uart_frame
instances delay_frame
instead Register type with factory
 Factory Overrides
• Type override replaces ALL instances:-
– For a specific test, replace all uart_frame A uart_frame drv_c
packets with delay_frame packets
B delay_frame drv1_c
set_type_override_by_type(uart_frame::get_type(),
env1
delay_frame::get_type());
agent[0] agent[1]
• Instance override replaces specific seqr seqr
instances: A
B A
B

– Replace uart_frame in agent[0] sequencer driver monitor driver monitor

A
B AB A
B B
A
– Replace agent[1] driver drv_c with
dvr1_c
set_inst_override_by_type("env1.agent[0].seqr", env1
agent[0] agent[1]
uart_frame::get_type(),delay_frame::get_type());
seqr seqr
B
A A
set_inst_override_by_type("env1.agent[1]",
driver monitor driver monitor
drv_c::get_type(), drv1_c::get_type()); A A A
A A
 Agenda

Introduction to UVM and Coverage Driven Verification

UVM:
• The UVM Library
• Stimulus Generation
– Modeling Data Items
– Reusable Sequences
• Building Reusable Verification Components
• Testbench Creation Using Reusable Components
UVM Multi-Language and UVM Acceleration
Summary

31
 Scenario Creation Requirements

• Achieving full coverage using constraint layering is highly

recommended
– The technology evenly selects items from legal ranges
– Efficient in capturing unanticipated bugs
• Many times, single items cannot capture high-level intention
– Ordered streams of transactions are required
– Examples: configuration of a device, program generation
• A sequence is a set of transactions that accomplish a defined
task
• Sequences are provided as part of a reusable component
– Capture important scenarios that should be exercised
• UVM provides an advanced sequence generation mechanism

32
 UVM Sequencer – an Advanced Generator
UVM sequencer
Sequencer
Generator • By default works exactly like a generator
– Generates random transactions on request
We replace the generator
Produces data • Addresses all randomization requirements:
with a sequencer
– random by-default, reactive generation,
i/f
system-level ready, modeling timing, etc
•
sequences User-defined sequences of transactions are
created and executed
i/f
– For example, a user creates a sequence that
Bus Driver
interleaves legal and illegal frames
Consumes and • Test writer sets the sequencer to execute a
send to DUT specific sequence

33
 Sequences Example: UART Retry Sequence

// Send one BAD_PARITY frame followed by a GOOD_PARITY

// frame with the same payload extend from uvm_sequence
class retry_seq extends uvm_sequence #(uart_frame);
// uart_frame req; // built-in data item field Data item
`uvm_object_utils(retry_seq)
Registers the retry_seq with
the factory
rand bit [7:0] pload; // randomizable sequence parameter
...
virtual task body ( ); // sequence behavior
`uvm_do_with(req, {payload == pload; parity == BAD_PARITY;} )
`uvm_do_with(req, {payload == pload; parity==GOOD_PARITY;} )
endtask : body
endclass body() can also include time consuming
statements, fork…join, function calls, etc
34
 The ‘uvm_do’ Operation
…
virtual task body (); // sequence behavior
`uvm_do_with(req, {payload == pload; parity == BAD_PARITY;} )
endtask
Reactive generation

• Translates into: • Combines procedural and

declarative (constraint layering)
– Wait till item is requested directives
– Create items using a factory • Factory support out-of-the-box
– Randomize (with constraints or not)
– Return the item to the requester Inline constraints for
– Block code execution till item_done() additional control

• Allows modeling timing • built-in TLM to allow reuse

• e.g. scenario that calls for and support multi-language
a frame, wait for FIFO full communication
New and expert users deploy all key randomization concepts!
and do illegal frame
35
 Nesting Sequences

// call retry sequence wrapped with random frames

class rand_retry_seq extends uvm_sequence #(uart_frame);
`uvm_object_utils(rand_retry_seq)

retry_seq retry_sequence; Using a previously

defined sequence

virtual task body (); // executable sequence behavior

`uvm_do (req)
`uvm_do_with(retry_sequence , {pload inside {[0:31]};})
`uvm_do(req)
endtask Create and randomize a
retry_seq sequence and
endclass
call it’s body

36
 Sequence Execution

Sequencer
// Sequence: retry_seq
// Sequence: rand_retry_seq class retry_seq extends uvm_sequence #(…);
class rand_retry_seq extends … // uart_frame req; // built into base seq
//uart_frame req; //built into seq rand bit[7:0] pload;
retry_seq retry; virtual task body ();
virtual task body (); `uvm_do_with(req, {payload ==pload;
`uvm_do(req) parity==BAD_PARITY;})
`uvm_do_with(retry, {pload `uvm_do_with(req,{payload==pload;
inside {[0:31]};)) parity==GOOD_PARITY;})
`uvm_do(req) endtask
endtask endclass
endclass

get_next_item()
get_next_item()
item_done()

Driver
37
 Controlling Sequencer Behavior
• How do we control which sequences run on a UVC
sequencer and when?
1. run_phase() (and every run sub-phase) has a default_sequence
property.
• Set default_sequence to a sequence to execute in that
phase.
// Test: Set uart_tx_sequencer to use retry_seq as the default sequence
uvm_config_db#(uvm_config_wrapper)::set(this,"uart_tx_sequencer.run_phase
", "default_sequence",
retry_seq::type_id::get());

2. Execute a sequence directly on a UVC sequencer from a test class, by

calling the sequence’s start method

3. Group sequences into a sequence library; Set default_sequence to

execute the sequence library

38 Notes: 2 & 3 will be covered in UVM Training class

 The UVM Driver
Pulls transactions from the sequencer and drives the DUT interface

class uart_tx_driver extends uvm_driver #(uart_frame);

Sequencer
// uart_frame req; // built-in field Derived from
uvm_driver
Produces data `uvm_component_utils(uart_tx_driver)

i/f virtual task get_and_drive(); Main control loop

forever begin
seq_item_port.get_next_item(req);
send_tx_frame(req);
i/f
seq_item_port.item_done (); Interface to the
Driver end sequencer via TLM
endtask

Consumes and virtual task send_tx_frame(input uart_frame cur_tx_frame);

send to DUT ...
endtask
endclass Drive interface signals
following the protocol

39
 Agenda

Introduction to UVM and Coverage Driven Verification

UVM:
• The UVM Library
• Stimulus Generation
• Building Reusable Verification Components
– Concepts for reuse
– Reusable environment topology
• Testbench Creation Using Reusable Components
UVM Multi-Language and UVM Acceleration
Summary

40
 Creating a Reusable Verification Environment

UVM Testbench BUS UVC

• Tasks to be done:
Mon
Mon
BFM
BFM – Apply stimulus on each external interface
Module VC
SEQR – Coordinate stimulus across multiple ports for
Scoreboard system-level scenarios
Mon DRV
coverage
VC3
– Emulate the CPU by reading and writing device
registers
• Issues:
Project1 DUT
– How do we model complex environments?
Generation? Checking? Coverage?
Multi Channel Sequence Generator

– How do we facilitate reuse?

CPU Mem
• Solution: “divide and conquer”
– Create a reusable verification component per
interface
Periph Periph – Following the protocol, each component:
• Stimulates the interface
• Checks for protocol correctness
• Collects coverage
Mon BFM Mon BFM
Mon
Mon
BFM
DRV
Mon
Mon
BFM
DRV
– Add a mechanism for multi-channel traffic
generation
SEQR SEQR
– Create end-to-end checker and coverage
Protocol2
VC3 UVC
collector
Protocol1
VC3 UVC
41
 Packaging UVM Components for Reuse

• UVM methodology combines all components Coverage

for a single interface into a reusable package

Scoreboard
Data Checking

Monitor Monitor
Coverage

seed
23098432
38748932
23432239
17821961
10932893
20395483
Tests
DUT
18902904
23843298
Tests Sequencer Driver UART APB
23432432
24324322
55252255
09273822
Packaged for reuse

42
 Reuse at the System Level
• Configure APB UVC as passive:
– Monitor still collects coverage
Coverage
• New blocks are added as they are developed
• Reuse of scoreboard for checking
Scoreboard
Checking
Passive Coverage

Coverage Monitor Monitor

AHB to APB
Random DUT
Tests
Tests Sequence Driver
APB UART
Bridge
Generator
Reusable Component
43
 Reusable Environments: Main Players

• Contributors have different skill sets and responsibilities

• Who are they?
– Reusable component developers
• Experts in protocol knowledge and verification
– Environment integrators
• Build test environments using reusable components
• Less protocol knowledge, more target system knowledge
– Test-writers
• May have little verification expertise
• UVM allows each contributor to focus on his responsibilities and be
productive quickly

Note: At times the same person is doing two or all the roles above

44
 Facilitating Reuse

Testbench Mon BFM • Create a components repository

Mon BFM
Mon DRV

SEQR • Reuse existing components for next project

VC3
VC2 – Can use various languages based on needs
and preferences
Multi Channel Sequence Generator

• New components are added as needed

Project2 DUT
• Over time, components repository grows
and matures
Periph
– Proven on multiple projects
– Becomes a major company strength!
Periph
VC Repository
Mon BFM Mon BFM Mon BFM
BUS
Mon
VC
BFM
Mon BFM Mon BFM Mon BFM Mon BFM
Mon DRV Mon BFM Mon DRV
Module VC Mon
Mon
BFM
BFM
Mon DRV
SEQR
SEQR SEQR SEQR
Scoreboard Mon DRV
SEQR
VC3 VC3
eVC VC3
VC2 VC3
coverage
VC3

45
 Coverage and Checking

Sequencer • From where should we collect

coverage?
Produces data • Neither the sequencer nor the driver
i/f
are the ideal option
– What if we want to monitor an interface
that we do not drive?

i/f
• For this we need a third component
Driver called a “Monitor”
Consumes and
send to DUT

46
 The Monitor

• Monitor
– A passive component that collects information on a monitored
interface
– Builds abstract transactions
– Contains events, status, checkers and coverage
• Protocol specific
• Passive entity Monitor

– Never drives signals!

Checking and
• Monitor is independent of the driver! coverage
– May need to monitor information driven
by the testbench

47
 The UVM Monitor – Coverage Implementation
class uart_monitor extends uvm_monitor; Derived from uvm_monitor
`uvm_component_utils(uart_monitor) and registered with the
uart_frame frame; // data item to be collected factory

covergroup uart_trans_frame_cg;
NUM_STOP_BITS : coverpoint frame.nbstop {
bins ONE = {0};
bins TWO = {1}; Implement coverage
} model based on your
DATA_LENGTH : coverpoint frame.char_length { …} verification plan
PARITY_MODE : coverpoint frame.parity_mode { … }
endgroup
function new (string name = "", uvm_component parent = null);
super.new(name, parent);
uart_trans_frame_cg = new();
new() covergroup in the constructor
endfunction: new
task collect_frame ( ); Task to collect data items
// Collect uart data from interface from the DUT interface
uart_trans_frame_cg.sample();
endtask: collect_frame Sample coverage when
endclass: uart_monitor frame is collected
48
 Creating Assertion/Formal-Ready Interface
Components

• Assertions are useful for dynamic simulation

– Can identify overlooked issues
• DUT and reference model can be wrong
– Can significantly reduce debug time vs. end-to-end checkers
• Can be leveraged in formal verification
– Another efficient, complementary path to discover bugs
– Can be exploited before a dynamic environment exists
• Interface UVCs are protocol specific
– Ideal place to capture protocol assertions inside
• UVM introduces a unified flow for dynamic and formal
verification

49
 UVM Assertions Methodology
The methodology was designed to: Env Immediate assertion
• Combine upfront planning and (UVC) Agent
checks in the monitor
assertions development into your Agent
flow Agent
• Instantiate and control assertions Sequencer
Config:
• Reuse assertions active_passive sequences

• Between projects tlm i/f

• Across teams (designers,
verification engineers, etc) tlm i/f
tlm i/f
Monitor
• Using multiple technologies
Coverage Driver
• Measure thoroughness using Checking
assertions vif vif

Concurrent assertions
reside in the SV interface I/F

DUT
Ask us for information or T=training
on UVM and Assertions
50
 Agenda

Introduction to UVM and Coverage Driven Verification

UVM:
• The UVM Library
• Stimulus Generation
• Building Reusable Verification Components
– Concepts for reuse
– Reusable environment topology
• Testbench Creation Using Reusable Components
UVM Multi-Language and UVM Acceleration
Summary

51
 Consider This: Your Next Verification
Challenge!
Trace Port SDRAM SDRAM
SRAM ROM Flash LCD Display
Analyser Bank 0 Bank 2
SDRAM SDRAM
Bank 1 Bank 3

PC Cards
MOVE Static Vectored
SDRAM Memory Color
Interrupt DMA
Controller Interface LCD
Control M M S
ETM

ARM926 PCMCIA
CPU Host

ARM I AHB
ARM D AHB
LCD AHB
DMA 1 AHB (Periph)
SRAM Our new
Buffer
DMA 2 AHB (Memory)
EXPANSION AHB
system
specs are
Core APB DMA APB MPEG-4
Engine
Colour
Convert in the mail
AHB/ AHB/ SSP
WATCHDOG TIMERS
APB APB
Camera
Interface
Camera
GPIO (x4) RTC SYSTEM
GPIO x4 UART SIM Card USB Camera
CONTROL Interface Control

Clk/Reset Trans-
Generator ceiver
32KHz
32 GPIO CLK
lines PLL
Xtal Osc Xtal Osc

USB Connection
to PC

Scalability is a must! Class level

52 reuse is not enough!
 The Solution: Agents
• Agents provide all the verification logic
uvm_agent for a device in the system
uvm_
• Instantiation and connection logic is
Config: sequencer done by the developer in a standard
manner
sequences
– Integrator does not need to worry about
seq_item_export this
• A standard agent has:
uvm_monitor
seq_item_port – Sequencer for generating traffic
events, – Driver to drive the DUT
status, uvm_driver
data – Monitor
vif vif • Note: that the monitor is independent of
the driving logic to allow a passive
operation mode
interface • Agent has standard configuration
DUT parameters for the integrator to use
53
 Agent Standard Configuration

• A standard agent is configured using

uvm_agent
an enumeration field: is_active
Config: uvm_
is_active: sequencer UVM_ACTIVE:
UVM_PASSIVE
UVM_ACTIVE • Actively drive an interface or device
sequences
• Driver, Sequencer and Monitor are
seq_item_export allocated
passive
uvm_monitor seq_item_port UVM_PASSIVE:
events, • Only the Monitor is allocated
status, uvm_driver • Still able to do checking and collect
data coverage
vi vi

interface
DUT
54
 Creating the Agent Derived from uvm_agent

class master_agent extends uvm_agent; Configuration field

uvm_active_passive_enum is_active = UVM_ACTIVE;
UVM field declaration for
library automation
`uvm_component_utils_begin(master_agent)
`uvm_field_enum(uvm_active_passive_enum, is_active, UVM_ALL_ON)
`uvm_component_utils_end
// agent sub component instances
master_driver driver; Using the constructor to allocate the
master_sequencer sequencer; sub-instances is problematic
because new() is not polymorphic
master_monitor monitor;
function new( input string name, input uvm_component parent);
super.new( name, parent); agent
// create the sequencer, driver and monitor sequencer
Config:
monitor = new (“monitor”,this); Is_active sequences
if (is_active == UVM_ACTIVE) begin
driver = new(“driver”,this); monitor
sequencer = new(“sequencer”, this); events,
end status, driver
data
Allocation using new() forces a
endfunction vi vi
re-write when modifications are
endclass required
55
 Creating the Agent Using build_phase() Method
class master_agent extends uvm_agent;
active_passive_enum is_active = UVM_ACTIVE;
`uvm_component_utils_begin(master_agent)
`uvm_field_enum(active_passive_enum, is_active, ALL_ON)
`uvm_component_utils_end
// agent sub component instances
master_driver driver;
master_sequencer sequencer; Constructor is still required
master_monitor monitor;
function new(input string name, input uvm_component parent);
super.new(name, parent); Use the build_phase() method to
endfunction allocate components and address
virtual function void build_phase(uvm_phase phase); the polymorphism requirement
// Allocate sequencer, driver and monitor here
endfunction
virtual function void connect_phase(uvm_phase phase);
// Make TLM connections here
Use the connect_phase() method
endfunction to make TLM connections between
endclass the sub-components

56
 The Agent build_phase() and connect_phase()
class master_agent extends uvm_agent;
... class v2_mdriver extends master_driver;
// agent sub component instances // add attributes + override virtual methods
master_driver driver; endclass
master_sequencer sequencer; // syntax for introducing the new driver – in test
master_monitor monitor; master_driver::type_id::set_type_override (
... v2_mdriver::get_type());
virtual function void build_phase(uvm_phase phase); Use the factory to override
super.build_phase(uvm_phase phase); the driver for a specific test
// create sequencer, driver and monitor Call super.build_phase(…)
monitor = master_monitor::type_id::create( “monitor”, this);
if (is_active == UVM_ACTIVE) begin
driver = master_driver::type_id:: create(“driver”, this);
sequencer = master_sequencer::type_id::create(“sequencer”, this);
end Use create() for factory
endfunction allocation
virtual function void connect_phase(uvm_phase phase);
driver.seq_item_port.connect(sequencer.seq_item_export);
endfunction
Standard TLM mechanism for connecting
endclass the driver and sequencer
57
 Allows changing the number
Example: Bus SomeEnvironment
agent config of agents without further
parameters come from configuration per agent
Environment the environment config
master agent Config:
master agent slave agent num_masters=3
master agent
sequencer slave agent arbiter agent num_slaves=2
sequencer sequencer
Config: sequencer sequencer sequencer
Config: Config: Virtual
Config: Config: Config: interface
seq
seq seq
i/f seq
vi seq seq
i/f vi i/f vi
i/f i/f i/f
monitor
monitor monitor
monitor i/f monitor monitor monitor
i/f i/f
events, i/f i/f i/f
events,
status, events,
events,driver
status, events,
status, events,
events,
data driver status,
driver status,
status,
data driver data driver driver
data
status,
vi data vi data
vi vi vi vi data
vi vi vi vi vi vi vi

Bus level monitoring can

interface
Envs allow reuse at the interface level! be used by all agents
58 DUT
 Simulation Phases and Coordination

• When moving to classes you need to manage

environment creation at run-time …
• Test execution is divided to phases
– Configuration, testbench creation, run-time, check, etc
• Unique tasks are performed in each simulation phase
– Set-up activities may be performed during “testbench creation”
while expected results may be addressed in “check”
– Phases run in order – next phase does not begin until previous
phase is complete
• A set of standard phases enables VIP plug & play
– Allows orchestrating the activity of components that were
created by different resources

59
 Simulation Phases and Coordination
Simulation Phases
What if UVC1 starts Now we can start build_phase
sending traffic right sending traffic connect_phase
after build_phase()?
end_of_elaboration_phase
start_of_simulation_phase
run_phase
UVC1 DUT UVC2
extract_phase
check_phase
report_phase
Can this VC check for non-
empty scoreboard?
Environment was not fully UVC3
Not yet! All components must finish
elaborated yet!
their run phase first!
Must wait for run_phase()
Now can check
scoreboards
60
 UVM Simulation Phases
UVM component’s built-in phases – run in order
All phases except run_phase()
Execute in zero time
build_phase
build Build Top-Level Testbench Topology
connect_phase
connect Connect environment topology
end
end of elaboration Post-elaboration activity (e.g. print topology)
of elaboration_phase
start_of_simulation Configure verification components
start_of_simulation_phase
run_phase
run task – Run-time execution of the test
extract_phase
extract Gathers details on the final DUT state
check_phase
check Processes and checks the simulation results
report_phase
report Simulation results analysis and reporting

61 © 2011 Cadence Design Systems, Inc. All rights reserved.

 UVM Run-Time Phases
Time consuming and run in parallel to run_phase

build_phase pre-reset Allow components to

perform operations
reset related to reset
connect_phase
post-reset

end of elaboration_phase Perform operations

pre-configure related to device
start of simulation_phase configure configuration (register
settings and more)
post-configure
run_phase
Defines the normal
pre-main operation of the
extract_phase main component for the
bulk of the test
post-main
check_phase
Data can “drain” from
pre-shutdown
report_phase the device and other
shutdown operations for
finalize post-shutdown graceful termination

62 © 2011 Cadence Design Systems, Inc. All rights reserved.

 Agenda

Introduction to UVM and Coverage Driven Verification

UVM:
• The UVM Library
• Stimulus Generation
• Building Reusable Verification Components
• Testbench Creation Using Reusable Components
– Controlling verification environment
– Automating environment creation with IVB
UVM Multi-Language and UVM Acceleration
Summary

63
 Testbench Environment (TB)

module top ( );
• Separate the env configuration
class test extends … and the test
class tb extends uvm_env…
BUS
Mon UVC
BFM
– TB class instantiates and configures
Mon BFM

Module VC SEQR
reusable components
Scoreboard
coverage
Mon
VC3
DRV
• Specific tests are built on top of
testbenches (tbs)
DUT – Specify the nature of generated traffic
Multi Channel Sequence Generator

CPU Mem – Can modify configuration parameters

as needed
• Benefits
Periph Periph
– Tests are shorter, and descriptive
– Less knowledge to create a test
Mon
Mon
BFM
BFM
Mon DRV
Mon
Mon
BFM
BFM – Easier to maintain – changes are done
Mon DRV

SEQR
in a central location
SEQR

UVC1
VC3 UVC
VC32

64
 Using a tb for Multiple Tests

• A single tb describes the tb If config needs to be

testbench topology and changed, no need to
run-time settings visit all tests
• Multiple tests instantiate
this testbench

Test1
Test2
- Use only legal frames
• Tests determine the
Test3 nature of the generated
Use zero frame delay
sendTest4
- Do not Have out-of-order
Send long
4 masters
Back-to-back short
frame streams
traffic
frames frames
Change the clock speed
Send many illegal frames

65
 The Test Launching Mechanism

test3 module top

`include …. // uvm lib, test, and components
tbtest2
tbtest1 IF IF IF rst clks
env
tb
env
env
env Creates the test and
env DUT
env
env starts the simulation
env
phasing mechanism
initial begin
run_test(“test1”); for all components
virtual task run_phase();
… end
endtask

endmodule : top
Multiple tests DUT snapshot

Allows execution Compile the entire

of multiple teststest
on suite together
the same and use
snapshot
command-line option to select a test:
% irun –f run.f +UVM_TESTNAME=test3
66
 Testbench Example

class uart_ctrl_tb extends uvm_env;

`uvm_component_utils(uart_ctrl_tb)
Extends from uvm_env
apb_env apb0; // APB UVC
uart_env uart0; // UART UVC
uart_ctrl_env uart_ctrl0; // Module UVC Configure using wildcards
Minimal effort and
virtual function void build(); component knowledge
super.build(); required
uvm_config_db#(uvm_bitstream_t)::set(this,“apb0.master*”,
“is_active”, UVM_ACTIVE);
uvm_config_db#(uvm_bitstream_t)::set(this,“uart0.tx”, “is_active”,
UVM_ACTIVE);
uvm_config_db#(uart_ctrl_config)::set(this,“uart_ctrl0”, “cfg”, cfg);
apb0 = apb_env::type_id::create(“apb0”, this); Create and build using
uart0 = uart_env::type_id::create(“uart0”, this); standard mechanism
uart_ctrl0 = uart_ctrl_env::type_id::create(“uart_ctrl0”, this);
endfunction
endclass
67
 How a Test Uses a UVM Testbench?
class apb_uart_rx_tx extends uvm_test; Extends from uvm_test
`uvm_component_utils(apb_uart_rx_tx)

uart_ctrl_tb uart_ctrl_tb0; //testbench

virtual function void build_phase(uvm_phase phase); Configuration information
super.build_phase(phase); specific for this test
// Set the default sequence for master
uvm_config_db#(uvm_object_wrapper)::set(this,“uart_ctrl_tb0.apb0.master.
sequencer.run_phase",“default_sequence",
"read_modify_write::type_id::get()");
//Construct and build the uart_ctrl_tb0 environment
uart_ctrl_tb0 = uart_ctrl_tb::type_id::create(“uart_ctrl_tb0”, this);
endfunction: build_phase
Test creates and builds
virtual task run_phase(uvm_phase phase); the testbench
uvm_top.print_topology();
… run() task is optionally used for run-
endtask time test control or status. e.g.,
endclass: apb_uart_rx_tx print dynamic testbench topology
68
 Multi-Channel Sequences

• So far, we have seen how to control stimulus for a single

channel (interface)
– Create a sequencer
– Create and register sequences
• In a verification environment, we need to coordinate
traffic on multiple interfaces in parallel
– Coordinate data and time
– “After finishing configuring the device send Ethernet traffic”
• Multi-channel sequences are called virtual sequences
– Single procedural thread to control multiple interfaces
– Can create reusable system-level sequences

69
 Multi-Channel Sequences
class u2a_incr_payload extends uvm_sequence;
. . .
virtual task body();
`uvm_do_on (config_dut,
uart_ctrl_env p_sequencer.p_apb_seqr);
fork
virtual_sequencer
config_dut `uvm_do_on(uart_incr_seq,
u2a_incr_payload p_sequencer.p_uart_seqr);
uart_incr_seq `uvm_do_on(apb_rd_rx_fifo,
p_apb_seqr
p_sequencer.p_apb_seqr);
p_uart_seqr
apb_rd_rx_fifo join
endtask

uart_env apb_env
uart_agent apb_agent
uart_sequencer apb_sequencer
seq
config_dut
uart_incr_seq seq
rd_rx_fifo

Driver Driver

70
 Determining End-of-Test Each UVC and the virtual
sequencer have a list of
Virtual Sequencer executable sequences
coordinates traffic on
UVC1 and UVC2 virtual ...
sequences fork
`uvm_do_on(ovc2_seq1, ovc2)
Virtual `uvm_do_on(ovc1_seq3, ovc1)
vseq2
Sequencer Join
...

UVC1 UVC2 sequences

sequences
agent mon mon agent
ovc1_seq3
DUT ovc2_seq1

seqr drvr drvr seqr

Sequences (and virtual

How do we decide
sequences) can be nested.
when to end a test?
UVC3
We can’t just rely on the sequences Reactive: runs forever, serving
agent mon
virtual sequence because ovc3_seq1 requests as they appear
other sequences may be seqr drvr
executing in parallel
71
 Raising and Dropping Objections
class retry_seq extends uvm_sequence#(uart_frame);
...
task body();
`uvm_info(get_type_name(), “Executing retry_seq", UVM_LOW)
starting_phase.raise_objection(this, “retry_seq");
`uvm_do_with(req, {payload == pload; parity == BAD_PARITY;} )
...
starting_phase.drop_objection(this, " retry_seq ");
endtask
endclass

• starting_phase is a pointer to the phase in which the sequence is executed

• Objections are handled hierarchically
– Every component has a objection count (phase_done) for every run phase
– Both raised and dropped objections propagate up the hierarchy
– When the uvm_top objection count for a phase returns to zero, the phase
can end
• Not all sequences should raise objections
– Not appropriate for background traffic, response generators, sub-sequences
etc.

72 21 December 2011 Cadence Confidential

 Drain Time
• When all raised objections are dropped, simulation is stopped
• A drain time allows propagation of outstanding items (e.g., DUT
response)
– If no drain time is set, the test will stop immediately
• Drain time can be set as:
– Absolute delay by calling set_drain_time for a specific phase
• Usually from a test class
task run_phase(uvm_phase phase);
. phase.phase_done.set_drain_time(this, 200ns);
endtask : run_phase

– Event delay by defining method all_dropped in env or other

component
• Automatically called when objection count for component returns to 0.
task all_dropped (uvm_objection objection, uvm_object source_obj,
string description, int count)

73 21 December 2011 Cadence Confidential

 Agenda

Introduction to UVM and Coverage Driven Verification

UVM:
• The UVM Library
• Stimulus Generation
• Building Reusable Verification Components
• Testbench Creation Using Reusable Components
– Controlling verification environment
– Automating environment creation with IVB
UVM Multi-Language and UVM Acceleration
Summary

74
 IVB – About the Incisive Verification Builder
What is IVB ?

• Incisive Verification Builder (IVB) is a GUI-based tool

– Automates the process of creating reusable multi-language
verification environments from the interface-level to the system-
level
• Creates UVM-compliant Verification Component skeleton
– UVC architecture, including agents, data-items, sequencers,
driver, monitor, tb, test
• Specifies (via NOTES) where to add protocol-specific
implementation code
• Produces a working example on how to use the UVC in a
simulation environment

75
 Automated Creation of UVCs with IVB

76
 Agenda

Introduction to UVM and Coverage Driven Verification

UVM:
• The UVM Library
• Stimulus Generation
• Building Reusable Verification Components
• Testbench Creation Using Reusable Components
UVM Multi-Language and UVM Acceleration
Summary

77
 UVM Multi-Language (ML) – Enable Mixed-Language Env

“UVM” is an umbrella term for

environment construction and
reuse methodology + libraries

OOP AOP

UVM VM
U VM
U
System
All libraries are open
SystemC Verilog e
source under the
Apache license

SysC SV e
Methodology includes TLM
communication between implementations

Proven methodology independent of language

Built-in language interoperability

78 December 21, 2011 Cadence Confidential

 UVM Enables Mixed-Language Verification
Reduces risk and unifies SoC verification teams

• Single UVM methodology for

e SV
UVC
SystemVerilog, e and SystemC
UVC UVC

SoC
• Unifies VIP for reuse
SC
UVC
SC
UVC
• Choose best language for
application and group skills
C/C++ SV VMM
VIP VIP VIP

• Enables companies to choose

best verification solution

79
 UVM for acceleration
Extending agents for acceleration
UVMUVM
Acceleration
Simulation
Agent
Agent
• Cadence provides
– UVM library extensions: UVM_Accel
Simulator

Monitor
Monitor Sequencer
Sequencer
events, sequences
Coverage
status,
Checking
data
sequences
– Methodology
Simulator

– Examples
SoftwareSoftware

Collector Driver
• Support SV and e
Collector
UVM ACCEL mode
Driver
UVM ACCEL mode

VIF
SCE-MI VIF
SCE-MI
• Enables verification re-use
PROXY PROXY
between simulation and
acceleration
Hardware Accelerator

I/F
I/F I/F
(collector_bfm) (driver_bfm)

DUT
DUT

80
 The Software – HDL Interface
SCE-MI 2.0 modules
• scemi_input_pipe
• scemi_output_pipe

Simulator Clock
Accelerator

Driver
UVM (HVL)

Sce-mi modules
SCE-MI DUT
Pipes Proxy

Testbench
2.0 BFM
Interface (HDL)
UVM

(RTL)
Trans- signal-level
SCE-MI pipe C
actions interface
HDL Side API interface

Cadence
Host PdXP
Workstation

81
 SimVision - Advanced UVM Analysis and Debug

• UVM-aware dynamic object

debug
– Debug testbench configuration
and hierarchy
– Set breakpoints
• Step in, step through classes
– Flexible TCL to manipulate
testbench at run-time
• UVM transaction analysis
– UVM transaction recording
– Stripe chart
• Debug constraint conflicts
– Identify over-constrained
issues
– Interactively reduce constraints
and randomize on the fly

82
 Design Browser

Icon for UVM data

members Click on icon
will “route” to Design
Browser

83
 Methods Tab

Methods Tab of the

displayed UVM
Component

84
 Interactive Sequence Debug
Callstack Viewing

• When stopping a breakpoint, you can use the “callstack”

sidebar to see where your method was called from and
to traverse the callstack.

85
 Transaction Stripe Chart (TSC)

86
 When there is a constraint solver failure, a new
Constraint Debugger constraint debugger window is created for
showing random variables and constraints
associated with the class instance.

87
 Constraint Debug At the top of the window is a toolbar which has
buttons that allow the user to create or delete a
new constraint.

This portion lists

This portion
the constraints for
lists the
the object. This
variables and
displays the
their values. All
constraint name
variables are
and the first line of
listed in the
the constraint
object since
from the source
state variables
file.
can be used in a
constraint.

Source view region will show the selected rand

variables and constraints in context.

88
 Constraint Debug – Dynamic Analysis
Show All constraints

Click to add new constraints

Click to disable constraint

Do a “run –rand_solve” for this

instance

With refined
constraints,
constraint
solver success
now.

89
 Agenda

Introduction to UVM and Coverage Driven Verification

UVM:
• The UVM Library
• Stimulus Generation
• Building Reusable Verification Components
• Testbench Creation Using Reusable Components
UVM Multi-Language and UVM Acceleration
Summary

90
 What Have We Seen Today?

• Introduction to coverage-driven verification concepts

• Using UVM methodology and the UVM library to:
– Accelerate CDV environments creation
– Build reusable environments (and not only reusable classes)
• Ways to automate the verification process and achieve
plan-driven verification
• Deploying the concepts and technology above allow
you to:
– Significantly shorten your verification cycle
– Get better leverage of your entire team
– Improve the overall quality of your DUTs

91
 Beyond UVM …
Inside the Incisive Platform

• Unique Metrics Driven Methodology around UVM

• Scalable register & memory modeling package
– reg_mem downloadable from uvmworld.org/contributions.php
• Only proven plan-based verification management solution
• VIP plug & play with module-based SystemVerilog and eRM
– Mixed-language methodology and automation
• Best simulation, formal, and hardware verification engines
• Wizards for environment creation (IVB)
• Transaction level dynamic environment debug
Over 200 worldwide verification Applications Engineers with
Plan-to-Closure and methodology expertise to ensure
successful project deployment

92
 Useful Websites…

• UVM World Website:

http://uvmworld.org
– Download latest version of UVM library, join the Community Forum to share
ideas and have discussions with other UVM users
• Cadence User Community Website:
http://www.cdnusers.org
– Share ideas and have discussions with other Cadence tool users
• Cadence Educational Services Offerings:
http://www.cadence.com/support/education/index.aspx
• SystemVerilog Advanced Verification using UVM
• SystemVerilog Language and Application

93
 Learning more…

• A Practical Guide to Adapting the Universal

Verification Methodology (UVM), by Sharon
Rosenberg and Kathleen A Meade

• UVM Reference Flow

http://uvmworld.org /uvm-reference-flow.php
– An open-source contribution by Cadence Design systems, Inc.
– Providing a UVM reference for users to train and learn
– Enabling a uniform environment for executing UVM code
– Establishing a standardized solution for benchmarking
– Demonstrating the features provided with UVM Verification
Components (UVCs)

94
 Thank You!

95