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IC package physical
design best practices
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IC Package physical design best practices
Today’s heterogeneously
integrated semiconductor
A heterogeneously integrated design includes two or
packages represent a more ASIC dies, or chiplets, integrated into a single
breakthrough technology package – where a chiplet is defined as an ASIC die
specifically designed and optimized for operation
that enables dramatic within a package in conjunction with other chiplets.
increases in bandwidth and Historically IC package design has been a relatively
simple task which allowed the die bumps to be
performance with reduced fanned out on a package substrate with a floorplan
geometry suitable for connecting to a PCB. But today
power and cost compared the industry is moving to disaggregation of tradi-
tional monolithic SoC functions into chiplets, often
to what can be currently interfaced with local high-speed memory to avoid
silicon reticle limits and yield challenges. Today’s
achieved in traditional packages are now complex systems containing
monolithic (single ASIC die high-speed, chiplet-to-chiplet interfaces, using
specifications like UCIe and BoW along with high
in a package) SoC designs. bandwidth memory (HBM) – all heterogeneously
integrated on a high-performance substrate.
To efficiently design these new types of packages,
designers and design teams need to embrace an
emerging set of best practice design techniques,
processes and methodologies.
These best practices are defined as:
• Achieving substrate supplier’s fabrication
requirements
• Shifting-left “big-rock” power delivery analysis
• Adopting efficient integration methodologies
for HBM memory
• Leveraging concurrent team design
• Utilizing physical design IP reuse
• Designing daisy-chain test vehicles efficiently
• Using datapath planning and routing
Example of a heterogeneously integrated device with 47 chiplets.
Image Source: Intel
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IC Package physical design best practices
Achieving substrate supplier
fabrication requirements
Creating large metal filled areas incurs the risk of challenge. Further, the diversity of substrate tech-
substrate manufacturing issues. Often designers nologies from numerous vendors means there’s no
are amazed at the diversity of requirements one-size-fits-all solution.
fabricators have for metal filled areas in advanced There are three methodologies that are typically
package designs. used by designers to mitigate or control
Package fabricators have strict metal fill require- these issues:
ments that address two main issues. First, the • Hatched filled metal areas with layer offsets
dielectric and metal layers can be very thin, 15 µm
• Outgassing void pattern insertion
or less, and during the build-up and redistribution
• Dummy metal fill insertion
layer creation processes they can suffer from areas
of delamination due to trapped pockets of gas. These are the most common methods to achieve the
Second, uneven conductor densities on the same substrate fabricators requirements for metal areas
layer or across layer pairs can cause warpage in the and planes in advanced package designs, such as
package and/or the wafer. As a result, substrate interposers, high-density-fan-out wafer level pack-
fabricators do not like solid metal planes or large ages and high pin count flip-chip BGAs.
metal areas. To avoid such issues, they typically
Xpedition Package Designer has proven automated
provide designers with strict metal fill requirements
capabilities for all three methodologies, so it is
in the form of rules, design rule checks and often a
important to understand how to use them efficiently
design rule manual. The combination of these issues
and effectively to prevent extended design cycles or
and all the rules makes the designer’s job of
ECOs due to fabricator rejection of the design.
meeting the fabricators acceptance criteria a
Hatched copper fill with additional automated degassing and wagon wheel pads.
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IC Package physical design best practices
Shift-left “big rock” power delivery analysis
Today, power requirements are continually the design requirements of all the chiplets, which
increasing as more dies (or chiplets) are added to a can result in additional layers in the package just to
package. This is a big challenge from a power support the current requirements for all these
delivery perspective. The ability to analyze the core different dies.
power characteristics and understand if there are
To ensure the correct architecture and delivery of
enough vias and copper for the IC current require-
power to all the chiplets in these complex high
ments is essential to success. As multiple dies are
density advanced packaging designs, designers
integrated into a high-density heterogeneous
must be able to predict design behavior early and
package, not only must power be delivered through
make the right layout trade-offs.
multiple rails, but the complexity of the current
delivery path increases, since there are multiple dies The recommended approach is to identify big
in different locations pulling current from the rail. DC-drop problems (rocks) early on to improve the
Additionally, there is less room than there would be end results. This procedure is not focused on
in a single monolithic package to connect supply seeking the highest level of accuracy for sign-off
voltage and current to the die. With these increased purposes. The “big rock” approach is basically
densities, there may not be enough copper to meet allowing the designer to identify the possibility of a
problem that they wouldn’t have seen otherwise, as
early as possible, to avoid costly changes and
delays. The designer starts with capturing some
very basic information about the die or the compo-
nents that are in the design.
For example, on a particular die and power rail, the
designer starts with the assumptions that current is
distributed evenly and every bump consumes 15
milliamps. In reality, some bumps draw more, some
less, but the idea isn’t to be perfect here – the
designer just wants to find the “rocks.”
Once the package designer has that basic informa-
“Big rock” analysis showing current density in Powerscope. tion, Siemens Xpedition™ Package Designer soft-
ware (xPD) makes it extremely easy to fill in a
current value for the voltage rail – all from within
the tool. Analysis results from Siemens HyperLynx™
software are automatically annotated to xPD so
users can clearly see that they’ve got a violation at a
specific location where, for example, the current
density is too high or a via is over current, or the
voltage drop is too high. The designer can then click
on an error, automatically zoom to the area of the
problem, fix it and rerun the analysis.
Powerscope highlighting a potential current bottleneck
between two vias.
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IC Package physical design best practices
Integration methodologies for HBM memory
HBM memory is a de facto standard for high- bits of the channel from the complex via breakouts
performance computing applications, such as CPUs, on the logic die side to the breakouts on the HBM
GPUs and AI, but they are challenging to route in stack. Once this initial channel is completed and
an efficient manner, in part because they have a characterized for electrical compliance, it can then
1024-bit bus divided into channels, either 8 x 128 bit be considered good and ready for replication
or 16 x 64 bit. and reuse.
The challenges for the package designer fall into Meanwhile, it’s common that the compute chiplets,
four broad areas: or SoC, will undergo refinement that impacts the
1. Maintaining signal integrity. die bump or pin assignments. When a part of an
existing, replicated channel is modified and that
2. Enforcing power delivery stability.
change needs to be reflected to other channels,
3. Ensuring enough real-estate for routing.
time-consuming ECOs will result – unless intelligent
4. Allowing sufficient design cycle time to circuit replication is used. That’s where PhRC comes
implement them within specification. to the rescue. PhRC can yield a 25 percent total time
Creating the complex via geometries for the fanout saving over conventional cut-copy-paste, and this
and breakout structures is the first step in imple- increases up to as much as 75 percent when
menting a channel. This is followed by routing the combined with automated ECOs.
A complete HBM bus as a PhRC that can be intelligently replicated.
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IC Package physical design best practices
Concurrent team design
There is an old saying “many hands make light work” drop, power supply stability, metal area and fill
and this is especially true in package substrate specifications, along with signoff of the complete
design. Modern, heterogeneously integrated pack- assembly, involving thermal, mechanical stress and
ages can be substantial in size, content and layout versus schematic analyses. The list is exhaus-
complexity, making the process of ensuring design tive. No one designer can be expected to be a
adherence to fabrication and assembly rules as well master in every domain.
as achieving PPA and cost goals very challenging for
Fortunately, with concurrent team design, no one
a single designer.
needs to be. Imagine having three to five different
Historically this challenge has been approached by design domain experts working concurrently in
using design shifts, especially useful when a real-time, each one focused on a particular design
company has geographically dispersed team. In challenge that aligns with their expertise. Each
theory, there can be three different designers, each designer can see what the others are doing and can
working an eight-hour shift, to deliver continuous even set up floorplan restriction areas to inform
24 hour design. But while this is good and may work others not to focus on those areas. The result is a
for some companies, the expertise of only one powerful design environment that can multiply
designer can be applied at a time. engineering resources and bring specialists into the
picture concurrently. The result is a shorter design
This arrangement falters when a design has multiple
cycle, improved design quality and faster time to
design challenges requiring different areas of exper-
volume manufacture.
tise throughout the design process. Additionally, a
slew of requirements must be met, including IR
Designer one desktop Designer two desktop
Designers can set restrictions on specific floorplan areas.
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IC Package physical design best practices
Physical design IP reuse
People often think of cut-copy-paste as physical and device fanouts, among others. These physical
design IP reuse, and at the most basic level it is, but design reuse circuits (PhRC) are native, first-class
it has severe limitations. It’s acceptable in some design objects that provide dynamic net propaga-
circumstances, but not for most, as it can be error- tion from the parent netlist, allow for rapid ECOs,
prone, requires manual netlist manipulation, and and manage the golden source of verified design
lacks traceability to the golden source data. content. PhRCs drive modularity in design, require
no netlist modifications, and offer a non-invasive
Most package designs contain areas of symmetry
ECO process. They are built using verified content,
that are perfect for reuse – such as die-to-die
and their placement can be used across designs,
routing of standard interfaces, core power and
designers and teams.
ground supply structures with complex via arrays,
Power and ground mesh grid PhRC.
Eight PhRC blocks of reusable fanout routing.
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IC Package physical design best practices
Efficient design of daisy-chain
test vehicles
Semiconductor package test vehicles are commonly vehicle designs can be quite time consuming to
called daisy-chain design because the design is full design and visualize. By working closely with a
of daisy-chain metal routing. Test vehicles have the number of customers, Siemens developed the
physical characteristics of the actual target design, Daisy Chain Creator toolkit based around a graphical
such as number of layers, and use the same parts. user interface.
The daisy-chain routing of a test vehicle is used to
The Daisy Chain Creator toolkit enables selection of
test mechanical connections such as CTE and solder-
chains across the interfaces of dies, packages and
ability, etc. Then physical structures such as mate-
PCBs. It provides the ability to easily color and name
rials, processes and design features are tested.
the chains. It also enables the creation of documen-
Finally copper structures such as heaters, serpen-
tation for the technicians performing the tests.
tine, or offset vias are tested. Creating the test
Daisy-chain documentation view (right) and 3D view (left).
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IC Package physical design best practices
Datapath planning and routing
Packages used to be just point-to-point redistribu- Connectivity is no longer simply “connecting the
tion connections between dies, micro bumps dots,” in part because there are wide data buses,
and the package’s BGA. There were some differen- such as HBM and other protocols, connecting the
tial pairs, but overall, it was largely a “connect the compute chiplets. Datapath planning takes place
dots” challenge. during package floorplanning as chiplet placement
is dependent on the interconnect datapaths to other
The game has changed with the emergence of
chiplets and the external package pins. Designers
heterogeneously integrated chiplets, which are
can group interfaces or byte lanes into bundles and
themselves disaggregated functions of what once
floorplan them to evaluate route real-estate and
would have been a monolithic SoC. A lot of data is
chiplet breakout strategies. Once these datapath
passed between these chiplets, most of it at very
plans are deemed to be viable scenarios, they can
high speeds using complex data bus protocols.
be annotated and forwarded to the actual physical
Packages are now true, system interconnect plat-
design for detailed implementation.
forms enabling the collection of compute chiplets
and associated memory to meet the device archi-
tect’s intended goals.
Datapath planning and routing.
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IC Package physical design best practices
Conclusion
The evolving landscape of packaging design
demands that designers and design teams adapt to
a new and dynamic set of best practices, tech-
niques, processes and methodologies. Embracing
these emerging approaches is essential for crafting
packages that not only captivate consumers but also
address the evolving demands of sustainability,
technology and consumer preferences. By staying at
the forefront of these innovations, designers can
ensure that their creations are not only visually
appealing but also functionally efficient and envi-
ronmentally responsible, ultimately contributing to
a more successful and sustainable future in the field
of packaging design.
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