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TMS320DM814x DaVinci™
Video Processors
Check for Samples: TMS320DM8148, TMS320DM8147

1 High-Performance System-on-Chip (SoC)

1.1
12
Features
• High-Performance DaVinci Video Processors – 32KB of L1D RAM/Cache
– Up to 1-GHz ARM® Cortex®-A8 RISC Core – 256KB of L2 Unified Mapped RAM/Caches
– Up to 750-MHz C674x™ VLIW DSP With ECC
– Up to 6000 MIPS and 4500 MFLOPS • System Memory Management Unit (MMU)
– Fully Software-Compatible with C67x+™, – Maps C674x DSP and EDMA TC Memory
C64x+™ Accesses to System Addresses
• ARM Cortex-A8 Core • 128KB of On-Chip Memory Controller (OCMC)
RAM
– ARMv7 Architecture
• Imaging Subsystem (ISS)
• In-Order, Dual-Issue, Superscalar
Processor Core – Camera Sensor Connection
• Neon™ Multimedia Architecture • Parallel Connection for Raw (up to 16-Bit)
and BT.656 or BT.1120 (8- and 16-Bit)
• Supports Integer and Floating Point
– Image Sensor Interface (ISIF) for Handling
• Jazelle® RCT Execution Environment
Image and Video Data From the Camera
• ARM Cortex-A8 Memory Architecture Sensor
– 32KB of Instruction and Data Caches – Resizer
– 512KB of L2 Cache • Resizing Image and Video From 1/16x to
– 64KB of RAM, 48KB of Boot ROM 8x
• TMS320C674x Floating-Point VLIW DSP • Generating Two Different Resizing
– 64 General-Purpose Registers (32-Bit) Outputs Concurrently
– Six ALU (32-/40-Bit) Functional Units • Programmable High-Definition Video Image
• Supports 32-Bit Integer, SP (IEEE Single Coprocessing (HDVICP v2) Engine
Precision/32-Bit) and DP (IEEE Double – Encode, Decode, Transcode Operations
Precision/64-Bit) Floating Point – H.264, MPEG-2, VC-1, MPEG-4, SP/ASP,
• Supports up to Four SP Adds Per Clock JPEG/MJPEG
and Four DP Adds Every Two Clocks • Media Controller
• Supports up to Two Floating-Point (SP or – Controls the HDVPSS, HDVICP2, and ISS
DP) Approximate Reciprocal or Square • SGX530 3D Graphics Engine
Root Operations Per Cycle
– Delivers up to 25 MPoly/sec
– Two Multiply Functional Units
– Universal Scalable Shader Engine
• Mixed-Precision IEEE Floating-Point
– Direct3D Mobile, OpenGLES 1.1 and 2.0,
Multiply Supported up to:
OpenVG 1.0, OpenMax API Support
– 2 SP x SP → SP Per Clock
– Advanced Geometry DMA Driven Operation
– 2 SP x SP → DP Every Two Clocks
– Programmable HQ Image Anti-Aliasing
– 2 SP x DP → DP Every Three Clocks
• Endianness
– 2 DP x DP → DP Every Four Clocks
– ARM and DSP Instructions/Data – Little
• Fixed-Point Multiply Supports Two 32 x Endian
32 Multiplies, Four 16 x 16-Bit Multiplies
• HD Video Processing Subsystem (HDVPSS)
Including Complex Multiplies, or Eight 8 x
8-Bit Multiplies per Clock Cycle – Two 165-MHz, 2-channel HD Video Capture
Modules
• C674x Two-Level Memory Architecture
• One 16-/24-Bit Input or Dual 8-Bit SD
– 32KB of L1P RAM/Cache With EDC
Input Channels
1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to Copyright © 2011–2013, Texas Instruments Incorporated
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
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• One 8-/16-/24-Bit Input and One 8-Bit Only or OTG

Input Channels – Supports End Points 0–15
– Two 165-MHz HD Video Display Outputs • One PCI Express 2.0 Port With Integrated PHY
• One 16-, 24-, or 30-Bit Output and One 16- – Single Port With One Lane at 5.0 GT/s
or 24-Bit Output – Configurable as Root Complex or Endpoint
– Composite or S-Video Analog Output • Eight 32-Bit General-Purpose Timers
– Macrovision® Support Available (Timer1–8)
– Digital HDMI 1.3 Transmitter With Integrated • One System Watchdog Timer (WDT0)
PHY • Six Configurable UART/IrDA/CIR Modules
– Advanced Video Processing Features Such – UART0 With Modem Control Signals
as Scan, Format, Rate Conversion
– Supports up to 3.6864 Mbps UART0/1/2
– Three Graphics Layers and Compositors
– Supports up to 12 Mbps UART3/4/5
• Dual 32-Bit DDR2/DDR3 SDRAM Interfaces
– SIR, MIR, FIR (4.0 MBAUD), and CIR
– Supports up to DDR2-800 and DDR3-1066
• Four Serial Peripheral Interfaces (SPIs) (up to
– Up to Eight x 8 Devices Total 2GB of Total 48 MHz)
Address Space
– Each With Four Chip Selects
– Dynamic Memory Manager (DMM)
• Three MMC/SD/SDIO Serial Interfaces (up to
• Programmable Multi-Zone Memory 48 MHz)
Mapping and Interleaving
– Three Supporting up to 1-, 4-, or 8-Bit Modes
• Enables Efficient 2D Block Accesses
• Dual Controller Area Network (DCAN) Modules
• Supports Tiled Objects in 0°, 90°, 180°, or
– CAN Version 2 Part A, B
270° Orientation and Mirroring
• Four Inter-Integrated Circuit (I2C Bus) Ports
• Optimizes Interlaced Accesses
• Six Multichannel Audio Serial Ports (McASPs)
• General-Purpose Memory Controller (GPMC)
– Dual Ten Serializer Transmit and Receive
– 8- or 16-Bit Multiplexed Address and Data
Ports
Bus
– Quad Four Serializer Transmit and Receive
– 512MB of Address Space Divided Among up
Ports
to 8 Chip Selects
– DIT-Capable For S/PDIF (All Ports)
– Glueless Interface to NOR Flash, NAND
Flash (BCH/Hamming Error Code Detection), • Multichannel Buffered Serial Port (McBSP)
SRAM and Pseudo-SRAM – Transmit and Receive Clocks up to 48 MHz
– Error Locator Module (ELM) Outside of – Two Clock Zones and Two Serial Data Pins
GPMC to Provide Up to 16-Bit or 512-Byte – Supports TDM, I2S, and Similar Formats
Hardware ECC for NAND • Serial ATA (SATA) 3.0 Gbps Controller With
– Flexible Asynchronous Protocol Control for Integrated PHY
Interface to FPGA, CPLD, ASICs, and so – Direct Interface to One Hard Disk Drive
Forth – Hardware-Assisted Native Command
• Enhanced Direct Memory Access (EDMA) Queuing (NCQ) from up to 32 Entries
Controller – Supports Port Multiplier and Command-
– Four Transfer Controllers Based Switching
– 64 Independent DMA Channels and 8 • Real-Time Clock (RTC)
Independent QDMA Channels – One-Time or Periodic Interrupt Generation
• Dual Port Ethernet (10/100/1000 Mbps) With • Up to 128 General-Purpose I/O (GPIO) Pins
Optional Switch
• One Spin Lock Module with up to 128 Hardware
– IEEE 802.3 Compliant (3.3-V I/O Only) Semaphores
– MII/RMII/GMII/RGMII Media Independent • One Mailbox Module with 12 Mailboxes
Interfaces
• On-Chip ARM ROM Bootloader (RBL)
– Management Data I/O (MDIO) Module
• Power, Reset, and Clock Management
– Reset Isolation
– Multiple Independent Core Power Domains
– IEEE 1588 Time-Stamping and Industrial
– Multiple Independent Core Voltage Domains
Ethernet Protocols
– Support for Three Operating Points (OPP100,
• Dual USB 2.0 Ports With Integrated PHYs
OPP120, OPP166) per Voltage Domain
– USB2.0 High- and Full-Speed Clients
– Clock Enable and Disable Control for
– USB2.0 High-, Full-, and Low-Speed Hosts, Subsystems and Peripherals
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• 32KB of Embedded Trace Buffer (ETB) and Technology to Reduce PCB Cost
5-Pin Trace Interface for Debug • 45-nm CMOS Technology
• IEEE 1149.1 (JTAG) Compatible • 1.8- and 3.3-V Dual Voltage Buffers for General
• 684-Pin Pb-Free BGA Package (CYE Suffix), I/O
0.8-mm Ball Pitch With Via Channel

1.2 Applications
• HD Video Conferencing - Skype® Endpoints
• Video Surveillance DVRs, IP Netcam
• Digital Signage
• Media Players and Adapters
• Mobile Medical Imaging
• Network Projectors
• Home Audio and Video Equipment

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1.3 Description
TMS320DM814x DaVinci video processors are highly integrated, programmable platforms that leverage
the DaVinci processor technology to meet the processing needs of the following applications to name a
few:
• HD Video Conferencing - Skype endpoints
• Video Surveillance DVRs
• IP Netcam
• Digital Signage
• Media Players and Adapters
• Mobile Medical Imaging
• Network Projectors
• Home Audio and Video Equipment
The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers
(ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces,
and high processing performance through the maximum flexibility of a fully integrated mixed processor
solution. The device also combines programmable video and audio processing with a highly integrated
peripheral set.
The TMS320DM814x DaVinci video processors also present OEMs and ODMs with new levels of
processor scalability and software reuse. An OEM or ODM that used the AM387x processors in a design
and can make a similar product with added features could scale up to the pin-compatible and software-
compatible TMS320DM814x processors from TI. The TMS320DM814x DaVinci video processors add a
powerful C674x DSP core along with a video encoder and decoder to the hardware on the AM38x.
Additionally, OEMs or ODMs that have used the AM387x or DM814x processors and find a need for a
faster ARM and DSP core performance could scale up to the software-compatible AM389x or
TMS320DM816x devices with higher core speeds.
Programmability is provided by an ARM Cortex-A8 RISC CPU with Neon extension, TI C674x VLIW
floating-point DSP core, and high-definition video and imaging coprocessors. The ARM lets developers
keep control functions separate from A/V algorithms programmed on the DSP and coprocessors, thus
reducing the complexity of the system software. The ARM Cortex-A8 32-Bit RISC Core with Neon floating-
point extension includes: 32KB of Instruction cache; 32KB of Data cache; 512KB of L2 Cache; 48KB of
Boot ROM; and 64KB of RAM.
The rich peripheral set provides the ability to control external peripheral devices and communicate with
external processors. For details on each of the peripherals, see the related sections in this document and
the associated peripheral reference guides. The peripheral set includes:
• HD Video Processing Subsystem
• Dual Port Gigabit Ethernet MACs (10/100/1000 Mbps) [Ethernet Switch] with MII/RMII/GMII/RGMII and
MDIO interface supporting IEEE 1588 Time-Stamping and Industrial Ethernet Protocols
• Two USB ports with integrated 2.0 PHY
• PCIe x1 GEN2 Compliant interface
• Two 10-serializer McASP audio serial ports (with DIT mode)
• Four quad-serilaizer McASP audio serial ports (with DIT mode)
• One McBSP multichannel buffered serial port
• Six UARTs with IrDA and CIR support
• Four SPI serial interfaces
• Three MMC/SD/SDIO serial interfaces
• Four I2C master and slave interfaces
• Parallel Camera Interface (CAM)
• Up to 128 General-Purpose I/Os (GPIOs)
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• Eight 32-bit general-purpose timers

• System watchdog timer
• Dual DDR2, and DDR3 SDRAM interfaces
• Flexible 8- or 16-bit asynchronous memory interface
• Two Controller Area Network (DCAN) modules
• Spin Lock
• Mailbox
• Serial Hard Disk Drive Interface (SATA 300)
The TMS320DM814x DaVinci video processors also include a high-definition video and imaging
coprocessor 2 (HDVICP2), and an SGX530 3D graphics engine to off-load many video and imaging
processing tasks from the DSP core, making more DSP MIPS available for common video and imaging
algorithms. Additionally, it has a complete set of development tools for both the ARM and DSP, which
include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Microsoft®
Windows® debugger interface for visibility into source code execution.
The C674x DSP core is the high-performance floating-point DSP generation in the TMS320C6000 DSP
platform and is code-compatible with previous generation C64x Fixed-Point and C67x Floating-Point DSP
generation. The C674x Floating-Point DSP processor uses 32KB of L1 program memory with EDC and
32KB of L1 data memory. Up to 32KB of L1P can be configured as program cache. The remaining
memory is noncacheable no-wait-state program memory. Up to 32KB of L1D can be configured as data
cache. The remaining memory is noncacheable no-wait-state data memory. The DSP has 256KB of L2
RAM with ECC, which can be defined as SRAM, L2 cache, or a combination of both. All C674x L3 and off-
chip memory accesses are routed through an MMU.

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1.4 Functional Block Diagram

Figure 1-1 shows the functional block diagram of the device.

ARM Subsystem Video Processing Imaging

DSP Subsystem

(A)
Subsystem Subsystem

High Definition Video Image

SGX530 3D Graphics Engine
Cortex -A8
TM
NEON C674xTM

Coprocessor (HDVICP2)
Video Capture Parallel Cam Input

128 KB On-Chip RAM

CPU FPU DSP CPU

Media Controller
32 KB 32 KB Display Processing
32KB 32 KB
I-Cache D-Cache
L1 Pgm L1 Data
512 KB L2 Cache HD OSD SD OSD
256 KB L2 Cache
Boot ROM RAM HD VENC SD VENC Resizer
48 KB 64 KB AET
HDMI Xmt SD DACs
ICE Crusher
System MMU

System Interconnect

System Control Peripherals

Serial Interfaces Program/Data Storage Connectivity
Real-Time
PRCM
Clock
DDR2/3 GPMC EMAC
McASP
McBSP 32-bit + (R)(G)MII MDIO
GP Timer (6)
JTAG (2) ELM (2)
(8)
USB 2.0 PCIe 2.0

EDMA
SPI I 2C SATA
(4) (4) 3Gbp/s Ctlr/PHY (One x1
Watchdog (1 Drives) (2) Port)
Timer
MMC/SD/
DCAN UART
SDIO
(2) (6)
Spin Lock Mailbox (3)

A. SGX530 is only available on the DM8148 device.

Figure 1-1. TMS320DM814x DaVinci video Processors Functional Block Diagram

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1 High-Performance System-on-Chip (SoC) ......... 1 7.2 Power .............................................. 181

1.1 Features............................................. 1 7.3 Reset.............................................. 189
1.2 Applications .......................................... 3 7.4 Clocking........................................... 197
1.3 Description ........................................... 4 7.5 Interrupts .......................................... 214
1.4 Functional Block Diagram ........................... 6 8 Peripheral Information and Timings ............. 221
Revision History .............................................. 8 8.1 Parameter Information ............................ 221
2 Device Overview ....................................... 12 8.2 Recommended Clock and Control Signal Transition
2.1 Device Comparison ................................ 12 Behavior ........................................... 222
2.2 Device Characteristics .............................. 12 8.3 Controller Area Network Interface (DCAN) ....... 223
2.3 Device Compatibility ................................ 14 8.4 EDMA ............................................. 225
2.4 ARM® Cortex™-A8 Microprocessor Unit (MPU) 8.5 Emulation Features and Capability ............... 232
Subsystem Overview ............................... 14 8.6 Ethernet MAC Switch (EMAC SW) ................ 236
2.5 C674x™ DSP Overview ............................ 16 8.7 General-Purpose Input/Output (GPIO) ............ 251
2.6 System Memory Management Unit (MMU) ........ 20 8.8 General-Purpose Memory Controller (GPMC) and
2.7 Media Controller Overview ......................... 21 Error Location Module (ELM) ..................... 254
2.8 HDVICP2 Overview ................................ 21 8.9 High-Definition Multimedia Interface (HDMI) ...... 271
8.10 High-Definition Video Processing Subsystem
2.9 SGX530 Overview .................................. 22
(HDVPSS) ......................................... 274
2.10 Spinlock Module Overview ......................... 22
8.11 ......................
Inter-Integrated Circuit (I2C) 280
2.11 Mailbox Module Overview .......................... 23
8.12 Imaging Subsystem (ISS) ......................... 284
2.12 Memory Map Summary ............................. 24
8.13 DDR2/DDR3 Memory Controller .................. 287
3 Device Pins ............................................. 34
8.14 Multichannel Audio Serial Port (McASP) .......... 324
3.1 Pin Maps ........................................... 34
8.15 Multichannel Buffered Serial Port (McBSP) ....... 332
3.2 Terminal Functions ................................. 43
8.16 MultiMedia Card/Secure Digital/Secure Digital Input
4 Device Configurations .............................. 153 Output (MMC/SD/SDIO) ........................... 337
4.1 Control Module Registers ......................... 153 8.17 Peripheral Component Interconnect Express (PCIe)
4.2 Boot Modes ....................................... 153 ..................................................... 340
4.3 Pin Multiplexing Control ........................... 159 8.18 Serial ATA Controller (SATA) ..................... 347
4.4 Handling Unused Pins ............................ 170 8.19 Serial Peripheral Interface (SPI) .................. 351
4.5 DeBugging Considerations ........................ 170 8.20 Timers .............................................358
5 System Interconnect ................................ 172 8.21 Universal Asynchronous Receiver/Transmitter
(UART) ............................................ 360
6 Device Operating Conditions ...................... 176
6.1 Absolute Maximum Ratings ....................... 176
8.22 Universal Serial Bus (USB2.0).................... 362

6.2 Recommended Operating Conditions ............. 177

9 Device and Documentation Support ............. 370
9.1 Device Support .................................... 370
6.3 Power-On Hours (POH) ........................... 178
6.4 Electrical Characteristics Over Recommended 9.2 Documentation Support ........................... 371
Ranges of Supply Voltage and Operating 9.3 Community Resources ............................ 371
Temperature (Unless Otherwise Noted) .......... 179 10 Mechanical ............................................ 372
7 Power, Reset, Clocking, and Interrupts ......... 181 10.1 Thermal Data for CYE-04 (Top Hat) .............. 372
7.1 Power, Reset and Clock Management (PRCM) 10.2 Packaging Information ............................ 372
Module ............................................ 181

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Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

This data manual revision history highlights the technical changes made to the SPRS647D device-specific
data manual to make it an SPRS647E revision.
Scope: Applicable updates to the DM814x DaVinci™ Video DMP device family, specifically relating to the
TMS320DM8148/47 devices (Silicon Revisions 3.0, 2.1), which are now in the production data (PD) stage
of development have been incorporated.
• Updated/Changed Power-Up Sequence
• Updated/Changed Power-Down Sequence
• Low-end OPP combinations no longer supported (CVDD_x < CVDD)
• Added RXACTIVE Function (Bit 18) to PINCTRLx Register Description
• Added Power-On Hours (POH) section
• Added Latch-Up Performance Absolute Maximum Ratings
• DDR2/DDR3 supports up to 533 MHz
• OPP50 is not supported
• SmartReflex™ (AVS) is not supported
• Deep Sleep Mode is not supported
• HDMI HDCP encryption is not supported

SEE ADDITIONS/MODIFICATIONS/DELETIONS
• Replaced all instances of "DSP/EDMA MMU" with "System MMU"
Global • Deleted all references to OPP50 and Deep Sleep Mode
• Deleted the TMS320DM8146 device along with any device-specific information; no longer
supported

• Updated/Changed description the HD Video Processing Subsystem (HDVPSS)

Section 1
Features • Updated/Changed the Dual 32-Bit DDR2/DDR3 SDRAM Interfaces sub-bullet from "Supports up to
DDR2-800 and DDR3-800" to "Supports up to DDR2-800 and DDR3-1066"

Table 2-2, Characteristics of the Processor:

Section 2.2 • Updated/Changed the HD Video Processing Subsystem (HDVPSS) row
Device Characteristics • Updated/Changed Core Logic (V), OPP100, OPP120 range from "0.95 V – 1.20 V" to "1.10 V –
1.20 V"

Table 2-7, L4 Slow Peripheral Memory Map:

Section 2.12.4.2 • Updated/Changed 0x4818_8000–0x4818_BFFF Device Name from "SmartReflex0/1 Peripheral
L4 Slow Peripheral and Support Registers" to "Reserved"
Memory Map • Updated/Changed 0x4819_0000–0x4819_3FFF Device Name from "SmartReflex2/3 Peripheral
and Support Registers" to "Reserved"

Section 3.2.7 Table 3-11, GP1 Terminal Functions:

General-Purpose • Added "The ENLVCMOS bit in the MLBP_DAT_IO_CTRL register...." to the pin descriptions for
Input/Outputs (GPIOs) pins GP1[10:7] (V2, V1, W2, and W1 respectively).

Section 3.2.25 Table 3-48, Reserved Terminal Functions:

Reserved Pins • Updated/Changed TYPE for Signal No. Y14 (RSV4) and AC8 (RSV5) from "S" to "I"

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SEE ADDITIONS/MODIFICATIONS/DELETIONS
Section 4.3, Pin Multiplexing Control:
• Updated/Changed bit 18 from "RSV" to "RXACTIVE"
Table 4-11, PINCNTL1 – PINCNTL270 (PINCNTLx) Registers Bit Descriptions:
• Updated/Changed the MUXMODE[7:0] Description from "Values other than those ..." to "A value
of zero results ..."
Section 4 • Updated/Changed bit 18 description to now support RXACTIVE
Device Configurations Table 4-13, PINCNTLx Registers MUXMODE Functions:
• Updated/Changed PINCNTL173 row under 0x20 from "UART2_TXD(M1)" to "UART2_TXD(M0)"
• Updated/Changed PINCNTL231 under 0x80 from "GP3[30](M0)" to "GP3[30](M1)"

Section 4.4, Handling Unused Pins:

• Added "Unless otherwise noted" to the beginning of, "All supply pins must always ..."

Section 6.1, Absolute Maximum Ratings:

• Deleted the "V I/O...(Transient Overshoot/Undershoot)" rows of Input and Output voltage ranges
Section 6 • Added Latch-Up Performance row and Latch-Up footnotes
Device Operating • Updated/Changed ESD-HBM footnote to "Level listed is passing level per ANSI/ESDA/JEDEC J5-
Conditions 001..."
• Updated/Changed ESD-CDM footnote to "Level listed is passing level per EIA-JEDEC JESD22-
C101E..."

Section 6.3, Power on Hours (POH):

• Added Power-On Hour (POH) section [New]

Section 7.2.2.1
Dynamic Voltage Table 7-5, Supported OPP Combinations:
Frequency Scaling • Deleted lower-end OPP combinations supported for ARM, DSP, and HDVICP2
(DVFS)

Table 7-6 , Power-Up Sequence Ramping Values:

• Added NO. 1 MIN value of "0" ms.
• Updated/Changed NO. 1 description to "1.8 V and DVDD_DDR[x] supplies stable..."
Section 7.2.8.1 • Added NO. 13, "CVDD variable supply ramp...."
Power-Up Sequence
• Updated/Changed Figure 7-1 according to table changes
• Deleted 3.3 V Supplies Rising Before 1.8 V Supplies Delta Figure (was Figure 7.2) and associated
footnote references
• Deleted footnote, "The 3.3 V supplies must be..."

Section 7.2.8.2, Power-Down Sequence:

• Added, "Ramping down all supplies at the same time...For proper device..." paragraph

Table 7-7, Power-Down Sequence Ramping Values:

• Updated/Changed "The 1.5-/1.8-V DVDD_DDR[x]..." footnote
• Updated/Changed figure reference to Figure 7-3
Section 7.2.8.2
Power-Down Sequence • Added NO. 14, "CVDD_x variable supplies ramp-down..."
• Added associated footnote, "CVDD_x must never exceed CVDD by more than 150mV"
Figure 7-2, Power-Down Sequence:
• Updated/Changed figure according to table changes
Figure 7-3,1.8 V Supplies Falling Before 3.3 V Supplies Delta:
• Added figure [New]

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SEE ADDITIONS/MODIFICATIONS/DELETIONS
Section 7.4.1.1, Using the Internal Oscillators:
Table 7-11, Requirements for Crystal Circuit on the Device Oscillator (DEVOSC):
• Added three conditions and the MAX values to the Crystal Frequency Stability PARAMETER
Table 7-15, Timing Requirements for DEVOSC_MXI/DEV_CLKIN
• Added three conditions and the MAX values to the Frequency Stability PARAMETER
Section 7.4.3, AUD_CLKINx Input Clocks:
Section 7.4 • Added section [New]
Clocking Section 7.4.4, CLKIN32 Input Clock:
• Added "/8" to the TIMER1/2/3/4/5/6/7 bullet
Section 7.4.7, Input/Output Clocks Electrical Data/Timing:
• Added Table 7-17, Timing Requirements for AUD_CLKINx [New]
• Added Figure 7-14, AUD_CLKINx Timing [New]
Section 7.4.8, PLLs:
• Deleted PLL Electrical Data/Timing subsection
Section 7.4.9 Table 7-26, Maximum SYSCLK Clock Frequencies:
SYSCLKs • Added footnote, "The maximum frequencies listed..."

Table 7-27, Maximum Module Clock Frequencies:

Section 7.4.10 • Updated/Changed Media Controller CLOCK SOURCES from "PLL_MEDIACTL" to
Module Clocks "PLL_MEDIACTL/2"
• Updated/Changed Media Controller MAX FREQUENCY OPP100 (MHz) value from "400" to "200"
• Added footnote, "The maximum frequencies listed..."

Section 8.4.1, EDMA Channel Synchronization Events:

• Updated/Changed paragraphs
Section 8.4
EDMA Section 8.4.2, EDMA Peripheral Register Descriptions:
• Added Table 8-5, EDMA Channel Controller (EDMA TPCC) Control Registers
• Added Table 8-6, EDMA Transfer Controller (EDMA TPTC) Control Registers
Section 8.5.3 Table 8-8, JTAG ID Register Table:
IEEE 1149.1 JTAG • Added silicon-revision specific information to the VARIANT bit field

Section 8.6.2.3
EMAC RGMII Electrical • Updated/Changed all instances of "at DSP" to "at device"
Data/Timing

Section 8.10.1 Table 8-42, Timing Requirements for HDVPSS Input:

HDVPSS Electrical • Deleted NO. 7, tt(CLK), Transition time, VIN[x]A_CLK (10%-90%)
Data/Timing • Deleted NO. 7, tt(CLK), Transition time, VIN[x]B_CLK (10%-90%)

Table 8-53, Switching Characteristics Over Recommended Operating Conditions for DDR2/DDR3
Section 8.13.4, Memory Controller:
DDR2/DDR3 Memory
• Updated/Changed NO. 1, tc(DDR_CLK) , Cycle time, DDR[x]_CLK, DDR2/DDR3 mode to DDR2
Controller Electrical
mode
Data/Timing
• Added additional row to NO.1, tc(DDR_CLK), Cycle time, DDR[x]_CLK: DDR3 mode
Section 8.13.4.1.1.1, DDR2 Interface Schematic:
Section 8.13.4.1 • Updated/Changed the sentence from, "... pins by pulling the non-inverted DQS pin..." to "...
DDR2 Routing DDR[x]_DQS[n] pins to the corresponding..."
Specifications • Updated/Changed a sentence from, "... inverted DQS pin..." to "... DDR[x]_DQS[n] pins..."
• Added sentence, "The DVDD_DDR[x] and VREFSSTL_DDR[x] power..."

Section 8.13.4.1.2 Table 8-63, CK and ADDR_CTRL Routing Specification:

DDR2 CK and
ADDR_CTRL Routing • Updated/Changed the "Series terminator,...the DSP" footnote to "Series terminator,..the processor"

Section 8.13.4.2.4, DDR3 Interface Schematic:

Section 8.13.4.2 • Combined 16-Bit and 32-Bit DDR3 Interface subsections
DDR3 Routing • Deleted repeated figure references
Specifications • Deleted the sentence, "and the unused DQS......pulled to ground via 1-kΩ resistors."
• Added sentence, "The DVDD_DDR[x] and VREFSSTL_DDR[x]..."

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SEE ADDITIONS/MODIFICATIONS/DELETIONS
Section 8.13.4.2.4.1 Table 8-66, Compatible JEDEC DDR3 Devices (Per Interface):
Compatible JEDEC DDR3 • Updated/Changed the max clock rate in footnote, "DDR3 devices with speed...." from "400" MHz to
Devices "533" MHz

Table 8-78, Timing Requirements for McASP:

Section 8.14.3 • Updated/Changed McASP1 Only ACLKR/X ext out, MIN value for NO. 5, tsu(AFSRX-ACLKRX), Setup
McASP (McASP[5:0]) time, MCA[x]_AFSR/X input valid before MCA[X]_ACLKR/X from "4" to "2" ns.
Electrical Data/Timing
• Updated/Changed McASP1 Only ACLKR/X ext out, MIN value for NO. 7,tsu(AXR-ACLKRX), Setup
time, MCA[x]_AXR input valid before MCA[X]_ACLKR/X from "4" to "2" ns.
Table 8-80, McBSP Registers:
Section 8.15 • Updated/Changed McBSP HEX ADDRESS range from "0x4700 0000 - 0x4700 00C0" to "0x4700
Multichannel Buffered 0100 – 0x4700 01C0" (DDR_REG to STATUS_REG)
Serial Port (McBSP) • Added McBSP registers in HEX ADDRESS range "0x4700 0000 – 0x4700 004C" (REVNB to
DMATXWAKE_EN)
Section 9.1.2 Figure 9-1, Device Nomenclature:
Device and Development- • Added "D = -40ºC to 90ºC, Industrial Temperature" to the TEMPERATURE RANGE area
Support Tool
Nomenclature

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2 Device Overview

2.1 Device Comparison

Table 2-1 shows a comparison between devices, highlighting the differences.

Table 2-1. DM814x Device Comparison

DEVICES
FEATURES
TMS320DM8148 TMS320DM8147
SGX530 YES (1) NONE

2.2 Device Characteristics

Table 2-2 provides an overview of the TMS320DM814x DaVinci™ Digital Media Processors, which
includes significant features of the device, including the capacity of on-chip RAM, peripherals, and the
package type with pin count.

Table 2-2. Characteristics of the Processor

HARDWARE FEATURES DM814x
1 16-/24-bit HD Capture Port or
2 8-bit SD Capture Ports
and
1 8-bit SD Capture Port
and
1 16-/24-/30-bit HD Display Port or
HD Video Processing Subsystem (HDVPSS) 1 8-/16-/24-bit HD Capture Port
and
1 16-24-bit HD Display Port
and
1 HDMI 1.3 Transmitter
and
2 SD Video DACs
1 Parallel Camera Input for Raw (up to
Imaging Subsystem (ISS) 16-bit)
Peripherals and BT.656/BT.1120 (8/16-bit)
Not all peripherals DDR2/3 Memory Controller 2 (32-bit Bus Widths)
pins are available Asynchronous (8-/16-bit bus width)
at the same time GPMC + ELM
RAM, NOR, NAND
(for more details,
see the Device 64 Independent Channels
EDMA
Configurations 8 QDMA Channels
section). 10/100/1000 Ethernet MAC Switch with Management Data Input/Output 1 (with 2 MII/RMII/GMII/RGMII
(MDIO) Interfaces)
2 (Supports High- and Full-Speed as a
Device and
USB 2.0
High-, Full-, and Low-Speed as a Host,
or OTG)
PCI Express 2.0 1 Port (1 5.0GT/s lane)
8 (32-bit General purpose)
Timers and
1 (System Watchdog)
6 (with SIR, MIR, FIR, CIR support and
UART RTS/CTS flow control)
(UART0 Supports Modem Interface)
SPI 4 (Supports 4 slave devices)
1 (1-bit or 4-bit or 8-bit modes)
and
MMC/SD/SDIO
1 (8-bit mode) or
2 (1-bit or 4-bit modes)

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Table 2-2. Characteristics of the Processor (continued)

HARDWARE FEATURES DM814x
I2C 4 (Master/Slave)
Media Controller Controls HDVPSS, HDVICP2, and ISS
6 (10/10/4/4/4/4 Serializers, Each with
McASP
Transmit/Receive and DIT capability)
McBSP 1 (2 Data Pins, Transmit/Receive)
Controller Area Network (DCAN) 2
Serial ATA (SATA) 3.0 Gbps 1 (Supports 1 Hard Disk Drive)
RTC 1
GPIO Up to 128 pins
Parallel Camera Interface (CAM) 1
Spin Lock Module 1 (up to 128 H/W Semaphores)
Mailbox Module 1 (with 12 Mailboxes)
Size (Bytes) 1088KB RAM, 48KB ROM
ARM
32KB I-cache
32KB D-cache
512KB L2 Cache
64KB RAM
On-Chip Memory Organization 48KB Boot ROM
DSP
32KB L1 Program (L1P)/Cache (up to
32KB) with EDC
32KB L1 Data (L1D)/Cache (up to 32KB)
256KB Unified Mapped RAM/Cache (L2)
with ECC
ADDITIONAL SHARED MEMORY
128KB On-chip RAM
ARM® Cortex™-A8 Main ID Register Variant/Revision r3p2
CPU ID + CPU Rev
Control Status Register (CSR.[31:16]) 0x1401
ID
C674x
Megamodule Revision ID Register (MM_REVID[15:0]) 0x0000
Revision
see Section 8.5.3.1, JTAG ID (JTAGID)
JTAG BSDL ID DEVICE_ID Register (address location: 0x4814_0600)
Register Description
ARM® Cortex™-A8 1000, 720 MHz
CPU Frequency MHz
DSP 600 MHz
ARM® Cortex™ -A8 1.0, 1.39 ns
Cycle Time ns
DSP 1.66 ns
OPP100, OPP120 1.10 V – 1.20 V
Core Logic (V)
Voltage OPP166 1.35 V
I/O (V) 1.5 V, 1.8 V, 3.3 V
684-Pin BGA (CYE) [with Via Channel
Package 23 x 23 mm [Flip Chip Ball Grid Array (FCBGA)]
Technology]
Process
μm 0.045 μm
Technology
Product Preview (PP),
Product Status (1) Advance Information (AI), PD
or Production Data (PD)
(1) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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2.3 Device Compatibility

2.4 ARM® Cortex™-A8 Microprocessor Unit (MPU) Subsystem Overview

The ARM® Cortex™-A8 Subsystem is designed to give the ARM Cortex-A8 Master control of the device.
In general, the ARM Cortex-A8 is responsible for configuration and control of the various subsystems,
peripherals, and external memories.
The ARM Cortex-A8 Subsystem includes the following features:
• ARM Cortex-A8 RISC processor:
– ARMv7 ISA plus Thumb2™, JazelleX™, and Media Extensions
– Neon™ Floating-Point Unit
– Enhanced Memory Management Unit (MMU)
– Little Endian
– 32KB L1 Instruction Cache
– 32KB L1 Data Cache
– 512KB L2 Cache
• CoreSight Embedded Trace Module (ETM)
• ARM Cortex-A8 Interrupt Controller (AINTC)
• Embedded PLL Controller (PLL_ARM)
• 64KB Internal RAM
• 48KB Internal Public ROM
Figure 2-1 shows the ARM Cortex-A8 Subsystem for the device.

DEVOSC L3 DMM System Events

PLL_ARM
128 128 128 128 128

128 32 ARM Cortex-A8

ARM Cortex-A8 Interrupt Controller
32 (AINTC)
128
32KB L1I$ 32KB L1D$ 64 48KB ROM
512KB L2$ Arbiter
Trace ETM NEON 64KB RAM
64
Debug

ICECrusher

Figure 2-1. ARM Cortex-A8 Subsystem

For more details on the ARM Cortex-A8 Subsystem, see the System MMU section of the Chip Level
Resources chapter of the TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual
(Literature Number: SPRUGZ8).

2.4.1 ARM Cortex-A8 RISC Processor

The ARM Cortex-A8 Subsystem integrates the ARM Cortex-A8 processor. The ARM Cortex-A8 processor
is a member of ARM Cortex family of general-purpose microprocessors. This processor is targeted at
multi-tasking applications where full memory management, high performance, low die size, and low power
are all important. The ARM Cortex-A8 processor supports the ARM debug architecture and includes logic
to assist in both hardware and software debug. The ARM Cortex-A8 processor has a Harvard architecture
and provides a complete high-performance subsystem, including:
• ARM Cortex-A8 Integer Core
• Superscalar ARMv7 Instruction Set

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• Thumb-2 Instruction Set

• Jazelle RCT Acceleration
• CP14 Debug Coprocessor
• CP15 System Control Coprocessor
• NEON™ 64-/128-bit Hybrid SIMD Engine for Multimedia
• Enhanced VFPv3 Floating-Point Coprocessor
• Enhanced Memory Management Unit (MMU)
• Separate Level-1 Instruction and Data Caches
• Integrated Level-2 Cache
• 128-bit Interconnector-to-System Memories and Peripherals
• Embedded Trace Module (ETM).

2.4.2 Embedded Trace Module (ETM)

To support real-time trace, the ARM Cortex-A8 processor provides an interface to enable connection of an
embedded trace module (ETM). The ETM consists of two parts:
• The Trace port which provides real-time trace capability for the ARM Cortex-A8.
• Triggering facilities that provide trigger resources, which include address and data comparators,
counter, and sequencers.
The ARM Cortex-A8 trace port is not pinned out and is, instead, only connected to the system-level
Embedded Trace Buffer (ETB). The ETB has a 32KB buffer memory. ETB enabled debug tools are
required to read/interpret the captured trace data.
For more details on the ETM, see Section 8.5.2, Trace.

2.4.3 ARM Cortex-A8 Interrupt Controller (AINTC)

The ARM Cortex-A8 subsystem contains an interrupt controller (AINTC) that prioritizes all service requests
from the system peripherals and generates either IRQ or FIQ to the ARM Cortex-A8 processor. For more
details on the AINTC, see Section 7.5.1, ARM Cortex-A8 Interrupts.
Note: For General-Purpose devices, the AINTC does not support the generation of FIQs to the ARM
processor.

2.4.4 ARM Cortex-A8 PLL (PLL_ARM)

The ARM Cortex-A8 subsystem contains an embedded PLL Controller (PLL_ARM) for generating the
subsystem’s clocks from the DEV Clock input. For more details on the PLL_ARM, see Section 7.4,
Clocking.

2.4.5 ARM MPU Interconnect

The ARM Cortex-A8 processor is connected through the arbiter to both an L3 interconnect port and a
DMM port. The DMM port is 128 bits wide and provides the ARM Cortex-A8 direct access to the DDR
memories, while the L3 interconnect port is 64 bits wide and provides access to the remaining device
modules.

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2.5 C674x™ DSP Overview

The DSP Subsystem includes the following features:
• C674x DSP CPU
• 32KB L1 Program (L1P)/Cache (up to 32KB) with Error Detection Circuitry (EDC)
• 32KB L1 Data (L1D)/Cache (up to 32KB)
• 256KB Unified Mapped RAM/Cache (L2) with Error Correction Circuitry (ECC)
• Direct Connection to the HDVICP2 Host SL2 Port
• Little Endian

32K Bytes
256K Bytes
L1P RAM/ HDVICP2 Host
L2 RAM
Cache SL2 Port
w/ ECC
w/EDC

256 256 256

256
Cache Control Cache Control
Memory Protect L1P Memory Protect L2
Bandwidth Mgmt Bandwidth Mgmt

256 256

256 256 Power Down

Instruction Fetch
Interrupt
Controller
C674x
Fixed/Floating Point CPU
IDMA
Register Register
File A File B 256

64 64
32 L3 (Fast)
Bandwidth Mgmt CFG
Interconnect
EMC
Memory Protect L1D
Cache Control
MDMA SDMA

8 x 32 128 128

32K Bytes L3 (Fast)

L1D RAM/ Interconnect
Cache

Figure 2-2. C674x Megamodule Block Diagram

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2.5.1 C674x DSP CPU Description

The C674x central processing unit (CPU) consists of eight functional units, two register files, and two data
paths as shown in Figure 2-2. The two general-purpose register files (A and B) each contain 32 32-bit
registers for a total of 64 registers. The general-purpose registers can be used for data or can be data
address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40-
bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are stored in
register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or 32 MSBs in the
next upper register (which is always an odd-numbered register).
The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one
instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units
perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from
memory to the register file and store results from the register file into memory.
The C674x CPU combines the performance of the C64x+ core with the floating-point capabilities of the
C67x+ core.
Each C674x .M unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, one 16 x
32 bit multiply, two 16 x 16 bit multiplies, two 16 x 32 bit multiplies, two 16 x 16 bit multiplies with
add/subtract capabilities, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add operations, and four 16
x 16 multiplies with add/subtract capabilities (including a complex multiply). There is also support for
Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and
modems require complex multiplication. The complex multiply (CMPY) instruction takes four 16-bit inputs
and produces a 32-bit real and a 32-bit imaginary output. There are also complex multiplies with rounding
capability that produces one 32-bit packed output that contain 16-bit real and 16-bit imaginary values. The
32 x 32 bit multiply instructions provide the extended precision necessary for high-precision algorithms on
a variety of signed and unsigned 32-bit data types.
The .L or (Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on a
pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data
performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions.
The C674x core enhances the .S unit in several ways. On the previous cores, dual 16-bit MIN2 and MAX2
comparisons were only available on the .L units. On the C674x core they are also available on the .S unit
which increases the performance of algorithms that do searching and sorting. Finally, to increase data
packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit/16-bit
and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack
instructions return parallel results to output precision including saturation support.
Other new features include:
• SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where
multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size
associated with software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible.
• Compact Instructions - The native instruction size for the C6000 devices is 32 bits. Many common
instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C674x
compiler can restrict the code to use certain registers in the register file. This compression is
performed by the code generation tools.
• Instruction Set Enhancement - As noted above, there are new instructions such as 32-bit
multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field
multiplication.
• Exceptions Handling - Intended to aid the programmer in isolating bugs. The C674x CPU is able to
detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and
from system events (such as a watchdog time expiration).
• Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a
basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with
read, write, and execute permissions.

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• Time-Stamp Counter - Primarily targeted for Real-Time Operating System (RTOS) robustness, a free-
running time-stamp counter is implemented in the CPU which is not sensitive to system stalls.
For more details on the C674x CPU and its enhancements over the C64x architecture, see the following
documents:
• TMS320C674x DSP CPU and Instruction Set Reference Guide (Literature Number: SPRUFE8)
• TMS320C674x DSP Megamodule Reference Guide (Literature Number: SPRUFK5)

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Even
src1 Odd register
register file A
file A (A0, A2,
(A1, A3, A4...A30)
src2 A5...A31)
.L1
odd dst
(D)
even dst
long src 8
32 MSB
ST1b
32 LSB
ST1a
8
long src

even dst (D)

.S1 odd dst
Data path A src1

src2
32
dst2 (A)
32 (B)
dst1
.M1 src1
src2
32 MSB (C)
LD1b
32 LSB
LD1a
dst
.D1 src1
DA1
src2 2x

1x Even
register
Odd
DA2 src2 file B
register
.D2 (B0, B2,
src1 file B
B4...B30)
dst (B1, B3,
B5...B31)
LD2a 32 LSB
LD2b 32 MSB

src2
(C)
.M2 src1
dst2 32 (B)
dst1 32
(A)

src2

src1
.S2 odd dst
(D)
Data path B even dst
8
long src

32 MSB
ST2a
32 LSB
ST2b

long src 8
even dst
(D)
odd dst
.L2
src2

src1

Control Register

A. .M unit, dst2 is 32 MSB.

B On .M unit, dst1 is 32 LSB.
C. On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits.
D. On .L and .S units, odd dst connects to odd register files and even dst connects to even register files

Figure 2-3. TMS320C674x CPU (DSP Core) Data Paths

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2.6 System Memory Management Unit (MMU)

All C674x accesses through its MDMA port will be directed through the system MMU module where they
are remapped to physical system addresses. This protects the ARM Cortex-A8 memory regions from
accidental corruption by C674x code and allows for direct allocation of buffers in user space without the
need for translation between ARM and DSP applications.
In addition, accesses by the EDMA TC0 and TC1 may optionally be routed through the system MMU. This
allows EDMA Channels 0 and 1 to be used by the DSP to perform transfers using only the known virtual
addresses of the associated buffers. The MMU_CFG register in the Control Module is used to
enable/disable use of the system MMU by the EDMA TCs.
For more details on the system MMU features, see the system MMU section of the Chip Level Resources
chapter in the TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual (Literature
Number: SPRUGZ8).

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2.7 Media Controller Overview

The Media Controller has the responsibility of managing the HDVPSS, HDVICP2, and ISS modules.
For more details on the Media Controller, see the Media Controller Subsystem section of the Chip Level
Resources chapter of the TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual
(Literature Number: SPRUGZ8).

2.8 HDVICP2 Overview

The HDVICP2 is a Video Encoder/Decoder hardware accelerator supporting a range of encode, decode,
and transcode operations for most major video codec standards. The main video Codec standards
supported in hardware are MPEG1/2/4 ASP/SP, H.264 BL/MP/HP, VC-1 SP/MP/AP, RV9/10, AVS-1.0,
and ON2 VP6.2/VP7.
The HDVICP2 hardware accelerator is composed of the following elements:
• Motion estimation acceleration engine
• Loop filter acceleration engine
• Sequencer, including its memories and an interrupt controller
• Intra-prediction estimation engine
• Calculation engine
• Motion compensation engine
• Entropy coder/decoder
• Video Direct Memory Access (DMA)
• Synchronization boxes
• Shared L2 controller
• Local interconnect
For more details on the HDVICP2, see the HD Video Coprocessor SubSystem section of the Chip Level
Resources chapter of the TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual
(Literature Number: SPRUGZ8).

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2.9 SGX530 Overview

The SGX530 is a vector/3D graphics accelerator for vector and 3-dimensional (3D) graphics applications.
The SGX530 graphics accelerator efficiently processes a number of various multimedia data types
concurrently:
• Pixel data
• Vertex data
• Video data
This is achieved using a multi-threaded architecture using two levels of scheduling and data partitioning
enabling zero overhead task switching.
The SGX530 has the following major features:
• Vector graphics and 3D graphics
• Tile-based architecture
• Universal Scalable Shader Engine (USSE™) - multi-threaded engine incorporating pixel and vertex
shader functionality
• Advanced shader feature set - in excess of Microsoft VS3.0, PS3.0, and OpenGL2.0
• Industry standard API support - OpenGL ES 1.1 and 2.0, OpenVG v1.1
• Fine-grained task switching, load balancing, and power management
• Advanced geometry DMA driven operation for minimum CPU interaction
• Programmable high-quality image anti-aliasing
• POWERVR® SGX core MMU for address translation from the core virtual address to the external
physical address (up to 4GB address range)
• Fully-virtualized memory addressing for OS operation in a unified memory architecture
• Advanced and standard 2D operations [for example, vector graphics, block level transfers (BLTs),
raster operations (ROPs)]
For more details on the SGX530, see the Chip Level Resources chapter of the TMS320DM814x DaVinci
Digital Media Processors Technical Reference Manual (Literature Number: SPRUGZ8).

2.10 Spinlock Module Overview

The Spinlock module provides hardware assistance for synchronizing the processes running on multiple
processors in the device:
• ARM Cortex-A8 processor
• C674x DSP
• Media Controller
The Spinlock module implements 128 spinlocks (or hardware semaphores) that provide an efficient way to
perform a lock operation of a device resource using a single read-access, avoiding the need for a read-
modify-write bus transfer of which the programmable cores are not capable.
For more details on the Spinlock Module, see the Spinlock section of the Chip Level Resources chapter of
the TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual (Literature Number:
SPRUGZ8).

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2.11 Mailbox Module Overview

The device Mailbox module facilitates communication between the ARM Cortex-A8, C674x DSP, and the
Media Controller. The device mailbox consists of twelve mailboxes, each supporting a 1-way
communication between two of the above processors. The sender sends information to the receiver by
writing a message to the mailbox registers. Interrupt signaling is used to notify the receiver that a message
has been queued or to notify the sender about an overflow situation.
The Mailbox module supports the following features (see Figure 2-4):
• 12 mailboxes
• Flexible mailbox-to-processor assignment scheme
• Four-message FIFO depth for each message queue
• 32-bit message width
• Message reception and queue-not-full notification using interrupts
• Four interrupts (one to ARM Cortex-A8, one to C674x, and two to Media Controller)

Mailbox Module

Mailbox Mailbox Mailbox Mailbox Mailbox Mailbox

L4
Interconnect
Mailbox Mailbox Mailbox Mailbox Mailbox Mailbox

Interrupt Interrupt Interrupt Interrupt

ARM Cortex-A8 C674x+ DSP Media Controller

Figure 2-4. Mailbox Module Block Diagram

For more details on the Mailbox Module, see the Mailbox section of the Chip Level Resources chapter of
the TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual (Literature Number:
SPRUGZ8).

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2.12 Memory Map Summary

The device has multiple on-chip memories associated with its two processors and various subsystems. To
help simplify software development a unified memory map is used where possible to maintain a consistent
view of device resources across all bus masters.

2.12.1 L3 Memory Map

Table 2-3 shows the L3 memory map for all system masters (including Cortex-A8). Table 2-3 and Table 2-
6 show the memory map of the C674x DSP which has limited access to the following peripherals:
McASPx, McBSP, UARTx, I2Cx, SPIx, EDMA, GPIO/INT, GPMC, DDRx, EMAC, PCIe, Timers, and USB.
Table 2-4 shows the memory map for the C674x DSP.
For more details on the interconnect topology and connectivity across the L3 and L4 interconnects, see
Table 7-17, System Interconnect.

Table 2-3. L3 Memory Map

START ADDRESS END ADDRESS
SIZE DESCRIPTION
(HEX) (HEX)
0x0000_0000 0x00FF_FFFF 16MB GPMC (Reserved for BOOTROM)
0x0100_0000 0x1FFF_FFFF 496MB GPMC
0x2000_0000 0x2FFF_FFFF 256MB PCIe
0x3000_0000 0x3FFF_FFFF 256MB Reserved
0x4000_0000 0x4001_FFFF 128KB Reserved
ARM Cortex-A8 ROM
0x4002_0000 0x4002_BFFF 48KB
(Accessible by ARM Cortex-A8 only)
0x4002_C000 0x402E_FFFF 2832KB Reserved
0x402F_0000 0x402F_03FF 1KB Reserved
ARM Cortex-A8 RAM
0x402F_0400 0x402F_FFFF 64KB - 1KB
(Accessible by ARM Cortex-A8 only)
0x4030_0000 0x4031_FFFF 128KB OCMC SRAM
0x4032_0000 0x407F_FFFF 4992KB Reserved
0x4080_0000 0x4083_FFFF 256KB C674x™ L2 RAM
0x4084_0000 0x40DF_FFFF 5888KB Reserved
0x40E0_0000 0x40E0_7FFF 32KB C674x L1P Cache/RAM
0x40E0_8000 0x40EF_FFFF 992KB Reserved
0x40F0_0000 0x40F0_7FFF 32KB C674x L1D Cache/RAM
0x40F0_8000 0x40FF_FFFF 992KB Reserved
0x4100_0000 0x41FF_FFFF 16MB Reserved
0x4200_0000 0x43FF_FFFF 32MB Reserved
0x4400_0000 0x443F_FFFF 4MB L3 Fast configuration registers
0x4440_0000 0x447F_FFFF 4MB L3 Mid configuration registers
0x4480_0000 0x44BF_FFFF 4MB L3 Slow configuration registers
0x44C0_0000 0x45FF_FFFF 20MB Reserved
0x4600_0000 0x463F_FFFF 4MB McASP0 Data Peripheral Registers
0x4640_0000 0x467F_FFFF 4MB McASP1 Data Peripheral Registers
0x4680_0000 0x46BF_FFFF 4MB McASP2 Data Peripheral Registers
0x46C0_0000 0x46FF_FFFF 4MB HDMI
0x4700_0000 0x473F_FFFF 4MB McBSP
0x4740_0000 0x477F_FFFF 4MB USB
0x4780_0000 0x4780_FFFF 64KB Reserved
0x4781_0000 0x4781_1FFF 8KB MMC/SD/SDIO2 Peripheral Registers
0x4781_2000 0x47BF_FFFF 4MB - 72KB Reserved

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Table 2-3. L3 Memory Map (continued)

START ADDRESS END ADDRESS
SIZE DESCRIPTION
(HEX) (HEX)
0x47C0_0000 0x47C0_BFFF 48KB Reserved
0x47C0_C000 0x47C0_C3FF 1KB Reserved
0x47C0_C400 0x47C0_C7FF 1KB DDR0 PHY Registers
0x47C0_C800 0x47C0_CBFF 1KB DDR1 PHY Registers
0x47C0_CC00 0x47C0_CFFF 1KB Reserved
0x47C0_D000 0x47FF FFFF 4044KB Reserved
0x4800_0000 0x48FF_FFFF 16MB L4 Slow Peripheral Domain
(see Table 2-7)
0x4900_0000 0x490F_FFFF 1MB EDMA TPCC Registers
0x4910_0000 0x497F_FFFF 7MB Reserved
0x4980_0000 0x498F_FFFF 1MB EDMA TPTC0 Registers
0x4990_0000 0x499F_FFFF 1MB EDMA TPTC1 Registers
0x49A0_0000 0x49AF_FFFF 1MB EDMA TPTC2 Registers
0x49B0_0000 0x49BF_FFFF 1MB EDMA TPTC3 Registers
0x49C0_0000 0x49FF_FFFF 4MB Reserved
0x4A00_0000 0x4AFF_FFFF 16MB L4 Fast Peripheral Domain
(see Table 2-6)
0x4B00_0000 0x4BFF_FFFF 16MB Emulation Subsystem
0x4C00_0000 0x4CFF_FFFF 16MB DDR0 Registers
0x4D00_0000 0x4DFF_FFFF 16MB DDR1 Registers
0x4E00_0000 0x4FFF_FFFF 32MB DDR DMM Registers
0x5000_0000 0x50FF_FFFF 16MB GPMC Registers
0x5100_0000 0x51FF_FFFF 16MB PCIE Registers
0x5200_0000 0x54FF_FFFF 48MB Reserved
0x5500_0000 0x55FF_FFFF 16MB Media Controller
0x5600_0000 0x56FF_FFFF 16MB SGX530
0x5700_0000 0x57FF_FFFF 16MB Reserved
0x5800_0000 0x58FF_FFFF 16MB HDVICP2 Configuration
0x5900_0000 0x59FF_FFFF 16MB HDVICP2 SL2
0x5A00_0000 0x5BFF_FFFF 32MB Reserved
0x5C00_0000 0x5DFF_FFFF 32MB ISS
0x5E00_0000 0x5FFF_FFFF 32MB Reserved
0x6000_0000 0x7FFF_FFFF 512MB DDR DMM TILER Window (see Table 2-8)
0x8000_0000 0xFFFF_FFFF 2GB DDR
0x1 0000 0000 0x1 FFFF FFFF 4GB DDR DMM TILER Extended Address Map
(ISS and HDVPSS only) [see Table 2-8]

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2.12.2 C674x Memory Map

Table 2-4 shows the memory map for the C674x DSP.

Table 2-4. C674x Memory Map

START ADDRESS END ADDRESS
SIZE DESCRIPTION
(HEX) (HEX)
0x0000_0000 0x003F_FFFF 4MB Reserved
0x0040_0000 0x0043_FFFF 256KB HDVICP2 SL2
0x0044_0000 0x007F_FFFF 3840KB Reserved
0x0080_0000 0x0083_FFFF 256KB C674x™ L2 RAM
0x0084_0000 0x00DF_FFFF 5888KB Reserved
0x00E0_0000 0x00E0_7FFF 32KB C674x L1P Cache/RAM
0x00E0_8000 0x00EF_FFFF 992KB Reserved
0x00F0_0000 0x00F0_7FFF 32KB C674x L1D Cache/RAM
0x00F0_8000 0x017F_FFFF 9184KB Reserved
0x0180_0000 0x01BF_FFFF 4MB C674x Internal CFG registers
0x01C0_0000 0x07FF_FFFF 100MB Reserved
0x0800_0000 0x08FF_FFFF 16MB L4 Slow Peripheral Domain
(see Table 2-7)
0x0900_0000 0x090F_FFFF 1MB EDMA TPCC Registers
0x0910_0000 0x097F_FFFF 7MB Reserved
0x0980_0000 0x098F_FFFF 1MB EDMA TPTC0 Registers
0x0990_0000 0x099F_FFFF 1MB EDMA TPTC1 Registers
0x09A0_0000 0x09AF_FFFF 1MB EDMA TPTC2 Registers
0x09B0_0000 0x09BF_FFFF 1MB EDMA TPTC3 Registers
0x09C0_0000 0x09FF_FFFF 4MB Reserved
0x0A00_0000 0x0AFF_FFFF 16MB L4 Fast Peripheral Domain
(see Table 2-6)
0x0B00_0000 0x0FFF_FFFF 80MB Reserved
0x1000_0000 0x10FF_FFFF 16MB C674x Internal Global Address (1)
0x1100_0000 0xFFFF_FFFF 3824MB System MMU Mapped L3
Regions (2)
(1) Addresses 0x1000_0000 to 0x10FF_FFFF are mapped to C674x internal addresses 0x0000_0000 to 0x00FF_FFFF.
(2) For more details on the system MMU features, see the System MMU section of the Chip Level Resources chapter in the
TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual (Literature Number: SPRUGZ8).

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2.12.3 C674x Memory Map (Memory Management Unit Bypassed)

Table 2-5 shows the memory map for the C674x DSP when bypassing the Memory Management Unit.

Table 2-5. MMU Bypassed C674x DSP Memory Map

START ADDRESS END ADDRESS
SIZE DESCRIPTION
(HEX) (HEX)
0x0000_0000 0x007F_FFFF Reserved
0x0080_0000 0x0083_FFFF 256KB C674x™ Level 2 (L2) Cache / RAM
0x0084_0000 0x00DF_FFFF Reserved
0x00E0_0000 0x00E0_7FFF 32KB C674x Level 1 Program (L1P) Cache/RAM
0x00E0_8000 0x00EF_FFFF Reserved
0x00F0_0000 0x00F0_7FFF 32KB C674x Level 1 Data (L1D) Cache and RAM
0x00F0_8000 0x017F_FFFF Reserved
0x0180_0000 0x01BF_FFFF 4MB C674x Interrupt Controller and Configuration Registers
0x01C0_0000 0x07FF_FFFF Reserved
0x0800_0000 0x083F_FFFF 4MB L4 Slow0 Peripheral Domain
(see )
0x0840_0000 0x08FF_FFFF 12MB L4 Slow1 Peripheral Domain
(see )
0x0900_0000 0x090F_FFFF 1MB EDMA Channel Controller 0 Configuration Registers
0x0910_0000 0x097F_FFFF Reserved
0x0980_0000 0x098F_FFFF 1MB EDMA Transfer Controller 0 Configuration Registers
0x0990_0000 0x099F_FFFF 1MB EDMA Transfer Controller 1 Configuration Registers
0x09A0_0000 0x09AF_FFFF 1MB EDMA Transfer Controller 2 Configuration Registers
0x09B0_0000 0x09BF_FFFF 1MB EDMA Transfer Controller 3 Configuration Registers
0x09C0_0000 0x09FF_FFFF Reserved
0x0A00_0000 0x0AFF_FFFF 16MB L4 Fast Peripheral Domain
(see Table 2-6)
0x0B00_0000 0x0FFF_FFFF Reserved
0x1000_0000 0x10FF_FFFF 16MB C674x Internal Global Address (1)
0x1100_0000 0x1FFF+FFFF 240MB GPMC Slave Address Space
0x2000_0000 0x2FFF_FFFF 256MB PCI Express (PCI-e) Slave Port
0x3000_0000 0x3FFF_FFFF Reserved
0x4002_0000 0x400F_FFFF Reserved (BOOTROM)
0x4010_0000 0x402F_FFFF Reserved
0x4030_0000 0x4033_FFFF 256KB On Chip Level 3 (L3) RAM
0x4034_0000 0x43FF_FFFF Reserved
0x4400_0000 0x443F_FFFF 4MB Level 3 Fast (L3F) Interconnect Configuration Registers
0x4440_0000 0x447F_FFFF 4MB Level 3 Mid (L3M) Interconnect Configuration Registers
0x4480_0000 0x44BF_FFFF 4MB Level 3 Slow (L3S) Interconnect Configuration Registers
0x44C0_0000 0x44FF_FFFF Reserved
0x4500_0000 0x45FF_FFFF 16MB Expansion L3 port
0x4600_0000 0x463F_FFFF 4MB McASP0 Data Port
0x4640_0000 0x467F_FFFF 4MB McASP1 Data Port
0x4680_0000 0x46BF_FFFF 4MB McASP2 Data Port
0x46C0_0000 0x46FF_FFFF Reserved
0x4700_0000 0x473F_FFFF 4MB McBSP Peripheral Configuration Registers
0x4740_0000 0x477F_FFFF 4MB USB Subsystem Configuration Registers
0x4780_0000 0x4780_FFFF 64KB Viterbi Coprocessor 2 Configuration Registers

(1) Addresses 0x1000_0000 to 0x10FF_FFFF are mapped to C674x internal addresses 0x0000_0000 to 0x00FF_FFFF.
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Table 2-5. MMU Bypassed C674x DSP Memory Map (continued)

START ADDRESS END ADDRESS
SIZE DESCRIPTION
(HEX) (HEX)
0x4781_0000 0x4781_1FFF 8KB MMC/SD2 Peripheral Configuration Registers
0x4781_2000 0x47FF_FFFF Reserved
0x4800_0000 0x483F_FFFF 4MB L4 Slow0 Peripheral Domain
(see )
0x4840_0000 0x48FF_FFFF 12MB L4 Slow1 Peripheral Domain
(see )
0x4900_0000 0x490F_FFFF 1MB EDMA Channel Controller Registers
0x4910_0000 0x497F_FFFF Reserved
0x4980_0000 0x498F_FFFF 1MB EDMA Transfer Controller 0 Registers
0x4990_0000 0x499F_FFFF 1MB EDMA Transfer Controller 1 Registers
0x49A0_0000 0x49AF_FFFF 1MB EDMA Transfer Controller 2 Registers
0x49B0_0000 0x49BF_FFFF 1MB EDMA Transfer Controller 3 Registers
0x49C0_0000 0x49FF_FFFF Reserved
0x4A00_0000 0x4AFF_FFFF 16MB L4 Fast Peripheral Domain
(see Table 2-6)
0x4B00_0000 0x4BFF_FFFF 16MB Emulation Subsystem
0x4C00_0000 0x4CFF_FFFF 16MB DDR Configuration Registers
0x4D00_0000 0x4FFF_FFFF Reserved
0x5000_0000 0x50FF_FFFF 16MB General Purpose Memory Controller Configuration Registers
0x5100_0000 0x51FF_FFFF 16MB PCI Express (PCIe) Peripheral Configuration Registers
0x5200_0000 0x523F_FFFF Reserved
0x5240_0000 0x527F_FFFF 4MB BitBLT 2D Graphics Engine Configuration Registers
0x5280_0000 0x54BF_FFFF Reserved
0x54C0_0000 0x54FF_FFFF 4MB Analog-to-Digital Converter / Touchscreen Controller DMA
Port Registers
0x5500_0000 0x55FF_FFFF 16MB Media Controller Registers (2)
0x5600_0000 0x56FF_FFFF 16MB SGX530 3D Graphics Engine Configuration Registers
0x5700_0000 0x7FFF_FFFF Reserved
0x8000_0000 0xFFFF_FFFF 2GB DDR Addressable Memory Space
(2) This range maps into the 0x5500 0000 - 0x55FF FFFF region of )

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2.12.4 L4 Memory Map

The L4 Fast Peripheral Domain, L4 Slow Peripheral Domain regions of the memory maps above are
broken out into Table 2-6 and Table 2-7.
For more details on the interconnect topology and connectivity across the L3 and L4 interconnects, see
Table 7-17, System Interconnect.

2.12.4.1 L4 Fast Peripheral Memory Map

Table 2-6. L4 Fast Peripheral Memory Map

Cortex-A8 and L3 Masters C674x DSP
START START SIZE DEVICE NAME
END ADDRESS END ADDRESS
ADDRESS ADDRESS
(HEX) (HEX)
(HEX) (HEX)
0x4A00_0000 0x4A00_07FF 0x0A00_0000 0x0A00_07FF 2KB L4 Fast Configuration - Address/Protection
(AP)
0x4A00_0800 0x4A00_0FFF 0x0A00_0800 0x0A00_0FFF 2KB L4 Fast Configuration - Link Agent (LA)
0x4A00_1000 0x4A00_13FF 0x0A00_1000 0x0A00_13FF 1KB L4 Fast Configuration - Initiator Port (IP0)
0x4A00_1400 0x4A00_17FF 0x0A00_1400 0x0A00_17FF 1KB L4 Fast Configuration - Initiator Port (IP1)
0x4A00_1800 0x4A00_1FFF 0x0A00_1800 0x0A00_1FFF 2KB Reserved
0x4A00_2000 0x4A07_FFFF 0x0A00_2000 0x0A07_FFFF 504KB Reserved
0x4A08_0000 0x4A0F_FFFF 0x0A08_0000 0x0A0F_FFFF 512KB Reserved
0x4A10_0000 0x4A10_7FFF 0x0A10_0000 0x0A10_7FFF 32KB EMAC SW Peripheral Registers
0x4A10_8000 0x4A10_8FFF 0x0A10_8000 0x0A10_8FFF 4KB EMAC SW Support Registers
0x4A14_0000 0x4A14_FFFF 64KB SATA Peripheral Registers
0x4A15_0000 0x4A15_0FFF 4KB SATA Support Registers
0x4A15_1000 0x4A17_FFFF 0x0A15_1000 0x0A17_FFFF 188KB Reserved
0x4A18_0000 0x4A1A_1FFF 0x0A18_0000 0x0A1A_1FFF 136KB Reserved
0x4A1A_2000 0x4A1A_3FFF 0x0A1A_2000 0x0A1A_3FFF 8KB McASP3 Configuration Peripheral Registers
0x4A1A_4000 0x4A1A_4FFF 0x0A1A_4000 0x0A1A_4FFF 4KB McASP3 Configuration Support Registers
0x4A1A_5000 0x4A1A_5FFF 0x0A1A_5000 0x0A1A_5FFF 4KB McASP3 Data Peripheral Registers
0x4A1A_6000 0x4A1A_6FFF 0x0A1A_6000 0x0A1A_6FFF 4KB McASP3 Data Support Registers
0x4A1A_7000 0x4A1A_7FFF 0x0A1A_7000 0x0A1A_7FFF 4KB Reserved
0x4A1A_8000 0x4A1A_9FFF 0x0A1A_8000 0x0A1A_9FFF 8KB McASP4 Configuration Peripheral Registers
0x4A1A_A000 0x4A1A_AFFF 0x0A1A_A000 0x0A1A_AFFF 4KB McASP4 Configuration Support Registers
0x4A1A_B000 0x4A1A_BFFF 0x0A1A_B000 0x0A1A_BFFF 4KB McASP4 Data Peripheral Registers
0x4A1A_C000 0x4A1A_CFFF 0x0A1A_C000 0x0A1A_CFFF 4KB McASP4 Data Support Registers
0x4A1A_D000 0x4A1A_DFFF 0x0A1A_D000 0x0A1A_DFFF 4KB Reserved
0x4A1A_E000 0x4A1A_FFFF 0x0A1A_E000 0x0A1A_FFFF 8KB McASP5 Configuration Peripheral Registers
0x4A1B_0000 0x4A1B_0FFF 0x0A1B_0000 0x0A1B_0FFF 4KB McASP5 Configuration Support Registers
0x4A1B_1000 0x4A1B_1FFF 0x0A1B_1000 0x0A1B_1FFF 4KB McASP5 Data Peripheral Registers
0x4A1B_2000 0x4A1B_2FFF 0x0A1B_2000 0x0A1B_2FFF 4KB McASP5 Data Support Registers
0x4A1B_3000 0x4A1B_5FFF 0x0A1B_3000 0x0A1B_5FFF 12KB Reserved
0x4A1B_6000 0x4A1B_6FFF 0x0A1B_6000 0x0A1B_6FFF 4KB Reserved
0x4A1B_4000 0x4AFF_FFFF 0x0A1B_4000 0x0AFF_FFFF 14632KB Reserved

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2.12.4.2 L4 Slow Peripheral Memory Map

Table 2-7. L4 Slow Peripheral Memory Map

Cortex-A8 and L3 Masters C674x DSP
START SIZE DEVICE NAME
END ADDRESS START END ADDRESS
ADDRESS
(HEX) ADDRESS (HEX) (HEX)
(HEX)
0x4800_0000 0x4800_07FF 0x0800_0000 0x0800_07FF 2KB L4 Slow Configuration –
Address/Protection (AP)
0x4800_0800 0x4800_0FFF 0x0800_0800 0x0800_0FFF 2KB L4 Slow Configuration – Link Agent
(LA)
0x4800_1000 0x4800_13FF 0x0800_1000 0x0800_13FF 1KB L4 Slow Configuration – Initiator Port
(IP0)
0x4800_1400 0x4800_17FF 0x0800_1400 0x0800_17FF 1KB L4 Slow Configuration – Initiator Port
(IP1)
0x4800_1800 0x4800_1FFF 0x0800_1800 0x0800_1FFF 2KB Reserved
0x4800_2000 0x4800_7FFF 0x0800_2000 0x0800_7FFF 24KB Reserved
0x4800_8000 0x4800_8FFF 0x0800_8000 0x0800_8FFF 32KB Reserved
0x4801_0000 0x4801_0FFF 0x0801_0000 0x0801_0FFF 4KB System MMU Peripheral Registers
0x4801_1000 0x4801_1FFF 0x0801_1000 0x0801_1FFF 4KB System MMU Support Registers
0x4801_2000 0x4801_FFFF 0x0801_2000 0x0801_FFFF 56KB Reserved
0x4802_0000 0x4802_0FFF 0x0802_0000 0x0802_0FFF 4KB UART0 Peripheral Registers
0x4802_1000 0x4802_1FFF 0x0802_1000 0x0802_1FFF 4KB UART0 Support Registers
0x4802_2000 0x4802_2FFF 0x0802_2000 0x0802_2FFF 4KB UART1 Peripheral Registers
0x4802_3000 0x4802_3FFF 0x0802_3000 0x0802_3FFF 4KB UART1 Support Registers
0x4802_4000 0x4802_4FFF 0x0802_4000 0x0802_4FFF 4KB UART2 Peripheral Registers
0x4802_5000 0x4802_5FFF 0x0802_5000 0x0802_5FFF 4KB UART2 Support Registers
0x4802_6000 0x4802_7FFF 0x0802_6000 0x0802_7FFF 8KB Reserved
0x4802_8000 0x4802_8FFF 0x0802_8000 0x0802_8FFF 4KB I2C0 Peripheral Registers
0x4802_9000 0x4802_9FFF 0x0802_9000 0x0802_9FFF 4KB I2C0 Support Registers
0x4802_A000 0x4802_AFFF 0x0802_A000 0x0802_AFFF 4KB I2C1 Peripheral Registers
0x4802_B000 0x4802_BFFF 0x0802_B000 0x0802_BFFF 4KB I2C1 Support Registers
0x4802_C000 0x4802_DFFF 0x0802_C000 0x0802_DFFF 8KB Reserved
0x4802_E000 0x4802_EFFF 0x0802_E000 0x0802_EFFF 4KB TIMER1 Peripheral Registers
0x4802_F000 0x4802_FFFF 0x0802_F000 0x0802_FFFF 4KB TIMER1 Support Registers
0x4803_0000 0x4803_0FFF 0x0803_0000 0x0803_0FFF 4KB SPI0 Peripheral Registers
0x4803_1000 0x4803_1FFF 0x0803_1000 0x0803_1FFF 4KB SPI0 Support Registers
0x4803_2000 0x4803_2FFF 0x0803_2000 0x0803_2FFF 4KB GPIO0 Peripheral Registers
0x4803_3000 0x4803_3FFF 0x0803_3000 0x0803_3FFF 4KB GPIO0 Support Registers
0x4803_4000 0x4803_7FFF 0x0803_4000 0x0803_7FFF 16KB Reserved
0x4803_8000 0x4803_9FFF 0x0803_8000 0x0803_9FFF 8KB McASP0 CFG Peripheral Registers
0x4803_A000 0x4803_AFFF 0x0803_A000 0x0803_AFFF 4KB McASP0 CFG Support Registers
0x4803_B000 0x4803_BFFF 0x0803_B000 0x0803_BFFF 4KB Reserved
0x4803_C000 0x4803_DFFF 0x0803_C000 0x0803_DFFF 8KB McASP1 CFG Peripheral Registers
0x4803_E000 0x4803_EFFF 0x0803_E000 0x0803_EFFF 4KB McASP1 CFG Support Registers
0x4803_F000 0x4803_FFFF 0x0803_F000 0x0803_FFFF 4KB Reserved
0x4804_0000 0x4804_0FFF 0x0804_0000 0x0804_0FFF 4KB TIMER2 Peripheral Registers
0x4804_1000 0x4804_1FFF 0x0804_1000 0x0804_1FFF 4KB TIMER2 Support Registers
0x4804_2000 0x4804_2FFF 0x0804_2000 0x0804_2FFF 4KB TIMER3 Peripheral Registers
0x4804_3000 0x4804_3FFF 0x0804_3000 0x0804_3FFF 4KB TIMER3 Support Registers
0x4804_4000 0x4804_4FFF 0x0804_4000 0x0804_4FFF 4KB TIMER4 Peripheral Registers

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Table 2-7. L4 Slow Peripheral Memory Map (continued)

Cortex-A8 and L3 Masters C674x DSP
START SIZE DEVICE NAME
END ADDRESS START END ADDRESS
ADDRESS
(HEX) ADDRESS (HEX) (HEX)
(HEX)
0x4804_5000 0x4804_5FFF 0x0804_5000 0x0804_5FFF 4KB TIMER4 Support Registers
0x4804_6000 0x4804_6FFF 0x0804_6000 0x0804_6FFF 4KB TIMER5 Peripheral Registers
0x4804_7000 0x4804_7FFF 0x0804_7000 0x0804_7FFF 4KB TIMER5 Support Registers
0x4804_8000 0x4804_8FFF 0x0804_8000 0x0804_8FFF 4KB TIMER6 Peripheral Registers
0x4804_9000 0x4804_9FFF 0x0804_9000 0x0804_9FFF 4KB TIMER6 Support Registers
0x4804_A000 0x4804_AFFF 0x0804_A000 0x0804_AFFF 4KB TIMER7 Peripheral Registers
0x4804_B000 0x4804_BFFF 0x0804_B000 0x0804_BFFF 4KB TIMER7 Support Registers
0x4804_C000 0x4804_CFFF 0x0804_C000 0x0804_CFFF 4KB GPIO1 Peripheral Registers
0x4804_D000 0x4804_DFFF 0x0804_D000 0x0804_DFFF 4KB GPIO1 Support Registers
0x4804_E000 0x4804_FFFF 0x0804_E000 0x0804_FFFF 8KB Reserved
0x4805_0000 0x4805_1FFF 0x0805_0000 0x0805_1FFF 8KB McASP2 CFG Peripheral Registers
0x4805_2000 0x4805_2FFF 0x0805_2000 0x0805_2FFF 4KB McASP2 CFG Support Registers
0x4805_3000 0x4805_FFFF 0x0805_3000 0x0805_FFFF 52KB Reserved
0x4806_0000 0x4806_FFFF 64KB MMC/SD/SDIO0 Peripheral Registers
0x4807_0000 0x4807_0FFF 4KB MMC/SD/SDIO0 Support Registers
0x4807_1000 0x4807_FFFF 0x0807_1000 0x0807_FFFF 60KB Reserved
0x4808_0000 0x4808_FFFF 64KB ELM Peripheral Registers
0x4809_0000 0x4809_0FFF 4KB ELM Support Registers
0x4809_1000 0x4809_FFFF 0x0809_1000 0x0809_FFFF 60KB Reserved
0x480A_0000 0x480A_FFFF 0x080A_0000 0x080A_FFFF 64KB Reserved
0x480B_0000 0x480B_0FFF 0x080B_0000 0x080B_0FFF 4KB Reserved
0x480B_1000 0x480B_FFFF 0x080B_1000 0x080B_FFFF 60KB Reserved
0x480C_0000 0x480C_0FFF 4KB RTC Peripheral Registers
0x480C_1000 0x480C_1FFF 4KB RTC Support Registers
0x480C_2000 0x480C_3FFF 0x080C_2000 0x080C_3FFF 8KB Reserved
0x480C_4000 0x480C_7FFF 0x080C_4000 0x080C_7FFF 16KB Reserved
0x480C_8000 0x480C_8FFF 0x080C_8000 0x080C_8FFF 4KB Mailbox Peripheral Registers
0x480C_9000 0x480C_9FFF 0x080C_9000 0x080C_9FFF 4KB Mailbox Support Registers
0x480C_A000 0x480C_AFFF 0x080C_A000 0x080C_AFFF 4KB Spinlock Peripheral Registers
0x480C_B000 0x480C_BFFF 0x080C_B000 0x080C_BFFF 4KB Spinlock Support Registers
0x480C_C000 0x480F_FFFF 0x080C_C000 0x080F_FFFF 208KB Reserved
0x4810_0000 0x4811_FFFF 128KB HDVPSS Peripheral Registers
0x4812_0000 0x4812_0FFF 4KB HDVPSS Support Registers
0x4812_1000 0x4812_1FFF 0x0812_1000 0x0812_1FFF 4KB Reserved
0x4812_2000 0x4812_2FFF 4KB HDMI Peripheral Registers
0x4812_3000 0x4812_3FFF 4KB HDMI Support Registers
0x4812_4000 0x4813_FFFF 0x0812_4000 0x0813_FFFF 112KB Reserved
0x4814_0000 0x4815_FFFF 0x0814_0000 0x0815_FFFF 128KB Control Module Peripheral Registers
(C674x DSP Restricted to only
exposed peripherals)
0x4816_0000 0x4816_0FFF 0x0816_0000 0x0816_0FFF 4KB Control Module Support Registers
(C674x DSP Restricted to only
exposed peripherals)
0x4816_1000 0x4817_FFFF 0x0816_1000 0x0817_FFFF 124KB Reserved
0x4818_0000 0x4818_2FFF 0x0818_0000 0x0818_2FFF 12KB PRCM Peripheral Registers
(C674x DSP Restricted to only
exposed peripherals)

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Table 2-7. L4 Slow Peripheral Memory Map (continued)

Cortex-A8 and L3 Masters C674x DSP
START SIZE DEVICE NAME
END ADDRESS START END ADDRESS
ADDRESS
(HEX) ADDRESS (HEX) (HEX)
(HEX)
0x4818_3000 0x4818_3FFF 0x0818_3000 0x0818_3FFF 4KB PRCM Support Registers
(C674x DSP Restricted to only
exposed peripherals)
0x4818_4000 0x4818_7FFF 0x0818_4000 0x0818_7FFF 16KB Reserved
0X4818_8000 0X4818_BFFF 0x0818_8000 0x0818_BFFF 16KB Reserved
0x4818_C000 0x4818_CFFF 4KB OCP Watchpoint Peripheral Registers
0x4818_D000 0x4818_DFFF 4KB OCP Watchpoint Support Registers
0x4818_E000 0x4818_EFFF 0x0818_E000 0x0818_EFFF 4KB Reserved
0x4818_F000 0x4818_FFFF 0x0818_F000 0x0818_FFFF 4KB Reserved
0x4819_0000 0x4819_3FFF 0x0819_0000 0x0819_3FFF 16KB Reserved
0x4819_4000 0x4819_BFFF 0x0819_4000 0x0819_BFFF 32KB Reserved
0x4819_C000 0x481F_FFFF 0x0819_C000 0x081F_FFFF 400KB Reserved
0x4819_C000 0x4819_CFFF 0x0819_C000 0x0819_CFFF 4KB I2C2 Peripheral Registers
0x4819_D000 0x4819_DFFF 0x0819_D000 0x0819_DFFF 4KB I2C2 Support Registers
0x4819_E000 0x4819_EFFF 0x0819_E000 0x0819_EFFF 4KB I2C3 Peripheral Registers
0x4819_F000 0x4819_FFFF 0x0819_F000 0x0819_FFFF 4KB I2C3 Support Registers
0x481A_0000 0x481A_0FFF 0x081A_0000 0x081A_0FFF 4KB SPI1 Peripheral Registers
0x481A_1000 0x481A_1FFF 0x081A_1000 0x081A_1FFF 4KB SPI1 Support Registers
0x481A_2000 0x481A_2FFF 0x081A_2000 0x081A_2FFF 4KB SPI2 Peripheral Registers
0x481A_3000 0x481A_3FFF 0x081A_3000 0x081A_3FFF 4KB SPI2 Support Registers
0x481A_4000 0x481A_4FFF 0x081A_4000 0x081A_4FFF 4KB SPI3 Peripheral Registers
0x481A_5000 0x481A_5FFF 0x081A_5000 0x081A_5FFF 4KB SPI3 Support Registers
0x481A_6000 0x481A_6FFF 0x081A_6000 0x081A_6FFF 4KB UART3 Peripheral Registers
0x481A_7000 0x481A_7FFF 0x081A_7000 0x081A_7FFF 4KB UART3 Support Registers
0x481A_8000 0x481A_8FFF 0x081A_8000 0x081A_8FFF 4KB UART4 Peripheral Registers
0x481A_9000 0x481A_9FFF 0x081A_9000 0x081A_9FFF 4KB UART4 Support Registers
0x481A_A000 0x481A_AFFF 0x081A_A000 0x081A_AFFF 4KB UART5 Peripheral Registers
0x481A_B000 0x481A_BFFF 0x081A_B000 0x081A_BFFF 4KB UART5 Support Registers
0x481A_C000 0x481A_CFFF 0x081A_C000 0x081A_CFFF 4KB GPIO2 Peripheral Registers
0x481A_D000 0x481A_DFFF 0x081A_D000 0x081A_DFFF 4KB GPIO2 Support Registers
0x481A_E000 0x481A_EFFF 0x081A_E000 0x081A_EFFF 4KB GPIO3 Peripheral Registers
0x481A_F000 0x481A_FFFF 0x081A_F000 0x081A_FFFF 4KB GPIO3 Support Registers
0x481B_0000 0x481B_FFFF 0x081B_0000 0x081B_FFFF 64KB Reserved
0x481C_0000 0x481C_0FFF 0x081C_0000 0x081C_0FFF 4KB Reserved
0x481C_1000 0x481C_1FFF 0x081C_1000 0x081C_1FFF 4KB TIMER8 Peripheral Registers
0x481C_2000 0x481C_2FFF 0x081C_2000 0x081C_2FFF 4KB TIMER8 Support Registers
0x481C_3000 0x481C_3FFF 4KB SYNCTIMER32K Peripheral Registers
0x481C_4000 0x481C_4FFF 4KB SYNCTIMER32K Support Registers
0x481C_5000 0x481C_5FFF 4KB PLLSS Peripheral Registers
0x481C_6000 0x481C_6FFF 4KB PLLSS
0x481C_7000 0x481C_7FFF 4KB WDT0 Peripheral Registers
0x481C_8000 0x481C_8FFF 4KB WDT0 Support Registers
0x481C_9000 0x481C_9FFF 0x081C_9000 0x081C_9FFF 8KB Reserved
0x481C_A000 0x481C_BFFF 0x081C_A000 0x081C_BFFF 8KB Reserved
0x481C_C000 0x481C_DFFF 8KB DCAN0 Peripheral Registers

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Table 2-7. L4 Slow Peripheral Memory Map (continued)

Cortex-A8 and L3 Masters C674x DSP
START SIZE DEVICE NAME
END ADDRESS START END ADDRESS
ADDRESS
(HEX) ADDRESS (HEX) (HEX)
(HEX)
0x481C_E000 0x481C_FFFF 8KB DCAN0 Support Registers
0x481D_0000 0x481D_1FFF 8KB DCAN1 Peripheral Registers
0x481D_2000 0x481D_3FFF 8KB DCAN1 Support Registers
0x481D_4000 0x481D_5FFF 0x081D_4000 0x081D_5FFF 8KB Reserved
0x481D_6000 0x481D_6FFF 0x081D_6000 0x081D_6FFF 4KB Reserved
0x481D_7000 0x481D_7FFF 0x081D_7000 0x081D_7FFF 4KB Reserved
0x481D_8000 0x481E_7FFF 64KB MMC/SD/SDIO1 Peripheral Registers
0x481E_8000 0x481E_8FFF 4KB MMC/SD/SDIO1 Support Registers
0x481E_9000 0x481F_FFFF 0x081E_9000 0x081F_FFFF 52KB Reserved
0x4820_0000 0x4820_0FFF 4KB Interrupt controller (1)
0x4820_1000 0x4823_FFFF 0x0820_1000 0x0823_FFFF 252KB Reserved (1)
0x4824_0000 0x4824_0FFF 4KB MPUSS config register (1)
0x4824_1000 0x4827_FFFF 0x0824_1000 0x0827_FFFF 252KB Reserved (1)
0x4828_0000 0x4828_0FFF 4KB Reserved (1)
0x4828_1000 0x482F_FFFF 0x0828_1000 0x082F_FFFF 508KB Reserved (1)
0x4830_0000 0x48FF_FFFF 0x0830_0000 0x08FF_FFFF 13MB Reserved
(1) These regions decoded internally by the Cortex™-A8 Subsystem and are not physically part of the L4 Slow. They are included here only
for reference when considering the Cortex™-A8 Memory Map. For Masters other than the Cortex-A8 these regions are reserved.

2.12.5 DDR DMM TILER Extended Addressing Map

The TILER includes an additional 4-GBytes of addressing range, enabled by a 33rd address bit, to access
the frame buffer in rotated and mirrored views. shows the details of the TILER Extended Address
Mapping. This entirety of this additional range is only accessible to the HDVPSS and ISS subsystems.
However, other masters can access any one single view through the 512-MB TILER region in the base
4GByte address memory map.

Table 2-8. DDR DMM TILER Extended Address Mapping

START ADDRESS END ADDRESS
BLOCK NAME SIZE DESCRIPTION
(HEX) (HEX)
TILER View 0 0x1 0000_0000 0x1 1FFF_FFFF 512MB Natural 0° View
TILER View 1 0x1 2000_0000 0x1 3FFF_FFFF 512MB 0° with Vertical Mirror
View
TILER View 2 0x1 4000_0000 0x1 5FFF_FFFF 512MB 0° with Horizontal Mirror
View
TILER View 3 0x1 6000_0000 0x1 7FFF_FFFF 512MB 180° View
TILER View 4 0x1 8000_0000 0x1 9FFF_FFFF 512MB 90° with Vertical Mirror
View
TILER View 5 0x1 A000_0000 0x1 BFFF_FFFF 512MB 270° View
TILER View 6 0x1 C000_0000 0x1 DFFF_FFFF 512MB 90° View
TILER View 7 0x1 E000_0000 0x1 FFFF_FFFF 512MB 90° with Horizontal Mirror
View

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3 Device Pins

3.1 Pin Maps

Figure 3-1 through Figure 3-8 show the bottom view of the package pin assignments in eight pin maps (A,
B, C, D, E, F, G, and H).

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E F G H

A B C D

SD1_CMD/
P SD1_DAT[0]
GP0[0]
SD1_CLK SD1_DAT[2]_SDRW SD1_DAT[1]_SDIRQ SD1_DAT[3] DVDD_SD

MCA[2]_AXR[0]/
SD0_CMD/
SD0_DAT[6]/ MCA[1]_AXR[3]/
N SD1_CMD/
UART5_RXD MCB_CLKR
DVDD
GP0[2]
GP0[12]

MCA[0]_AXR[9]/
MCA[1]_ACLKR/ MCA[1]_AFSR/ MCA[0]_AXR[5]/ MCA[0]_AXR[6]/
M MCA[1]_AXR[4] MCA[1]_AXR[5] MCA[1]_AXR[9] MCB_DR
MCA[0]_AXR[3] MCB_CLKX/ VDDA_1P8
MCB_CLKR

AUD_CLKIN0/
MCA[5]_AXR[1]/
MCA[0]_AXR[8]/ MCA[0]_AXR[2]/ MCA[0]_AXR[7]/ MCA[5]_AXR[0]/
MCA[0]_AXR[7]/ MCA[4]_AXR[3]/
L MCB_FSX/
MCB_DX
MCA[0]_AFSX I2C[3]_SDA MCA[0]_AHCLKX/
TIM7_IO/
MCA[4]_AXR[2]/
MCB_FSR MCA[3]_AHCLKX]/ GP0[27]
GP0[28]
USB1_DRVVBUS

MCA[0]_AFSR/ MCA[0]_ACLKR/ MCA[4]_ACLKX/

K MCA[5]_AXR[3] MCA[5]_AXR[2]
RSTOUT_WD_OUT
GP0[21]

MCA[4]_AXR[1]/ CLKIN32/
MCA[0]_AXR[1]/ MCA[0]_AXR[0] MCA[5]_ACLKX/ MCA[3]_AXR[3]/ CLKOUT0/
J TIM6_IO/ RESET
I2C[3]_SCL GP0[25] MCA[1]_AXR[9] TIM3_IO/
GP0[24]
GP3[31]

AUD_CLKIN2/
MCA[0]_AXR[9]/
MCA[2]_AXR[3]/
MCA[2]_AHCLKX/
MCA[1]_AXR[7]/ MCA[4]_AFSX/ MCA[3]_AFSX/ MCA[5]_AFSX/ MCA[4]_AXR[0]/
H MCA[5]_AHCLKX/
TIM3_IO/ GP0[22] GP0[17] GP0[26] GP0[23]
NMI
EDMA_EVT2/
GP0[15]
TIM3_IO/
GP0[9]

MCA[3]_AXR[0]/ MCA[3]_AXR[1]/
MCA[3]_ACLKX/
G TIM4_IO/ TIM5_IO/
GP0[16]
GP0[18] GP0[19]

MCA[3]_AXR[2]/
F POR MCA[1]_AXR[8]/ DDR[1]_D[1] DDR[1]_DQM[0] DDR[1]_D[4] DDR[1]_D[17]
GP0[20]

E DDR[1]_D[3] DDR[1]_D[2] DDR[1]_D[0] DDR[1]_D[5] DDR[1]_D[21]

D DDR[1]_DQS[0] DDR[1]_DQS[0] DDR[1]_D[6] DDR[1]_D[9] DDR[1]_D[22]

C DDR[1]_D[7] DDR[1]_D[8] DDR[1]_D[10] DDR[1]_D[13] DDR[1]_D[18] DDR[1]_D[20]

B DDR[1]_VTP DDR[1]_DQM[1] DDR[1]_DQS[1] DDR[1]_D[12] DDR[1]_D[19] DDR[1]_DQS[2] DDR[1]_D[23]

A VSS DDR[1]_D[11] DDR[1]_DQS[1] DDR[1]_D[14] DDR[1]_D[15] DDR[1]_DQS[2] DDR[1]_D[27]

1 2 3 4 5 6 7

Figure 3-1. Pin Map A

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E F G H

A B C D

P DVDD DVDD_SD LDOCAP_DSP VDDA_DSPPLL_1P8 CVDD VSS CVDD

N VSS CVDD_DSP LDOCAP_HDVICP LDOCAP_HDVICPRAM VSS CVDD_HDVICP CVDD_HDVICP

M DVDD VSS CVDD_DSP LDOCAP_DSPRAM CVDD_DSP CVDD_HDVICP CVDD_HDVICP

L VSS CVDD_DSP CVDD_DSP CVDD_DSP CVDD_DSP VSS CVDD_HDVICP

K CVDD CVDD_DSP VSS CVDD VSS VSS

J DVDD_DDR[1] DVDD_DDR[1] VSS DVDD_DDR[1] VSS

H DDR[1]_D[16] DDR[1]_D[25] DDR[1]_ODT[0] DDR[1]_CKE DVDD_DDR[1] DVDD_DDR[1] DVDD_DDR[1]

G DDR[1]_DQM[2] DDR[1]_DQM[3] DDR[1]_RST DDR[1]_CS[1] DDR[1]_CS[0] DVDD_DDR[1] VREFSSTL_DDR[1]

F DDR[1]_D[26] DDR[1]_D[24] DDR[1]_A[1] DDR[1]_ODT[1] DDR[1]_A[10] DDR[1]_CAS DDR[1]_BA[0]

E DVDD_DDR[1] DVDD_DDR[1] DDR[1]_A[13] DDR[1]_WE DDR[1]_A[8]

D DDR[1]_D[29] VSS DDR[1]_A[14] DDR[1]_BA[2] DDR[1]_A[6]

C DDR[1]_D[30] DDR[1]_D[28] DDR[1]_A[2] DDR[1]_RAS DDR[1]_A[9]

B DDR[1]_DQS[3] DDR[1]_D[31] DDR[1]_A[12] DDR[1]_A[0] DDR[1]_A[5] DDR[1]_CLK DDR[1]_A[4]

A DDR[1]_DQS[3] DDR[1]_A[7] DDR[1]_BA[1] DDR[1]_A[11] VSS DDR[1]_CLK DDR[1]_A[3]

8 9 10 11 12 13 14

Figure 3-2. Pin Map B

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E F G H

A B C D

VSS CVDD VSS LDOCAP_RAM0 VSS DVDD_GPMCB VSS P

VSS VSS CVDD VDDA_L3PLL_1P8 CVDD VSS VSS N

VSS CVDD VSS CVDD VSS DVDD_GPMC VSS M

CVDD VSS CVDD LDOCAP_RAM2 CVDD VDDA_1P8 DVDD_GPMC L

VSS VSS VSS CVDD VSS DVDD_GPMC K

DVDD_DDR[0] DVDD_DDR[0] DVDD_DDR[0] DVDD_DDR[0] VSS J

VDDA_DDRPLL_1P8 DVDD_DDR[0] DVDD_DDR[0] DDR[0]_CKE DDR[0]_ODT[1] DDR[0]_D[24] DDR[0]_D[18] H

VREFSSTL_DDR[0] DVDD_DDR[0] DDR[0]_CS[1] DDR[0]_ODT[0] DDR[0]_RST DDR[0]_D[26] DDR[0]_D[19] G

DDR[0]_BA[0] DDR[0]_A[14] DDR[0]_A[13] DDR[0]_CS[0] DDR[0]_A[1] DDR[0]_DQM[3] DDR[0]_D[25] F

DDR[0]_A[3] DDR[0]_A[12] DDR[0]_A[7] DVDD_DDR[0] DVDD_DDR[0] E

DDR[0]_A[4] DDR[0]_A[11] DDR[0]_A[2] VSS DDR[0]_D[30] D

DDR[0]_A[9] DDR[0]_WE DDR[0]_CAS DDR[0]_D[28] DDR[0]_D[29] C

DDR[0]_A[8] DDR[0]_CLK DDR[0]_A[5] DDR[0]_RAS DDR[0]_A[0] DDR[0]_D[31] DDR[0]_DQS[3] B

DDR[0]_A[6] DDR[0]_CLK VSS DDR[0]_BA[2] DDR[0]_A[10] DDR[0]_BA[1] DDR[0]_DQS[3] A

15 16 17 18 19 20 21

Figure 3-3. Pin Map C

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E F G H

A B C D

SD2_DAT[5]/ EMAC[0]_MRXD[1]/
GPMC_CS[3]/
GPMC_A[26]/ EMAC[0]_RGRXD[0]/ GPMC_CS[4]/
MDIO/ VIN[1]B_CLK/
GPMC_A[22]/ VIN[1]B_D[6]/ SD2_CMD/ RSV13 RSV12 P
GP1[12] SPI[2]_SCS[0]/
TIM6_IO/ EMAC[0]_RMTXD[1]/ GP1[8]
GP1[26]
GP1[21] GP3[29]

SD2_DAT[6]/
GPMC_A[25]/
VSS GPMC_A[21]/ RSV11 RSV10 N
UART2_TXD/
GP1[20]

GPMC_ADV_ALE/
SD2_DAT[1]_SDIRQ/ GPMC_CS[2]/
SD2_CLK/ GPMC_CS[6]/
VDDA_1P8 GPMC_A[3]/ GPMC_A[24]/ RSV8 RSV9 M
GP1[15] TIM5_IO/
GP1[13] GP1[25]
GP1[28]

EMAC[0]_MTCLK/
EMAC[0]_MCOL/ SD2_DAT[7]/
EMAC[0]_RGRXC/
EMAC[0]_RGRXCTL/ GPMC_A[24]/ SD2_DAT[0]/
VIN[1]B_D[0]/
VSS VIN[1]B_D[1]/ GPMC_A[20]/ GPMC_A[4]/ RSV6 RSV7 L
SPI[3]_SCS[3]/
EMAC[0]_RMRXD[0]/ UART2_RXD/ GP1[14]
I2C[2]_SDA/
GP3[24] GP1[19]
GP3[23]

EMAC[0]_MRXDV/ EMAC[0]_GMTCLK/
SD2_DAT[2]_SDRW/ GPMC_CS[1]/
EMAC[1]_RGRXD[1]/ EMAC[1]_RGRXC/
GPMC_A[2]/ GPMC_A[25]/ K
GPMC_A[5]/ GPMC_A[6]/
GP2[6] GP1[24]
SPI[2]_SCLK SPI[2]_D[1]

EMAC[0]_MRXD[3]/
EMAC[0]_MTXD[6]/ EMAC[0]_MTXEN/ EMAC[0]_MRXER/
EMAC[0]_MTXD[0]/ EMAC[1]_RGRXCTL/
EMAC[1]_RGRXD[0]/ EMAC[1]_RGRXD[2]/ EMAC[0]_RGTXCTL/ EMAC_RMREFCLK/ SD2_DAT[3]/
EMAC[1]_RGRXD[3]/ GPMC_A[27]/
EMAC[1]_RMTXD[0]/ EMAC[1]_RMTXEN/ VIN[1]B_D[3]/ TIM2_IO/ GPMC_A[1]/ J
GPMC_A[7]/ GPMC_A[26]/
GPMC_A[13]/ GPMC_A[15]/ EMAC[0]_RMRXER/ GP1[10] GP2[5]
SPI[2]_D[0] GPMC_A[0]/
UART1_TXD UART1_RTS GP3[26]
UART5_RXD

EMAC[0]_MRCLK/
EMAC[0]_MTXD[2]/ EMAC[0]_MTXD[3]/ EMAC[0]_MTXD[7]/
EMAC[0]_MTXD[1]/ EMAC[0]_MRXD[5]/ EMAC[0]_RGTXC/
EMAC[1]_RGTXCTL/ EMAC[1]_RGTXD[0]/ EMAC[1]_RGTXD[3]/
EMAC[1]_RGTXD[1]/ EMAC[0]_RGTXD[3]/ VIN[1]B_D[4]/ MDCLK/
EMAC[1]_RMRXD[0]/ EMAC[1]_RMRXD[1]/ EMAC[1]_RMTXD[1]/ H
GPMC_A[8]/ GPMC_A[2]/ EMAC[0]_RMCRSDV/ GP1[11]
GPMC_A[9]/ GPMC_A[10]/ GPMC_A[14]/
UART4_RXD UART5_CTS SPI[3]_SCS[2]/
UART4_TXD UART4_CTS UART1_CTS
GP3[27]

EMAC[0]_MTXD[4]/ EMAC[0]_MRXD[0]/
EMAC[0]_MRXD[7]/
EMAC[1]_RGTXD[2]/ EMAC[0]_RGTXD[0]/
EMAC[0]_RGTXD[1]/
EMAC[1]_RMRXER/ VIN[1]B_D[5]/ G
GPMC_A[4]/
GPMC_A[11]/ EMAC[0]_RMTXD[0]/
SPI[2]_SCS[3]
UART4_RTS GP3[28]

EMAC[0]_MTXD[5]/
EMAC[0]_MRXD[6]/
EMAC[1]_RGTXC/
EMAC[0]_RGTXD[2]/
DDR[0]_D[17] DDR[0]_D[4] DDR[0]_D[3] DDR[0]_D[1] EMAC[1]_RMCRSDV/ F
GPMC_A[3]/
GPMC_A[12]/
UART5_RTS
UART1_RXD

DDR[0]_D[21] DDR[0]_D[5] DDR[0]_D[2] DDR[0]_D[0] DDR[0]_DQM[0] E

DDR[0]_D[20] DDR[0]_D[13] DDR[0]_D[6] DDR[0]_DQS[0] DDR[0]_DQS[0] D

DDR[0]_D[22] DDR[0]_DQM[2] DDR[0]_D[9] DDR[0]_D[10] DDR[0]_D[8] DDR[0]_D[7] C

DDR[0]_D[23] DDR[0]_DQS[2] DDR[0]_D[16] DDR[0]_D[12] DDR[0]_DQS[1] DDR[0]_VTP DDR[0]_DQM[1] B

DDR[0]_D[27] DDR[0]_DQS[2] DDR[0]_D[15] DDR[0]_D[14] DDR[0]_DQS[1] DDR[0]_D[11] VSS A

22 23 24 25 26 27 28

Figure 3-4. Pin Map D

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UART0_DCD/
UART3_RXD/ DCAN0_TX/
VOUT[0]_G_Y_YC[2]/
DEVOSC_MXI/ SPI[0]_SCS[3]/ UART2_TXD/
AH VSS DEVOSC_MXO UART0_RXD EMU3/
DEV_CLKIN I2C[2]_SCL/ I2C[3]_SDA/
GP2[24]
SD1_POW/ GP1[0]
GP1[2]

UART0_DSR/
UART0_DTR/ UART3_TXD/ DCAN0_RX/
VOUT[0]_B_CB_C[2]
UART3_CTS/ SPI[0]_SCS[2]/ UART2_RXD/
AG VSS VSSA_DEVOSC UART0_TXD EMU2/
UART1_TXD/ I2C[2]_SDA/ I2C[3]_SCL/
GP2[22]
GP1[4] SD1_SDWP/ GP1[1]
GP1[3]

UART0_RTS/
UART0_RIN/
UART4_TXD/
UART3_RTS/
AF SERDES_CLKP SERDES_CLKN SPI[0]_D[1] DCAN1_RX/ VOUT[0]_R_CR[6]/
UART1_RXD/
SPI[1]_SCS[2]/
GP1[5]
SD2_SDCD

SPI[0]_SCS[1]/
UART0_CTS/
SD1_SDCD/
UART4_RXD/
SATA_ACT0_LED/
AE VSS VSS SPI[0]_D[0] DCAN1_TX/
EDMA_EVT1/
SPI[1]_SCS[3]/
TIM4_IO/
SD0_SDCD
GP1[6]

SPI[1]_SCS[0]/
AD PCIE_TXN0 PCIE_TXP0 RTCK SPI[0]_SCS[0]
GP1[16]

SPI[1]_SCLK/
AC PCIE_RXN0 PCIE_RXP0 I2C[0]_SCL TDO SPI[0]_SCLK
GP1[17]

AB SATA_TXN0 SATA_TXP0 I2C[0]_SDA

SPI[1]_D[1]/ MCA[2]_AFSX/ SPI[1]_D[0]/

AA SATA_RXP0 SATA_RXN0 TRST TMS
GP1[18] GP0[11] GP1[26]

SD0_DAT[2]_SDRW/ SD0_DAT[3]/ SD0_DAT[1]_SDIRQ/

SD0_CLK/
Y VSS VSS SD1_DAT[6]/ SD1_DAT[7]/ SD1_DAT[5]/ TDI
GP0[1]
GP0[5] GP0[6] GP0[4]

DEVOSC_WAKE/
SPI[1]_SCS[1]/
W GP1[7] GP1[8] TCLK
TIM5_IO/
GP1[7]

MCA[2]_AXR[2]/ MCA[2]_AXR[1]/
MCA[1]_AXR[0]/ MCA[1]_AXR[6]/ SD0_DAT[7]/
V GP1[9] GP1[10] MCA[1]_AFSX VSS
SD0_DAT[4] TIM2_IO/ UART5_TXD/
GP0[14] GP0[13]

UART2_TXD/ UART2_RXD/ MCA[2]_ACLKX//

U RSV16 RSV17 MCA[1]_ACLKX VDDA_1P8
GP0[31] GP0[29] GP0[10]

TCLKIN/ MCA[1]_AXR[1]/
T AUXOSC_MXO DVDD
GP0[30] SD0_DAT[5]

AUD_CLKIN1/
MCA[0]_AXR[8]/
MCA[1]_AHCLKX/ SD0_DAT[0]/
AUXOSC_MXI/ MCA[1]_AXR[2]/ MCA[0]_AXR[4]/
R VSSA_AUXOSC MCA[0]_ACLKX MCA[4]_AHCLKX/ SD1_DAT[4]/
AUX_CLKIN MCB_FSR EDMA_EVT3/
MCA[1]_AXR[8]
GP0[3]
TIM2_IO/
GP0[8]

1 2 3 4 5 6 7
E F G H

A B C D

Figure 3-5. Pin Map E

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VIN[0]A_D[4]/ VIN[0]A_D[10]_BD[2]/
AH USB0_CE USB0_DM USB1_ID USB1_DM USB1_CE
GP2[9] GP2[15]

VIN[0]A_D[9]_BD[1]/
AG EMU0 USB0_ID USB0_DP USB0_VBUSIN USB1_DP USB1_VBUSIN
GP2[14]

VIN[0]A_D[0]/ USB0_DRVVBUS/
AF VOUT[0]_R_CR[5] VOUT[0]_R_CR[7] VOUT[0]_G_Y_YC[9]
GP1[11] GP0[7]

VIN[0]A_D[3]/
AE VOUT[0]_R_CR[8] VSS EMU1 VOUT[0]_G_Y_YC[8]
GP2[8]

VOUT[0]_R_CR[2]/
AD RSV1 EMU4/ VOUT[0]_B_CB_C[4] VOUT[0]_CLK VOUT[0]_G_Y_YC[7]
GP2[26]

VIN[0]A_D[14]_BD[6]/ VIN[0]A_D[15]_BD[7]/
VIN[0]A_D[2]/
AC RSV5 VOUT[0]_B_CB_C[6] VOUT[0]_HSYNC CAM_STROBE/ VOUT[0]_R_CR[9] CAM_SHUTTER/
GP2[7]
GP2[19] GP2[20]

VOUT[0]_R_CR[3]/ VIN[0]A_D[1]/
AB VOUT[0]_G_Y_YC[4] VOUT[0]_B_CB_C[7] VOUT[0]_G_Y_YC[5] VOUT[0]_VSYNC DVDD
GP2[27] GP1[12]

VOUT[0]_AVID/
VOUT[0]_FLD/
VIN[0]A_D[7]/ VSS
AA VOUT[0]_G_Y_YC[6] VOUT[0]_R_CR[4] SPI[3]_SCLK/ VDDA_USB0_1P8 VDDA_USB_3P3
GP2[12]
TIM7_IO/
GP2[21]

Y VSS DVDD VSS VDDA_1P8 RSV4

W VDDA_PCIE_1P8 VDDA_PCIE_1P8 CVDD VSS VDDA_USB1_1P8 LDOCAP_ARM

V RSV3 VSS VDDA_1P8 VSS VSSA_USB VSSA_USB LDOCAP_ARMRAM

U RSV2 VDDA_SATA_1P8 VDDA_SATA_1P8 CVDD VSS CVDD VSS

T VSS VSS LDOCAP_SGX LDOCAP_SERDESCLK CVDD VSS CVDD_ARM

R VSS VSS DVDD_M LDOCAP_RAM1 VSS VDDA_ARMPLL_1P8 VSS

8 9 10 11 12 13 14
E F G H

A B C D

Figure 3-6. Pin Map F

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VIN[0]A_D[11]_BD[3]/
VOUT[0]_G_Y_YC[3]/ VIN[0]A_D[6]/
CAM_WE/ HDMI_CLKN HDMI_DN0 HDMI_DN1 HDMI_DN2 AH
GP2[25] GP2[11]
GP2[16]

VIN[0]A_D[12]_BD[4]/
VIN[0]A_D[5]/
VOUT[0]_B_CB_C[9] CLKOUT1/ HDMI_CLKP HDMI_DP0 HDMI_DP1 HDMI_DP2 AG
GP2[10]
GP2[17]

VOUT[0]_FLD/ VIN[0]A_D[18]/ VIN[0]A_D[19]/

VIN[0]A_D[13]_BD[5]/ CAM_PCLK/ CAM_D[10]/ CAM_D[11]/
VOUT[0]_B_CB_C[8] CAM_RESET/ GPMC_A[12]/ EMAC[1]_RMRXD[1]/ EMAC[1]_RMRXD[0]/ AF
GP2[18] UART2_RTS/ I2C[3]_SCL/ I2C[3]_SDA/
GP2[2] GP0[12] GP0[13]

VIN[0]A_D[21]/ VIN[0]A_DE/
VIN[0]B_CLK/ CAM_D[13]/ VIN[0]B_HSYNC/
VOUT[0]_B_CB_C[3]/
CLKOUT0/ EMAC[1]_RMTXD[0]/ VSS UART5_TXD/ AE
GP2[23]
GP1[9] SPI[3]_SCLK/ I2C[2]_SDA/
GP0[15] GP2[0]

VOUT[1]_G_Y_YC[1]/
VIN[0]B_FLD/ CAM_D[3]/ VIN[0]A_VSYNC/
VOUT[0]_B_CB_C[5] CAM_D[4]/ GPMC_A[5]/ UART5_CTS/ VSS AD
GP0[21] UART4_RXD/ GP2[4]
GP0[22]

VIN[0]A_D[23]/ VIN[0]A_D[20]/ VOUT[1]_G_Y_YC[0]/ VOUT[1]_R_CR[1]/ VIN[0]A_D[22]/

VIN[0]B_DE/ CAM_D[15]/ CAM_D[12]/ CAM_D[2]/ CAM_D[1]/ VIN[0]A_HSYNC/ CAM_D[14]/
CAM_D[6]/ EMAC[1]_RMTXEN/ EMAC[1]_RMCRSDV/ GPMC_A[6]/ GPMC_A[7]/ UART5_RTS/ EMAC[1]_RMTXD[1]/ AC
GP0[19] SPI[3]_D[0]/ SPI[3]_SCS[0]/ UART4_TXD/ UART4_CTS/ GP2[3] SPI[3]_D[1]/
GP0[17] GP0[14] GP0[23] GP0[24] GP0[16]

VIN[0]A_D[17]/
VIN[0]A_DE/
VIN[0]A_D[8]_BD[0]/ VIN[0]A_CLK/ CAM_D[9]/
DVDD CAM_D[7]/ VDDA_VID0PLL_1P8 VDDA_VDAC_1P8 AB
GP2[13] GP2[2] EMAC[1]_RMRXER/
GP0[18]
GP0[11]

VIN[0]A_FLD/
VIN[0]A_D[16]/
VIN[0]B_VSYNC/
CAM_D[8]/
DVDD VSS DVDD VDDA_VID1PLL_1P8 VSSA_VDAC UART5_RXD/ AA
I2C[2]_SCL/
I2C[2]_SCL/
GP0[10]
GP2[1]

VSS DVDD VSS VSS VSS Y

VDDA_1P8 VSS VSS VDDA_HDMI_1P8 DVDD_C DVDD_C W

CVDD_ARM CVDD_ARM VSS VSSA_HDMI VSS DVDD VSS V

CVDD_ARM CVDD_ARM CVDD VSS CVDD VSS DVDD U

CVDD_ARM CVDD_ARM VSS VSS VSS DVDD_GPMCB VSS T

CVDD VSS CVDD VDDA_AUDIOPLL_1P8 CVDD VDDA_1P8 VSS R

15 16 17 18 19 20 21
E F G H

A B C D

Figure 3-7. Pin Map G

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VOUT[1]_B_CB_C[3]/ VOUT[1]_B_CB_C[8]/
VOUT[1]_G_Y_YC[6]/
EMAC[1]_MRCLK/ EMAC[1]_MRXD[4]/
EMAC[1]_GMTCLK/
TV_OUT1 TV_RSET TV_OUT0 VIN[1]A_D[0]/ VIN[1]A_D[5]/ VSS AH
VIN[1]A_D[11]/
UART4_CTS/ I2C[3]_SCL/
GP3[10]
GP3[0] GP3[5]

VOUT[1]_R_CR[3]/
VOUT[1]_B_CB_C[4]/ VOUT[1]_R_CR[4]/ GPMC_A[14]/
VOUT[1]_G_Y_YC[5]/
EMAC[1]_MRXD[0]/ EMAC[1]_MTXD[3]/ VIN[1]A_D[22]/
I2C[1]_SDA/ EMAC[1]_MRXDV/
TV_VFB1 TV_VFB0 VIN[1]A_D[1]/ VIN[1]A_D[15]/ HDMI_SDA/ AG
HDMI_SDA VIN[1]A_D[10]/
UART4_RXD/ SPI[3]_SCS[1]/ SPI[2]_SCLK/
GP3[9] I2C[2]_SDA
GP3[1] GP3[14]
GP3[21]

VOUT[1]_G_Y_YC[2]/ VOUT[1]_B_CB_C[2]/
VOUT[1]_B_CB_C[5]/ GPMC_A[13]/
VOUT[1]_G_Y_YC[7]/ GPMC_A[0]/
EMAC[1]_MRXD[1]/ VIN[1]A_D[21]/
I2C[1]_SCL/ EMAC[1]_MTXD[0]/ VIN[1]A_D[7]/
VSS VIN[1]A_D[2]/ HDMI_SCL/ AF
HDMI_SCL VIN[1]A_D[12]/ SPI[2]_SCS[2]/ HDMI_CEC/
UART4_TXD/
GP3[11] I2C[2]_SCL/ SPI[2]_D[0]/
GP3[2]
GP3[20] GP3[30]

VOUT[1]_R_CR[2]/
VOUT[1]_B_CB_C[1]/
VOUT[1]_CLK/ VOUT[1]_G_Y_YC[8]/ GPMC_A[15]/
CAM_HS/ GPMC_A[18]/
EMAC[1]_MTCLK/ EMAC[1]_MTXD[1]/ VIN[1]A_D[23]/
GPMC_A[9]/ TIM2_IO/ AE
VIN[1]A_HSYNC/ VIN[1]A_D[13]/ HDMI_HPDET/
UART2_RXD/ GP1[13]
GP2[28] GP3[12] SPI[2]_D[1]/
GP0[26]
GP3[22]

VOUT[1]_B_CB_C[0]/ VOUT[1]_B_CB_C[6 ]/
VOUT[1]_G_Y_YC[9]/
CAM_VS/ EMAC[1]_MRXD[2]/ GPMC_A[20]/
EMAC[1]_MTXD[2]/ GPMC_A[16]/
GPMC_A[10]/ VIN[1]A_D[3]/ SPI[2]_SCS[1]/ AD
VIN[1]A_D[14]/ GP2[5]
UART2_TXD/ UART3_RXD/ GP1[15]
GP3[13]
GP0[27] GP3[3]

VOUT[1]_HSYNC/
VOUT[1]_B_CB_C[7]/ VOUT[1]_R_CR[5]/
EMAC[1]_MCOL/
VIN[0]A_FLD/ EMAC[1]_MRXD[3]/ EMAC[1]_MTXD[4]/ GPMC_A[19]/ GPMC_A[21]/
VIN[1]A_VSYNC/
CAM_D[5]/ VIN[1]A_D[4]/ VIN[1]A_D[16]/ TIM3_IO/ SPI[2]_D[0]/ AC
SPI[3]_D[1]/
GP0[20] UART3_TXD/ SPI[3]_SCLK/ GP1[14] GP1[16]
UART3_RTS/
GP3[4] GP3[15]
GP2[29]

VOUT[1]_FLD/
GPMC_A[22]/
CAM_FLD/
SPI[2]_D[1]/
CAM_WE/ GPMC_D[9]/
HDMI_CEC/ AB
GPMC_A[11]/ BTMODE[9]
TIM4_IO/
UART2_CTS/
GP1[17]
GP0[28]

VOUT[1]_VSYNC/
VOUT[1]_R_CR[0]/ EMAC[1]_MCRS/ VOUT[1]_B_CB_C[9]/ VOUT[1]_R_CR[6]/ GPMC_A[23]/
CAM_D[0]/ VIN[1]A_FLD/ EMAC[1]_MRXD[5]/ EMAC[1]_MTXD[5]/ SPI[2]_SCLK/
GPMC_D[11]/ GPMC_D[5]/
GPMC_A[8]/ VIN[1]A_DE/ VIN[1]A_D[6]/ VIN[1]A_D[17]/ HDMI_HPDET/ AA
BTMODE[11] BTMODE[5]
UART4_RTS/ SPI[3]_D[0]/ I2C[3]_SDA/ SPI[3]_D[1]/ TIM5_IO/
GP0[25] UART3_CTS/ GP3[6] GP3[16] GP1[18]
GP2[30]

VOUT[1]_AVID/
VOUT[1]_R_CR[9]/
EMAC[1]_MRXER/ VOUT[1]_G_Y_YC[3]/
EMAC[1]_MTXEN/
VIN[1]A_CLK/ EMAC[1]_MRXD[6]/ GPMC_D[15]/ GPMC_D[10]/ GPMC_D[8]/ GPMC_D[1]/
VIN[1]A_D[20]/ Y
UART4_RTS/ VIN[1]A_D[8]/ BTMODE[15] BTMODE[10] BTMODE[8] BTMODE[1]
UART5_TXD/
TIM6_IO/ GP3[7]
GP3[19]
GP2[31]

VOUT[1]_R_CR[8]/
VOUT[1]_G_Y_YC[4]/ GPMC_WAIT[0]/
EMAC[1]_MTXD[7]/
EMAC[1]_MRXD[7]/ GPMC_D[3]/ GPMC_A[26]/
VIN[1]A_D[19]/ W
VIN[1]A_D[9]/ BTMODE[3] EDMA_EVT0/
UART5_RXD/
GP3[8] GP1[31]
GP3[18]

VOUT[1]_R_CR[7]/ GPMC_BE[1]/
EMAC[1]_MTXD[6]/ GPMC_A[24]/
GPMC_A[17]/ GPMC_D[14]/ GPMC_D[7]/ GPMC_D[4]/ GPMC_D[2]/
VIN[1]A_D[18]/ EDMA_EVT1/ V
GP2[6] BTMODE[14] BTMODE[7] BTMODE[4] BTMODE[2]
SPI[3]_D[0]/ TIM7_IO/
GP3[17] GP1[30]

GPMC_BE[0]_CLE/
GPMC_A[25]/
DVDD GPMC_D[13]/ GPMC_D[12]/ GPMC_D[6]/ GPMC_D[0]/ GPMC_WE
EDMA_EVT2/ U
BTMODE[13] BTMODE[12] BTMODE[6] BTMODE[0]
TIM6_IO/
GP1[29]

EMAC[0]_MRXD[4]/
EMAC[0]_RGRXD[3]/ GPMC_CS[0]/
VSS GPMC_OE_RE T
GPMC_A[1]/ GP1[23]
UART5_TXD

SD2_DAT[4]/ GPMC_CLK/
EMAC[0]_MRXD[2]/ GPMC_A[27]/ EMAC[0]_MCRS/ GPMC_CS[5]/
EMAC[0]_RGRXD[1]/ GPMC_A[23]/ EMAC[0]_RGRXD[2]/ GPMC_WAIT[1]/
VSS VIN[1]B_D[7]/ GPMC_CS[7]/ VIN[1]B_D[2]/ CLKOUT1/ RSV14 RSV15 R
EMAC[0]_RMTXEN/ EDMA_EVT0/ EMAC[0]_RMRXD[1]/ EDMA_EVT3/
GP3[30] TIM7_IO/ GP3[25] TIM4_IO/
GP1[22] GP1[27]

22 23 24 25 26 27 28
E F G H

A B C D

Figure 3-8. Pin Map H

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3.2 Terminal Functions

The terminal functions tables identify the external signal names and their pin multiplexing, the associated
pin (ball) numbers along with the mechanical package designator, the pin type (for example, I, O, Z, S, A,
or GND), whether the pin has any internal pullup or pulldown resistors (for example, IPU, IPD, or DIS), the
supply voltage source, and describe the function or functions on the pin. The MUXED column in the tables
also identifies all peripheral pin functions multiplexed on a pin, the pin control register (PINCNTLx) that
controls which peripheral pin function is selected for that particular pin, and indicates the state driven on
the peripheral input (logic 0, logic 1, or PIN level) when the peripheral pin function is not selected (that is,
the de-selected input state [DSIS]), and the Multi-Muxed [MM] option for that peripheral pin function). For
more detailed information on device configuration, boot mode order, peripheral selection, and
multiplexed/shared pin control, and so on, see Section 4, Device Configurations of this data manual.

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3.2.1 Boot Configuration

Table 3-1. Boot Configuration Terminal Functions

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
BOOT
GPMC CS0 default GPMC_Wait enable input. This pin is
multiplexed between ARM Cortex-A8 boot mode and
General-Purpose Memory Controller (GPMC) peripheral
functions. At reset, BTMODE[15] is sampled to determine
GPMC the GPMC CS0 Wait enable:
GPMC_D[15]/ DIS
Y25 I PINCNTL104
BTMODE[15] DVDD_GPMC • 0 = Wait disabled
DSIS: PIN
• 1 = Wait enabled
After reset, this pin functions as GPMC multiplexed
data/address pin 15 (GPMC_D[15]).
GPMC GPMC CS0 default Address/Data multiplexing mode
GPMC_D[14]/ DIS
V24 I PINCNTL103 input. These pins are multiplexed between ARM Cortex-
BTMODE[14] DVDD_GPMC
DSIS: PIN A8 boot mode and General-Purpose Memory Controller
(GPMC) peripheral functions. At reset, BTMODE[14:13]
are sampled to determine the GPMC CS0 Address/Data
multiplexing:
• 00 = Not muxed
GPMC
GPMC_D[13]/ DIS • 01 = A/A/D muxed
U23 I PINCNTL102
BTMODE[13] DVDD_GPMC • 10 = A/D muxed
DSIS: PIN
• 11 = Reserved
After reset, this pin functions as GPMC multiplexed
data/address pins 14 through 13 (GPMC_D[14:13]).
GPMC CS0 default Data Bus Width input. This pin is
multiplexed between ARM Cortex-A8 boot mode and
General-Purpose Memory Controller (GPMC) peripheral
functions. At reset, BTMODE[12] is sampled to determine
GPMC the GPMC CS0 bus width:
GPMC_D[12]/ DIS
U24 I PINCNTL101
BTMODE[12] DVDD_GPMC • 0 = 8-bit data bus
DSIS: PIN
• 1 = 16-bit data bus
After reset, this pin functions as GPMC multiplexed
data/address pin 12 (GPMC_D[12]).
RSTOUT_WD_OUT Configuration. This pin is
multiplexed between ARM Cortex-A8 boot mode and
General-Purpose Memory Controller (GPMC) peripheral
functions. At reset, BTMODE[11] is sampled to determine
the function of the RSTOUT_WD_OUT pin:
GPMC • 0 = RSTOUT is asserted when a Watchdog Timer
GPMC_D[11]/ DIS
AA27 I PINCNTL100 reset, POR, RESET, or Emulation/Software-Global
BTMODE[11] DVDD_GPMC
DSIS: PIN Cold/Warm reset occurs
• 1 = RSTOUT_WD_OUT is asserted only when a
Watchdog Timer reset occurs
After reset, this pin functions as GPMC multiplexed
data/address pin 11 (GPMC_D[11]).

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal
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Table 3-1. Boot Configuration Terminal Functions (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
XIP (NOR) on GPMC Configuration. This pin is
multiplexed between ARM Cortex-A8 boot mode and
General-Purpose Memory Controller (GPMC) peripheral
functions. At reset, when the XIP (MUX0), XIP (MUX1),
XIP w/ WAiT (MUX0) or XIP w/ WAiT (MUX1) bootmode
is selected (see Table 4-1), BTMODE[10] is sampled to
GPMC select between GPMC pin muxing options A or B shown
GPMC_D[10]/ DIS
Y26 I PINCNTL99 in Table 4-2, XIP (on GPMC) Boot Options [Muxed or
BTMODE[10] DVDD_GPMC
DSIS: PIN Non-Muxed].
• 0 = GPMC Option A
• 1 = GPMC Option B
After reset, this pin functions as GPMC multiplexed
data/address pin 10 (GPMC_D[10]).
GPMC Ethernet PHY Configuration. These pins are multiplexed
GPMC_D[9]/ DIS
AB28 I PINCNTL98 between ARM Cortex-A8 boot mode and General-
BTMODE[9] DVDD_GPMC
DSIS: PIN Purpose Memory Controller (GPMC) peripheral functions.
At reset, when EMAC bootmode is selected (see Table 4-
1), BTMODE[9:8] pins are sampled to determine the
function of the Ethernet PHY Mode selection.
• 00 = MII (GMII)
• 01 = RMII
GPMC • 10 = RGMII
GPMC_D[8]/ DIS • 11 = Reserved
Y27 I PINCNTL97
BTMODE[8] DVDD_GPMC
DSIS: PIN
For more detailed information on the EMAC PHY boot
modes and the EMAC pin functions selected, see
Section 4.2.6, Ethernet PHY Mode Selection.
After reset, these pins function as GPMC multiplexed
data/address pins 9 and 8 (GPMC_D[9] and
GPMC_D[8]).
GPMC
GPMC_D[7]/ DIS Reserved Boot Pins. These pins are multiplexed between
V25 I PINCNTL96
BTMODE[7] DVDD_GPMC ARM Cortex-A8 boot mode and General-Purpose
DSIS: PIN
Memory Controller (GPMC) peripheral functions.
GPMC
GPMC_D[6]/ DIS
U25 I PINCNTL95 For proper device operation at reset, these pins should
BTMODE[6] DVDD_GPMC
DSIS: PIN be externally pulled low.
GPMC After reset, these pins function as GPMC multiplexed
GPMC_D[5]/ DIS
AA28 I PINCNTL94 data/address pins 10 through 5 (GPMC_D[7:5]).
BTMODE[5] DVDD_GPMC
DSIS: PIN
GPMC
GPMC_D[4]/ DIS ARM Cortex-A8 Boot Mode Configuration Bits. These
V26 I PINCNTL93
BTMODE[4] DVDD_GPMC pins are multiplexed between ARM Cortex-A8 boot mode
DSIS: PIN
and the General-Purpose Memory Controller (GPMC)
GPMC peripheral functions.
GPMC_D[3]/ DIS
W27 I PINCNTL92
BTMODE[3] DVDD_GPMC
DSIS: PIN At reset, the boot mode inputs BTMODE[4:0] are
sampled to determine the ARM boot configuration. For
GPMC
GPMC_D[2]/ DIS more details on the types of boot modes supported, see
V27 I PINCNTL91
BTMODE[2] DVDD_GPMC Section 4.2, Boot Modes, of this document, along with
DSIS: PIN
the TMS320DM814x ROM Code Memory and Peripheral
GPMC Booting chapter of the TMS320DM814x DaVinci™ Digital
GPMC_D[1]/ DIS
Y28 I PINCNTL90 Media Processors Technical Reference Manual
BTMODE[1] DVDD_GPMC
DSIS: PIN (Literature Number: SPRUGZ8).
GPMC After reset, these pins function as GPMC multiplexed
GPMC_D[0]/ DIS
U26 I PINCNTL89 data/address pins 4 through 0 (GPMC_D[4:0]).
BTMODE[0] DVDD_GPMC
DSIS: PIN

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3.2.2 Camera Interface (I/F)

Table 3-2. Camera I/F Terminal Functions

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
CAMERA I/F
VOUT[0]_FLD/
VOUT[0], GPMC, UART2,
CAM_PCLK/
IPD GP2
GPMC_A[12]/ AF18 I Camera Pixel Clock.
DVDD_C PINCNTL175
UART2_RTS/
DSIS: 0
GP2[2]
VIN[0]A_D[23]/
VIN[0]A, EMAC[1], SPI[3],
CAM_D[15]/
IPD GP0
EMAC[1]_RMTXEN/ AC16 I
DVDD_C PINCNTL163
SPI[3]_D[0]/
DSIS: PIN
GP0[17]
VIN[0]A_D[22]/
VIN[0]A, EMAC[1]_RM,
CAM_D[14]/
IPD SPI[3], GP0
EMAC[1]_RMTXD[1]/ AC21 I
DVDD_C PINCNTL162
SPI[3]_D[1]/
DSIS: PIN
GP0[16]
VIN[0]A_D[21]/
VIN[0]A, EMAC[1]_RM,
CAM_D[13]/
IPD SPI[3], GP0
EMAC[1]_RMTXD[0]/ AE18 I
DVDD_C PINCNTL161
SPI[3]_SCLK/
DSIS: PIN
GP0[15]
VIN[0]A_D[20]/
VIN[0]A, EMAC[1]_RM,
CAM_D[12]/
IPD SPI[3], GP0
EMAC[1]_RMCRSDV/ AC17 I
DVDD_C PINCNTL160
SPI[3]_SCS[0]/
DSIS: PIN Camera data inputs
GP0[14]
VIN[0]A_D[19]/
VIN[0]A, EMAC[1]_RM,
CAM_D[11]/
IPU I2C[3], GP0
EMAC[1]_RMRXD[0]/ AF21 I
DVDD_C PINCNTL159
I2C[3]_SDA/
DSIS: PIN
GP0[13]
VIN[0]A_D[18]/
VIN[0]A, EMAC[1]_RM,
CAM_D[10]/
IPU I2C[3], GP0
EMAC[1]_RMRXD[1]/ AF20 I
DVDD_C PINCNTL158
I2C[3]_SCL/
DSIS: PIN
GP0[12]
VIN[0]A_D[17]/ VIN[0]A, EMAC[1]_RM,
CAM_D[9]/ IPD GP0
AB21 I
EMAC[1]_RMRXER/ DVDD_C PINCNTL157
GP0[11] DSIS: PIN
VIN[0]A_D[16]/
VIN[0]A, I2C[2], GP0
CAM_D[8]/ IPU
AA21 I PINCNTL156
I2C[2]_SCL/ DVDD_C
DSIS: PIN
GP0[10]

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown
resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal
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Table 3-2. Camera I/F Terminal Functions (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
VIN[0]A_DE/ VIN[0]A, GP0
IPU
CAM_D[7]/ AB17 I PINCNTL164
DVDD_C
GP0[18] DSIS: PIN
VIN[0]B_DE/ VIN[0]A, GP0
IPU
CAM_D[6]/ AC15 I PINCNTL165
DVDD_C
GP0[19] DSIS: PIN
VIN[0]A_FLD/ VIN[0]A, GP0
IPU
CAM_D[5]/ AC22 I PINCNTL166
DVDD_C
GP0[20] DSIS: PIN
VIN[0]B_FLD/ VIN[0]B, GP0
IPU
CAM_D[4]/ AD17 I PINCNTL167
DVDD_C
GP0[21] DSIS: PIN
VOUT[1]_G_Y_YC[1]/
VOUT[1], GPMC, UART4,
CAM_D[3]/
IPU GP0
GPMC_A[5]/ AD18 I
DVDD_C PINCNTL168
UART4_RXD/ Camera data inputs
DSIS: PIN
GP0[22]
VOUT[1]_G_Y_YC[0]/
VOUT[1], GPMC, UART4,
CAM_D[2]/
IPD GP0
GPMC_A[6]/ AC18 I
DVDD_C PINCNTL169
UART4_TXD/
DSIS: PIN
GP0[23]
VOUT[1]_R_CR[1]/
VOUT[1], GPMC, UART4,
CAM_D[1]/
IPD GP0
GPMC_A[7]/ AC19 I
DVDD_C PINCNTL170
UART4_CTS/
DSIS: PIN
GP0[24]
VOUT[1]_R_CR[0]/
VOUT[1], GPMC, UART4,
CAM_D[0]/
IPD GP0
GPMC_A[8]/ AA22 I
DVDD_C PINCNTL171
UART4_RTS/
DSIS: PIN
GP0[25]
VOUT[1]_B_CB_C[1]/
VOUT[1], GPMC, UART2,
CAM_HS/
IPD GP0
GPMC_A[9]/ AE23 I/O Camera Horizontal Synchronization
DVDD_C PINCNTL172
UART2_RXD/
DSIS: 0
GP0[26]
VOUT[1]_B_CB_C[0]/
VOUT[1], GPMC, UART2,
CAM_VS/
IPU GP0
GPMC_A[10]/ AD23 I/O Camera Vertical Synchronization
DVDD_C PINCNTL173
UART2_TXD/
DSIS: 0
GP0[27]
VIN[0]A_D[13]_BD[5]/ VIN[0]AB, GP2
IPD
CAM_RESET/ AF17 I/O PINCNTL153 Camera Reset. Used for Strobe Synchronization
DVDD
GP2[18] DSIS: 0
VIN[0]AB. GP2
VIN[0]A_D[11]_BD[3]/
IPD PINCNTL151
CAM_WE/ AH17 I
DVDD DSIS: 0
GP2[16]
MM: MUX1
VOUT[1]_FLD/ Camera Write Enable
VOUT[1], CAMERA_I/F,
CAM_FLD/
GPMC, UART2, GP0
CAM_WE/ IPD
AB23 I PINCNTL174
GPMC_A[11]/ DVDD_C
DSIS: 0
UART2_CTS/
MM: MUX0
GP0[28]
VOUT[1]_FLD/
CAM_FLD/ VOUT[1], CAMERA_I/F,
CAM_WE/ IPD GPMC, UART2, GP0
AB23 I/O Camera Field Identification input
GPMC_A[11]/ DVDD_C PINCNTL174
UART2_CTS/ DSIS: 0
GP0[28]

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Table 3-2. Camera I/F Terminal Functions (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
VIN[0]A_D[14]_BD[6]/ VIN[0]AB, GP2
IPD
CAM_STROBE/ AC12 O PINCNTL154 Camera Flash Strobe Control Signal
DVDD
GP2[19] DSIS: N/A
VIN[0]A_D[15]_BD[7]/ VIN[0]AB, GP2
IPD
CAM_SHUTTER/ AC14 O PINCNTL155 Camera Mechanical Shutter Control Signal
DVDD
GP2[20] DSIS: N/A

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3.2.3 Controller Area Network (DCAN) Modules (DCAN0, DCAN1)

Table 3-3. DCAN Terminal Functions

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
DCAN0
DCAN0_RX/
UART2, I2C[3], GP1
UART2_RXD/ IPU
AG6 I/O PINCNTL69 DCAN0 receive data pin.
I2C[3]_SCL/ DVDD
DSIS: 1
GP1[1]
DCAN0_TX/
UART2, I2C[3], GP1
UART2_TXD/ IPU
AH6 I/O PINCNTL68 DCAN0 transmit data pin.
I2C[3]_SDA/ DVDD
DSIS: 1
GP1[0]
DCAN1
UART0_RTS/
UART0, UART4, SPI[1],
UART4_TXD/
IPU SD2
DCAN1_RX/ AF5 I/O DCAN1 receive data pin.
DVDD PINCNTL73
SPI[1]_SCS[2]/
DSIS: 1
SD2_SDCD
UART0_CTS/
UART0, UART4, SPI[1],
UART4_RXD/
IPU SD0
DCAN1_TX/ AE6 I/O DCAN1 transmit data pin.
DVDD PINCNTL72
SPI[1]_SCS[3]/
DSIS: 1
SD0_SDCD
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown
resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

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3.2.4 DDR2/DDR3 Memory Controller

Table 3-4. DDR2/DDR3 Memory Controller 0 Terminal Functions

SIGNAL
TYPE (1) OTHER (2) (3)
DESCRIPTION
NAME NO.
DDR2/DDR3 Memory Controller 0 (DDR[0])
DDR[0] Clock
IPD/DIS
DDR[0]_CLK B16 O The internal pulldown (IPD) is enabled for this pin when the device is
DVDD_DDR[0]
in reset and the IPD is disabled (DIS) when reset is released.
DDR[0] Negative Clock
IPU/DIS
DDR[0]_CLK A16 O The internal pullup (IPU) is enabled for this pin when the device is in
DVDD_DDR[0]
reset and the IPU is disabled (DIS) when reset is released.
IPD
DDR[0]_CKE H18 O DDR[0] Clock Enable
DVDD_DDR[0]
DDR[0] Write Enable
IPU/DIS
DDR[0]_WE C17 O The internal pullup (IPU) is enabled for this pin when the device is in
DVDD_DDR[0]
reset and the IPU is disabled (DIS) when reset is released.
DDR[0] Chip Select 0
IPU/DIS
DDR[0]_CS[0] F18 O The internal pullup (IPU) is enabled for this pin when the device is in
DVDD_DDR[0]
reset and the IPU is disabled (DIS) when reset is released.
DDR[0] Chip Select 1
IPU/DIS
DDR[0]_CS[1] G17 O The internal pullup (IPU) is enabled for this pin when the device is in
DVDD_DDR[0]
reset and the IPU is disabled (DIS) when reset is released.
DDR[0] Row Address Strobe output
IPU/DIS
DDR[0]_RAS B18 O The internal pullup (IPU) is enabled for this pin when the device is in
DVDD_DDR[0]
reset and the IPU is disabled (DIS) when reset is released.
DDR[0] Column Address Strobe output
IPU/DIS
DDR[0]_CAS C18 O The internal pullup (IPU) is enabled for this pin when the device is in
DVDD_DDR[0]
reset and the IPU is disabled (DIS) when reset is released.
IPU/IPD
DDR[0]_DQM[3] F20 O DDR[0] Data Mask outputs
DVDD_DDR[0]
DDR[0]_DQM[3]: For upper byte data bus DDR[0]_D[31:24]
IPU/IPD DDR[0]_DQM[2]: For DDR[0]_D[23:16]
DDR[0]_DQM[2] C24 O
DVDD_DDR[0] DDR[0]_DQM[1]: For DDR[0]_D[15:8]
IPU/IPD DDR[0]_DQM[0]: For lower byte data bus DDR[0]_D[7:0]
DDR[0]_DQM[1] B28 O
DVDD_DDR[0]
The internal pullup (IPU) is enabled for these pins when the device is
IPU/IPD in reset and switches to an IPD enabled when reset is released.
DDR[0]_DQM[0] E28 O
DVDD_DDR[0]
IPD
DDR[0]_DQS[3] B21 I/O
DVDD_DDR[0] Data strobe input/outputs for each byte of the 32-bit data bus. They
IPD are outputs to the DDR[0] memory when writing and inputs when
DDR[0]_DQS[2] B23 I/O reading. They are used to synchronize the data transfers.
DVDD_DDR[0]
DDR[0]_DQS[3]: For upper byte data bus DDR[0]_D[31:24]
IPD DDR[0]_DQS[2]: For DDR[0]_D[23:16]
DDR[0]_DQS[1] B26 I/O
DVDD_DDR[0] DDR[0]_DQS[1]: For DDR[0]_D[15:8]
IPD DDR[0]_DQS[0]: For lower byte data bus DDR[0]_D[7:0]
DDR[0]_DQS[0] D28 I/O
DVDD_DDR[0]
IPU
DDR[0]_DQS[3] A21 I/O Complementary data strobe input/outputs for each byte of the 32-bit
DVDD_DDR[0]
data bus. They are outputs to the DDR[0] memory when writing and
IPU inputs when reading. They are used to synchronize the data
DDR[0]_DQS[2] A23 I/O
DVDD_DDR[0] transfers.
IPU DDR[0]_DQS[3]: For upper byte data bus DDR[0]_D[31:24]
DDR[0]_DQS[1] A26 I/O DDR[0]_DQS[2]: For DDR[0]_D[23:16]
DVDD_DDR[0]
DDR[0]_DQS[1]: For DDR[0]_D[15:8]
IPU DDR[0]_DQS[0]: For lower byte data bus DDR[0]_D[7:0]
DDR[0]_DQS[0] D27 I/O
DVDD_DDR[0]

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal
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Table 3-4. DDR2/DDR3 Memory Controller 0 Terminal Functions (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
DESCRIPTION
NAME NO.
DDR[0] On-Die Termination for Chip Select 0.
IPD/DIS
DDR[0]_ODT[0] G18 O The internal pulldown (IPD) is enabled for this pin when the device is
DVDD_DDR[0]
in reset and the IPD is disabled (DIS) when reset is released.
DDR[0] On-Die Termination for Chip Select 1.
IPD/DIS
DDR[0]_ODT[1] H19 O The internal pulldown (IPD) is enabled for this pin when the device is
DVDD_DDR[0]
in reset and the IPD is disabled (DIS) when reset is released.
DDR[0] Reset output
IPD/DIS
DDR[0]_RST G19 O The internal pulldown (IPD) is enabled for this pin when the device is
DVDD_DDR[0]
in reset and the IPD is disabled (DIS) when reset is released.
IPU/DIS
DDR[0]_BA[2] A18 O
DVDD_DDR[0]
DDR[0] Bank Address outputs
IPU/DIS
DDR[0]_BA[1] A20 O The internal pullup (IPU) is enabled for these pins when the device is
DVDD_DDR[0]
in reset and the IPU is disabled (DIS) when reset is released.
IPU/DIS
DDR[0]_BA[0] F15 O
DVDD_DDR[0]
IPU/DIS
DDR[0]_A[14] F16 O
DVDD_DDR[0]
IPU/DIS
DDR[0]_A[13] F17 O
DVDD_DDR[0]
IPU/DIS
DDR[0]_A[12] E17 O
DVDD_DDR[0]
IPU/DIS
DDR[0]_A[11] D17 O
DVDD_DDR[0]
IPU/DIS
DDR[0]_A[10] A19 O
DVDD_DDR[0]
IPU/DIS
DDR[0]_A[9] C15 O
DVDD_DDR[0]
IPU/DIS
DDR[0]_A[8] B15 O
DVDD_DDR[0]
DDR[0] Address Bus
IPU/DIS
DDR[0]_A[7] E18 O The internal pullup (IPU) is enabled for these pins when the device is
DVDD_DDR[0]
in reset and the IPU is disabled (DIS) when reset is released.
IPU/DIS
DDR[0]_A[6] A15 O
DVDD_DDR[0]
IPU/DIS
DDR[0]_A[5] B17 O
DVDD_DDR[0]
IPU/DIS
DDR[0]_A[4] D15 O
DVDD_DDR[0]
IPU/DIS
DDR[0]_A[3] E15 O
DVDD_DDR[0]
IPU/DIS
DDR[0]_A[2] D18 O
DVDD_DDR[0]
IPU/DIS
DDR[0]_A[1] F19 O
DVDD_DDR[0]
IPU/DIS
DDR[0]_A[0] B19 O
DVDD_DDR[0]

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Table 3-4. DDR2/DDR3 Memory Controller 0 Terminal Functions (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
DESCRIPTION
NAME NO.
IPD
DDR[0]_D[31] B20 I/O
DVDD_DDR[0]
IPD
DDR[0]_D[30] D21 I/O
DVDD_DDR[0]
IPD
DDR[0]_D[29] C21 I/O
DVDD_DDR[0]
IPD
DDR[0]_D[28] C20 I/O
DVDD_DDR[0]
IPD
DDR[0]_D[27] A22 I/O
DVDD_DDR[0]
IPD
DDR[0]_D[26] G20 I/O
DVDD_DDR[0]
IPD
DDR[0]_D[25] F21 I/O
DVDD_DDR[0]
IPD
DDR[0]_D[24] H20 I/O
DVDD_DDR[0]
DDR[0] Data Bus
IPD
DDR[0]_D[23] B22 I/O
DVDD_DDR[0]
IPD
DDR[0]_D[22] C23 I/O
DVDD_DDR[0]
IPD
DDR[0]_D[21] E23 I/O
DVDD_DDR[0]
IPD
DDR[0]_D[20] D23 I/O
DVDD_DDR[0]
IPD
DDR[0]_D[19] G21 I/O
DVDD_DDR[0]
IPD
DDR[0]_D[18] H21 I/O
DVDD_DDR[0]
IPD
DDR[0]_D[17] F22 I/O
DVDD_DDR[0]
IPD
DDR[0]_D[16] B24 I/O
DVDD_DDR[0]

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Table 3-4. DDR2/DDR3 Memory Controller 0 Terminal Functions (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
DESCRIPTION
NAME NO.
IPD
DDR[0]_D[15] A24 I/O
DVDD_DDR[0]
IPD
DDR[0]_D[14] A25 I/O
DVDD_DDR[0]
IPD
DDR[0]_D[13] D24 I/O
DVDD_DDR[0]
IPD
DDR[0]_D[12] B25 I/O
DVDD_DDR[0]
IPD
DDR[0]_D[11] A27 I/O
DVDD_DDR[0]
IPD
DDR[0]_D[10] C26 I/O
DVDD_DDR[0]
IPD
DDR[0]_D[9] C25 I/O
DVDD_DDR[0]
IPD
DDR[0]_D[8] C27 I/O
DVDD_DDR[0]
DDR[0] Data Bus
IPD
DDR[0]_D[7] C28 I/O
DVDD_DDR[0]
IPD
DDR[0]_D[6] D26 I/O
DVDD_DDR[0]
IPD
DDR[0]_D[5] E25 I/O
DVDD_DDR[0]
IPD
DDR[0]_D[4] F24 I/O
DVDD_DDR[0]
IPD
DDR[0]_D[3] F25 I/O
DVDD_DDR[0]
IPD
DDR[0]_D[2] E26 I/O
DVDD_DDR[0]
IPD
DDR[0]_D[1] F26 I/O
DVDD_DDR[0]
IPD
DDR[0]_D[0] E27 I/O
DVDD_DDR[0]
–
DDR[0]_VTP B27 I DDR VTP Compensation Resistor Connection
DVDD_DDR[0]

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Table 3-5. DDR2/DDR3 Memory Controller 1 Terminal Functions

SIGNAL
TYPE (1) OTHER (2) (3)
DESCRIPTION
NAME NO.
DDR2/DDR3 Memory Controller 1 (DDR[1])
DDR[1] Clock
IPD/DIS
DDR[1]_CLK B13 O The internal pulldown (IPD) is enabled for this pin when the device is
DVDD_DDR[1]
in reset and the IPD is disabled (DIS) when reset is released.
DDR[1] Negative Clock
IPU/DIS
DDR[1]_CLK A13 O The internal pullup (IPU) is enabled for this pin when the device is in
DVDD_DDR[1]
reset and the IPU is disabled (DIS) when reset is released.
IPD
DDR[1]_CKE H11 O DDR[1] Clock Enable
DVDD_DDR[1]
DDR[1] Write Enable
IPU/DIS
DDR[1]_WE E12 O The internal pullup (IPU) is enabled for this pin when the device is in
DVDD_DDR[1]
reset and the IPU is disabled (DIS) when reset is released.
DDR[1] Chip Select 0
IPU/DIS
DDR[1]_CS[0] G12 O The internal pullup (IPU) is enabled for this pin when the device is in
DVDD_DDR[1]
reset and the IPU is disabled (DIS) when reset is released.
DDR[1] Chip Select 1
IPU/DIS
DDR[1]_CS[1] G11 O The internal pullup (IPU) is enabled for this pin when the device is in
DVDD_DDR[1]
reset and the IPU is disabled (DIS) when reset is released.
DDR[1] Row Address Strobe output
IPU/DIS
DDR[1]_RAS C12 O The internal pullup (IPU) is enabled for this pin when the device is in
DVDD_DDR[1]
reset and the IPU is disabled (DIS) when reset is released.
DDR[1] Column Address Strobe output
IPU/DIS
DDR[1]_CAS F13 O The internal pullup (IPU) is enabled for this pin when the device is in
DVDD_DDR[1]
reset and the IPU is disabled (DIS) when reset is released.
IPU/IPD
DDR[1]_DQM[3] G9 O
DVDD_DDR[1] DDR[1] Data Mask outputs
DDR[1]_DQM[3]: For upper byte data bus DDR[1]_D[31:24]
IPU/IPD DDR[1]_DQM[2]: For DDR[1]_D[23:16]
DDR[1]_DQM[2] G8 O
DVDD_DDR[1] DDR[1]_DQM[1]: For DDR[1]_D[15:8]
IPU/IPD DDR[1]_DQM[0]: For lower byte data bus DDR[1]_D[7:0]
DDR[1]_DQM[1] B2 O
DVDD_DDR[1]
The internal pullup (IPU) is enabled for these pins when the device is
IPU/IPD in reset and switches to an IPD enabled when reset is released.
DDR[1]_DQM[0] F4 O
DVDD_DDR[1]
IPD
DDR[1]_DQS[3] B8 I/O
DVDD_DDR[1] Data strobe input/outputs for each byte of the 32-bit data bus. They are
IPD outputs to the DDR[1] memory when writing and inputs when reading.
DDR[1]_DQS[2] A6 I/O
DVDD_DDR[1] They are used to synchronize the data transfers.
DDR[1]_DQS[3]: For upper byte data bus DDR[1]_D[31:24]
IPD DDR[1]_DQS[2]: For DDR[1]_D[23:16]
DDR[1]_DQS[1] B3 I/O
DVDD_DDR[1] DDR[1]_DQS[1]: For DDR[1]_D[15:8]
IPD DDR[1]_DQS[0]: For lower byte data bus DDR[1]_D[7:0]
DDR[1]_DQS[0] D1 I/O
DVDD_DDR[1]
IPU
DDR[1]_DQS[3] A8 I/O
DVDD_DDR[1] Complementary data strobe input/outputs for each byte of the 32-bit
IPU data bus. They are outputs to the DDR[1] memory when writing and
DDR[1]_DQS[2] B6 I/O
DVDD_DDR[1] inputs when reading. They are used to synchronize the data transfers.
DDR[1]_DQS[3]: For upper byte data bus DDR[1]_D[31:24]
IPU DDR[1]_DQS[2]: For DDR[1]_D[23:16]
DDR[1]_DQS[1] A3 I/O
DVDD_DDR[1] DDR[1]_DQS[1]: For DDR[1]_D[15:8]
IPU DDR[1]_DQS[0]: For lower byte data bus DDR[1]_D[7:0]
DDR[1]_DQS[0] D2 I/O
DVDD_DDR[1]
DDR[1] On-Die Termination for Chip Select 0.
IPD/DIS
DDR[1]_ODT[0] H10 O The internal pulldown (IPD) is enabled for this pin when the device is
DVDD_DDR[1]
in reset and the IPD is disabled (DIS) when reset is released.

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal
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Table 3-5. DDR2/DDR3 Memory Controller 1 Terminal Functions (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
DESCRIPTION
NAME NO.
DDR[1] On-Die Termination for Chip Select 1.
IPD/DIS
DDR[1]_ODT[1] F11 O The internal pulldown (IPD) is enabled for this pin when the device is
DVDD_DDR[1]
in reset and the IPD is disabled (DIS) when reset is released.
DDR[1] Reset output.
IPD/DIS
DDR[1]_RST G10 O The internal pulldown (IPD) is enabled for this pin when the device is
DVDD_DDR[1]
in reset and the IPD is disabled (DIS) when reset is released.
IPU/DIS
DDR[1]_BA[2] D12 O
DVDD_DDR[1]
DDR[1] Bank Address outputs
IPU/DIS
DDR[1]_BA[1] A10 O
DVDD_DDR[1] The internal pullup (IPU) is enabled for these pins when the device is
in reset and the IPU is disabled (DIS) when reset is released.
IPU/DIS
DDR[1]_BA[0] F14 O
DVDD_DDR[1]
IPU/DIS
DDR[1]_A[14] D11 O
DVDD_DDR[1]
IPU/DIS
DDR[1]_A[13] E11 O
DVDD_DDR[1]
IPU/DIS
DDR[1]_A[12] B10 O
DVDD_DDR[1]
IPU/DIS
DDR[1]_A[11] A11 O
DVDD_DDR[1]
IPU/DIS
DDR[1]_A[10] F12 O
DVDD_DDR[1]
IPU/DIS
DDR[1]_A[9] C14 O
DVDD_DDR[1]
IPU/DIS
DDR[1]_A[8] E14 O
DVDD_DDR[1]
DDR[1] Address Bus
IPU/DIS
DDR[1]_A[7] A9 O
DVDD_DDR[1] The internal pullup (IPU) is enabled for these pins when the device is
in reset and the IPU is disabled (DIS) when reset is released.
IPU/DIS
DDR[1]_A[6] D14 O
DVDD_DDR[1]
IPU/DIS
DDR[1]_A[5] B12 O
DVDD_DDR[1]
IPU/DIS
DDR[1]_A[4] B14 O
DVDD_DDR[1]
IPU/DIS
DDR[1]_A[3] A14 O
DVDD_DDR[1]
IPU/DIS
DDR[1]_A[2] C11 O
DVDD_DDR[1]
IPU/DIS
DDR[1]_A[1] F10 O
DVDD_DDR[1]
IPU/DIS
DDR[1]_A[0] B11 O
DVDD_DDR[1]

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Table 3-5. DDR2/DDR3 Memory Controller 1 Terminal Functions (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
DESCRIPTION
NAME NO.
IPD
DDR[1]_D[31] B9 I/O
DVDD_DDR[1]
IPD
DDR[1]_D[30] C8 I/O
DVDD_DDR[1]
IPD
DDR[1]_D[29] D8 I/O
DVDD_DDR[1]
IPD
DDR[1]_D[28] C9 I/O
DVDD_DDR[1]
IPD
DDR[1]_D[27] A7 I/O
DVDD_DDR[1]
IPD
DDR[1]_D[26] F8 I/O
DVDD_DDR[1]
IPD
DDR[1]_D[25] H9 I/O
DVDD_DDR[1]
IPD
DDR[1]_D[24] F9 I/O
DVDD_DDR[1]
DDR[1] Data Bus
IPD
DDR[1]_D[23] B7 I/O
DVDD_DDR[1]
IPD
DDR[1]_D[22] D6 I/O
DVDD_DDR[1]
IPD
DDR[1]_D[21] E6 I/O
DVDD_DDR[1]
IPD
DDR[1]_D[20] C6 I/O
DVDD_DDR[1]
IPD
DDR[1]_D[19] B5 I/O
DVDD_DDR[1]
IPD
DDR[1]_D[18] C5 I/O
DVDD_DDR[1]
IPD
DDR[1]_D[17] F7 I/O
DVDD_DDR[1]
IPD
DDR[1]_D[16] H8 I/O
DVDD_DDR[1]

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Table 3-5. DDR2/DDR3 Memory Controller 1 Terminal Functions (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
DESCRIPTION
NAME NO.
IPD
DDR[1]_D[15] A5 I/O
DVDD_DDR[1]
IPD
DDR[1]_D[14] A4 I/O
DVDD_DDR[1]
IPD
DDR[1]_D[13] C4 I/O
DVDD_DDR[1]
IPD
DDR[1]_D[12] B4 I/O
DVDD_DDR[1]
IPD
DDR[1]_D[11] A2 I/O
DVDD_DDR[1]
IPD
DDR[1]_D[10] C3 I/O
DVDD_DDR[1]
IPD
DDR[1]_D[9] D5 I/O
DVDD_DDR[1]
IPD
DDR[1]_D[8] C2 I/O
DVDD_DDR[1]
DDR[1] Data Bus
IPD
DDR[1]_D[7] C1 I/O
DVDD_DDR[1]
IPD
DDR[1]_D[6] D3 I/O
DVDD_DDR[1]
IPD
DDR[1]_D[5] E4 I/O
DVDD_DDR[1]
IPD
DDR[1]_D[4] F5 I/O
DVDD_DDR[1]
IPD
DDR[1]_D[3] E1 I/O
DVDD_DDR[1]
IPD
DDR[1]_D[2] E2 I/O
DVDD_DDR[1]
IPD
DDR[1]_D[1] F3 I/O
DVDD_DDR[1]
IPD
DDR[1]_D[0] E3 I/O
DVDD_DDR[1]
–
DDR[1]_VTP B1 I DDR[1] VTP Compensation Resistor Connection
DVDD_DDR[1]

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3.2.5 EDMA

Table 3-6. EDMA Terminal Functions

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
EDMA
AUD_CLKIN1/ AUD_CLKIN1,
MCA[0]_AXR[8]/ MCA[0], MCA[1],
MCA[1]_AHCLKX/ MCA[4], TIMER2,
IPD
MCA[4]_AHCLKX/ R5 I GP0
DVDD
EDMA_EVT3/ PINCNTL15
TIM2_IO/ DSIS: PIN
GP0[8] MM: MUX1
External EDMA Event 3
GPMC_CLK/
GPMC_CS[5]/ GPMC, CLKOUT1,
GPMC_WAIT[1]/ TIMER4, GP1
IPU
CLKOUT1/ R26 I PINCNTL127
DVDD_GPMC
EDMA_EVT3/ DSIS: PIN
TIM4_IO/ MM: MUX0
GP1[27]
AUD_CLKIN2/ AUD_CLKIN2,
MCA[0]_AXR[9]/ MCA[0], MCA[2].
MCA[2]_AHCLKX/ MCA[5], TIMER3,
IPD
MCA[5]_AHCLKX/ H1 I GP0
DVDD
EDMA_EVT2/ PINCNTL16
TIM3_IO/ DSIS: PIN
GP0[9] MM: MUX1 External EDMA Event 2
GPMC_BE[0]_CLE/ GPMC, TIMER6,
GPMC_A[25]/ GP1
IPD
EDMA_EVT2/ U27 I PINCNTL131
DVDD_GPMC
TIM6_IO/ DSIS: PIN
GP1[29] MM: MUX0
SPI[0]_SCS[1]/ SPI[0], SD1,
SD1_SDCD/ SATA, TIMER4,
SATA_ACT0_LED/ IPU GP1
AE5 I
EDMA_EVT1/ DVDD PINCNTL80
TIM4_IO/ DSIS: PIN
GP1[6] MM: MUX1 External EDMA Event 1
GPMC_BE[1]/ GPMC, TIMER7,
GPMC_A[24]/ GP1
IPD
EDMA_EVT1/ V28 I PINCNTL132
DVDD_GPMC
TIM7_IO/ DSIS: PIN
GP1[30] MM: MUX0
SD2_DAT[4]/
GPMC_A[27]/ SD2, GPMC,
GPMC_A[23]/ TIMER7, GP1
IPU
GPMC_CS[7]/ R24 I PINCNTL116
DVDD_GPMC
EDMA_EVT0/ DSIS: PIN
TIM7_IO/ MM: MUX1 External EDMA Event 0
GP1[22]
GPMC_WAIT[0]/ GPMC, GP1
GPMC_A[26]/ IPU PINCNTL133
W28 I
EDMA_EVT0/ DVDD_GPMC DSIS: PIN
GP1[31] MM: MUX0
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown
resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and the Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

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3.2.6 EMAC [(R)(G)MII Modes] and MDIO

Table 3-7. EMAC[0] Terminal Functions [(R)(G)MII]

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
EMAC[0] (G)MII Mode
An EMAC bootmode must be selected via the BTMODE[4:0] pins. Once the EMAC bootmode is selected, the BTMODE[9:8] pins determine
the Ethernet PHY Mode Selection (for example, 00b is MII mode). For more detailed information on EMAC bootmodes and Ethernet PHY
Mode selection, see Section 4.2.6, Ethernet PHY Mode Selection.
These pin functions are available only when GMII or MII modes are selected.
EMAC[0]_MCOL/
EMAC[0],
EMAC[0]_RGRXCTL/
IPD VIN[1]B, GP3
VIN[1]B_D[1]/ L23 I [G]MII Collision Detect (Sense) input
DVDD_GPMC PINCNTL236
EMAC[0]_RMRXD[0]/
DSIS: 0
GP3[24]
EMAC[0]_MCRS/
EMAC[0],
EMAC[0]_RGRXD[2]/
IPD VIN[1]B, GP3
VIN[1]B_D[2]/ R25 I [G]MII Carrier Sense input
DVDD_GPMC PINCNTL237
EMAC[0]_RMRXD[1]/
DSIS: 0
GP3[25]
EMAC[0]_GMTCLK/ EMAC[1],
EMAC[1]_RGRXC/ IPD GPMC, SPI[2]
K23 O GMII Source Synchronous Transmit Clock
GPMC_A[6]/ DVDD_GPMC PINCNTL249
SPI[2]_D[1] DSIS: N/A
EMAC[0]_MRCLK/
EMAC[0],
EMAC[0]_RGTXC/
VIN[1]B, SPI[3],
VIN[1]B_D[4]/ IPD
H27 I GP3 [G]MII Receive Clock
EMAC[0]_RMCRSDV/ DVDD_GPMC
PINCNTL239
SPI[3]_SCS[2]/
DSIS: 0
GP3[27]

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown
resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal
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Table 3-7. EMAC[0] Terminal Functions [(R)(G)MII] (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
EMAC[0]_MRXD[7]/ EMAC[0],
EMAC[0]_RGTXD[1]/ GPMC, SPI[2]
G27
GPMC_A[4]/ PINCNTL247
SPI[2]_SCS[3] DSIS: PIN
EMAC[0]_MRXD[6]/ EMAC[0],
EMAC[0]_RGTXD[2]/ GPMC, UART5
F28
GPMC_A[3]/ PINCNTL246
UART5_RTS DSIS: PIN
EMAC[0]_MRXD[5]/ EMAC[0],
EMAC[0]_RGTXD[3]/ GPMC, UART5
H26
GPMC_A[2]/ PINCNTL245
UART5_CTS DSIS: PIN
EMAC[0]_MRXD[4]/ EMAC[0],
EMAC[0]_RGRXD[3]/ GPMC, UART5
T23
GPMC_A[1]/ PINCNTL244
UART5_TXD DSIS: PIN
EMAC[0]_MRXD[3]/ [G]MII Receive Data [7:0]. For 1000 EMAC GMII
EMAC[1]_RGRXCTL/ IPD EMAC[1], operation, EMAC[0]_RXD[7:0] are used. For 10/100
GPMC_A[27]/ I GPMC, UART5
J25 DVDD_GPMC EMAC MII operation, only EMAC[0]_RXD[3:0] are
GPMC_A[26]/ PINCNTL243 used.
GPMC_A[0]/ DSIS: PIN
UART5_RXD
EMAC[0]_MRXD[2]/
EMAC[0],
EMAC[0]_RGRXD[1]/
VIN[1]B, GP3
VIN[1]B_D[7]/ R23
PINCNTL242
EMAC[0]_RMTXEN/
DSIS: PIN
GP3[30]
EMAC[0]_MRXD[1]/
EMAC[0],
EMAC[0]_RGRXD[0]/
VIN[1]B, GP3
VIN[1]B_D[6]/ P23
PINCNTL241
EMAC[0]_RMTXD[1]/
DSIS: PIN
GP3[29]
EMAC[0]_MRXD[0]/
EMAC[0],
EMAC[0]_RGTXD[0]/
VIN[1]B, GP3
VIN[1]B_D[5]/ G28
PINCNTL240
EMAC[0]_RMTXD[0]/
DSIS: PIN
GP3[28]
EMAC[0]_MRXDV/ EMAC[1],
EMAC[1]_RGRXD[1]/ IPD GPMC, SPI[2]
K22 I [G]MII Receive Data Valid input
GPMC_A[5]/ DVDD_GPMC PINCNTL248
SPI[2]_SCLK DSIS: 0
EMAC[0]_MRXER/
EMAC[0],
EMAC[0]_RGTXCTL/
IPD VIN[1]B, GP3
VIN[1]B_D[3]/ J26 I [G]MII Receive Data Error input
DVDD_GPMC PINCNTL238
EMAC[0]_RMRXER/
DSIS: 0
GP3[26]
EMAC[0]_MTCLK/
EMAC[0],
EMAC[0]_RGRXC/
VIN[1]B, SPI[3],
VIN[1]B_D[0]/ IPD
L24 I I2C[2], GP3 [G]MII Transmit Clock input
SPI[3]_SCS[3]/ DVDD_GPMC
PINCNTL235
I2C[2]_SDA/
DSIS: 0
GP3[23]

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Table 3-7. EMAC[0] Terminal Functions [(R)(G)MII] (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
EMAC[0]_MTXD[7]/
EMAC[1],
EMAC[1]_RGTXD[3]/
GPMC, UART1
EMAC[1]_RMTXD[1]/ H24
PINCNTL257
GPMC_A[14]/
DSIS: N/A
UART1_CTS
EMAC[0]_MTXD[6]/
EMAC[1],
EMAC[1]_RGRXD[0]/
GPMC, UART1
EMAC[1]_RMTXD[0]/ J22
PINCNTL256
GPMC_A[13]/
DSIS: N/A
UART1_TXD
EMAC[0]_MTXD[5]/
EMAC[1],
EMAC[1]_RGTXC/
GPMC, UART1
EMAC[1]_RMCRSDV/ F27
PINCNTL255
GPMC_A[12]/
DSIS: N/A
UART1_RXD
EMAC[0]_MTXD[4]/
EMAC[1],
EMAC[1]_RGTXD[2]/
GPMC, UART4
EMAC[1]_RMRXER/ G23 [G]MII Transmit Data [7:0]. For 1000 EMAC GMII
PINCNTL254
GPMC_A[11]/ IPD operation, EMAC[0]_TXD[7:0] are used. For 10/100
O DSIS: N/A
UART4_RTS DVDD_GPMC EMAC MII operation, only EMAC[0]_TXD[3:0] are
EMAC[0]_MTXD[3]/ used.
EMAC[1],
EMAC[1]_RGTXD[0]/
GPMC, UART4
EMAC[1]_RMRXD[1]/ H23
PINCNTL253
GPMC_A[10]/
DSIS: N/A
UART4_CTS
EMAC[0]_MTXD[2]/
EMAC[1],
EMAC[1]_RGTXCTL/
GPMC, UART4
EMAC[1]_RMRXD[0]/ H22
PINCNTL252
GPMC_A[9]/
DSIS: N/A
UART4_TXD
EMAC[0]_MTXD[1]/ EMAC[1],
EMAC[1]_RGTXD[1]/ GPMC, UART4
H25
GPMC_A[8]/ PINCNTL251
UART4_RXD DSIS: N/A
EMAC[0]_MTXD[0]/ EMAC[1],
EMAC[1]_RGRXD[3]/ GPMC, UART4
J24
GPMC_A[7]/ PINCNTL250
SPI[2]_D[0] DSIS: N/A
EMAC[0]_MTXEN/
EMAC[1],
EMAC[1]_RGRXD[2]/
IPD GPMC, UART4
EMAC[1]_RMTXEN/ J23 O [G]MII Transmit Data Enable output
DVDD_GPMC PINCNTL258
GPMC_A[15]/
DSIS: N/A
UART1_RTS
EMAC[0] RMII Mode
An EMAC bootmode must be selected via the BTMODE[4:0] pins. Once the EMAC bootmode is selected, the BTMODE[9:8] pins determine
the Ethernet PHY Mode Selection (for example, 01b is RMII mode). For more detailed information on EMAC bootmodes and Ethernet PHY
Mode selection, see Section 4.2.6, Ethernet PHY Mode Selection.
These pin functions are available only when RMII mode is selected.
RMII Reference Clock (EMAC[0] and EMAC[1] RMII
mode)
Regardless of EMAC[0] RMII Mode, the GMII_EN bit
EMAC_RMREFCLK/ TIMER2, GP1 in the MACCONTROL register, of the Control
IPD
TIM2_IO/ J27 I/O PINCNTL232 Module, configures the RMREFCLK pin function as
DVDD_GPMC
GP1[10] DSIS: PIN an INPUT or OUTPUT clock reference. During RMII
ROM Boot, the RMREFCLK pin function is
configured as an OUTPUT clock reference (driving
50 MHz).

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Table 3-7. EMAC[0] Terminal Functions [(R)(G)MII] (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
EMAC[0]_MRCLK/
EMAC[0],
EMAC[0]_RGTXC/
VIN[1]B, SPI[3],
VIN[1]B_D[4]/ IPD
H27 I GP3 RMII Carrier Sense input
EMAC[0]_RMCRSDV/ DVDD_GPMC
PINCNTL239
SPI[3]_SCS[2]/
DSIS: 0
GP3[27]
EMAC[0]_MCRS/ EMAC[0],
EMAC[0]_RGRXD[2]/ VIN[1]B, SPI[3],
IPD
VIN[1]B_D[2]/ R25 I GPI3
DVDD_GPMC
EMAC[0]_RMRXD[1]/ PINCNTL237
GP3[25] DSIS: PIN RMII Receive Data [1:0]. For 10/100 EMAC RMII
EMAC[0]_MCOL/ operation, EMAC[0]_RMRXD[1:0] are used.
EMAC[0],
EMAC[0]_RGRXCTL/
IPD VIN[1]B, GP3
VIN[1]B_D[1]/ L23 I
DVDD_GPMC PINCNTL236
EMAC[0]_RMRXD[0]/
DSIS: PIN
GP3[24]
EMAC[0]_MRXER/
EMAC[0],
EMAC[0]_RGTXCTL/
IPD VIN[1]B, GP3
VIN[1]B_D[3]/ J26 I RMII Receive Data Error input
DVDD_GPMC PINCNTL238
EMAC[0]_RMRXER/
DSIS: 0
GP3[26]
EMAC[0]_MRXD[1]/
EMAC[0],
EMAC[0]_RGRXD[0]/
IPD VIN[1]B, GP3
VIN[1]B_D[6]/ P23 O
DVDD_GPMC PINCNTL241
EMAC[0]_RMTXD[1]/
DSIS: N/A
GP3[29] RMII Transmit Data [7:0]. For 10/100 EMAC RMII
EMAC[0]_MRXD[0]/ operation, EMAC[0]_RMTXD[1:0] are used.
EMAC[0],
EMAC[0]_RGTXD[0]/
IPD VIN[1]B, GP3
VIN[1]B_D[5]/ G28 O
DVDD_GPMC PINCNTL240
EMAC[0]_RMTXD[0]/
DSIS: N/A
GP3[28]
EMAC[0]_MRXD[2]/
EMAC[0],
EMAC[0]_RGRXD[1]/
IPD VIN[1]B, GP3
VIN[1]B_D[7]/ R23 O RMII Transmit Data Enable output
DVDD_GPMC PINCNTL242
EMAC[0]_RMTXEN/
DSIS: N/A
GP3[30]
EMAC[0] RGMII Mode
An EMAC bootmode must be selected via the BTMODE[4:0] pins. Once the EMAC bootmode is selected, the BTMODE[9:8] pins determine
the Ethernet PHY Mode Selection (for example, 10b is RGMII mode). For more detailed information on EMAC bootmodes and Ethernet
PHY Mode selection, see Section 4.2.6, Ethernet PHY Mode Selection
These pin functions are available only when RGMII mode is selected.
EMAC[0]_MTCLK/
EMAC[0],
EMAC[0]_RGRXC/
VIN[1]B, SPI[3],
VIN[1]B_D[0]/ IPD
L24 I I2C[2], GP3 RGMII Receive Clock
SPI[3]_SCS[3]/ DVDD_GPMC
PINCNTL235
I2C[2]_SDA/
DSIS: PIN
GP3[23]
EMAC[0]_MCOL/
EMAC[0],
EMAC[0]_RGRXCTL/
IPD VIN[1]B, GP3
VIN[1]B_D[1]/ L23 I RGMII Receive Control
DVDD_GPMC PINCNTL236
EMAC[0]_RMRXD[0]/
DSIS: PIN
GP3[24]

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Table 3-7. EMAC[0] Terminal Functions [(R)(G)MII] (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
EMAC[0]_MRXD[4]/ EMAC[0],
EMAC[0]_RGRXD[3]/ IPD GPMC, UART5
T23 I
GPMC_A[1]/ DVDD_GPMC PINCNTL244
UART5_TXD DSIS: PIN
EMAC[0]_MCRS/
EMAC[0],
EMAC[0]_RGRXD[2]/
IPD VIN[1]B, GP3
VIN[1]B_D[2]/ R25 I
DVDD_GPMC PINCNTL237
EMAC[0]_RMRXD[1]/
DSIS: PIN
GP3[25]
EMAC[0]_MRXD[2]/ RGMII Receive Data [3:0]
EMAC[0],
EMAC[0]_RGRXD[1]/
IPD VIN[1]B, GP3
VIN[1]B_D[7]/ R23 I
DVDD_GPMC PINCNTL242
EMAC[0]_RMTXEN/
DSIS: PIN
GP3[30]
EMAC[0]_MRXD[1]/
EMAC[0],
EMAC[0]_RGRXD[0]/
IPD VIN[1]B, GP3
VIN[1]B_D[6]/ P23 I
DVDD_GPMC PINCNTL241
EMAC[0]_RMTXD[1]/
DSIS: PIN
GP3[29]
EMAC[0]_MRCLK/
EMAC[0],
EMAC[0]_RGTXC/
VIN[1]B, SPI[3],
VIN[1]B_D[4]/ IPD
H27 O GP3 RGMII Transmit Clock
EMAC[0]_RMCRSDV/ DVDD_GPMC
PINCNTL239
SPI[3]_SCS[2]/
DSIS: N/A
GP3[27]
EMAC[0]_MRXER/
EMAC[0],
EMAC[0]_RGTXCTL/
IPD VIN[1]B, GP3
VIN[1]B_D[3]/ J26 O RGMII Transmit Enable
DVDD_GPMC PINCNTL238
EMAC[0]_RMRXER/
DSIS: N/A
GP3[26]
EMAC[0]_MRXD[5]/ EMAC[0],
EMAC[0]_RGTXD[3]/ IPD GPMC, UART5
H26 O
GPMC_A[2]/ DVDD_GPMC PINCNTL245
UART5_CTS DSIS: N/A
EMAC[0]_MRXD[6]/ EMAC[0],
EMAC[0]_RGTXD[2]/ IPD GPMC, UART5
F28 O
GPMC_A[3]/ DVDD_GPMC PINCNTL246
UART5_RTS DSIS: N/A
EMAC[0]_MRXD[7]/ EMAC[0], RGMII Transmit Data [3:0]
EMAC[0]_RGTXD[1]/ IPD GPMC, SPI[2]
G27 O
GPMC_A[4]/ DVDD_GPMC PINCNTL247
SPI[2]_SCS[3] DSIS: N/A
EMAC[0]_MRXD[0]/
EMAC[0],
EMAC[0]_RGTXD[0]/
IPD VIN[1]B, GP3
VIN[1]B_D[5]/ G28 O
DVDD_GPMC PINCNTL240
EMAC[0]_RMTXD[0]/
DSIS: N/A
GP3[28]

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Table 3-8. EMAC[1] Terminal Functions [(R)(G)MII]

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
EMAC[1] (G)MII Mode
An EMAC bootmode must be selected via the BTMODE[4:0] pins. Once the EMAC bootmode is selected, the BTMODE[9:8] pins determine
the Ethernet PHY Mode Selection (for example, 00b is MII mode). For more detailed information on EMAC bootmodes and Ethernet PHY
Mode selection, see Section 4.2.6, Ethernet PHY Mode Selection.
These pin functions are available only when GMII and MII modes are selected.
VOUT[1]_HSYNC/
VOUT[1],
EMAC[1]_MCOL/
VIN[1]A, SPI[3],
VIN[1]A_VSYNC/ IPD
AC24 I UART3, GP2 [G]MII Collision Detect (Sense) input
SPI[3]_D[1]/ DVDD
PINCNTL205
UART3_RTS/
DSIS: 0
GP2[29]
VOUT[1]_VSYNC/
EMAC[1]_MCRS/ VOUT[1],
VIN[1]A_FLD/ VIN[1]A, SPI[3],
IPD
VIN[1]A_DE/ AA23 I UART3, GP2 [G]MII Carrier Sense input
DVDD
SPI[3]_D[0]/ PINCNTL206
UART3_CTS/ DSIS: 0
GP2[30]
VOUT[1]_G_Y_YC[6]/ VOUT[1],
EMAC[1]_GMTCLK/ IPD VIN[1]A, GP3
AH27 O GMII Source Synchronous Transmit Clock
VIN[1]A_D[11]/ DVDD PINCNTL218
GP3[10] DSIS: N/A
VOUT[1]_B_CB_C[3]/ VOUT[1],
EMAC[1]_MRCLK/ VIN[1]A,
IPD
VIN[1]A_D[0]/ AH25 I UART4, GP3 [G]MII Receive Clock
DVDD
UART4_CTS/ PINCNTL208
GP3[0] DSIS: 0

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown
resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and the Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal
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Table 3-8. EMAC[1] Terminal Functions [(R)(G)MII] (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
VOUT[1]_G_Y_YC[4]/ VOUT[1],
EMAC[1]_MRXD[7]/ VIN[1]A, GP3
W22
VIN[1]A_D[9]/ PINCNTL216
GP3[8] DSIS: PIN
VOUT[1]_G_Y_YC[3]/ VOUT[1],
EMAC[1]_MRXD[6]/ VIN[1]A, GP3
Y23
VIN[1]A_D[8]/ PINCNTL215
GP3[7] DSIS: PIN
VOUT[1]_B_CB_C[9]/ VOUT[1],
EMAC[1]_MRXD[5]/ VIN[1]A, I2C[3],
VIN[1]A_D[6]/ AA24 GP3
I2C[3]_SDA/ PINCNTL214
GP3[6] DSIS: PIN
VOUT[1]_B_CB_C[8]/ VOUT[1],
EMAC[1]_MRXD[4]/ VIN[1]A, I2C[3],
VIN[1]A_D[5]/ AH26 GP3
I2C[3]_SCL/ PINCNTL213
GP3[5] DSIS: PIN [G]MII Receive Data [7:0]. For 1000 EMAC GMII
VOUT[1]_B_CB_C[7]/ IPD VOUT[1], operation, EMAC[0]_RXD[7:0] are used. For 10/100
I
EMAC[1]_MRXD[3]/ DVDD VIN[1]A, EMAC MII operation, only EMAC[0]_RXD[3:0] are
VIN[1]A_D[4]/ AC25 UART3, GP3 used.
UART3_TXD/ PINCNTL212
GP3[4] DSIS: PIN
VOUT[1]_B_CB_C[6]/ VOUT[1],
EMAC[1]_MRXD[2]/ VIN[1]A,
VIN[1]A_D[3]/ AD25 UART3, GP3
UART3_RXD/ PINCNTL211
GP3[3] DSIS: PIN
VOUT[1]_B_CB_C[5]/ VOUT[1],
EMAC[1]_MRXD[1]/ VIN[1]A,
VIN[1]A_D[2]/ AF25 UART4, GP3
UART4_TXD/ PINCNTL210
GP3[2] DSIS: PIN
VOUT[1]_B_CB_C[4]/ VOUT[1],
EMAC[1]_MRXD[0]/ VIN[1]A,
VIN[1]A_D[1]/ AG25 UART4, GP3
UART4_RXD/ PINCNTL209
GP3[1] DSIS: PIN
VOUT[1]_G_Y_YC[5]/ VOUT[1],
EMAC[1]_MRXDV/ IPD VIN[1]A, GP3
AG26 I [G]MII Receive Data Valid input
VIN[1]A_D[10]/ DVDD PINCNTL217
GP3[9] DSIS: 0
VOUT[1]_AVID/ VOUT[1],
EMAC[1]_MRXER/ VIN[1]A,
VIN[1]A_CLK/ IPD UART4, TIMER
Y22 I [G]MII Receive Data Error input
UART4_RTS/ DVDD 6, GP2
TIM6_IO/ PINCNTL207
GP2[31] DSIS: 0
VOUT[1]_CLK/ VOUT[1],
EMAC[1]_MTCLK/ IPD VIN[1]A, GP2
AE24 I [G]MII Transmit Clock input
VIN[1]A_HSYNC/ DVDD PINCNTL204
GP2[28] DSIS: 0

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Table 3-8. EMAC[1] Terminal Functions [(R)(G)MII] (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
VOUT[1]_R_CR[8]/ VOUT[1],
EMAC[1]_MTXD[7]/ VIN[1]A,
VIN[1]A_D[19]/ W23 UART5, GP3
UART5_RXD/ PINCNTL226
GP3[18] DSIS: N/A
VOUT[1]_R_CR[7]/ VOUT[1],
EMAC[1]_MTXD[6]/ VIN[1]A, SPI[3],
VIN[1]A_D[18]/ V22 GP3
SPI[3]_D[0]/ PINCNTL225
GP3[17] DSIS: N/A
VOUT[1]_R_CR[6]/ VOUT[1],
EMAC[1]_MTXD[5]/ VIN[1]A, SPI[3],
VIN[1]A_D[17]/ AA25 GP3
SPI[3]_D[1]/ PINCNTL224
GP3[16] DSIS: N/A
VOUT[1]_R_CR[5]/ VOUT[1],
EMAC[1]_MTXD[4]/ VIN[1]A, SPI[3],
VIN[1]A_D[16]/ AC26 GP3 [G]MII Transmit Data [7:0]. For 1000 EMAC GMII
SPI[3]_SCLK/ IPD PINCNTL223 operation, EMAC[0]_TXD[7:0] are used. For 10/100
O
GP3[15] DVDD DSIS: N/A EMAC MII operation, only EMAC[0]_TXD[3:0] are
used.
VOUT[1]_R_CR[4]/ VOUT[1],
EMAC]1]_MTXD[3]/ VIN[1]A, SPI[3],
VIN]1]A_D[15]/ AG27 GP3
SPI[3]_SCS[1]/ PINCNTL222
GP3[14] DSIS: N/A
VOUT[1]_G_Y_YC[9]/ VOUT[1],
EMAC[1]_MTXD[2]/ VIN[1]A, GP3
AD26
VIN[1]A_D[14]/ PINCNTL221
GP3[13] DSIS: N/A
VOUT[1]_G_Y_YC[8]/ VOUT[1],
EMAC[1]_MTXD[1]/ VIN[1]A, GP3
AE26
VIN[1]A_D[13]/ PINCNTL220
GP3[12] DSIS: N/A
VOUT[1]_G_Y_YC[7]/ VOUT[1],
EMAC[1]_MTXD[0]/ VIN[1]A, GP3
AF26
VIN[1]A_D[12]/ PINCNTL219
GP3[11] DSIS: N/A
VOUT[1]_R_CR[9]/ VOUT[1],
EMAC[1]_MTXEN/ VIN[1]A,
IPD
VIN[1]A_D[20]/ Y24 O UART5, GP3 [G]MII Transmit Data Enable output
DVDD
UART5_TXD/ PINCNTL227
GP3[19] DSIS: N/A
EMAC[1] RMII Mode
An EMAC bootmode must be selected via the BTMODE[4:0] pins. Once the EMAC bootmode is selected, the BTMODE[9:8] pins determine
the Ethernet PHY Mode Selection (for example, 01b is RMII mode). For more detailed information on EMAC bootmodes and Ethernet PHY
Mode selection, see Section 4.2.6, Ethernet PHY Mode Selection.
These pin functions are available only when RMII mode is selected.
EMAC_RMREFCLK/ TIMER2, GP1
IPD RMII Reference Clock (EMAC[0] and EMAC[1] RMII
TIM2_IO/ J27 I/O PINCNTL232
DVDD_GPMC mode)
GP1[10] DSIS: PIN

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Table 3-8. EMAC[1] Terminal Functions [(R)(G)MII] (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
VIN[0]A,
VIN[0]A_D[20]/
CAMERA_I/F,
CAM_D[12]/
IPD SPI[3], GP0
EMAC[1]_RMCRSDV/ AC17 I
DVDD_C PINCNTL160
SPI[3]_SCS[0]/
DSIS: 0
GP0[14]
MM: MUX1
RMII Carrier Sense input
EMAC[0],
EMAC[0]_MTXD[5]/
EMAC[1],
EMAC[1]_RGTXC/
IPD GPMC, UART1
EMAC[1]_RMCRSDV/ F27 I
DVDD_GPMC PINCNTL255
GPMC_A[12]/
DSIS: 0
UART1_RXD
MM: MUX0
VIN[0]A,
VIN[0]A_D[18]/
CAMERA_I/F,
CAM_D[10]/
IPU I2C[3], GP0
EMAC[1]_RMRXD[1]/ AF20 I
DVDD_C PINCNTL158
I2C[3]_SCL/
DSIS: PIN
GP0[12]
MM: MUX1
EMAC[0],
EMAC[0]_MTXD[3]/
EMAC[1],
EMAC[1]_RGTXD[0]/
IPD GPMC, UART4
EMAC[1]_RMRXD[1]/ H23 I
DVDD_GPMC PINCNTL253
GPMC_A[10]/
DSIS: PIN
UART4_CTS
MM: MUX0
RMII Receive Data [1:0].
VIN[0]A,
VIN[0]A_D[19]/
CAMERA_I/F,
CAM_D[11]/
IPU I2C[3], GP0
EMAC[1]_RMRXD[0]/ AF21 I
DVDD_C PINCNTL159
I2C[3]_SDA/
DSIS: PIN
GP0[13]
MM: MUX1
EMAC[0],
EMAC[0]_MTXD[2]/
EMAC[1],
EMAC[1]_RGTXCTL/
IPD GPMC, UART4
EMAC[1]_RMRXD[0]/ H22 I
DVDD_GPMC PINCNTL252
GPMC_A[9]/
DSIS: PIN
UART4_TXD
MM: MUX0
VIN[0]A,
VIN[0]A_D[17]/ CAMERA_I/F,
CAM_D[9]/ IPD SPI[3], GP0
AB21 I
EMAC[1]_RMRXER/ DVDD_C PINCNTL157
GP0[11] DSIS: 0
MM: MUX1
RMII Receive Data Error input
EMAC[0],
EMAC[0]_MTXD[4]/
EMAC[1],
EMAC[1]_RGTXD[2]/
IPD GPMC, UART1
EMAC[1]_RMRXER/ G23 I
DVDD_GPMC PINCNTL254
GPMC_A[11]/
DSIS: 0
UART4_RTS
MM: MUX0

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Table 3-8. EMAC[1] Terminal Functions [(R)(G)MII] (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
VIN[0]A,
VIN[0]A_D[22]/
CAMERA_I/F,
CAM_D[14]/
IPD SPI[3], GP0
EMAC[1]_RMTXD[1]/ AC21 O
DVDD_C PINCNTL162
SPI[3]_D[1]/
DSIS: N/A
GP0[16]
MM: MUX1
EMAC[0]_MTXD[7]/ EMAC[0],
EMAC[1]_RGTXD[3]/ GPMC, UART1
IPD
EMAC[1]_RMTXD[1]/ H24 O PINCNTL257
DVDD_GPMC
GPMC_A[14]/ DSIS: N/A
UART1_CTS MM: MUX0
VIN[0]A RMII Transmit Data [1:0].
VIN[0]A_D[21]/
CAMERA_I/F,
CAM_D[13]/
IPD SPI[3], GP0
EMAC[1]_RMTXD[0]/ AE18 O
DVDD_C PINCNTL161
SPI[3]_SCLK/
DSIS: N/A
GP0[15]
MM: MUX1
EMAC[0],
EMAC[0]_MTXD[6]/
EMAC[1],
EMAC[1]_RGRXD[0]/
IPD GPMC, UART1
EMAC[1]_RMTXD[0]/ J22 O
DVDD_GPMC PINCNTL256
GPMC_A[13]/
DSIS: N/A
UART1_TXD
MM: MUX0
VIN[0]A,
VIN[0]A_D[23]/
CAMERA_I/F,
CAM_D[15]/
IPD SPI[3], GP0
EMAC[1]_RMTXEN/ AC16 O
DVDD_C PINCNTL163
SPI[3]_D[0]/
DSIS: N/A
GP0[17]
MM: MUX1
RMII Transmit Data Enable output
EMAC[0],
EMAC[0]_MTXEN/
EMAC[1],
EMAC[1]_RGRXD[2]/
IPD GPMC, UART1
EMAC[1]_RMTXEN/ J23 O
DVDD_GPMC PINCNTL258
GPMC_A[15]/
DSIS: N/A
UART1_RTS
MM: MUX0
EMAC[1] RGMII MODE
An EMAC bootmode must be selected via the BTMODE[4:0] pins. Once the EMAC bootmode is selected, the BTMODE[9:8] pins determine
the Ethernet PHY Mode Selection (for example, 10b is RGMII mode). For more detailed information on EMAC bootmodes and Ethernet
PHY Mode selection, see Section 4.2.6, Ethernet PHY Mode Selection
These pin functions are available only when RGMII mode is selected.
EMAC[0]_GMTCLK/ EMAC[0],
EMAC[1]_RGRXC/ IPD GPMC, SPI[2]
K23 I RGMII Receive Clock
GPMC_A[6]/ DVDD_GPMC PINCNTL249
SPI[2]_D[1] DSIS: PIN
EMAC[0]_MRXD[3]/
EMAC[1]_RGRXCTL/ EMAC[0],
GPMC_A[27]/ IPD GPMC, UART5
J25 I RGMII Receive Control
GPMC_A[26]/ DVDD_GPMC PINCNTL243
GPMC_A[0]/ DSIS: PIN
UART5_RXD

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Table 3-8. EMAC[1] Terminal Functions [(R)(G)MII] (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
EMAC[0]_MTXD[0]/ EMAC[0],
EMAC[1]_RGRXD[3]/ IPD GPMC, UART4
J24 I
GPMC_A[7]/ DVDD_GPMC PINCNTL250
SPI[2]_D[0] DSIS: PIN
EMAC[0]_MTXEN/
EMAC[0],
EMAC[1]_RGRXD[2]/
IPD GPMC, UART4
EMAC[1]_RMTXEN/ J23 I
DVDD_GPMC PINCNTL258
GPMC_A[15]/
DSIS: PIN
UART1_RTS
RGMII Receive Data [3:0]
EMAC[0]_MRXDV/ EMAC[0],
EMAC[1]_RGRXD[1]/ IPD GPMC, SPI[2]
K22 I
GPMC_A[5]/ DVDD_GPMC PINCNTL248
SPI[2]_SCLK DSIS: PIN
EMAC[0]_MTXD[6]/
EMAC[0],
EMAC[1]_RGRXD[0]/
IPD GPMC, UART1
EMAC[1]_RMTXD[0]/ J22 I
DVDD_GPMC PINCNTL256
GPMC_A[13]/
DSIS: PIN
UART1_TXD
EMAC[0]_MTXD[5]/
EMAC[0],
EMAC[1]_RGTXC/
IPD GPMC, UART1
EMAC[1]_RMCRSDV/ F27 O RGMII Transmit Clock
DVDD_GPMC PINCNTL255
GPMC_A[12]/
DSIS: N/A
UART1_RXD
EMAC[0]_MTXD[2]/
EMAC[0],
EMAC[1]_RGTXCTL/
IPD GPMC, UART4
EMAC[1]_RMRXD[0]/ H22 O RGMII Transmit Enable
DVDD_GPMC PINCNTL252
GPMC_A[9]/
DSIS: N/A
UART4_TXD
EMAC[0]_MTXD[7]/
EMAC[0],
EMAC[1]_RGTXD[3]/
IPD GPMC, UART1
EMAC[1]_RMTXD[1]/ H24 O
DVDD_GPMC PINCNTL257
GPMC_A[14]/
DSIS: N/A
UART1_CTS
EMAC[0]_MTXD[4]/
EMAC[0],
EMAC[1]_RGTXD[2]/
IPD GPMC, UART4
EMAC[1]_RMRXER/ G23 O
DVDD_GPMC PINCNTL254
GPMC_A[11]/
DSIS: N/A
UART4_RTS RGMII Transmit Data [3:0]
EMAC[0]_MTXD[1]/ EMAC[0],
EMAC[1]_RGTXD[1]/ IPD GPMC, UART4
H25 O
GPMC_A[8]/ DVDD_GPMC PINCNTL251
UART4_RXD DSIS: N/A
EMAC[0]_MTXD[3]/ EMAC[0],
EMAC[1]_RGTXD[0]/ EMAC[1],
IPD
EMAC[1]_RMRXD[1]/ H23 O GPMC, UART4
DVDD_GPMC
GPMC_A[10]/ PINCNTL253
UART4_CTS DSIS: N/A

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Table 3-9. MDIO Terminal Functions

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
MDIO
GP1
MDCLK/ IPU
H28 O PINCNTL233 Management Data Serial Clock output
GP1[11] DVDD_GPMC
DSIS: N/A
GP1
MDIO/ IPU
P24 I/O PINCNTL234 Management Data I/O
GP1[12] DVDD_GPMC
DSIS: 1
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown
resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

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3.2.7 General-Purpose Input/Outputs (GPIOs)

Table 3-10. GP0 Terminal Functions

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
GPIO0
Note: General-Purpose Input/Output (I/O) pins can also serve as external interrupt inputs.
UART2
UART2_TXD/ IPD
U3 I/O PINCNTL61 General-Purpose Input/Output (I/O) 0 [GP0] pin 31
GP0[31] DVDD
DSIS: PIN
TCLKIN
TCLKIN/ IPD
T2 I/O PINCNTL60 General-Purpose Input/Output (I/O) 0 [GP0] pin 30
GP0[30] DVDD
DSIS: PIN
UART2
UART2_RXD/ IPD
U4 I/O PINCNTL59 General-Purpose Input/Output (I/O) 0 [GP0] pin 29
GP0[29] DVDD
DSIS: PIN
MCA[5], MCA[4],
MCA[5]_AXR[1]/
TIMER7
MCA[4]_AXR[3]/ IPD
L6 I/O PINCNTL58
TIM7_IO/ DVDD
DSIS: PIN
GP0[28]
MM: MUX1
VOUT[1]_FLD/ VOUT[1], General-Purpose Input/Output (I/O) 0 [GP0] pin 28
CAM_FLD/ CAMERA_I/F,
CAM_WE/ IPD GPMC, UART2
AB23 I/O
GPMC_A[11]/ DVDD_C PINCNTL174
UART2_CTS/ DSIS: PIN
GP0[28] MM: MUX0
MCA[5], MCA[4]
MCA[5]_AXR[0]/
IPD PINCNTL57
MCA[4]_AXR[2]/ L7 I/O
DVDD DSIS: PIN
GP0[27]
MM: MUX1
VOUT[1], General-Purpose Input/Output (I/O) 0 [GP0] pin 27
VOUT[1]_B_CB_C[0]/
CAMERA_I/F,
CAM_VS/
IPU GPMC, UART2
GPMC_A[10]/ AD23 I/O
DVDD_C PINCNTL173
UART2_TXD/
DSIS: PIN
GP0[27]
MM: MUX0
MCA[5]
MCA[5]_AFSX/ IPD PINCNTL56
H5 I/O
GP0[26] DVDD DSIS: PIN
MM: MUX1
VOUT[1], General-Purpose Input/Output (I/O) 0 [GP0] pin 26
VOUT[1]_B_CB_C[1]/
CAMERA_I/F,
CAM_HS/
IPD GPMC, UART2
GPMC_A[9]/ AE23 I/O
DVDD_C PINCNTL172
UART2_RXD/
DSIS: PIN
GP0[26]
MM: MUX0
MCA[5]
MCA[5]_ACLKX/ IPD PINCNTL55
J3 I/O
GP0[25] DVDD DSIS: PIN
MM: MUX1
VOUT[1], General-Purpose Input/Output (I/O) 0 [GP0] pin 25
VOUT[1]_R_CR[0]/
CAMERA_I/F,
CAM_D[0]/
IPD GPMC, UART4
GPMC_A[8]/ AA22 I/O
DVDD_C PINCNTL171
UART4_RTS/
DSIS: PIN
GP0[25]
MM: MUX0

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown
resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal
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Table 3-10. GP0 Terminal Functions (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
MCA[4], TIMER6
MCA[4]_AXR[1]/
IPD PINCNTL54
TIM6_IO/ J4 I/O
DVDD DSIS: PIN
GP0[24]
MM: MUX1
VOUT[1], General-Purpose Input/Output (I/O) 0 [GP0] pin 24
VOUT[1]_R_CR[1]/
CAMERA_I/F,
CAM_D[1]/
IPD GPMC, UART4
GPMC_A[7]/ AC19 I/O
DVDD_C PINCNTL170
UART4_CTS/
DSIS: PIN
GP0[24]
MM: MUX0
MCA[4]
MCA[4]_AXR[0]/ IPD PINCNTL53
H6 I/O
GP0[23] DVDD DSIS: PIN
MM: MUX1
VOUT[1], General-Purpose Input/Output (I/O) 0 [GP0] pin 23
VOUT[1]_G_Y_YC[0]/
CAMERA_I/F,
CAM_D[2]/
IPD GPMC, UART4
GPMC_A[6]/ AC18 I/O
DVDD_C PINCNTL169
UART4_TXD/
DSIS: PIN
GP0[23]
MM: MUX0
MCA[4]
MCA[4]_AFSX/ IPD PINCNTL52
H3 I/O
GP0[22] DVDD DSIS: PIN
MM: MUX1
VOUT[1], General-Purpose Input/Output (I/O) 0 [GP0] pin 22
VOUT[1]_G_Y_YC[1]/
CAMERA_I/F,
CAM_D[3]/
IPU GPMC, UART4
GPMC_A[5]/ AD18 I/O
DVDD_C PINCNTL168
UART4_RXD/
DSIS: PIN
GP0[22]
MM: MUX0
MCA[4]
MCA[4]_ACLKX/ IPD PINCNTL51
K7 I/O
GP0[21] DVDD DSIS: PIN
MM: MUX1
VIN[0]B, General-Purpose Input/Output (I/O) 0 [GP0] pin 21
VIN[0]B_FLD/ CAMERA_I/F
IPU
CAM_D[4]/ AD17 I/O PINCNTL167
DVDD_C
GP0[21] DSIS: PIN
MM: MUX0
MCA[3], MCA[1]
MCA[3]_AXR[2]/
IPD PINCNTL49
MCA[1]_AXR[8]/ F2 I/O
DVDD DSIS: PIN
GP0[20]
MM: MUX1
VIN[0]A, General-Purpose Input/Output (I/O) 0 [GP0] pin 20
VIN[0]A_FLD/ CAMERA_I/F
IPU
CAM_D[5]/ AC22 I/O PINCNTL166
DVDD_C
GP0[20] DSIS: PIN
MM: MUX0
MCA[3], TIMER5
MCA[3]_AXR[1]/
IPD PINCNTL48
TIM5_IO/ G2 I/O
DVDD DSIS: PIN
GP0[19]
MM: MUX1
VIN[0]B, General-Purpose Input/Output (I/O) 0 [GP0] pin 19
VIN[0]B_DE/ CAMERA_I/F
IPU
CAM_D[6]/ AC15 I/O PINCNTL165
DVDD_C
GP0[19] DSIS: PIN
MM: MUX0

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Table 3-10. GP0 Terminal Functions (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
MCA[3], TIMER4
MCA[3]_AXR[0]/
IPD PINCNTL47
TIM4_IO/ G1 I/O
DVDD DSIS: PIN
GP0[18]
MM: MUX1
VIN[0]A, General-Purpose Input/Output (I/O) 0 [GP0] pin 18
VIN[0]A_DE/ CAMERA_I/F
IPU
CAM_D[7]/ AB17 I/O PINCNTL164
DVDD_C
GP0[18] DSIS: PIN
MM: MUX0
MCA[3]
MCA[3]_AFSX/ IPD PINCNTL46
H4 I/O
GP0[17] DVDD DSIS: PIN
MM: MUX1
VIN[0]A,
VIN[0]A_D[23]/ CAMERA_I/F, General-Purpose Input/Output (I/O) 0 [GP0] pin 17
CAM_D[15]/ EMAC[1]_RM,
IPD
EMAC[1]_RMTXEN/ AC16 I/O SPI[3]
DVDD_C
SPI[3]_D[0]/ PINCNTL163
GP0[17] DSIS: PIN
MM: MUX0
MCA[3]
MCA[3]_ACLKX/ IPD PINCNTL45
G6 I/O
GP0[16] DVDD DSIS: PIN
MM: MUX1
VIN[0]A,
VIN[0]A_D[22]/ CAMERA_I/F, General-Purpose Input/Output (I/O) 0 [GP0] pin 16
CAM_D[14]/ EMAC[1]_RM,
IPD
EMAC[1]_RMTXD[1]/ AC21 I/O SPI[3]
DVDD_C
SPI[3]_D[1]/ PINCNTL162
GP0[16] DSIS: PIN
MM: MUX0
MCA[2], MCA[1],
MCA[2]_AXR[3]/
TIMER3
MCA[1]_AXR[7]/ IPD
H2 I/O PINCNTL44
TIM3_IO/ DVDD
DSIS: PIN
GP0[15]
MM: MUX1
VIN[0]A, General-Purpose Input/Output (I/O) 0 [GP0] pin 15
VIN[0]A_D[21]/ CAMERA_I/F,
CAM_D[13]/ EMAC[1]_RM,
IPD
EMAC[1]_RMTXD[0]/ AE18 I/O SPI[3]
DVDD_C
SPI[3]_SCLK/ PINCNTL161
GP0[15] DSIS: PIN
MM: MUX0
MCA[2], MCA[1],
MCA[2]_AXR[2]/
TIMER2
MCA[1]_AXR[6]/ IPD
V5 I/O PINCNTL43
TIM2_IO/ DVDD
DSIS: PIN
GP0[14]
MM: MUX1
VIN[0]A, General-Purpose Input/Output (I/O) 0 [GP0] pin 14
VIN[0]A_D[20]/ CAMERA_I/F,
CAM_D[12]/ EMAC[1]_RM,
IPD
EMAC[1]_RMCRSDV/ AC17 I/O SPI[3]
DVDD_C
SPI[3]_SCS[0]/ PINCNTL160
GP0[14] DSIS: PIN
MM: MUX0

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Table 3-10. GP0 Terminal Functions (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
MCA[2], SD0,
MCA[2]_AXR[1]/
UART5
SD0_DAT[7]/ IPU
V6 I/O PINCNTL42
UART5_TXD/ DVDD
DSIS: PIN
GP0[13]
MM: MUX1
VIN[0]A, General-Purpose Input/Output (I/O) 0 [GP0] pin 13
VIN[0]A_D[19]/ CAMERA_I/F,
CAM_D[11]/ EMAC[1]_RM,
IPU
EMAC[1]_RMRXD[0]/ AF21 I/O I2C[3]
DVDD_C
I2C[3]_SDA/ PINCNTL159
GP0[13] DSIS: PIN
MM: MUX0
MCA[2], SD0,
MCA[2]_AXR[0]/
UART5
SD0_DAT[6]/ IPU
N2 I/O PINCNTL41
UART5_RXD/ DVDD
DSIS: PIN
GP0[12]
MM: MUX1
VIN[0]A, General-Purpose Input/Output (I/O) 0 [GP0] pin 12
VIN[0]A_D[18]/ CAMERA_I/F,
CAM_D[10]/ EMAC[1]_RM,
IPU
EMAC[1]_RMRXD[1]/ AF20 I/O I2C[3]
DVDD_C
I2C[3]_SCL/ PINCNTL158
GP0[12] DSIS: PIN
MM: MUX0
MCA[2]
MCA[2]_AFSX/ IPU PINCNTL40
AA5 I/O
GP0[11] DVDD DSIS: PIN
MM: MUX1
VIN[0]A, General-Purpose Input/Output (I/O) 0 [GP0] pin 11
VIN[0]A_D[17]/ CAMERA_I/F,
CAM_D[9]/ IPD EMAC[1]_RM
AB21 I/O
EMAC[1]_RMRXER/ DVDD_C PINCNTL157
GP0[11] DSIS: PIN
MM: MUX0
MCA[2]
MCA[2]_ACLKX/ IPU PINCNTL39
U6 I/O
GP0[10] DVDD DSIS: PIN
MM: MUX1
VIN[0]A, General-Purpose Input/Output (I/O) 0 [GP0] pin 10
VIN[0]A_D[16]/ CAMERA_I/F,
CAM_D[8]/ IPU I2C[2]
AA21 I/O
I2C[2]_SCL/ DVDD_C PINCNTL156
GP0[10] DSIS: PIN
MM: MUX0
AUD_CLKIN2/
AUD_CLKIN2,
MCA[0]_AXR[9]/
MCA[0], MCA[2],
MCA[2]_AHCLKX/
IPD MCA[5], EDMA,
MCA[5]_AHCLKX/ H1 I/O General-Purpose Input/Output (I/O) 0 [GP0] pin 9
DVDD TIMER3
EDMA_EVT2/
PINCNTL16
TIM3_IO/
DSIS: PIN
GP0[9]
AUD_CLKIN1/
AUD_CLKIN1,
MCA[0]_AXR[8]/
MCA[0], MCA[1],
MCA[1]_AHCLKX/
IPD MCA[4], EDMA,
MCA[4]_AHCLKX/ R5 I/O General-Purpose Input/Output (I/O) 0 [GP0] pin 8
DVDD TIMER2
EDMA_EVT3/
PINCNTL15
TIM2_IO/
DSIS: PIN
GP0[8]
USB0
USB0_DRVVBUS/ IPD
AF11 I/O PINCNTL270 General-Purpose Input/Output (I/O) 0 [GP0] pin 7
GP0[7] DVDD
DSIS: PIN

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Table 3-10. GP0 Terminal Functions (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
SD0_DAT[3]/ SD0, SD1
IPU
SD1_DAT[7]/ Y4 I/O PINCNTL13 General-Purpose Input/Output (I/O) 0 [GP0] pin 6
DVDD_SD
GP0[6] DSIS: PIN
SD0_DAT[2]_SDRW/ SD0, SD1
IPU
SD1_DAT[6]/ Y3 I/O PINCNTL12 General-Purpose Input/Output (I/O) 0 [GP0] pin 5
DVDD_SD
GP0[5] DSIS: PIN
SD0_DAT[1]_SDIRQ/ SD0, SD1
IPU
SD1_DAT[5]/ Y5 I/O PINCNTL11 General-Purpose Input/Output (I/O) 0 [GP0] pin 4
DVDD_SD
GP0[4] DSIS: PIN
SD0_DAT[0]/ SD0, SD1
IPU
SD1_DAT[4]/ R7 I/O PINCNTL10 General-Purpose Input/Output (I/O) 0 [GP0] pin 3
DVDD_SD
GP0[3] DSIS: PIN
SD0_CMD/ SD0, SD1
IPU
SD1_CMD/ N1 I/O PINCNTL9 General-Purpose Input/Output (I/O) 0 [GP0] pin 2
DVDD_SD
GP0[2] DSIS: PIN
SD0
SD0_CLK/ IPU
Y6 I/O PINCNTL8 General-Purpose Input/Output (I/O) 0 [GP0] pin 1
GP0[1] DVDD_SD
DSIS: PIN
SD1
SD1_CMD/ IPU
P2 I/O PINCNTL2 General-Purpose Input/Output (I/O) 0 [GP0] pin 0
GP0[0] DVDD_SD
DSIS: PIN

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Table 3-11. GP1 Terminal Functions

SIGNAL OTHER (2)
TYPE (1) (3) MUXED DESCRIPTION
NAME NO.
GPIO1
Note: General-Purpose Input/Output (I/O) pins can also serve as external interrupt inputs.
GPMC_WAIT[0]/
IPU GPMC, EDMA
GPMC_A[26]/
W28 I/O DVDD_GP PINCNTL133 General-Purpose Input/Output (I/O) 1 [GP1] pin 31
EDMA_EVT0/
MC DSIS: PIN
GP1[31]
GPMC_BE[1]/
GPMC, EDMA,
GPMC_A[24]/ IPD
TIMER7
EDMA_EVT1/ V28 I/O DVDD_GP General-Purpose Input/Output (I/O) 1 [GP1] pin 30
PINCNTL132
TIM7_IO/ MC
DSIS: PIN
GP1[30]
GPMC_BE[0]_CLE/
GPMC, EDMA,
GPMC_A[25]/ IPD
TIMER6
EDMA_EVT2/ U27 I/O DVDD_GP General-Purpose Input/Output (I/O) 1 [GP1] pin 29
PINCNTL131
TIM6_IO/ MC
DSIS: PIN
GP1[29]
GPMC_ADV_ALE/
IPU GPMC, TIMER5
GPMC_CS[6]/
M26 I/O DVDD_GP PINCNTL128 General-Purpose Input/Output (I/O) 1 [GP1] pin 28
TIM5_IO/
MC DSIS: PIN
GP1[28]
GPMC_CLK/
GPMC_CS[5]/
GPMC, CLKOUT1,
GPMC_WAIT[1]/ IPU
EDMA, TIMER4
CLKOUT1/ R26 I/O DVDD_GP General-Purpose Input/Output (I/O) 1 [GP1] pin 27
PINCNTL127
EDMA_EVT3/ MC
DSIS: PIN
TIM4_IO/
GP1[27]
SPI[1]
SPI[1]_D[0]/ IPU PINCNTL88
AA6 I/O
GP1[26] DVDD DSIS: PIN
MM: MUX1
GPMC, VIN[1]B, General-Purpose Input/Output (I/O) 1 [GP1] pin 26
GPMC_CS[3]/
IPU SPI[2]
VIN[1]B_CLK/
P26 I/O DVDD_GP PINCNTL125
SPI[2]_SCS[0]/
MC DSIS: PIN
GP1[26]
MM: MUX0
GPMC_CS[2]/ IPU GPMC
GPMC_A[24]/ M25 I/O DVDD_GP PINCNTL124 General-Purpose Input/Output (I/O) 1 [GP1] pin 25
GP1[25] MC DSIS: PIN
GPMC_CS[1]/ IPU GPMC
GPMC_A[25]/ K28 I/O DVDD_GP PINCNTL123 General-Purpose Input/Output (I/O) 1 [GP1] pin 24
GP1[24] MC DSIS: PIN
IPU GPMC
GPMC_CS[0]/
T28 I/O DVDD_GP PINCNTL122 General-Purpose Input/Output (I/O) 1 [GP1] pin 23
GP1[23]
MC DSIS: PIN
SD2_DAT[4]/
GPMC_A[27]/
SD2, GPMC,
GPMC_A[23]/ IPU
EDMA, TIMER7
GPMC_CS[7]/ R24 I/O DVDD_GP General-Purpose Input/Output (I/O) 1 [GP1] pin 22
PINCNTL116
EDMA_EVT0/ MC
DSIS: PIN
TIM7_IO/
GP1[22]

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown
resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal
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Table 3-11. GP1 Terminal Functions (continued)

SIGNAL OTHER (2)
TYPE (1) (3) MUXED DESCRIPTION
NAME NO.
SD2_DAT[5]/
SD2, GPMC,
GPMC_A[26]/ IPU
TIMER6
GPMC_A[22]/ P22 I/O DVDD_GP General-Purpose Input/Output (I/O) 1 [GP1] pin 21
PINCNTL115
TIM6_IO/ MC
DSIS: PIN
GP1[21]
SD2_DAT[6]/
SD2, GPMC,
GPMC_A[25]/ IPU
UART2
GPMC_A[21]/ N23 I/O DVDD_GP General-Purpose Input/Output (I/O) 1 [GP1] pin 20
PINCNTL114
UART2_TXD/ MC
DSIS: PIN
GP1[20]
SD2_DAT[7]/
SD2, GPMC,
GPMC_A[24]/ IPU
UART2
GPMC_A[20]/ L25 I/O DVDD_GP General-Purpose Input/Output (I/O) 1 [GP1] pin 19
PINCNTL113
UART2_RXD/ MC
DSIS: PIN
GP1[19]
SPI[1]
SPI[1]_D[1]/ IPU PINCNTL87
AA3 I/O
GP1[18] DVDD DSIS: PIN
MM: MUX1
GPMC_A[23]/ GPMC, SPI[2], General-Purpose Input/Output (I/O) 1 [GP1] pin 18
SPI[2]_SCLK/ IPD HDMI, TIMER5
HDMI_HPDET/ AA26 I/O DVDD_GP PINCNTL112
TIM5_IO/ MC DSIS: PIN
GP1[18] MM: MUX0
SPI[1]
SPI[1]_SCLK/ IPU PINCNTL86
AC3 I/O
GP1[17] DVDD DSIS: PIN
MM: MUX1
GPMC_A[22]/ GPMC, SPI[2], General-Purpose Input/Output (I/O) 1 [GP1] pin 17
SPI[2]_D[1]/ IPU HDMI, TIMER4
HDMI_CEC/ AB27 I/O DVDD_GP PINCNTL111
TIM4_IO/ MC DSIS: PIN
GP1[17] MM: MUX0
SPI[1]
SPI[1]_SCS[0]/ IPU PINCNTL85
AD3 I/O
GP1[16] DVDD DSIS: PIN
MM: MUX1
General-Purpose Input/Output (I/O) 1 [GP1] pin 16
GPMC, SPI[2]
GPMC_A[21]/ IPD
PINCNTL110
SPI[2]_D[0]/ AC28 I/O DVDD_GP
DSIS: PIN
GP1[16] MC
MM: MUX0
SD2
IPU
SD2_CLK/ PINCNTL121
M23 I/O DVDD_GP
GP1[15] DSIS: PIN
MC
MM: MUX1
General-Purpose Input/Output (I/O) 1 [GP1] pin 15
GPMC, SPI[2]
GPMC_A[20]/ IPU
PINCNTL109
SPI[2]_SCS[1]/ AD28 I/O DVDD_GP
DSIS: PIN
GP1[15] MC
MM: MUX0
SD2, GPMC
SD2_DAT[0]/ IPU
PINCNTL120
GPMC_A[4]/ L26 I/O DVDD_GP
DSIS: PIN
GP1[14] MC
MM: MUX1
General-Purpose Input/Output (I/O) 1 [GP1] pin 14
GPMC, TIMER3
GPMC_A[19]/ IPD
PINCNTL108
TIM3_IO/ AC27 I/O DVDD_GP
DSIS: PIN
GP1[14] MC
MM: MUX0

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Table 3-11. GP1 Terminal Functions (continued)

SIGNAL OTHER (2)
TYPE (1) (3) MUXED DESCRIPTION
NAME NO.
SD2_DAT[1]_SDIRQ SD2, GPMC
IPU
/ PINCNTL119
M24 I/O DVDD_GP
GPMC_A[3]/ DSIS: PIN
MC
GP1[13] MM: MUX1
General-Purpose Input/Output (I/O) 1 [GP1] pin 13
GPMC, TIMER2
GPMC_A[18]/ IPD
PINCNTL107
TIM2_IO/ AE28 I/O DVDD_GP
DSIS: PIN
GP1[13] MC
MM: MUX0
VIN[0]A
VIN[0]A_D[1]/ IPD PINCNTL141
AB11 I/O
GP1[12] DVDD DSIS: PIN
MM: MUX1
General-Purpose Input/Output (I/O) 1 [GP1] pin 12
MDIO
IPU
MDIO/ PINCNTL234
P24 I/O DVDD_GP
GP1[12] DSIS: PIN
MC
MM: MUX0
VIN[0]A
VIN[0]A_D[0]/ IPD PINCNTL140
AF9 I/O
GP1[11] DVDD DSIS: PIN
MM: MUX1
General-Purpose Input/Output (I/O) 1 [GP1] pin 11
MDIO
IPU
MDCLK/ PINCNTL233
H28 I/O DVDD_GP
GP1[11] DSIS: PIN
MC
MM: MUX0
General-Purpose Input/Output (I/O) 1 [GP1] pin 10
The ENLVCMOS bit in the MLBP_DAT_IO_CTRL register
should be set to 1 to enable GPIO LVCMOS mode. The
PINCNTL65 ENN bit in the MLBP_DAT_IO_CTRL register should also
IPU
GP1[10] V2 I/O DSIS: PIN be set to 1 to enable the GPIO LVCMOS receiver. The
DVDD_M
MM: MUX1 internal Pullup/Pulldown is always disabled, regardless of
the state of the PULLUDEN bit in the PINCNTL65 register.
An external Pullup/Pulldown can be used to control the
floating state of this pin.
EMAC, TIMER2
EMAC_RMREFCLK/ IPD
PINCNTL232
TIM2_IO/ J27 I/O DVDD_GP General-Purpose Input/Output (I/O) 1 [GP1] pin 10
DSIS: PIN
GP1[10] MC
MM: MUX0
General-Purpose Input/Output (I/O) 1 [GP1] pin 9
The ENLVCMOS bit in the MLBP_DAT_IO_CTRL register
should be set to 1 to enable GPIO LVCMOS mode. The
PINCNTL64 ENP bit in the MLBP_DAT_IO_CTRL register should also
IPD
GP1[9] V1 I/O DSIS: PIN be set to 1 to enable the GPIO LVCMOS receiver. The
DVDD_M
MM: MUX1 internal Pullup/Pulldown is always disabled, regardless of
the state of the PULLUDEN bit in the PINCNTL64 register.
An external Pullup/Pulldown can be used to control the
floating state of this pin.
VIN[0]B, CLKOUT0
VIN[0]B_CLK/
IPD PINCNTL134
CLKOUT0/ AE17 I/O General-Purpose Input/Output (I/O) 1 [GP1] pin 9
DVDD DSIS: PIN
GP1[9]
MM: MUX0
General-Purpose Input/Output (I/O) 1 [GP1] pin 8
The ENLVCMOS bit in the MLBP_DAT_IO_CTRL register
should be set to 1 to enable GPIO LVCMOS mode. The
PINCNTL63 ENN bit in the MLBP_DAT_IO_CTRL register should also
IPU
GP1[8] W2 I/O DSIS: PIN be set to 1 to enable the GPIO LVCMOS receiver. The
DVDD_M
MM: MUX1 internal Pullup/Pulldown is always disabled, regardless of
the state of the PULLUDEN bit in the PINCNTL63 register.
An external Pullup/Pulldown can be used to control the
floating state of this pin.

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Table 3-11. GP1 Terminal Functions (continued)

SIGNAL OTHER (2)
TYPE (1) (3) MUXED DESCRIPTION
NAME NO.
GPMC, SD2
GPMC_CS[4]/ IPU
PINCNTL126
SD2_CMD/ P25 I/O DVDD_GP General-Purpose Input/Output (I/O) 1 [GP1] pin 8
DSIS: PIN
GP1[8] MC
MM: MUX0
General-Purpose Input/Output (I/O) 1 [GP1] pin 7
The ENLVCMOS bit in the MLBP_DAT_IO_CTRL register
should be set to 1 to enable GPIO LVCMOS mode. The
PINCNTL62 ENP bit in the MLBP_DAT_IO_CTRL register should also
IPD
GP1[7] W1 I/O DSIS: PIN be set to 1 to enable the GPIO LVCMOS receiver. The
DVDD_M
MM: MUX1 internal Pullup/Pulldown is always disabled, regardless of
the state of the PULLUDEN bit in the PINCNTL62 register.
An external Pullup/Pulldown can be used to control the
floating state of this pin.
DEVOSC, SPI[1],
DEVOSC_WAKE/
TIMER5
SPI[1]_SCS[1]/ IPU
W6 I/O PINCNTL7 General-Purpose Input/Output (I/O) 1 [GP1] pin 7
TIM5_IO/ DVDD_SD
DSIS: PIN
GP1[7]
MM: MUX0
SPI[0]_SCS[1]/
SD1_SDCD/ SPI[0], SD1, SATA,
SATA_ACT0_LED/ IPU EDMA, TIMER4
AE5 I/O General-Purpose Input/Output (I/O) 1 [GP1] pin 6
EDMA_EVT1/ DVDD PINCNTL80
TIM4_IO/ DSIS: PIN
GP1[6]
UART0_RIN/ UART0, UART3,
UART3_RTS/ IPU UART1
AF4 I/O General-Purpose Input/Output (I/O) 1 [GP1] pin 5
UART1_RXD/ DVDD PINCNTL77
GP1[5] DSIS: PIN
UART0_DTR/ UART0, UART3,
UART3_CTS/ IPU UART1
AG2 I/O General-Purpose Input/Output (I/O) 1 [GP1] pin 4
UART1_TXD/ DVDD PINCNTL76
GP1[4] DSIS: PIN
UART0_DSR/
UART3_TXD/ UART0, UART3,
SPI[0]_SCS[2]/ IPU SPI[0], I2C[2], SD1
AG4 I/O General-Purpose Input/Output (I/O) 1 [GP1] pin 3
I2C[2]_SDA/ DVDD PINCNTL75
SD1_SDWP/ DSIS: PIN
GP1[3]
UART0_DCD/
UART3_RXD/ UART0, UART3,
SPI[0]_SCS[3]/ IPU SPI[0], I2C[2], SD1
AH4 I/O General-Purpose Input/Output (I/O) 1 [GP1] pin 2
I2C[2]_SCL/ DVDD PINCNTL74
SD1_POW/ DSIS: PIN
GP1[2]
DCAN0_RX/ DCAN0, UART2,
UART2_RXD/ IPU I2C[3]
AG6 I/O General-Purpose Input/Output (I/O) 1 [GP1] pin 1
I2C[3]_SCL/ DVDD PINCNTL69
GP1[1] DSIS: PIN
DCAN0_TX/ DCAN0, UART2,
UART2_TXD/ IPU I2C[3]
AH6 I/O General-Purpose Input/Output (I/O) 1 [GP1] pin 0
I2C[3]_SDA/ DVDD PINCNTL68
GP1[0] DSIS: PIN

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Table 3-12. GP2 Terminal Functions

SIGNAL OTHER (2)
TYPE (1) (3) MUXED DESCRIPTION
NAME NO.
GPIO2
Note: General-Purpose Input/Output (I/O) pins can also serve as external interrupt inputs.
VOUT[1]_AVID/
VOUT[1], EMAC[1],
EMAC[1]_MRXER/
VIN[1]A, UART4,
VIN[1]A_CLK/ IPD
Y22 I/O TIMER6 General-Purpose Input/Output (I/O) 2 [GP2] pin 31
UART4_RTS/ DVDD
PINCNTL207
TIM6_IO/
DSIS: PIN
GP2[31]
VOUT[1]_VSYNC/
EMAC[1]_MCRS/ VOUT[1], EMAC[1],
VIN[1]A_FLD/ VIN[1]A, SPI[3],
IPD
VIN[1]A_DE/ AA23 I/O UART3 General-Purpose Input/Output (I/O) 2 [GP2] pin 30
DVDD
SPI[3]_D[0]/ PINCNTL206
UART3_CTS/ DSIS: PIN
GP2[30]
VOUT[1]_HSYNC/
VOUT[1], EMAC[1],
EMAC[1]_MCOL/
VIN[1]A, SPI[3],
VIN[1]A_VSYNC/ IPD
AC24 I/O UART3 General-Purpose Input/Output (I/O) 2 [GP2] pin 29
SPI[3]_D[1]/ DVDD
PINCNTL205
UART3_RTS/
DSIS: PIN
GP2[29]
VOUT[1]_CLK/ VOUT[1], EMAC[1],
EMAC[1]_MTCLK/ IPD VIN[1]A
AE24 I/O General-Purpose Input/Output (I/O) 2 [GP2] pin 28
VIN[1]A_HSYNC/ DVDD PINCNTL204
GP2[28] DSIS: PIN
VOUT[0]
VOUT[0]_R_CR[3]/ IPD
AB9 I/O PINCNTL197 General-Purpose Input/Output (I/O) 2 [GP2] pin 27
GP2[27] DVDD
DSIS: PIN
VOUT[0]_R_CR[2]/ VOUT[0], EMU
IPD
EMU4/ AD9 I/O PINCNTL196 General-Purpose Input/Output (I/O) 2 [GP2] pin 26
DVDD
GP2[26] DSIS: PIN
VOUT[0]
VOUT[0]_G_Y_YC[3]/ IPD
AH15 I/O PINCNTL189 General-Purpose Input/Output (I/O) 2 [GP2] pin 25
GP2[25] DVDD
DSIS: PIN
VOUT[0]_G_Y_YC[2]/ VOUT[0], EMU
IPD
EMU3/ AH7 I/O PINCNTL188 General-Purpose Input/Output (I/O) 2 [GP2] pin 24
DVDD
GP2[24] DSIS: PIN
VOUT[0]
VOUT[0]_B_CB_C[3]/ IPD
AE15 I/O PINCNTL181 General-Purpose Input/Output (I/O) 2 [GP2] pin 23
GP2[23] DVDD
DSIS: PIN
VOUT[0]_B_CB_C[2]/ VOUT[0], EMU
IPD
EMU2/ AG7 I/O PINCNTL180 General-Purpose Input/Output (I/O) 2 [GP2] pin 22
DVDD
GP2[22] DSIS: PIN
VOUT[0]_AVID/
VOUT[0], SPI[3],
VOUT[0]_FLD/
IPD TIMER7
SPI[3]_SCLK/ AA10 I/O General-Purpose Input/Output (I/O) 2 [GP2] pin 21
DVDD PINCNTL179
TIM7_IO/
DSIS: PIN
GP2[21]
VIN[0]AB,
VIN[0]A_D[15]_BD[7]/
DIS CAMERA_I/F
CAM_SHUTTER/ AC14 I/O General-Purpose Input/Output (I/O) 2 [GP2] pin 20
DVDD PINCNTL155
GP2[20]
DSIS: PIN

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown
resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal
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Table 3-12. GP2 Terminal Functions (continued)

SIGNAL OTHER (2)
TYPE (1) (3) MUXED DESCRIPTION
NAME NO.
VIN[0]AB,
VIN[0]A_D[14]_BD[6]/
IPD CAMERA_I/F
CAM_STROBE/ AC12 I/O General-Purpose Input/Output (I/O) 2 [GP2] pin 19
DVDD PINCNTL154
GP2[19]
DSIS: PIN
VIN[0]AB,
VIN[0]A_D[13]_BD[5]/
IPD CAMERA_I/F
CAM_RESET/ AF17 I/O General-Purpose Input/Output (I/O) 2 [GP2] pin 18
DVDD PINCNTL153
GP2[18]
DSIS: PIN
VIN[0]AB,
VIN[0]A_D[12]_BD[4]/
IPD CLKOUT1
CLKOUT1/ AG17 I/O General-Purpose Input/Output (I/O) 2 [GP2] pin 17
DVDD PINCNTL152
GP2[17]
DSIS: PIN
VIN[0]AB,
VIN[0]A_D[11]_BD[3]/
IPD CAMERA_I/F
CAM_WE/ AH17 I/O General-Purpose Input/Output (I/O) 2 [GP2] pin 16
DVDD PINCNTL151
GP2[16]
DSIS: PIN
VIN[0]AB
VIN[0]A_D[10]_BD[2]/ IPD
AH9 I/O PINCNTL150 General-Purpose Input/Output (I/O) 2 [GP2] pin 15
GP2[15] DVDD
DSIS: PIN
VIN[0]AB
VIN[0]A_D[9]_BD[1]/ IPD
AG9 I/O PINCNTL149 General-Purpose Input/Output (I/O) 2 [GP2] pin 14
GP2[14] DVDD
DSIS: PIN
VIN[0]AB
VIN[0]A_D[8]_BD[0]/ IPD
AB15 I/O PINCNTL148 General-Purpose Input/Output (I/O) 2 [GP2] pin 13
GP2[13] DVDD
DSIS: PIN
VIN[0]A
VIN[0]A_D[7]/ IPD
AA11 I/O PINCNTL147 General-Purpose Input/Output (I/O) 2 [GP2] pin 12
GP2[12] DVDD
DSIS: PIN
VIN[0]A
VIN[0]A_D[6]/ IPD
AH16 I/O PINCNTL146 General-Purpose Input/Output (I/O) 2 [GP2] pin 11
GP2[11] DVDD
DSIS: PIN
VIN[0]A
VIN[0]A_D[5]/ IPD
AG16 I/O PINCNTL145 General-Purpose Input/Output (I/O) 2 [GP2] pin 10
GP2[10] DVDD
DSIS: PIN
VIN[0]A
VIN[0]A_D[4]/ IPD
AH8 I/O PINCNTL144 General-Purpose Input/Output (I/O) 2 [GP2] pin 9
GP2[9] DVDD
DSIS: PIN
VIN[0]A
VIN[0]A_D[3]/ IPD
AE12 I/O PINCNTL143 General-Purpose Input/Output (I/O) 2 [GP2] pin 8
GP2[8] DVDD
DSIS: PIN
VIN[0]A
VIN[0]A_D[2]/ IPD
AC9 I/O PINCNTL142 General-Purpose Input/Output (I/O) 2 [GP2] pin 7
GP2[7] DVDD
DSIS: PIN
SD2, GPMC
SD2_DAT[2]_SDRW/ IPU
PINCNTL118
GPMC_A[2]/ K27 I/O DVDD_GP
DSIS: PIN
GP2[6] MC
MM: MUX1
General-Purpose Input/Output (I/O) 2 [GP2] pin 6
GPMC
IPD
GPMC_A[17]/ PINCNTL106
V23 I/O DVDD_GP
GP2[6] DSIS: PIN
MC
MM: MUX0
SD2, GPMC
SD2_DAT[3]/ IPU
PINCNTL117
GPMC_A[1]/ J28 I/O DVDD_GP
DSIS: PIN
GP2[5] MC
MM: MUX1
General-Purpose Input/Output (I/O) 2 [GP2] pin 5
GPMC
IPD
GPMC_A[16]/ PINCNTL105
AD27 I/O DVDD_GP
GP2[5] DSIS: PIN
MC
MM: MUX0

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Table 3-12. GP2 Terminal Functions (continued)

SIGNAL OTHER (2)
TYPE (1) (3) MUXED DESCRIPTION
NAME NO.
VIN[0]A_VSYNC/ VIN[0]A, UART5
IPU
UART5_CTS/ AD20 I/O PINCNTL139 General-Purpose Input/Output (I/O) 2 [GP2] pin 4
DVDD
GP2[4] DSIS: PIN
VIN[0]A_HSYNC/ VIN[0]A, UART5
IPU
UART5_RTS/ AC20 I/O PINCNTL138 General-Purpose Input/Output (I/O) 2 [GP2] pin 3
DVDD
GP2[3] DSIS: PIN
VIN[0]A
VIN[0]A_CLK/ IPD PINCNTL137
AB20 I/O
GP2[2] DVDD DSIS: PIN
MM: MUX1
VOUT[0], General-Purpose Input/Output (I/O) 2 [GP2] pin 2
VOUT[0]_FLD/
CAMERA_I/F,
CAM_PCLK/
IPD GPMC, UART2
GPMC_A[12]/ AF18 I/O
DVDD_C PINCNTL175
UART2_RTS/
DSIS: PIN
GP2[2]
MM: MUX0
VIN[0]A_FLD/
VIN[0]A, VIN[0]B,
VIN[0]B_VSYNC/
IPU UART5, I2C[2]
UART5_RXD/ AA20 I/O General-Purpose Input/Output (I/O) 2 [GP2] pin 1
DVDD PINCNTL136
I2C[2]_SCL/
DSIS: PIN
GP2[1]
VIN[0]A_DE/
VIN[0]A, VIN[0]B,
VIN[0]B_HSYNC/
IPU UART5, I2C[2]
UART5_TXD/ AE21 I/O General-Purpose Input/Output (I/O) 2 [GP2] pin 0
DVDD PINCNTL135
I2C[2]_SDA/
DSIS: PIN
GP2[0]

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Table 3-13. GP3 Terminal Functions

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
GPIO3
Note: General-Purpose Input/Output (I/O) pins can also serve as external interrupt inputs.
CLKIN32,
CLKIN32/
CLKOUT0,
CLKOUT0/ IPD
J7 I/O TIMER3 General-Purpose Input/Output (I/O) 3 [GP3] pin 31.
TIM3_IO/ DVDD
PINCNTL259
GP3[31]
DSIS: PIN
VOUT[1]_B_CB_C[2]/ VOUT[1], GPMC,
GPMC_A[0]/ VIN[1]A, HDMI,
VIN[1]A_D[7]/ IPU SPI[2]
AF28 I/O
HDMI_CEC/ DVDD PINCNTL231
SPI[2]_D[0]/ DSIS: PIN
GP3[30] MM: MUX1 General-Purpose Input/Output (I/O) 3 [GP3] pin 30.
EMAC[0]_MRXD[2]/
EMAC[0], VIN[1]B
EMAC[0]_RGRXD[1]/
IPD PINCNTL242
VIN[1]B_D[7]/ R23 I/O
DVDD_GPMC DSIS: PIN
EMAC[0]_RMTXEN/
MM: MUX0
GP3[30]
EMAC[0]_MRXD[1]/
EMAC[0]_RGRXD[0]/ EMAC[0], VIN[1]B
IPD
VIN[1]B_D[6]/ P23 I/O PINCNTL241 General-Purpose Input/Output (I/O) 3 [GP3] pin 29.
DVDD_GPMC
EMAC[0]_RMTXD[1]/ DSIS: PIN
GP3[29]
EMAC[0]_MRXD[0]/
EMAC[0]_RGTXD[0]/ EMAC[0], VIN[1]B
IPD
VIN[1]B_D[5]/ G28 I/O PINCNTL240 General-Purpose Input/Output (I/O) 3 [GP3] pin 28.
DVDD_GPMC
EMAC[0]_RMTXD[0]/ DSIS: PIN
GP3[28]
EMAC[0]_MRCLK/
EMAC[0]_RGTXC/ EMAC[0], VIN[1]B,
VIN[1]B_D[4]/ IPD SPI[3]
H27 I/O General-Purpose Input/Output (I/O) 3 [GP3] pin 27.
EMAC[0]_RMCRSDV/ DVDD_GPMC PINCNTL239
SPI[3]_SCS[2]/ DSIS: PIN
GP3[27]
EMAC[0]_MRXER/
EMAC[0]_RGTXCTL/ EMAC[0], VIN[1]B
IPD
VIN[1]B_D[3]/ J26 I/O PINCNTL238 General-Purpose Input/Output (I/O) 3 [GP3] pin 26.
DVDD_GPMC
EMAC[0]_RMRXER/ DSIS: PIN
GP3[26]
EMAC[0]_MCRS/
EMAC[0]_RGRXD[2]/ EMAC[0], VIN[1]B
IPD
VIN[1]B_D[2]/ R25 I/O PINCNTL237 General-Purpose Input/Output (I/O) 3 [GP3] pin 25.
DVDD_GPMC
EMAC[0]_RMRXD[1]/ DSIS: PIN
GP3[25]
EMAC[0]_MCOL/
EMAC[0]_RGRXCTL/ EMAC[0], VIN[1]B
IPD
VIN[1]B_D[1]/ L23 I/O PINCNTL236 General-Purpose Input/Output (I/O) 3 [GP3] pin 24.
DVDD_GPMC
EMAC[0]_RMRXD[0]/ DSIS: PIN
GP3[24]
EMAC[0]_MTCLK/
EMAC[0]_RGRXC/ EMAC[0], VIN[1]B,
VIN[1]B_D[0]/ IPD SPI[3], I2C[2]
L24 I/O General-Purpose Input/Output (I/O) 3 [GP3] pin 23.
SPI[3]_SCS[3]/ DVDD_GPMC PINCNTL235
I2C[2]_SDA/ DSIS: PIN
GP3[23]

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown
resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal
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Table 3-13. GP3 Terminal Functions (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
VOUT[1]_R_CR[2]/
VOUT[1], GPMC,
GPMC_A[15]/
VIN[1]A, HDMI,
VIN[1]A_D[23]/ IPD
AE27 I/O SPI[2] General-Purpose Input/Output (I/O) 3 [GP3] pin 22.
HDMI_HPDET/ DVDD
PINCNTL230
SPI[2]_D[1]/
DSIS: PIN
GP3[22]
VOUT[1]_R_CR[3]/
GPMC_A[14]/ VOUT[1], GPMC,
VIN[1]A_D[22]/ VIN[1]A, HDMI,
IPU
HDMI_SDA/ AG28 I/O SPI[2], I2C[2] General-Purpose Input/Output (I/O) 3 [GP3] pin 21.
DVDD
SPI[2]_SCLK/ PINCNTL229
I2C[2]_SDA DSIS: PIN
GP3[21]
VOUT[1]_G_Y_YC[2]/
GPMC_A[13]/ VOUT[1], GPMC,
VIN[1]A_D[21]/ VIN[1]A, HDMI,
IPU
HDMI_SCL/ AF27 I/O SPI[2], I2C[2] General-Purpose Input/Output (I/O) 3 [GP3] pin 20.
DVDD
SPI[2]_SCS[2]/ PINCNTL228
I2C[2]_SCL/ DSIS: PIN
GP3[20]
VOUT[1]_R_CR[9]/ VOUT[1],
EMAC[1]_MTXEN/ EMAC[1], VIN[1]A,
IPD
VIN[1]A_D[20]/ Y24 I/O UART5 General-Purpose Input/Output (I/O) 3 [GP3] pin 19.
DVDD
UART5_TXD/ PINCNTL227
GP3[19] DSIS: PIN
VOUT[1]_R_CR[8]/ VOUT[1],
EMAC[1]_MTXD[7]/ EMAC[1], VIN[1]A,
IPD
VIN[1]A_D[19]/ W23 I/O UART5 General-Purpose Input/Output (I/O) 3 [GP3] pin 18.
DVDD
UART5_RXD/ PINCNTL226
GP3[18] DSIS: PIN
VOUT[1]_R_CR[7]/ VOUT[1],
EMAC[1]_MTXD[6]/ EMAC[1], VIN[1]A,
IPD
VIN[1]A_D[18]/ V22 I/O SPI[3] General-Purpose Input/Output (I/O) 3 [GP3] pin 17.
DVDD
SPI[3]_D[0]/ PINCNTL225
GP3[17] DSIS: PIN
VOUT[1]_R_CR[6]/ VOUT[1],
EMAC[1]_MTXD[5]/ EMAC[1], VIN[1]A,
IPD
VIN[1]A_D[17]/ AA25 I/O SPI[3] General-Purpose Input/Output (I/O) 3 [GP3] pin 16.
DVDD
SPI[3]_D[1]/ PINCNTL224
GP3[16] DSIS: PIN
VOUT[1]_R_CR[5]/ VOUT[1],
EMAC[1]_MTXD[4]/ EMAC[1], VIN[1]A,
IPD
VIN[1]A_D[16]/ AC26 I/O SPI[3] General-Purpose Input/Output (I/O) 3 [GP3] pin 15.
DVDD
SPI[3]_SCLK/ PINCNTL223
GP3[15] DSIS: PIN
VOUT[1]_R_CR[4]/ VOUT[1],
EMAC[1]_MTXD[3]/ EMAC[1], VIN[1]A,
IPD
VIN[1]A_D[15]/ AG27 I/O SPI[3] General-Purpose Input/Output (I/O) 3 [GP3] pin 14.
DVDD
SPI[3]_SCS[1]/ PINCNTL222
GP3[14] DSIS: PIN
VOUT[1]_G_Y_YC[9]/ VOUT[1],
EMAC[1]_MTXD[2]/ IPD EMAC[1], VIN[1]A
AD26 I/O General-Purpose Input/Output (I/O) 3 [GP3] pin 13.
VIN[1]A_D[14]/ DVDD PINCNTL221
GP3[13] DSIS: PIN
VOUT[1]_G_Y_YC[8]/ VOUT[1],
EMAC[1]_MTXD[1]/ IPD EMAC[1], VIN[1]A
AE26 I/O General-Purpose Input/Output (I/O) 3 [GP3] pin 12.
VIN[1]A_D[13]/ DVDD PINCNTL220
GP3[12] DSIS: PIN
VOUT[1]_G_Y_YC[7]/ VOUT[1],
EMAC[1]_MTXD[0]/ IPD EMAC[1], VIN[1]A
AF26 I/O General-Purpose Input/Output (I/O) 3 [GP3] pin 11.
VIN[1]A_D[12]/ DVDD PINCNTL219
GP3[11] DSIS: PIN

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Table 3-13. GP3 Terminal Functions (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
VOUT[1]_G_Y_YC[6]/ VOUT[1],
EMAC[1]_GMTCLK/ IPD EMAC[1], VIN[1]A
AH27 I/O General-Purpose Input/Output (I/O) 3 [GP3] pin 10.
VIN[1]A_D[11]/ DVDD PINCNTL218
GP3[10] DSIS: PIN
VOUT[1]_G_Y_YC[5]/ VOUT[1],
EMAC[1]_MRXDV/ IPD EMAC[1], VIN[1]A
AG26 I/O General-Purpose Input/Output (I/O) 3 [GP3] pin 9.
VIN[1]A_D[10]/ DVDD PINCNTL217
GP3[9] DSIS: PIN
VOUT[1]_G_Y_YC[4]/ VOUT[1],
EMAC[1]_MRXD[7]/ IPD EMAC[1], VIN[1]A
W22 I/O General-Purpose Input/Output (I/O) 3 [GP3] pin 8.
VIN[1]A_D[9]/ DVDD PINCNTL216
GP3[8] DSIS: PIN
VOUT[1]_G_Y_YC[3]/ VOUT[1],
EMAC[1]_MRXD[6]/ IPD EMAC[1], VIN[1]A
Y23 I/O General-Purpose Input/Output (I/O) 3 [GP3] pin 7.
VIN[1]A_D[8]/ DVDD PINCNTL215
GP3[7] DSIS: PIN
VOUT[1]_B_CB_C[9]/ VOUT[1],
EMAC[1]_MRXD[5]/ EMAC[1], VIN[1]A,
IPD
VIN[1]A_D[6]/ AA24 I/O I2C[3] General-Purpose Input/Output (I/O) 3 [GP3] pin 6.
DVDD
I2C[3]_SDA/ PINCNTL214
GP3[6] DSIS: PIN
VOUT[1]_B_CB_C[8]/ VOUT[1],
EMAC[1]_MRXD[4]/ EMAC[1], VIN[1]A,
IPD
VIN[1]A_D[5]/ AH26 I/O I2C[3] General-Purpose Input/Output (I/O) 3 [GP3] pin 5.
DVDD
I2C[3]_SCL/ PINCNTL213
GP3[5] DSIS: PIN
VOUT[1]_B_CB_C[7]/ VOUT[1],
EMAC[1]_MRXD[3]/ EMAC[1], VIN[1]A,
IPD
VIN[1]A_D[4]/ AC25 I/O UART3 General-Purpose Input/Output (I/O) 3 [GP3] pin 4.
DVDD
UART3_TXD/ PINCNTL212
GP3[4] DSIS: PIN
VOUT[1]_B_CB_C[6]/ VOUT[1],
EMAC[1]_MRXD[2]/ EMAC[1], VIN[1]A,
IPD
VIN[1]A_D[3]/ AD25 I/O UART3 General-Purpose Input/Output (I/O) 3 [GP3] pin 3.
DVDD
UART3_RXD/ PINCNTL211
GP3[3] DSIS: PIN
VOUT[1]_B_CB_C[5]/ VOUT[1],
EMAC[1]_MRXD[1]/ EMAC[1], VIN[1]A,
IPD
VIN[1]A_D[2]/ AF25 I/O UART4 General-Purpose Input/Output (I/O) 3 [GP3] pin 2.
DVDD
UART4_TXD/ PINCNTL210
GP3[2] DSIS: PIN
VOUT[1]_B_CB_C[4]/ VOUT[1],
EMAC[1]_MRXD[0]/ EMAC[1], VIN[1]A,
IPD
VIN[1]A_D[1]/ AG25 I/O UART4 General-Purpose Input/Output (I/O) 3 [GP3] pin 1.
DVDD
UART4_RXD/ PINCNTL209
GP3[1] DSIS: PIN
VOUT[1]_B_CB_C[3]/ VOUT[1],
EMAC[1]_MRCLK/ EMAC[1], VIN[1]A,
IPD
VIN[1]A_D[0]/ AH25 I/O UART4 General-Purpose Input/Output (I/O) 2 [GP2] pin 0.
DVDD
UART4_CTS/ PINCNTL208
GP3[0] DSIS: PIN

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3.2.8 GPMC

Table 3-14. GPMC Terminal Functions

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
GPMC_CLK/
GPMC_CS[5]/ GPMC, CLKOUT1,
GPMC_WAIT[1]/ EDMA, TIMER4,
IPU
CLKOUT1/ R26 O GP1 GPMC Clock output
DVDD_GPMCB
EDMA_EVT3/ PINCNTL127
TIM4_IO/ DSIS: 0
GP1[27]
SD2_DAT[4]/
GPMC_A[27]/ SD2, GPMC,
GPMC_A[23]/ EDMA, TIMER7,
IPU
GPMC_CS[7]/ R24 O GP1 GPMC Chip Select 7
DVDD_GPMC
EDMA_EVT0/ PINCNTL116
TIM7_IO/ DSIS: N/A
GP1[22]
GPMC_ADV_ALE/ GPMC, TIMER5,
GPMC_CS[6]/ IPU GP1
M26 O GPMC Chip Select 6
TIM5_IO/ DVDD_GPMCB PINCNTL128
GP1[28] DSIS: N/A
GPMC_CLK/
GPMC_CS[5]/ GPMC, CLKOUT1,
GPMC_WAIT[1]/ EDMA, TIMER4,
IPU
CLKOUT1/ R26 O GP1 GPMC Chip Select 5
DVDD_GPMCB
EDMA_EVT3/ PINCNTL127
TIM4_IO/ DSIS: N/A
GP1[27]
GPMC_CS[4]/ SD2, GP1
IPU
SD2_CMD/ P25 O PINCNTL126 GPMC Chip Select 4
DVDD_GPMC
GP1[8] DSIS: N/A
GPMC_CS[3]/ VIN[1]B, SPI[2],
VIN[1]B_CLK/ IPU GP1
P26 O GPMC Chip Select 3
SPI[2]_SCS[0]/ DVDD_GPMC PINCNTL125
GP1[26] DSIS: N/A
GPMC_CS[2]/ GPMC, GP1
IPU
GPMC_A[24]/ M25 O PINCNTL124 GPMC Chip Select 2
DVDD_GPMC
GP1[25] DSIS: N/A
GPMC_CS[1]/ GPMC, GP1
IPU
GPMC_A[25]/ K28 O PINCNTL123 GPMC Chip Select 1
DVDD_GPMCB
GP1[24] DSIS: N/A
GP1
GPMC_CS[0]/ IPU
T28 O PINCNTL122 GPMC Chip Select 0
GP1[23] DVDD_GPMCB
DSIS: N/A
–
IPU
GPMC_WE U28 O PINCNTL130 GPMC Write Enable output
DVDD_GPMCB
DSIS: N/A
–
IPU
GPMC_OE_RE T27 O PINCNTL129 GPMC Output Enable output
DVDD_GPMCB
DSIS: N/A
GPMC_BE[1]/
GPMC, EDMA,
GPMC_A[24]/
IPD TIMER7, GP1
EDMA_EVT1/ V28 O GPMC Upper Byte Enable output
DVDD_GPMCB PINCNTL132
TIM7_IO/
DSIS: N/A
GP1[30]

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown
resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and the Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal
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Table 3-14. GPMC Terminal Functions (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
GPMC_BE[0]_CLE/
GPMC, EDMA,
GPMC_A[25]/
IPD TIMER6, GP1 GPMC Lower Byte Enable output or Command
EDMA_EVT2/ U27 O
DVDD_GPMCB PINCNTL131 Latch Enable output
TIM6_IO/
DSIS: PIN
GP1[29]
GPMC_ADV_ALE/ GPMC, TIMER5,
GPMC_CS[6]/ IPU GP1 GPMC Address Valid output or Address Latch
M26 O
TIM5_IO/ DVDD_GPMCB PINCNTL128 Enable output
GP1[28] DSIS: N/A
GPMC_CLK/
GPMC_CS[5]/ GPMC, CLKOUT1,
GPMC_WAIT[1]/ EDMA, TIMER4,
IPU
CLKOUT1/ R26 I GP1 GPMC Wait input 1
DVDD_GPMCB
EDMA_EVT3/ PINCNTL127
TIM4_IO/ DSIS: 1
GP1[27]
GPMC_WAIT[0]/ GPMC, EDMA,
GPMC_A[26]/ IPU GP1
W28 I GPMC Wait input 0
EDMA_EVT0/ DVDD_GPMCB PINCNTL133
GP1[31] DSIS: 1
EMAC[0]_MRXD[3]/ EMAC[0],
EMAC[1]_RGRXCTL/ EMAC[1], GPMC,
GPMC_A[27]/ IPD UART5
J25 O
GPMC_A[26]/ DVDD_GPMC PINCNTL243
GPMC_A[0]/ DSIS: N/A
UART5_RXD MM: MUX1
SD2_DAT[4]/ GPMC Address 27
SD2, GPMC,
GPMC_A[27]/
EDMA, TIMER7,
GPMC_A[23]/
IPU GP1
GPMC_CS[7]/ R24 O
DVDD_GPMC PINCNTL116
EDMA_EVT0/
DSIS: N/A
TIM7_IO/
MM: MUX0
GP1[22]
GPMC, EDMA,
GPMC_WAIT[0]/
GP1
GPMC_A[26]/ IPU
W28 O PINCNTL133
EDMA_EVT0/ DVDD_GPMCB
DSIS: N/A
GP1[31]
MM: MUX2
EMAC[0]_MRXD[3]/ EMAC[0],
EMAC[1]_RGRXCTL/ EMAC[1], GPMC,
GPMC_A[27]/ IPD UART5
J25 O GPMC Address 26
GPMC_A[26]/ DVDD_GPMC PINCNTL243
GPMC_A[0]/ DSIS: N/A
UART5_RXD MM: MUX1
SD2_DAT[5]/ SD2, GPMC,
GPMC_A[26]/ TIMER6, GP1
IPU
GPMC_A[22]/ P22 O PINCNTL115
DVDD_GPMC
TIM6_IO/ DSIS: N/A
GP1[21] MM: MUX0

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Table 3-14. GPMC Terminal Functions (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
GPMC_BE[0]_CLE/ GPMC, EDMA,
GPMC_A[25]/ TIMER6, GP1
IPD
EDMA_EVT2/ U27 O PINCNTL131
DVDD_GPMCB
TIM6_IO/ DSIS: N/A
GP1[29] MM: MUX2
GPMC, GP1
GPMC_CS[1]/
IPU PINCNTL123
GPMC_A[25]/ K28 O GPMC Address 25
DVDD_GPMCB DSIS: N/A
GP1[24]
MM: MUX1
SD2_DAT[6]/ SD2, GPMC,
GPMC_A[25]/ UART2, GP1
IPU
GPMC_A[21]/ N23 O PINCNTL114
DVDD_GPMC
UART2_TXD/ DSIS: N/A
GP1[20] MM: MUX0
GPMC_BE[1]/ GPMC, EDMA,
GPMC_A[24]/ TIMER7, GP1
IPD
EDMA_EVT1/ V28 O PINCNTL132
DVDD_GPMCB
TIM7_IO/ DSIS: N/A
GP1[30] MM: MUX2
GPMC, GP1
GPMC_CS[2]/
IPU PINCNTL124
GPMC_A[24]/ M25 O GPMC Address 24
DVDD_GPMC DSIS: N/A
GP1[25]
MM: MUX1
SD2_DAT[7]/ SD2, GPMC,
GPMC_A[24]/ UART2, GP1
IPU
GPMC_A[20]/ L25 O PINCNTL113
DVDD_GPMC
UART2_RXD/ DSIS: N/A
GP1[19] MM: MUX0
SD2_DAT[4]/
SD2, GPMC,
GPMC_A[27]/
EDMA, TIMER5,
GPMC_A[23]/
IPU GP1
GPMC_CS[7]/ R24 O
DVDD_GPMC PINCNTL116
EDMA_EVT0/
DSIS: N/A
TIM7_IO/
MM: MUX1 GPMC Address 23
GP1[22]
GPMC_A[23]/ SPI[2], HDMI,
SPI[2]_SCLK/ TIMER5, GP1
IPD
HDMI_HPDET/ AA26 O PINCNTL112
DVDD_GPMCB
TIM5_IO/ DSIS: N/A
GP1[18] MM: MUX0
SD2_DAT[5]/ SD2, GPMC,
GPMC_A[26]/ TIMER6, GP1
IPU
GPMC_A[22]/ P22 O PINCNTL115
DVDD_GPMC
TIM6_IO/ DSIS: N/A
GP1[21] MM: MUX1
GPMC Address 22
GPMC_A[22]/ SPI[2], HDMI,
SPI[2]_D[1]/ TIMER4, GP1
IPU
HDMI_CEC/ AB27 O PINCNTL111
DVDD_GPMCB
TIM4_IO/ DSIS: N/A
GP1[17] MM: MUX0
SD2_DAT[6]/ SD2, GPMC,
GPMC_A[25]/ UART2, GP1
IPU
GPMC_A[21]/ N23 O PINCNTL114
DVDD_GPMC
UART2_TXD/ DSIS: N/A
GP1[20] MM: MUX1 GPMC Address 21
SPI[2], GP1
GPMC_A[21]/
IPD PINCNTL110
SPI[2]_D[0]/ AC28 O
DVDD_GPMCB DSIS: N/A
GP1[16]
MM: MUX0

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Table 3-14. GPMC Terminal Functions (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
SD2_DAT[7]/ SD2, GPMC,
GPMC_A[24]/ UART2, GP1
IPU
GPMC_A[20]/ L25 O PINCNTL113
DVDD_GPMC
UART2_RXD/ DSIS: N/A
GP1[19] MM: MUX1 GPMC Address 20
SPI[2], GP1
GPMC_A[20]/
IPU PINCNTL109
SPI[2]_SCS[1]/ AD28 O
DVDD_GPMCB DSIS: N/A
GP1[15]
MM: MUX0
GPMC_A[19]/ TIMER2, GP1
IPD
TIM3_IO/ AC27 O PINCNTL108 GPMC Address 19
DVDD_GPMCB
GP1[14] DSIS: N/A
GPMC_A[18]/ TIMER2, GP1
IPD
TIM2_IO/ AE28 O PINCNTL107 GPMC Address 18
DVDD_GPMCB
GP1[13] DSIS: N/A
GP2
GPMC_A[17]/ IPD
V23 O PINCNTL106 GPMC Address 17
GP2[6] DVDD_GPMCB
DSIS: N/A
GP2
GPMC_A[16]/ IPD
AD27 O PINCNTL105 GPMC Address 16
GP2[5] DVDD_GPMCB
DSIS: N/A
VOUT[1]_R_CR[2]/
VOUT[1], VIN[1]A,
GPMC_A[15]/
HDMI, SPI[2],GP3
VIN[1]A_D[23]/ IPD
AE27 O PINCNTL230
HDMI_HPDET/ DVDD
DSIS: N/A
SPI[2]_D[1]/
MM: MUX1
GP3[22] GPMC Address 15
EMAC[0]_MTXEN/ EMAC[0],
EMAC[1]_RGRXD[2]/ EMAC[1], UART1
IPD
EMAC[1]_RMTXEN/ J23 O PINCNTL258
DVDD_GPMC
GPMC_A[15]/ DSIS: N/A
UART1_RTS MM: MUX0
VOUT[1]_R_CR[3]/
VOUT[1], VIN[1]A,
GPMC_A[14]/
HDMI, SPI[2],
VIN[1]A_D[22]/
IPU I2C[2], GP3
HDMI_SDA/ AG28 O
DVDD PINCNTL229
SPI[2]_SCLK/
DSIS: N/A
I2C[2]_SDA/
MM: MUX1 GPMC Address 14
GP3[21]
EMAC[0]_MTXD[7]/ EMAC[0],
EMAC[1]_RGTXD[3]/ EMAC[1], UART1
IPD
EMAC[1]_RMTXD[1]/ H24 O PINCNTL257
DVDD_GPMC
GPMC_A[14]/ DSIS: N/A
UART1_CTS MM: MUX0
VOUT[1]_G_Y_YC[2]/
VOUT[1], VIN[1]A,
GPMC_A[13]/
HDMI, SPI[2],
VIN[1]A_D[21]/
IPU I2C[2], GP3
HDMI_SCL/ AF27 O
DVDD PINCNTL228
SPI[2]_SCS[2]/
DSIS: N/A
I2C[2]_SCL/
MM: MUX1 GPMC Address 13
GP3[20]
EMAC[0]_MTXD[6]/ EMAC[0],
EMAC[1]_RGRXD[0]/ EMAC[1], UART1
IPD
EMAC[1]_RMTXD[0]/ J22 O PINCNTL256
DVDD_GPMC
GPMC_A[13]/ DSIS: N/A
UART1_TXD MM: MUX0

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Table 3-14. GPMC Terminal Functions (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
VOUT[0],
VOUT[0]_FLD/
CAMERA_I/F,
CAM_PCLK/
IPD UART2, GP2
GPMC_A[12]/ AF18 O
DVDD_C PINCNTL175
UART2_RTS/
DSIS: N/A
GP2[2]
MM: MUX1 GPMC Address 12
EMAC[0]_MTXD[5]/ EMAC[0],
EMAC[1]_RGTXC/ EMAC[1], UART1
IPD
EMAC[1]_RMCRSDV/ F27 O PINCNTL255
DVDD_GPMC
GPMC_A[12]/ DSIS: N/A
UART1_RXD MM: MUX0
VOUT[1]_FLD/ VOUT[1],
CAM_FLD/ CAMERA_I/F,
CAM_WE/ IPD UART2, GP0
AB23 O
GPMC_A[11]/ DVDD_C PINCNTL174
UART2_CTS/ DSIS: N/A
GP0[28] MM: MUX1 GPMC Address 11
EMAC[0]_MTXD[4]/ EMAC[0],
EMAC[1]_RGTXD[2]/ EMAC[1], UART4
IPD
EMAC[1]_RMRXER/ G23 O PINCNTL254
DVDD_GPMC
GPMC_A[11]/ DSIS: N/A
UART4_RTS MM: MUX0
VOUT[1],
VOUT[1]_B_CB_C[0]/
CAMERA_I/F,
CAM_VS/
IPU UART2, GP0
GPMC_A[10]/ AD23 O
DVDD_C PINCNTL173
UART2_TXD/
DSIS: N/A
GP0[27]
MM: MUX1 GPMC Address 10
EMAC[0]_MTXD[3]/ EMAC[0],
EMAC[1]_RGTXD[0]/ EMAC[1], UART4
IPD
EMAC[1]_RMRXD[1]/ H23 O PINCNTL253
DVDD_GPMC
GPMC_A[10]/ DSIS: N/A
UART4_CTS MM: MUX0
VOUT[1],
VOUT[1]_B_CB_C[1]/
CAMERA_I/F,
CAM_HS/
IPD UART2, GP0
GPMC_A[9]/ AE23 O
DVDD_C PINCNTL172
UART2_RXD/
DSIS: N/A
GP0[26]
MM: MUX1 GPMC Address 9
EMAC[0]_MTXD[2]/ EMAC[0],
EMAC[1]_RGTXCTL/ EMAC[1], UART4
IPD
EMAC[1]_RMRXD[0]/ H22 O PINCNTL252
DVDD_GPMC
GPMC_A[9]/ DSIS: N/A
UART4_TXD MM: MUX0
VOUT[1],
VOUT[1]_R_CR[0]/
CAMERA_I/F,
CAM_D[0]/
IPD UART4, GP0
GPMC_A[8]/ AA22 O
DVDD_C PINCNTL171
UART4_RTS/
DSIS: N/A
GP0[25]
MM: MUX1 GPMC Address 8
EMAC[0],
EMAC[0]_MTXD[1]/
EMAC[1], UART4
EMAC[1]_RGTXD[1]/ IPD
H25 O PINCNTL251
GPMC_A[8]/ DVDD_GPMC
DSIS: N/A
UART4_RXD
MM: MUX0

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Table 3-14. GPMC Terminal Functions (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
VOUT[1],
VOUT[1]_R_CR[1]/
CAMERA_I/F,
CAM_D[1]/
IPD UART4, GP0
GPMC_A[7]/ AC19 O
DVDD_C PINCNTL170
UART4_CTS/
DSIS: N/A
GP0[24]
MM: MUX1 GPMC Address 7
EMAC[0],
EMAC[0]_MTXD[0]/
EMAC[1], SPI[2]
EMAC[1]_RGRXD[3]/ IPD
J24 O PINCNTL250
GPMC_A[7]/ DVDD_GPMC
DSIS: N/A
SPI[2]_D[0]
MM: MUX0
VOUT[1],
VOUT[1]_G_Y_YC[0]/
CAMERA_I/F,
CAM_D[2]/
IPD UART4, GP0
GPMC_A[6]/ AC18 O
DVDD_C PINCNTL169
UART4_TXD/
DSIS: N/A
GP0[23]
MM: MUX1 GPMC Address 6
EMAC[0],
EMAC[0]_GMTCLK/
EMAC[1], SPI[2]
EMAC[1]_RGRXC/ IPD
K23 O PINCNTL249
GPMC_A[6]/ DVDD_GPMC
DSIS: N/A
SPI[2]_D[1]
MM: MUX0
VOUT[1],
VOUT[1]_G_Y_YC[1]/
CAMERA_I/F,
CAM_D[3]/
IPU UART4, GP0
GPMC_A[5]/ AD18 O
DVDD_C PINCNTL168
UART4_RXD/
DSIS: N/A
GP0[22]
MM: MUX1 GPMC Address 5
EMAC[0],
EMAC[0]_MRXDV/
EMAC[1], SPI[2]
EMAC[1]_RGRXD[1]/ IPD
K22 O PINCNTL248
GPMC_A[5]/ DVDD_GPMC
DSIS: N/A
SPI[2]_SCLK
MM: MUX0
SD2, GP1
SD2_DAT[0]/
IPU PINCNTL120
GPMC_A[4]/ L26 O
DVDD_GPMCB DSIS: N/A
GP1[14]
MM: MUX1
GPMC Address 4
EMAC[0]_MRXD[7]/ EMAC[0], SPI[2]
EMAC[0]_RGTXD[1]/ IPD PINCNTL247
G27 O
GPMC_A[4]/ DVDD_GPMC DSIS: N/A
SPI[2]_SCS[3] MM: MUX0
SD2, GP1
SD2_DAT[1]_ SDIRQ/
IPU PINCNTL119
GPMC_A[3]/ M24 O
DVDD_GPMC DSIS: N/A
GP1[13]
MM: MUX1
GPMC Address 3
EMAC[0]_MRXD[6]/ EMAC[0], UART5
EMAC[0]_RGTXD[2]/ IPD PINCNTL246
F28 O
GPMC_A[3]/ DVDD_GPMC DSIS: N/A
UART5_RTS MM: MUX0
SD2, GP2
SD2_DAT[2]_SDRW/
IPU PINCNTL118
GPMC_A[2]/ K27 O
DVDD_GPMC DSIS: N/A
GP2[6]
MM: MUX1
GPMC Address 2
EMAC[0]_MRXD[5]/ EMAC[0], UART5
EMAC[0]_RGTXD[3]/ IPD PINCNTL245
H26 O
GPMC_A[2]/ DVDD_GPMC DSIS: N/A
UART5_CTS MM: MUX0

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Table 3-14. GPMC Terminal Functions (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
SD2, GP2
SD2_DAT[3]/
IPU PINCNTL117
GPMC_A[1]/ J28 O
DVDD_GPMC DSIS: N/A
GP2[5]
MM: MUX1
GPMC Address 1
EMAC[0]_MRXD[4]/ EMAC[0], UART5
EMAC[0]_RGRXD[3]/ IPD PINCNTL244
T23 O
GPMC_A[1]/ DVDD_GPMC DSIS: N/A
UART5_TXD MM: MUX0
VOUT[1]_B_CB_C[2]/
VOUT[1], VIN[1]A,
GPMC_A[0]/
HDMI, SPI[2], GP3
VIN[1]A_D[7]/ IPU
AF28 O PINCNTL231
HDMI_CEC/ DVDD
DSIS: N/A
SPI[2]_D[0]/
MM: MUX1
GP3[30]
GPMC Address 0
EMAC[0]_MRXD[3]/ EMAC[0],
EMAC[1]_RGRXCTL/ EMAC[1], GPMC,
GPMC_A[27]/ IPD UART5
J25 O
GPMC_A[26]/ DVDD_GPMC PINCNTL243
GPMC_A[0]/ DSIS: N/A
UART5_RXD MM: MUX0

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Table 3-14. GPMC Terminal Functions (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
BTMODE
GPMC_D[15]/ DIS
Y25 I/O PINCNTL104
BTMODE[15] DVDD_GPMCB
DSIS: PIN
BTMODE
GPMC_D[14]/ DIS
V24 I/O PINCNTL103
BTMODE[14] DVDD_GPMCB
DSIS: PIN
BTMODE
GPMC_D[13]/ DIS
U23 I/O PINCNTL102
BTMODE[13] DVDD_GPMCB
DSIS: PIN
BTMODE
GPMC_D[12]/ DIS
U24 I/O PINCNTL101
BTMODE[12] DVDD_GPMCB
DSIS: PIN
BTMODE
GPMC_D[11]/ DIS
AA27 I/O PINCNTL100
BTMODE[11] DVDD_GPMCB
DSIS: PIN
BTMODE
GPMC_D[10]/ DIS
Y26 I/O PINCNTL99
BTMODE[10] DVDD_GPMCB
DSIS: PIN
BTMODE
GPMC_D[9]/ DIS
AB28 I/O PINCNTL98
BTMODE[9] DVDD_GPMCB
DSIS: PIN
BTMODE
GPMC_D[8]/ DIS
Y27 I/O PINCNTL97
BTMODE[8] DVDD_GPMCB
DSIS: PIN
GPMC Multiplexed Data/Address I/Os.
BTMODE
GPMC_D[7]/ DIS
V25 I/O PINCNTL96
BTMODE[7] DVDD_GPMCB
DSIS: PIN
BTMODE
GPMC_D[6]/ DIS
U25 I/O PINCNTL95
BTMODE[6] DVDD_GPMCB
DSIS: PIN
BTMODE
GPMC_D[5]/ DIS
AA28 I/O PINCNTL94
BTMODE[5] DVDD_GPMCB
DSIS: PIN
BTMODE
GPMC_D[4]/ DIS
V26 I/O PINCNTL93
BTMODE[4] DVDD_GPMCB
DSIS: PIN
BTMODE
GPMC_D[3]/ DIS
W27 I/O PINCNTL92
BTMODE[3] DVDD_GPMCB
DSIS: PIN
BTMODE
GPMC_D[2]/ DIS
V27 I/O PINCNTL91
BTMODE[2] DVDD_GPMCB
DSIS: PIN
BTMODE
GPMC_D[1]/ DIS
Y28 I/O PINCNTL90
BTMODE[1] DVDD_GPMCB
DSIS: PIN
BTMODE
GPMC_D[0]/ DIS+
U26 I/O PINCNTL89
BTMODE[0] DVDD_GPMCB
DSIS: PIN

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3.2.9 HDMI

Table 3-15. HDMI Terminal Functions

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
–
HDMI_CLKP AG18 O VDDA_HDMI_ – HDMI Clock Output.
1P8
– When the HDMI PHY is powered down, these pins
HDMI_CLKN AH18 O VDDA_HDMI_ – should be left unconnected.
1P8
–
HDMI_DN2 AH21 O VDDA_HDMI_ – HDMI Data 2 output.
1P8
– When the HDMI PHY is powered down, these pins
HDMI_DP2 AG21 O VDDA_HDMI_ – should be left unconnected.
1P8
–
HDMI_DN1 AH20 O VDDA_HDMI_ – HDMI Data 1 output.
1P8
– When the HDMI PHY is powered down, these pins
HDMI_DP1 AG20 O VDDA_HDMI_ – should be left unconnected.
1P8
–
HDMI_DN0 AH19 O VDDA_HDMI_ – HDMI Data 0 output.
1P8
– When the HDMI PHY is powered down, these pins
HDMI_DP0 AG19 O VDDA_HDMI_ – should be left unconnected.
1P8
VOUT[1]_G_Y_YC[2]/
VOUT[1], GPMC,
GPMC_A[13]/
VIN[1]ASPI[2],
VIN[1]A_D[21]/
IPU I2C[2], GP3
HDMI_SCL/ AF27 I/O
DVDD PINCNTL228
SPI[2]_SCS[2]/
DSIS: 1
I2C[2]_SCL/ HDMI I2C Serial Clock Output
MM: MUX1
GP3[20]
I2C[1]
I2C[1]_SCL/ PINCNTL78
AF24 I/O DVDD
HDMI_SCL DSIS: 1
MM: MUX0
VOUT[1]_R_CR[3]/
VOUT[1], GPMC,
GPMC_A[14]/
VIN[1]ASPI[2],
VIN[1]A_D[22]/
IPU I2C[2], GP3
HDMI_SDA/ AG28 I/O
DVDD PINCNTL229
SPI[2]_SCLK/
DSIS: 1
I2C[2]_SDA/ HDMI I2C Serial Data I/O
MM: MUX1
GP3[21]
I2C[1]
I2C[1]_SDA/ PINCNTL79
AG24 I/O DVDD
HDMI_SDA DSIS: 1
MM: MUX0

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown
resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal
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Table 3-15. HDMI Terminal Functions (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
VOUT[1]_B_CB_C[2]/ VOUT[1], GPMC,
GPMC_A[0]/ VIN[1]A, SPI[2],
VIN[1]A_D[7]/ IPU GP3
AF28 I/O
HDMI_CEC/ DVDD PINCNTL231
SPI[2]_D[0]/ DSIS: 1
GP3[30] MM: MUX1 HDMI Consumer Electronics Control I/O
GPMC_A[22]/ GPMC, SPI[2],
SPI[2]_D[1]/ TIMER4, GP1
IPU
HDMI_CEC/ AB27 I/O PINCNTL111
DVDD_GPMC
TIM4_IO/ DSIS: 1
GP1[17] MM: MUX0
VOUT[1]_R_CR[2]/ VOUT[1], GPMC,
GPMC_A[15]/ VIN[1]ASPI[2],
VIN[1]A_D[23]/ IPD GP3
AE27 I
HDMI_HPDET/ DVDD PINCNTL230
SPI[2]_D[1]/ DSIS: 0
GP3[22] MM: MUX1 HDMI Hot Plug Detect Input. Signals the connection /
removal of an HDMI cable at the connector.
GPMC_A[23]/ GPMC, SPI[2],
SPI[2]_SCLK/ TIMER5, GP1
IPD
HDMI_HPDET/ AA26 I PINCNTL112
DVDD_GPMC
TIM5_IO/ DSIS: 0
GP1[18] MM: MUX0

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3.2.10 I2C

Table 3-16. I2C Terminal Functions

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
I2C[0]
– I2C[0] Clock I/O. For proper device operation,
I2C[0]_SCL AC4 I/O DVDD
PINCNTL263 this pin must be pulled up via external resistor.
– I2C[0] Data I/O. For proper device operation,
I2C[0]_SDA AB6 I/O DVDD
PINCNTL264 this pin must be pulled up via external resistor.
I2C[1]
HDMI I2C[1] Clock I/O. For proper device operation in
I2C[1]_SCL/
AF24 I/O DVDD PINCNTL78 I2C mode, this pin must be pulled up via
HDMI_SCL
DSIS: 1 external resistor.
HDMI I2C[1] Data I/O. For proper device operation in
I2C[1]_SDA/
AG24 I/O DVDD PINCNTL79 I2C mode, this pin must be pulled up via
HDMI_SDA
DSIS: 1 external resistor.
I2C[2]
VIN[0]A_FLD/ VIN[0]A, VIN[0]B,UART5,
VIN[0]B_VSYNC/ GP2
IPU
UART5_RXD/ AA20 I/O PINCNTL136
DVDD
I2C[2]_SCL/ DSIS: 1
GP2[1] MM: MUX3
VOUT[1]_G_Y_YC[2]/
GPMC_A[13]/ VOUT[1], GPMC, VIN[1]A,
VIN[1]A_D[21]/ HDMI, SPI[2], GP3
IPU
HDMI_SCL/ AF27 I/O PINCNTL228
DVDD
SPI[2]_SCS[2]/ DSIS: 1
I2C[2]_SCL/ MM: MUX2 I2C[2] Clock I/O. For proper device operation in
GP3[20] I2C mode, this pin must be pulled up via
external resistor.
VIN[0]A_D[16]/ VIN[0]A, CAM I/F, GP0
CAM_D[8]/ IPU PINCNTL156
AA21 I/O
I2C[2]_SCL/ DVDD_C DSIS: 1
GP0[10] MM: MUX1
UART0_DCD/
UART0, UART3, SPI[0],
UART3_RXD/
SD1, GP1
SPI[0]_SCS[3]/ IPU
AH4 I/O PINCNTL74
I2C[2]_SCL/ DVDD
DSIS: 1
SD1_POW/
MM: MUX0
GP1[2]

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown
resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and the Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal
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Table 3-16. I2C Terminal Functions (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
EMAC[0]_MTCLK/
EMAC[0], VIN[1]B, SPI[3],
EMAC[0]_RGRXC/
GP3
VIN[1]B_D[0]/ IPD
L24 I/O PINCNTL235
SPI[3]_SCS[3]/ DVDD_GPMC
DSIS: 1
I2C[2]_SDA/
MM: MUX3
GP3[23]
VOUT[1]_R_CR[3]/
GPMC_A[14]/ VOUT[1], GPMC, VIN[1]A,
VIN[1]A_D[22]/ HDMI, SPI[2], GP3
IPU
HDMI_SDA/ AG28 I/O PINCNTL229
DVDD
SPI[2]_SCLK/ DSIS: 1
I2C[2]_SDA/ MM: MUX2 I2C[2] Data I/O. For proper device operation in
GP3[21] I2C mode, this pin must be pulled up via
external resistor.
VIN[0]A_DE/ VIN[0]A, VIN[0]B, UART5,
VIN[0]B_HSYNC/ GP2
IPU
UART5_TXD/ AE21 I/O PINCNTL135
DVDD
I2C[2]_SDA/ DSIS: 1
GP2[0] MM: MUX1
UART0_DSR/
UART0, UART3, SPI[0],
UART3_TXD/
SD1, GP1
SPI[0]_SCS[2]/ IPU
AG4 I/O PINCNTL75
I2C[2]_SDA/ DVDD
DSIS: 1
SD1_SDWP/
MM: MUX0
GP1[3]
I2C3
VOUT[1]_B_CB_C[8]/ VOUT[1], EMAC[1],
EMAC[1]_MRXD[4]/ VIN[1]A, GP3
IPD
VIN[1]A_D[5]/ AH26 I/O PINCNTL213
DVDD
I2C[3]_SCL/ DSIS: 1
GP3[5] MM: MUX3
VIN[0]A_D[18]/ VIN[0]A, CAM I/F,
CAM_D[10]/ EMAC[1], GP0
IPU
EMAC[1]_RMRXD[1]/ AF20 I/O PINCNTL158
DVDD_C I2C3 Clock I/O. For proper device operation in
I2C[3]_SCL/ DSIS: 1
GP0[12] MM: MUX2 I2C mode, this pin must be pulled up via
external resistor.
DCAN0_RX/ DCAN0, UART2, GP1
UART2_RXD/ IPU PINCNTL69
AG6 I/O
I2C[3]_SCL/ DVDD DSIS: 1
GP1[1] MM: MUX1
MCA[0]
MCA[0]_AXR[1]/ IPU PINCNTL22
J1 I/O
I2C[3]_SCL DVDD DSIS: 1
MM: MUX0
VOUT[1]_B_CB_C[9]/ VOUT[1], EMAC[1],
EMAC[1]_MRXD[5]/ VIN[1]A, GP3
IPD
VIN[1]A_D[6]/ AA24 I/O PINCNTL214
DVDD
I2C[3]_SDA/ DSIS: 1
GP3[6] MM: MUX3
VIN[0]A_D[19]/ VIN[0]A, CAM I/F,
CAM_D[11]/ EMAC[1], GP0
IPU
EMAC[1]_RMRXD[0]/ AF21 I/O PINCNTL159
DVDD_C I2C3 Data I/O. For proper device operation in
I2C[3]_SDA/ DSIS: 1
GP0[13] MM: MUX2 I2C mode, this pin must be pulled up via
external resistor.
DCAN0_TX/ DCAN0, UART2, GP1
UART2_TXD/ IPU PINCNTL68
AH6 I/O
I2C[3]_SDA/ DVDD DSIS: 1
GP1[0] MM: MUX1
MCA[0]
MCA[0]_AXR[2]/ IPU PINCNTL23
L4 I/O
I2C[3]_SDA DVDD DSIS: 1
MM: MUX0

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3.2.11 McASP

Table 3-17. McASP0 Terminal Functions

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
McASP0
MCA[5]
MCA[0]_ACLKR/ IPD
K2 I/O PINCNTL19 McASP0 Receive Bit Clock I/O
MCA[5]_AXR[2] DVDD
DSIS: 0
MCA[5]
MCA[0]_AFSR/ IPD
K1 I/O PINCNTL20 McASP0 Receive Frame Sync I/O
MCA[5]_AXR[3] DVDD
DSIS: 0
IPD –
MCA[0]_ACLKX R4 I/O McASP0 Transmit Bit Clock I/O
DVDD PINCNTL17
AUD_CLKIN0/ AUD_CLKIN0,
MCA[0]_AXR[7]/ MCA[0], MCA[3],
IPD
MCA[0]_AHCLKX/ L5 I/O USB1 McASP0 Transmit High-Frequency Master Clock I/O
DVDD
MCA[3]_AHCLKX/ PINCNTL14
USB1_DRVVBUS DSIS: PIN
IPD –
MCA[0]_AFSX L3 I/O McASP0 Transmit Frame Sync I/O
DVDD PINCNTL18
AUD_CLKIN2/ AUD_CLKIN2,
MCA[0]_AXR[9]/ MCA[1], MCA[4],
MCA[2]_AHCLKX/ EDMA, TIMER2,
IPD
MCA[5]_AHCLKX/ H1 I/O GP0
DVDD
EDMA_EVT2/ PINCNTL16
TIM3_IO/ DSIS: PIN
GP0[9] MM: MUX1
MCB
MCA[0]_AXR[9]/
IPD PINCNTL30
MCB_CLKX/ M6 I/O
DVDD DSIS: PIN
MCB_CLKR
MM: MUX0
AUD_CLKIN1/ AUD_CLKIN1,
MCA[0]_AXR[8]/ MCA[1], MCA[4],
MCA[1]_AHCLKX/ EDMA, TIMER2,
IPD
MCA[4]_AHCLKX/ R5 I/O GP0
DVDD
EDMA_EVT3/ PINCNTL15
TIM2_IO/ DSIS: PIN McASP0 Transmit/Receive Data I/Os
GP0[8] MM: MUX1
MCB
MCA[0]_AXR[8]/
IPD PINCNTL29
MCB_FSX/ L1 I/O
DVDD DSIS: PIN
MCB_FSR
MM: MUX0
AUD_CLKIN0,
AUD_CLKIN0/
MCA[0], MCA[3],
MCA[0]_AXR[7]/
IPD USB1
MCA[0]_AHCLKX/ L5 I/O
DVDD PINCNTL14
MCA[3]_AHCLKX/
DSIS: PIN
USB1_DRVVBUS
MM: MUX1
MCB
MCA[0]_AXR[7]/ IPD PINCNTL28
L2 I/O
MCB_DX DVDD DSIS: PIN
MM: MUX0

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal
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Table 3-17. McASP0 Terminal Functions (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
MCB
MCA[0]_AXR[6]/ IPD
M4 I/O PINCNTL27
MCB_DR DVDD
DSIS: PIN
MCA[1]
MCA[0]_AXR[5]/ IPD
M3 I/O PINCNTL26
MCA[1]_AXR[9] DVDD
DSIS: PIN
MCA[1]
MCA[0]_AXR[4]/ IPD
R6 I/O PINCNTL25
MCA[1]_AXR[8] DVDD
DSIS: PIN
IPD PINCNTL24 McASP0 Transmit/Receive Data I/Os
MCA[0]_AXR[3]/ M5 I/O
DVDD DSIS: PIN
I2C[3]
MCA[0]_AXR[2]/ IPU
L4 I/O PINCNTL23
I2C[3]_SDA DVDD
DSIS: PIN
I2C[3]
MCA[0]_AXR[1]/ IPU
J1 I/O PINCNTL22
I2C[3]_SCL DVDD
DSIS: PIN
IPD PINCNTL21
MCA[0]_AXR[0] J2 I/O
DVDD DSIS: PIN

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Table 3-18. McASP1 Terminal Functions

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
McASP1
MCA[1]
MCA[1]_ACLKR/ IPD
M1 I/O PINCNTL33 McASP1 Receive Bit Clock I/O
MCA[1]_AXR[4] DVDD
DSIS: 0
MCA[1]
MCA[1]_AFSR/ IPD
M2 I/O PINCNTL34 McASP1 Receive Frame Sync I/O
MCA[1]_AXR[5] DVDD
DSIS: 0
IPD –
MCA[1]_ACLKX U5 I/O McASP1 Transmit Bit Clock I/O
DVDD PINCNTL31
AUD_CLKIN1/
AUD_CLKIN1,
MCA[0]_AXR[8]/
MCA[0], MCA[4],
MCA[1]_AHCLKX/
IPD EDMA, TIMER2,
MCA[4]_AHCLKX/ R5 I/O McASP1 Transmit High-Frequency Master Clock I/O
DVDD GP0
EDMA_EVT3/
PINCNTL15
TIM2_IO/
DSIS: PIN
GP0[8]
IPD –
MCA[1]_AFSX V3 I/O McASP1 Transmit Frame Sync I/O
DVDD PINCNTL32
MCA[3]
MCA[3]_AXR[3]/ IPD PINCNTL50
J6 I/O
MCA[1]_AXR[9]/ DVDD DSIS: PIN
MM: MUX1
MCA[0]
MCA[0]_AXR[5]/ IPD PINCNTL26
M3 I/O
MCA[1]_AXR[9] DVDD DSIS: PIN
MM: MUX0
MCA[3], GP0
MCA[3]_AXR[2]/
IPD PINCNTL49
MCA[1]_AXR[8]/ F2 I/O
DVDD DSIS: PIN
GP0[20]
MM: MUX1
MCA[0]
MCA[0]_AXR[4]/ IPD PINCNTL25
R6 I/O
MCA[1]_AXR[8] DVDD DSIS: PIN
MM: MUX0
MCA[2]_AXR[3]/ MCA[2], TIMER3,
MCA[1]_AXR[7]/ IPD GP0
H2 I/O McASP1 Transmit/Receive Data I/Os
TIM3_IO/ DVDD PINCNTL44
GP0[15] DSIS: PIN
MCA[2]_AXR[2]/ MCA[2], TIMER2,
MCA[1]_AXR[6]/ IPD GP0
V5 I/O
TIM2_IO/ DVDD PINCNTL43
GP0[14] DSIS: PIN
MCA[1]
MCA[1]_AFSR/ IPD
M2 I/O PINCNTL34
MCA[1]_AXR[5] DVDD
DSIS: PIN
MCA[1]
MCA[1]_ACLKR/ IPD
M1 I/O PINCNTL33
MCA[1]_AXR[4] DVDD
DSIS: PIN
MCB
MCA[1]_AXR[3]/ IPD
N6 I/O PINCNTL38
MCB_CLKR DVDD
DSIS: PIN
MCB
MCA[1]_AXR[2]/ IPD
R3 I/O PINCNTL37
MCB_FSR DVDD
DSIS: PIN

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal
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Table 3-18. McASP1 Terminal Functions (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
SD0
MCA[1]_AXR[1]/ IPU
T6 I/O PINCNTL36
SD0_DAT[5]/ DVDD
DSIS: PIN
McASP1 Transmit/Receive Data I/Os
SD0
MCA[1]_AXR[0]/ IPU
V4 I/O PINCNTL35
SD0_DAT[4]/ DVDD
DSIS: PIN

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Table 3-19. McASP2 Terminal Functions

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
McASP2
GP0
MCA[2]_ACLKX/ IPU
U6 I/O PINCNTL39 McASP2 Transmit Bit Clock I/O
GP0[10] DVDD
DSIS: 0
AUD_CLKIN2/
AUD_CLKIN2,
MCA[0]_AXR[9]/
MCA[0], MCA[5],
MCA[2]_AHCLKX/
IPD EDMA, TIMER3,
MCA[5]_AHCLKX/ H1 I/O McASP2 Transmit High-Frequency Master Clock I/O
DVDD GP0
EDMA_EVT2/
PINCNTL16
TIM3_IO/
DSIS: PIN
GP0[9]
GP0
MCA[2]_AFSX/ IPU
AA5 I/O PINCNTL40 McASP2 Transmit Frame Sync I/O
GP0[11] DVDD
DSIS: 0
MCA[2]_AXR[3]/ MCA[1], TIMER3,
MCA[1]_AXR[7]/ IPD GP0
H2 I/O
TIM3_IO/ DVDD PINCNTL44
GP0[15] DSIS: PIN
MCA[2]_AXR[2]/ MCA[1], TIMER2,
MCA[1]_AXR[6]/ IPD GP0
V5 I/O
TIM2_IO/ DVDD PINCNTL43
GP0[14] DSIS: PIN
McASP2 Transmit/Receive Data I/Os
MCA[2]_AXR[1]/
SD0, UART5, GP0
SD0_DAT[7]/ IPU
V6 I/O PINCNTL42
UART5_TXD/ DVDD
DSIS: PIN
GP0[13]
MCA[2]_AXR[0]/
SD0, UART5, GP0
SD0_DAT[6]/ IPU
N2 I/O PINCNTL41
UART5_RXD/ DVDD
DSIS: PIN
GP0[12]
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17,Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

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Table 3-20. McASP3 Terminal Functions

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
McASP3
GP0
MCA[3]_ACLKX/ IPD
G6 I/O PINCNTL45 McASP3 Transmit Bit Clock I/O
GP0[16] DVDD
DSIS: 0
AUD_CLKIN0/
AUD_CLKIN0,
MCA[0]_AXR[7]/
IPD MCA[0], USB1
MCA[0]_AHCLKX/ L5 I/O McASP3 Transmit High-Frequency Master Clock I/O
DVDD PINCNTL14
MCA[3]_AHCLKX/
DSIS: PIN
USB1_DRVVBUS
GP0
MCA[3]_AFSX/ IPD
H4 I/O PINCNTL46 McASP3 Transmit Frame Sync I/O
GP0[17] DVDD
DSIS: 0
MCA[1]
MCA[3]_AXR[3]/ IPD
J6 I/O PINCNTL50
MCA[1]_AXR[9]/ DVDD
DSIS: PIN
MCA[3]_AXR[2]/ MCA[1], GP0
IPD
MCA[1]_AXR[8]/ F2 I/O PINCNTL49
DVDD
GP0[20] DSIS: PIN
McASP3 Transmit/Receive Data I/Os
MCA[3]_AXR[1]/ TIMER5, GP0
IPD
TIM5_IO/ G2 I/O PINCNTL48
DVDD
GP0[19] DSIS: PIN
MCA[3]_AXR[0]/ TIMER4, GP0
IPD
TIM4_IO/ G1 I/O PINCNTL47
DVDD
GP0[18] DSIS: PIN
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull before after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown
resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

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Table 3-21. McASP4 Terminal Functions

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
McASP4
GP0
MCA[4]_ACLKX/ IPD
K7 I/O PINCNTL51 McASP4 Transmit Bit Clock I/O
GP0[21] DVDD
DSIS: 0
AUD_CLKIN1/
AUD_CLKIN1,
MCA[0]_AXR[8]/
MCA[0], MCA[1],
MCA[1]_AHCLKX/
IPD EDMA, TIMER2,
MCA[4]_AHCLKX/ R5 I/O McASP4 Transmit High-Frequency Master Clock I/O
DVDD GP0
EDMA_EVT3/
PINCNTL15
TIM2_IO/
DSIS: PIN
GP0[8]
GP0
MCA[4]_AFSX/ IPD
H3 I/O PINCNTL52 McASP4 Transmit Frame Sync I/O
GP0[22] DVDD
DSIS: 0
MCA[5]_AXR[1]/ MCA[5], TIMER7,
MCA[4]_AXR[3]/ IPD GP0
L6 I/O
TIM7_IO/ DVDD PINCNTL58
GP0[28] DSIS: PIN
MCA[5]_AXR[0]/ MCA[5], GP0
IPD
MCA[4]_AXR[2]/ L7 I/O PINCNTL57
DVDD
GP0[27] DSIS: PIN McASP4 Transmit/Receive Data I/Os
MCA[4]_AXR[1]/ TIMER6, GP0
IPD
TIM6_IO/ J4 I/O PINCNTL54
DVDD
GP0[24] DSIS: PIN
GP0
MCA[4]_AXR[0]/ IPD
H6 I/O PINCNTL53
GP0[23] DVDD
DSIS: PIN
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

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Table 3-22. McASP5 Terminal Functions

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
McASP5
GP0
MCA[5]_ACLKX/ IPD
J3 I/O PINCNTL55 McASP5 Transmit Bit Clock I/O
GP0[25] DVDD
DSIS: 0
AUD_CLKIN2/
AUD_CLKIN2,
MCA[0]_AXR[9]/
MCA[0], MCA[2],
MCA[2]_AHCLKX/
IPD EDMA, TIMER3,
MCA[5]_AHCLKX/ H1 I/O McASP5 Transmit High-Frequency Master Clock I/O
DVDD GP0
EDMA_EVT2/
PINCNTL16
TIM3_IO/
DSIS: PIN
GP0[9]
GP0
MCA[5]_AFSX/ IPD
H5 I/O PINCNTL56 McASP5 Transmit Frame Sync I/O
GP0[26] DVDD
DSIS: 0
MCA[0]
MCA[0]_AFSR/ IPD
K1 I/O PINCNTL20
MCA[5]_AXR[3] DVDD
DSIS: PIN
MCA[0]
MCA[0]_ACLKR/ IPD
K2 I/O PINCNTL19
MCA[5]_AXR[2] DVDD
DSIS: PIN
MCA[5]_AXR[1]/ MCA[4], TIMER7, McASP5 Transmit/Receive Data I/Os
MCA[4]_AXR[3]/ IPD GP0
L6 I/O
TIM7_IO/ DVDD PINCNTL58
GP0[28] DSIS: PIN
MCA[5]_AXR[0]/ MCA[4], GP0
IPD
MCA[4]_AXR[2]/ L7 I/O PINCNTL57
DVDD
GP0[27] DSIS: PIN
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

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3.2.12 McBSP

Table 3-23. McBSP Terminal Functions

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
McBSP
MCA[0], MCB
MCA[0]_AXR[9]/
IPD PINCNTL30
MCB_CLKX/ M6 I/O
DVDD DSIS: PIN
MCB_CLKR
MM: MUX1
McBSP Receive Clock I/O
MCA[1]
MCA[1]_AXR[3]/ IPD PINCNTL38
N6 I/O
MCB_CLKR DVDD DSIS: PIN
MM: MUX0
MCA[0], MCB
MCA[0]_AXR[8]/
IPD PINCNTL29
MCB_FSX/ L1 I/O
DVDD DSIS: PIN
MCB_FSR
MM: MUX1
McBSP Receive Frame Sync I/O
MCA[1], MCB
MCA[1]_AXR[2]/ IPD PINCNTL37
R3 I/O
MCB_FSR DVDD DSIS: PIN
MM: MUX0
MCA[0]
MCA[0]_AXR[6]/ IPD
M4 I/O PINCNTL27 McBSP Receive Data Input
MCB_DR DVDD
DSIS: PIN
MCA[0]_AXR[9]/ MCA[0], MCB
IPD
MCB_CLKX/ M6 I/O PINCNTL30 McBSP Transmit Clock I/O
DVDD
MCB_CLKR DSIS: PIN
MCA[0]_AXR[8]/ MCA[0], MCB
IPD
MCB_FSX/ L1 I/O PINCNTL29 McBSP Transmit Frame Sync I/O
DVDD
MCB_FSR DSIS: PIN
MCA[0]
MCA[0]_AXR[7]/ IPD
L2 I/O PINCNTL28 McBSP Transmit Data Output
MCB_DX DVDD
DSIS: PIN
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

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3.2.13 PCI Express (PCIe)

Table 3-24. PCI Express (PCIe) Terminal Functions

SIGNAL
TYPE (1) OTHER (2) (3)
DESCRIPTION
NAME NO.
PCIE_TXP0 AD2 O PCIE Transmit Data Lane 0.
–
PCIE_TXN0 AD1 O VDDA_PCIE_1P8 When the PCIe SERDES are powered down, these pins should be
left unconnected.
PCIE_RXP0 AC2 I PCIE Receive Data Lane 0.
–
PCIE_RXN0 AC1 I VDDA_PCIE_1P8 When the PCIe SERDES are powered down, these pins should be
left unconnected.
–
SERDES_CLKP AF1 I SERDES_CLK LDO PCIE Serdes Reference Clock Inputs and optional SATA
(internal) Reference Clock Inputs.
Shared between PCI Express and Serial ATA. When PCI Express
– is not used, and these pins are not used as optional SATA
SERDES_CLKN AF2 I SERDES_CLK LDO Reference Clock Inputs, these pins can be left unconnected.
(internal)
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown
resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

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3.2.14 Reset, Interrupts, and JTAG Interface

Table 3-25. RESET, Interrupts, and JTAG Terminal Functions

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
RESET
IPU –
RESET J5 I Device Reset input
DVDD PINCNTL260
–
POR F1 I – Power-On Reset input
DVDD
Reset output (RSTOUT) or watchdog out (WD_OUT)
DIS –
RSTOUT_WD_OUT K6 O
DVDD PINCNTL262 For more detailed information on RSTOUT_WD_OUT pin
behavior, see Section 7.3.14, RSTOUT_WD_OUT Pin.
INTERRUPTS
IPU –
NMI H7 I Non-Maskable Interrupt input
DVDD PINCNTL261
Interrupt-capable general-purpose I/Os.
see see see NOTE: All pins are multiplexed with other pin functions.
GP0[31:0] I/O
Table 3-10 NOTE Table 3-10 See Table 3-10, GP0 Terminal Functions table for muxing
and internal pullup/pulldown/disable details.
Interrupt-capable general-purpose I/Os.
see see see NOTE: All pins are multiplexed with other pin functions.
GP1[31:0] I/O
Table 3-11 NOTE Table 3-11 See Table 3-11, GP1 Terminal Functions table for muxing
and internal pullup/pulldown/disable details.
Interrupt-capable general-purpose I/Os.
see see see NOTE: All pins are multiplexed with other pin functions.
GP2[31:0] I/O
Table 3-12 NOTE Table 3-12 See Table 3-12, GP2 Terminal Functions table for muxing
and internal pullup/pulldown/disable details.
Interrupt-capable general-purpose I/Os.
see see see NOTE: All pins are multiplexed with other pin functions.
GP3[31:0] I/O
Table 3-13 NOTE Table 3-13 See Table 3-13, GP3 Terminal Functions table for muxing
and internal pullup/pulldown/disable details.
JTAG
IPU
TCLK W7 I – JTAG test clock input
DVDD
JTAG return clock output
IPU/DIS The internal pullup (IPU) is enabled for this pin when the
RTCK AD4 O –
DVDD device is in reset and the IPU is disabled (DIS) when reset
is released.
IPU
TDI Y7 I – JTAG test data input
DVDD
IPU
TDO AC5 O – JTAG test port data output
DVDD
IPU JTAG test port mode select input. For proper operation, do
TMS AA7 I –
DVDD not oppose the IPU on this pin.
IPD
TRST AA4 I – JTAG test port reset input
DVDD
VOUT[0],
VOUT[0]_R_CR[2]/
IPD GP2
EMU4/ AD9 I/O Emulator pin 4
DVDD PINCNTL196
GP2[26]
DSIS: PIN
VOUT[0],
VOUT[0]_G_Y_YC[2]/
IPD GP2
EMU3/ AH7 I/O Emulator pin 3
DVDD PINCNTL188
GP2[24]
DSIS: PIN
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal
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Table 3-25. RESET, Interrupts, and JTAG Terminal Functions (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
VOUT[0],
VOUT[0]_B_CB_C[2]/
IPD GP0
EMU2/ AG7 I/O Emulator pin 2
DVDD PINCNTL180
GP2[22]
DSIS: PIN
IPU
EMU1 AE11 I/O – Emulator pin 1
DVDD
IPU
EMU0 AG8 I/O – Emulator pin 0
DVDD

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3.2.15 Serial ATA (SATA) Signals

Table 3-26. Serial ATA (SATA) Terminal Functions

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
– Serial ATA Data Transmit.
SATA_TXN0 AB1 O –
VDDA_SATA_1P8
– When the SATA SERDES are powered down, these
SATA_TXP0 AB2 O – pins should be left unconnected.
VDDA_SATA_1P8
– Serial ATA Data Receive.
SATA_RXN0 AA2 I –
VDDA_SATA_1P8
– When the SATA SERDES are powered down, these
SATA_RXP0 AA1 I – pins should be left unconnected.
VDDA_SATA_1P8
SPI[0]_SCS[1]/
SPI[0], SD1,
SD1_SDCD/
EDMA, TIMER 4,
SATA_ACT0_LED/ IPU
AE5 O GP1 Serial ATA disk 0 Activity LED output
EDMA_EVT1/ DVDD
PINCNTL80
TIM4_IO/
DSIS: N/A
GP1[6]
– PCIE Serdes Reference Clock Inputs and optional
SERDES_CLKP AF1 I SERDES_CLK – SATA Reference Clock Inputs.
LDO (internal) Shared between PCI Express and Serial ATA. When
– PCI Express is not used, and these pins are not used
SERDES_CLKN AF2 I SERDES_CLK – as optional SATA Reference Clock Inputs, these pins
LDO (internal) should be left unconnected.

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

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3.2.16 SD Signals (MMC/SD/SDIO)

Table 3-27. SD0 Terminal Functions

SIGNAL OTHER (2)
TYPE (1) (3) MUXED DESCRIPTION
NAME NO.
GP0
SD0_CLK/ IPU
Y6 O PINCNTL8 SD0 Clock output
GP0[1] DVDD_SD
DSIS: 1
SD0_CMD/ SD1, GP0
IPU
SD1_CMD/ N1 I/O PINCNTL9 SD0 Command input/output
DVDD_SD
GP0[2] DSIS: 1
SD0_DAT[0]/ SD1, GP0
IPU SD0 Data0 I/O. Functions as data bit 0 for 4-/8-bit SD mode
SD1_DAT[4]/ R7 I/O PINCNTL10
DVDD_SD and single data bit for 1-bit SD mode.
GP0[3] DSIS: PIN
SD0_DAT[1]_SDIRQ/ SD1, GP0
IPU SD0 Data1 I/O. Functions as data bit 1 for 4-/8-bit SD mode
SD1_DAT[5]/ Y5 I/O PINCNTL11
DVDD_SD and as an IRQ input for 1-bit SD mode.
GP0[4] DSIS: PIN
SD0_DAT[2]_SDRW/ SD1, GP0
IPU SD0 Data2 I/O. Functions as data bit 2 for 4-/8-bit SD mode
SD1_DAT[6]/ Y3 I/O PINCNTL12
DVDD_SD and as a Read Wait input for 1-bit SD mode.
GP0[5] DSIS: PIN
SD0_DAT[3]/ SD1, GP0
IPU
SD1_DAT[7]/ Y4 I/O PINCNTL13 SD0 Data3 I/O. Functions as data bit 3 for 4-/8-bit SD mode.
DVDD_SD
GP0[6] DSIS: PIN
MCA[1]
MCA[1]_AXR[0]/ IPU
V4 I/O PINCNTL35 SD0 Data4 I/O. Functions as data bit 4 for 8-bit SD mode.
SD0_DAT[4]/ DVDD
DSIS: PIN
MCA[1], SC0
MCA[1]_AXR[1]/ IPU
T6 I/O PINCNTL36 SD0 Data5 I/O. Functions as data bit 5 for 8-bit SD mode.
SD0_DAT[5]/ DVDD
DSIS: PIN
MCA[2]_AXR[0]/ MCA[2], UART5,
SD0_DAT[6]/ IPU GP0
N2 I/O SD0 Data6 I/O. Functions as data bit 6 for 8-bit SD mode.
UART5_RXD/ DVDD PINCNTL41
GP0[12] DSIS: PIN
MCA[2]_AXR[1]/ MCA[2], UART5,
SD0_DAT[7]/ IPU GP0
V6 I/O SD0 Data7 I/O. Functions as data bit 7 for 8-bit SD mode.
UART5_TXD/ DVDD PINCNTL42
GP0[13] DSIS: PIN
UART0_CTS/
UART0, UART4,
UART4_RXD/
IPD DCAN1, SPI[1]
DCAN1_TX/ AE6 I SD0 Card Detect input
DVDD PINCNTL72
SPI[1]_SCS[3]/
DSIS: 1
SD0_SDCD
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown
resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

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Table 3-28. SD1 Terminal Functions

SIGNAL OTHER (2)
TYPE (1) (3) MUXED DESCRIPTION
NAME NO.
–
IPU
SD1_CLK P3 O PINCNTL1 SD1 Clock output
DVDD_SD
DSIS: N/A
SD0, GP0
SD0_CMD/
IPU PINCNTL9
SD1_CMD/ N1 I/O
DVDD_SD DSIS: N/A
GP0[2]
MM: MUX1
SD1 Command input/output
GP1
SD1_CMD/ IPU PINCNTL2
P2 I/O
GP0[0] DVDD_SD DSIS: N/A
MM: MUX0
IPU – SD1 Data0 I/O. Functions as data bit 0 for 4-/8-bit SD mode
SD1_DAT[0] P1 I/O
DVDD_SD PINCNTL3 and single data bit for 1-bit SD mode.
IPU – SD1 Data1 I/O. Functions as data bit 1 for 4-/8-bit SD mode
SD1_DAT[1]_SDIRQ P5 I/O
DVDD_SD PINCNTL4 and as an IRQ input for 1-bit SD mode.
IPU – SD1 Data2 I/O. Functions as data bit 2 for 4-/8-bit SD mode
SD1_DAT[2]_SDRW P4 I/O
DVDD_SD PINCNTL5 and as a Read Wait input for 1-bit SD mode.
IPU –
SD1_DAT[3] P6 I/O SD1 Data3 I/O. Functions as data bit 3 for 4-/8-bit SD mode.
DVDD_SD PINCNTL6
SD0_DAT[0]/ SD0, GP0
IPU
SD1_DAT[4]/ R7 I/O PINCNTL10 SD1 Data4 I/O. Functions as data bit 4 for 8-bit SD mode.
DVDD_SD
GP0[3] DSIS: PIN
SD0_DAT[1]_SDIRQ/ SD0, GP0
IPU
SD1_DAT[5]/ Y5 I/O PINCNTL11 SD1 Data5 I/O. Functions as data bit 5 for 8-bit SD mode.
DVDD_SD
GP0[4] DSIS: PIN
SD0_DAT[2]_SDRW/ SD0, GP0
IPU
SD1_DAT[6]/ Y3 I/O PINCNTL12 SD1 Data6 I/O. Functions as data bit 6 for 8-bit SD mode.
DVDD_SD
GP0[5] DSIS: PIN
SD0_DAT[3]/ SD0, GP0
IPU
SD1_DAT[7]/ Y4 I/O PINCNTL13 SD1 Data7 I/O. Functions as data bit 7 for 8-bit SD mode.
DVDD_SD
GP0[6] DSIS: PIN
UART0_DCD/
UART3_RXD/ UART0, UART3,
SPI[0]_SCS[3]/ IPU SPI[0], I2C[2], GP1
AH4 O SD1 Card Power Enable output
I2C[2]_SCL/ DVDD PINCNTL74
SD1_POW/ DSIS: PIN
GP1[2]
SPI[0]_SCS[1]/
SD1_SDCD/ SPI[0], SATA,
SATA_ACT0_LED/ IPU EDMA, TIM4, GP1
AE5 I SD1 Card Detect input
EDMA_EVT1/ DVDD PINCNTL80
TIM4_IO/ DSIS: 1
GP1[6]
UART0_DSR/
UART3_TXD/ UART0, UART3,
SPI[0]_SCS[2]/ IPU SPI[0], I2C[2], GP1
AG4 I SD1 Card Write Protect input
I2C[2]_SDA/ DVDD PINCNTL75
SD1_SDWP/ DSIS: 0
GP1[3]
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown
resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

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Table 3-29. SD2 Terminal Functions

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
GP1
SD2_SCLK/ IPU
M23 O PINCNTL121 SD2 Clock output
GP1[15] DVDD_GPMC
DSIS: N/A
GPMC_CS[4]/ GPMC, GP1
IPU
SD2_CMD/ P25 I/O PINCNTL126 SD2 Command input/output
DVDD_GPMC
GP1[8] DSIS: N/A
SD2_DAT[0]/ GPMC, GP1
IPU SD2 Data0 I/O. Functions as data bit 0 for 4-/8-bit SD
GPMC_A[4]/ L26 I/O PINCNTL120
DVDD_GPMC mode and single data bit for 1-bit SD mode.
GP1[14] DSIS: PIN
SD2_DAT[1]_SDIRQ/ GMPC, GP1
IPU SD2 Data1 I/O. Functions as data bit 1 for 4-/8-bit SD
GPMC_A[3]/ M24 I/O PINCNTL119
DVDD_GPMC mode and as an IRQ input for 1-bit SD mode
GP1[13] DSIS: PIN
SD2_DAT[2]_SDRW/ GPMC, GP2
IPU SD2 Data2 I/O. Functions as data bit 2 for 4-/8-bit SD
GPMC_A[2]/ K27 I/O PINCNTL118
DVDD_GPMC mode and as a Read Wait input for 1-bit SD mode.
GP2[6] DSIS: PIN
SD2_DAT[3]/ GPMC, GP2
IPU SD2 Data3 I/O. Functions as data bit 3 for 4-/8-bit SD
GPMC_A[1]/ J28 I/O PINCNTL117
DVDD_GPMC mode.
GP2[5] DSIS: PIN
SD2_DAT[4]/
GPMC_A[27]/
GPMC, EDMA,
GPMC_A[23]/
IPU TIM7, GP1
GPMC_CS[7]/ R24 I/O SD2 Data4 I/O. Functions as data bit 4 for 8-bit SD mode.
DVDD_GPMC PINCNTL116
EDMA_EVT0/
DSIS: PIN
TIM7_IO/
GP1[22]
SD2_DAT[5]/
GPMC, TIM6,
GPMC_A[26]/
IPU GP1
GPMC_A[22]/ P22 I/O SD2 Data5 I/O. Functions as data bit 5 for 8-bit SD mode.
DVDD_GPMC PINCNTL115
TIM6_IO/
DSIS: PIN
GP1[21]
SD2_DAT[6]/
GPMC, UART2,
GPMC_A[25]/
IPU GP1
GPMC_A[21]/ N23 I/O SD2 Data6 I/O. Functions as data bit 6 for 8-bit SD mode.
DVDD_GPMC PINCNTL114
UART2_TXD/
DSIS: PIN
GP1[20]
SD2_DAT[7]/
GPMC, UART2,
GPMC_A[24]/
IPU GP1
GPMC_A[20]/ L25 I/O SD2 Data7 I/O. Functions as data bit 7 for 8-bit SD mode.
DVDD_GPMC PINCNTL113
UART2_RXD/
DSIS: PIN
GP1[19]
UART0_RTS/
UART0, UART4,
UART4_TXD/
IPD DCAN1, SPI[1]
DCAN1_RX/ AF5 I SD2 Card Detect input.
DVDD PINCNTL73
SPI[1]_SCS[2]/
DSIS: 1
SD2_SDCD
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

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3.2.17 SPI

Table 3-30. SPI 0 Terminal Functions

SIGNAL OTHER (2)
TYPE (1) (3) MUXED DESCRIPTION
NAME NO.
IPU –
SPI[0]_SCLK AC7 I/O SPI Clock I/O
DVDD PINCNTL82
UART0_DCD/
UART3_RXD/ UART0, UART3,
SPI[0]_SCS[3]/ IPU I2C[2], SD1, GP1
AH4 I/O
I2C[2]_SCL/ DVDD PINCNTL74
SD1_POW/ DSIS: PIN
GP1[2]
UART0_DSR/
UART3_TXD/ UART0, UART3,
SPI[0]_SCS[2]/ IPU I2C[2], SD1, GP1
AG4 I/O
I2C[2]_SDA/ DVDD PINCNTL75
SD1_SDWP/ DSIS: PIN SPI Chip Select I/O
GP1[3]
SPI[0]_SCS[1]/
SD1, SATA,
SD1_SDCD/
EDMA, TIMER4,
SATA_ACT0_LED/ IPU
AE5 I/O GP1
EDMA_EVT1/ DVDD
PINCNTL80
TIM4_IO/
DSIS: PIN
GP1[6]
IPU –
SPI[0]_SCS[0] AD6 I/O
DVDD PINCNTL81
IPU –
SPI[0]_D[1] AF3 I/O
DVDD PINCNTL83
SPI Data I/O. Can be configured as either MISO or MOSI
IPU –
SPI[0]_D[0] AE3 I/O
DVDD PINCNTL84
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

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Table 3-31. SPI 1 Terminal Functions

SIGNAL OTHER (2)
TYPE (1) (3) MUXED DESCRIPTION
NAME NO.
GP1
SPI[1]_SCLK/ IPU
AC3 I/O PINCNTL86 SPI Clock I/O
GP1[17] DVDD
DSIS: PIN
UART0_CTS/
UART0, UART4,
UART4_RXD/
IPU DCAN1, SD0
DCAN1_TX/ AE6 I/O
DVDD PINCNTL72
SPI[1]_SCS[3]/
DSIS: PIN
SD0_SDCD
UART0_RTS/
UART0, UART4,
UART4_TXD/
IPU DCAN1, SD2
DCAN1_RX/ AF5 I/O
DVDD PINCNTL73
SPI[1]_SCS[2]/ SPI Chip Select I/O
DSIS: PIN
SD2_SDCD
DEVOSC_WAKE/ DEVOSC,
SPI[1]_SCS[1]/ IPU TIMER5, GP1
W6 I/O
TIM5_IO/ DVDD_SD PINCNTL7
GP1[7] DSIS: PIN
GP1
SPI[1]_SCS[0]/ IPU
AD3 I/O PINCNTL85
GP1[16] DVDD
DSIS: PIN
GP1
SPI[1]_D[1]/ IPU
AA3 I/O PINCNTL87
GP1[18] DVDD
DSIS: PIN
SPI Data I/O. Can be configured as either MISO or MOSI
GP1
SPI[1]_D[0]/ IPU
AA6 I/O PINCNTL88
GP1[26] DVDD
DSIS: PIN
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

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Table 3-32. SPI 2 Terminal Functions

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
EMAC[0],
EMAC[0]_MRXDV/
EMAC[1], GPMC
EMAC[1]_RGRXD[1]/ IPD
K22 I/O PINCNTL248
GPMC_A[5]/ DVDD_GPMC
DSIS: 1
SPI[2]_SCLK
MM: MUX2
VOUT[1]_R_CR[3]/
VOUT[1], GPMC,
GPMC_A[14]/
VIN[1]A, HDMI,
VIN[1]A_D[22]/
IPU I2C[2], GP3
HDMI_SDA/ AG28 I/O SPI Clock I/O
DVDD PINCNTL229
SPI[2]_SCLK/
DSIS: 1
I2C[2]_SDA/
MM: MUX1
GP3[21]
GPMC_A[23]/ GPMC, HDMI,
SPI[2]_SCLK/ TIMER5, GP1
IPD
HDMI_HPDET/ AA26 I/O PINCNTL112
DVDD_GPMC
TIM5_IO/ DSIS: 1
GP1[18] MM: MUX0
EMAC[0]_MRXD[7]/
EMAC[0], GPMC
EMAC[0]_RGTXD[1]/ IPD
G27 I/O PINCNTL247
GPMC_A[4]/ DVDD_GPMC
DSIS: 1
SPI[2]_SCS[3]/
VOUT[1]_G_Y_YC[2]/
GPMC_A[13]/ VOUT[1].
VIN[1]A_D[21]/ VIN[1]A, HDMI,
IPU
HDMI_SCL/ AF27 I/O I2C[2], GP3
DVDD
SPI[2]_SCS[2]/ PINCNTL228
I2C[2]_SCL/ DSIS: 1 SPI Chip Select I/O
GP3[20]
GPMC_A[20]/ GPMC, GP1
IPU
SPI[2]_SCS[1]/ AD28 I/O PINCNTL109
DVDD_GPMC
GP1[15] DSIS: 1
GPMC_CS[3]/ GPMC, VIN[1]B,
VIN[1]B_CLK/ IPU GP1
P26 I/O
SPI[2]_SCS[0]/ DVDD_GPMC PINCNTL125
GP1[26] DSIS: 1

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal
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Table 3-32. SPI 2 Terminal Functions (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
EMAC[0],
EMAC[0]_GMTCLK/
EMAC[1], GPMC
EMAC[1]_RGRXC/ IPD
K23 I/O PINCNTL249
GPMC_A[6]/ DVDD_GPMC
DSIS: PIN
SPI[2]_D[1]
MM: MUX2
VOUT[1]_R_CR[2]/ VOUT[1], GPMC,
GPMC_A[15]/ VIN[1]A, HDMI,
VIN[1]A_D[23]/ IPD GP3
AE27 I/O
HDMI_HPDET/ DVDD PINCNTL230
SPI[2]_D[1]/ DSIS: PIN
GP3[22] MM: MUX1
GPMC_A[22]/ GPMC, HDMI,
SPI[2]_D[1]/ TIMER 4, GP1
IPU
HDMI_CEC/ AB27 I/O PINCNTL111
DVDD_GPMC
TIM4_IO/ DSIS: PIN
GP1[17] MM: MUX0 SPI Data I/O. Can be configured as either MISO or MOSI
EMAC[0],
EMAC[0]_MTXD[0]/
EMAC[1], GPMC
EMAC[1]_RGRXD[3]/ IPD
J24 I/O PINCNTL250
GPMC_A[7]/ DVDD_GPMC
DSIS: PIN
SPI[2]_D[0]
MM: MUX2
VOUT[1]_B_CB_C[2]/ VOUT[1], GPMC,
GPMC_A[0]/ VIN[1]A, HDMI,
VIN[1]A_D[7]/ IPU GP3
AF28 I/O
HDMI_CEC/ DVDD PINCNTL231
SPI[2]_D[0]/ DSIS: PIN
GP3[30] MM: MUX1
GPMC, GP1
GPMC_A[21]/
IPD PINCNTL110
SPI[2]_D[0]/ AC28 I/O
DVDD_GPMC DSIS: PIN
GP1[16]
MM: MUX0

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Table 3-33. SPI 3 Terminal Functions

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
VOUT[0]_AVID/ VOUT[0], TIMER
VOUT[0]_FLD/ 7, GP2
IPD
SPI[3]_SCLK/ AA10 I/O PINCNTL179
DVDD
TIM7_IO/ DSIS: 1
GP2[21] MM: MUX2
VOUT[0],
VOUT[1]_R_CR[5]/
EMAC[1],
EMAC[1]_MTXD[4]/
IPD VIN[1]A, GP3
VIN[1]A_D[16]/ AC26 I/O
DVDD PINCNTL223 SPI Clock I/O
SPI[3]_SCLK/
DSIS: 1
GP3[15]
MM: MUX1
VIN[0]A,
VIN[0]A_D[21]/
CAMERA_I/F,
CAM_D[13]/
IPD EMAC[1], GP0
EMAC[1]_RMTXD[0]/ AE18 I/O
DVDD_C PINCNTL161
SPI[3]_SCLK/
DSIS: 1
GP0[15]
MM: MUX0
EMAC[0]_MTCLK/
EMAC[0],
EMAC[0]_RGRXC/
VIN[1]B, I2C[2],
VIN[1]B_D[0]/ IPD
L24 I/O GP3
SPI[3]_SCS[3]/ DVDD
PINCNTL235
I2C[2]_SDA/
DSIS: 1
GP3[23]
EMAC[0]_MRCLK/
EMAC[0]_RGTXC/ EMAC[0],
VIN[1]B_D[4]/ IPD VIN[1]B, GP3
H27 I/O
EMAC[0]_RMCRSDV/ DVDD_GPMC PINCNTL239
SPI[3]_SCS[2]/ DSIS: 1
GP3[27] SPI Chip Select I/O
VOUT[1]_R_CR[4]/ VOUT[1].
EMAC[1]_MTXD[3]/ EMAC[1],
IPD
VIN[1]A_D[15]/ AG27 I/O VIN[1]A, GP3
DVDD
SPI[3]_SCS[1]/ PINCNTL222
GP3[14] DSIS: 1
VIN[0]A,
VIN[0]A_D[20]/
CAMERA,_I/F,
CAM_D[12]/
IPD EMAC[1]_RM,
EMAC[1]_RMCRSDV/ AC17 I/O
DVDD_C GP0
SPI[3]_SCS[0]/
PINCNTL160
GP0[14]
DSIS: 1

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal
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Table 3-33. SPI 3 Terminal Functions (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
VOUT[1],
VOUT[1]_HSYNC/
EMAC[1],
EMAC[1]_MCOL/
VIN[1]A, UART3,
VIN[1]A_VSYNC/ IPD
AC24 I/O GP2
SPI[3]_D[1]/ DVDD
PINCNTL205
UART3_RTS/
DSIS: PIN
GP2[29]
MM: MUX2
VOUT[1],
VOUT[1]_R_CR[6]/
EMAC[1],
EMAC[1]_MTXD[5]/
IPD VIN[1]A, GP3
VIN[1]A_D[17]/ AA25 I/O
DVDD PINCNTL224
SPI[3]_D[1]/
DSIS: PIN
GP3[16]
MM: MUX1
VIN[0]A,
VIN[0]A_D[22]/ CAMERA_I/F,
CAM_D[14]/ EMAC[1]_RM,
IPD
EMAC[1]_RMTXD[1]/ AC21 I/O GP0
DVDD_C
SPI[3]_D[1]/ PINCNTL162
GP0[16] DSIS: PIN
MM: MUX0 SPI Data I/O. Can be configured as either MISO or MOSI
VOUT[1]_VSYNC/ VOUT[1],
EMAC[1]_MCRS/ EMAC[1],
VIN[1]A_FLD/ VIN[1]A, UART3,
IPD
VIN[1]A_DE/ AA23 I/O GP2
DVDD
SPI[3]_D[0]/ PINCNTL206
UART3_CTS/ DSIS: PIN
GP2[30] MM: MUX2
VOUT[1],
VOUT[1]_R_CR[7]/
EMAC[1],
EMAC[1]_MTXD[6]/
IPD VIN[1]A, GP3
VIN[1]A_D[18]/ V22 I/O
DVDD PINCNTL225
SPI[3]_D[0]/
DSIS: PIN
GP3[17]
MM: MUX1
VIN[0]A,
VIN[0]A_D[23]/
CAMERA_I/F,
CAM_D[15]/
IPD EMAC[1], GP0
EMAC[1]_RMTXEN/ AC16 I/O
DVDD_C PINCNTL163
SPI[3]_D[0]/
DSIS: PIN
GP0[17]
MM: MUX0

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3.2.18 Oscillator/PLL, Audio Reference Clocks, and Clock Generator

Table 3-34. Oscillator/PLL, Audio Reference Clocks, and Clock Generator Terminal Functions
SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
CLOCK GENERATOR
VIN[0]A_D[12]_BD[4]/ VIN[0]A, GP2
IPD
CLKOUT1/ AG17 I/O PINCNTL152
DVDD
GP2[17] DSIS: PIN
GPMC_CLK/
GPMC_CS[5]/ Device Clock output 1. Can be used as a system clock
GPMC, EDMA, for other devices.
GPMC_WAIT[1]/
IPU TIM4, GP1
CLKOUT1/ R26 O
DVDD_GPMC PINCNTL127
EDMA_EVT3/
DSIS: N/A
TIM4_IO/
GP1[27]
VIN[0]B_CLK/ VIN[0]B, GP1
IPD
CLKOUT0/ AE17 I/O PINCNTL134
DVDD
GP1[9] DSIS: PIN
Device Clock output 0. Can be used as a system clock
CLKIN32/ CLKIN32, TIM3, for other devices.
CLKOUT0/ IPD GP3
J7 O
TIM3_IO/ DVDD PINCNTL259
GP3[31] DSIS: N/A
OSCILLATOR/PLL
Device Crystal input. Crystal connection to internal
DEVOSC_MXI/ –
AH2 AI – oscillator for system clock. Functions as DEV_CLKIN
DEV_CLKIN VDDA_1P8
clock input when an external oscillator is used.
Device Crystal output. Crystal connection to internal
–
DEVOSC_MXO AH3 AO – oscillator for system clock. When device oscillator is
VDDA_1P8
BYPASSED, leave this pin unconnected.
Supply Ground for DEV Oscillator. If the internal
VSSA_DEVOSC AG3 GND oscillator is bypassed, DEVOSC_VSS should be
connected to ground (VSS).
Auxiliary Crystal input [Optional Audio/Video Reference
AUXOSC_MXI/ – Crystal Input]. Crystal connection to internal oscillator
R1 AI –
AUX_CLKIN VDDA_1P8 for auxiliary clock. Functions as AUX_CLKIN clock input
when an external oscillator is used.
Auxiliary Crystal output [Optional Audio/Video
–
AUXOSC_MXO T1 AO – Reference Crystal Output]. When auxiliary oscillator is
VDDA_1P8
BYPASSED, leave this pin unconnected.
Supply Ground for AUX Oscillator. If the internal
VSSA_AUXOSC R2 GND oscillator is bypassed, AUXOSC_VSS should be
connected to ground (VSS).
CLKIN32/ CLKOUT0,
CLKOUT0/ IPD TIMER 3, GP3 RTC Clock input. Optional 32.768 KHz clock for RTC
J7 I
TIM3_IO/ DVDD PINCNTL259 reference.
GP3[31] DSIS: PIN
DEVOSC_WAKE/ SPI[1], TIMER 5,
SPI[1]_SCS[1]/ IPU GP1
W6 I Oscillator Wake-up input.
TIM5_IO/ DVDD_SD PINCNTL7
GP1[7] DSIS: 1
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

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Table 3-34. Oscillator/PLL, Audio Reference Clocks, and Clock Generator Terminal Functions (continued)
SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
AUDIO REFERENCE CLOCKS
AUD_CLKIN2/
MCA[0]_AXR[9]/ MCA[0], MCA[2],
MCA[2]_AHCLKX/ MCA[5], EDMA,
IPD
MCA[5]_AHCLKX/ H1 I TIMER 3, GP0 Audio Reference Clock 2 for Audio Peripherals.
DVDD
EDMA_EVT2/ PINCNTL16
TIM3_IO/ DSIS: PIN
GP0[9]
AUD_CLKIN1/
MCA[0]_AXR[8]/ MCA[0], MCA[1],
MCA[1]_AHCLKX/ MCA[4], EDMA,
IPD
MCA[4]_AHCLKX/ R5 I TIMER 2, GP0 Audio Reference Clock 1 for Audio Peripherals.
DVDD
EDMA_EVT3/ PINCNTL15
TIM2_IO/ DSIS: PIN
GP0[8]
AUD_CLKIN0/
MCA[0], MCA[3],
MCA[0]_AXR[7]/
IPD USB1
MCA[0]_AHCLKX/ L5 I Audio Reference Clock 0 for Audio Peripherals.
DVDD PINCNTL14
MCA[3]_AHCLKX/US
DSIS: PIN
B1_DRVVBUS

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3.2.19 Timer

Table 3-35. Timer Terminal Functions

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
Timers 8-1 and Watchdog Timer 0
Timer 8 and Timer1
There are no external pins for these timers.
Timers TCLKIN
GP0
TCLKIN/ IPD
T2 I PINCNTL60 Timer external clock input
GP0[30] DVDD
DSIS: 0
Timer 7
GPMC_BE[1]/ GPMC, EDMA,
GPMC_A[24]/ GP1
IPD
EDMA_EVT1/ V28 I/O PINCNTL132
DVDD_GPMC
TIM7_IO/ DSIS: PIN
GP1[30] MM: MUX3
SD2_DAT4
GPMC_A[27]/ SD2, GPMC,
GPMC_A[23]/ EDMA, GP1
IPU
GPMC_CS[7]/ R24 I/O PINCNTL116
DVDD_GPMC
EDMA_EVT0/ DSIS: PIN
TIM7_IO/ MM: MUX2
GP1[22] Timer 7 capture event input or PWM output
VOUT[0]_AVID/ VOUT[0], SPI[3],
VOUT[0]_FLD/ GP2
IPD
SPI[3]_SCLK/ AA10 I/O PINCNTL179
DVDD
TIM7_IO/ DSIS: PIN
GP2[21] MM: MUX1
MCA[5], MCA[4],
MCA[5]_AXR[1]/
GP0
MCA[4]_AXR[3]/ IPD
L6 I/O PINCNTL58
TIM7_IO/ DVDD
DSIS: PIN
GP0[28]
MM: MUX0
Timer 6
GPMC_BE[0]_CLE/ GPMC, EDMA,
GPMC_A[25]/ GP1
IPD
EDMA_EVT2/ U27 I/O PINCNTL131
DVDD_GPMC
TIM6_IO/ DSIS: PIN
GP1[29] MM: MUX3
SD2_DAT[5]/
SD2, GPMC, GP1
GPMC_A[26]/
IPU PINCNTL115
GPMC_A[22]/ P22 I/O
DVDD_GPMC DSIS: PIN
TIM6_IO/
MM: MUX2
GP1[21]
Timer 6 capture event input or PWM output
VOUT[1]_AVID/ VOUT[1],
EMAC[1]_MRXER/ EMAC[1], VIN[1]A,
VIN[1]A_CLK/ IPD UART4, GP2
Y22 I/O
UART4_RTS/ DVDD PINCNTL207
TIM6_IO/ DSIS: PIN
GP2[31] MM: MUX1
MCA[4], GP0
MCA[4]_AXR[1]/
IPD PINCNTL54
TIM6_IO/ J4 I/O
DVDD DSIS: PIN
GP0[24]
MM: MUX0
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown
resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

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Table 3-35. Timer Terminal Functions (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
Timer 5
GPMC_ADV_ALE/ GPMC, GP1
GPMC_CS[6]/ IPU PINCNTL128
M26 I/O
TIM5_IO/ DVDD_GPMC DSIS: PIN
GP1[28] MM: MUX3
GPMC_A[23]/ GPMC, SPI[2],
SPI[2]_SCLK/ HDMI, GP1
IPD
HDMI_HPDET/ AA26 I/O PINCNTL112
DVDD_GPMC
TIM5_IO/ DSIS: PIN
GP1[18] MM: MUX2 Timer 5 capture event input or PWM output
DEVOSC_WAKE/ OSC, SPI[1], GP1
SPI[1]_SCS[1]/ IPU PINCNTL7
W6 I/O
TIM5_IO/ DVDD_SD DSIS: PIN
GP1[7] MM: MUX1
MCA[3], GP0
MCA[3]_AXR[1]/
IPD PINCNTL48
TIM5_IO/ G2 I/O
DVDD DSIS: PIN
GP0[19]
MM: MUX0
Timer 4
GPMC_CLK/
GPMC_CS[5]/ GPMC, CLKOUT1,
GPMC_WAIT[1]/ EDMA, GP1
IPU
CLKOUT1/ R26 I/O PINCNTL127
DVDD_GPMC
EDMA_EVT3/ DSIS: PIN
TIM4_IO/ MM: MUX3
GP1[27]
GPMC_A[22]/ GPMC, SPI[2],
SPI[2]_D[1]/ HDMI, GP1
IPU
HDMI_CEC/ AB27 I/O PINCNTL111
DVDD_GPMC
TIM4_IO/ DSIS: PIN
GP1[17] MM: MUX2 Timer 4 capture event input or PWM output
SPI[0]_SCS[1]/ SPI[0], SD1,
SD1_SDCD/ SATA, EDMA,
SATA_ACT0_LED/ IPU GP1
AE5 I/O
EDMA_EVT1/ DVDD PINCNTL80
TIM4_IO/ DSIS: PIN
GP1[6] MM: MUX1
MCA[3], GP0
MCA[3]_AXR[0]/
IPD PINCNTL47
TIM4_IO/ G1 I/O
DVDD DSIS: PIN
GP0[18]
MM: MUX0

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Table 3-35. Timer Terminal Functions (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
Timer 3
CLKIN32,
CLKIN32/
CLKOUT, GP3
CLKOUT0/ IPD
J7 I/O PINCNTL259
TIM3_IO/ DVDD
DSIS: PIN
GP3[31]
MM: MUX3
GPMC, GP1
GPMC_A[19]/
IPD PINCNTL108
TIM3_IO/ AC27 I/O
DVDD_GPMC DSIS: PIN
GP1[14]
MM: MUX2
AUD_CLKIN2/ AUD_CLKIN2,
MCA[0]_AXR[9]/ MCA[0], MCA[2]. Timer 3 capture event input or PWM output
MCA[2]_AHCLKX/ MCA[5], EDMA,
IPD
MCA[5]_AHCLKX/ H1 I/O GP0
DVDD
EDMA_EVT2/ PINCNTL16
TIM3_IO/ DSIS: PIN
GP0[9] MM: MUX1
MCA[2], MCA[1],
MCA[2]_AXR[3]/
GP0
MCA[1]_AXR[7]/ IPD
H2 I/O PINCNTL44
TIM3_IO/ DVDD
DSIS: PIN
GP0[15]
MM: MUX0
Timer 2
EMAC, GP1
EMAC_RMREFCLK/
IPD PINCNTL232
TIM2_IO/ J27 I/O
DVDD_GPMC DSIS: PIN
GP1[10]
MM: MUX3
GPMC, GP0
GPMC_A[18]/
IPD PINCNTL107
TIM2_IO/ AE28 I/O
DVDD_GPMC DSIS: PIN
GP0[13]
MM: MUX2
AUD_CLKIN1/ AUD_CLKIN1,
MCA[0]_AXR[8]/ MCA[0], MCA[1], Timer 2 capture event input or PWM output
MCA[1]_AHCLKX/ MCA[4], EDMA,
IPD
MCA[4]_AHCLKX/ R5 I/O GP0
DVDD
EDMA_EVT3/ PINCNTL15
TIM2_IO/ DSIS: PIN
GP0[8] MM: MUX1
MCA[2], MCA[1],
MCA[2]_AXR[2]/
GP0
MCA[1]_AXR[6]/ IPD
V5 I/O PINCNTL43
TIM2_IO/ DVDD
DSIS: PIN
GP0[14]
MM: MUX0
Watchdog Timer 0
DIS –
RSTOUT_WD_OUT O Watchdog timer 0 event output
DVDD PINCNTL262

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3.2.20 UART

Table 3-36. UART0 Terminal Functions

SIGNAL OTHER (2)
TYPE (1) (3) MUXED DESCRIPTION
NAME NO.
UART0
–
IPU UART0 Receive Data Input. Functions as IrDA receive input
UART0_RXD AH5 I PINCNTL70
DVDD in IrDA modes and CIR receive input in CIR mode.
DSIS: PIN
–
IPU UART0 Transmit Data Output. Functions as CIR transmit
UART0_TXD AG5 O PINCNTL71
DVDD output in CIR mode.
DSIS: PIN
UART0_RTS/
UART4, DCAN1,
UART4_TXD/ UART0 Request to Send Output. Indicates module is ready
IPU SPI[1], SD2
DCAN1_RX/ AF5 O to receive data. Functions as transmit data output in IrDA
DVDD PINCNTL73
SPI[1]_SCS[2]/ modes.
DSIS: PIN
SD2_SDCD
UART0_CTS/
UART4, DCAN1,
UART4_RXD/
IPU SPI[1], SD0 UART0 Clear to Send Input. Functions as SD transceiver
DCAN1_TX/ AE6 I/O
DVDD PINCNTL72 control output in IrDA and CIR modes.
SPI[1]_SCS[3]/
DSIS: 1
SD0_SDCD
UART0_DTR/ UART3, UART1,
UART3_CTS/ IPU GP1
AG2 O UART0 Data Terminal Ready Output
UART1_TXD/ DVDD PINCNTL76
GP1[4] DSIS: PIN
UART0_DSR/
UART3_TXD/ UART3, SPI[0],
SPI[0]_SCS[2]/ IPU I2C[2], SD1, GP1
AG4 I UART0 Data Set Ready Input
I2C[2]_SDA/ DVDD PINCNTL75
SD1_SDWP/ DSIS: 1
GP1[3]
UART0_DCD/
UART3_RXD/ UART3, SPI[0],
SPI[0]_SCS[3]/ IPU I2C[2], SD1, GP1
AH4 I UART0 Data Carrier Detect Input
I2C[2]_SCL/ DVDD PINCNTL74
SD1_POW/ DSIS: 1
GP1[2]
UART0_RIN/ UART3, UART1,
UART3_RTS/ IPU GP1
AF4 I UART0 Ring Indicator Input
UART1_RXD/ DVDD PINCNTL77
GP1[5] DSIS: 1
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown
resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

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Table 3-37. UART1 Terminal Functions

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
UART1
EMAC[0]_MTXD[5]/ EMAC[0],
EMAC[1]_RGTXC/ EMAC[1], GPMC
IPD
EMAC[1]_RMCRSDV/ F27 I PINCNTL255
DVDD_GPMC
GPMC_A[12]/ DSIS: 1
UART1_RXD MM: MUX1 UART1 Receive Data Input. Functions as IrDA receive
UART0, UART3, input in IrDA modes and CIR receive input in CIR mode.
UART0_RIN/
GP1
UART3_RTS/ IPU
AF4 I PINCNTL77
UART1_RXD/ DVDD
DSIS: 1
GP1[5]
MM: MUX0
EMAC[0]_MTXD[6]/ EMAC[0],
EMAC[1]_RGRXD[0]/ EMAC[1], GPMC
IPD
EMAC[1]_RMTXD[0]/ J22 O PINCNTL256
DVDD_GPMC
GPMC_A[13]/ DSIS: PIN
UART1_TXD MM: MUX1 UART1 Transmit Data Output. Functions as CIR transmit
UART0, UART3, output in CIR mode.
UART0_DTR/
GP1
UART3_CTS/ IPU
AG2 O PINCNTL76
UART1_TXD/ DVDD
DSIS: PIN
GP1[4]
MM: MUX0
EMAC[0]_MTXEN/
EMAC[0],
EMAC[1]_RGRXD[2]/ UART1 Request to Send Output. Indicates module is
IPD EMAC[1], GPMC
EMAC[1]_RMTXEN/ J23 O ready to receive data. Functions as transmit data output
DVDD_GPMC PINCNTL258
GPMC_A[15]/ in IrDA modes.
DSIS: PIN
UART1_RTS
EMAC[0]_MTXD[7]/
EMCA[0],
EMAC[1]_RGTXD[3]/
IPD EMAC[1], GPMC UART1 Clear to Send Input. Functions as SD
EMAC[1]_RMTXD[1]/ H24 I/O
DVDD_GPMC PINCNTL257 transceiver control output in IrDA and CIR modes.
GPMC_A[14]/
DSIS: 1
UART1_CTS
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown
resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

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Table 3-38. UART2 Terminal Functions

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
UART2
SD2_DAT[7]/
SD2, GPMC, GP1
GPMC_A[24]/
IPU PINCNTL113
GPMC_A[20]/ L25 I
DVDD_GPMC DSIS: 1
UART2_RXD/
MM: MUX3
GP1[19]
DCAN0, I2C[3],
DCAN0_RX/
GP1
UART2_RXD/ IPU
AG6 I PINCNTL69
I2C[3]_SCL/ DVDD
DSIS: 1
GP1[1]
MM: MUX2 UART2 Receive Data Input. Functions as IrDA receive
GP0 input in IrDA modes and CIR receive input in CIR mode.
UART2_RXD/ IPD PINCNTL59
U4 I
GP0[29] DVDD DSIS: 1
MM: MUX1
VOUT[1],
VOUT[1]_B_CB_C[1]/
CAMERA_I/F,
CAM_HS/
IPD GPMC, GP0
GPMC_A[9]/ AE23 I
DVDD_C PINCNTL172
UART2_RXD/
DSIS: 1
GP0[26]
MM: MUX0
SD2_DAT[6]/
SD2, GPMC, GP1
GPMC_A[25]/
IPU PINCNTL114
GPMC_A[21]/ N23 O
DVDD_GPMC DSIS: PIN
UART2_TXD/
MM: MUX3
GP1[20]
DCAN0, I2C[3],
DCAN0_TX/
GP1
UART2_TXD/ IPU
AH6 O PINCNTL68
I2C[3]_SDA/ DVDD
DSIS: PIN
GP1[0]
MM: MUX2 UART2 Transmit Data Output. Functions as CIR
GP0 transmit output in CIR mode.
UART2_TXD/ IPD PINCNTL61
U3 O
GP0[31] DVDD DSIS: PIN
MM: MUX1
VOUT[1],
VOUT[1]_B_CB_C[0]/
CAMERA_I/F,
CAM_VS/
IPU GPMC, GP0
GPMC_A[10]/ AD23 O
DVDD_C PINCNTL173
UART2_TXD/
DSIS: PIN
GP0[27]
MM: MUX0
VOUT[0]_FLD/ VOUT[0],
CAM_PCLK/ CAMERA_I/F, UART2 Request to Send Output. Indicates module is
IPD
GPMC_A[12]/ AF18 O GPMC, GP2 ready to receive data. Functions as transmit data output
DVDD_C
UART2_RTS/ PINCNTL175 in IrDA modes.
GP2[2] DSIS: PIN
VOUT[1]_FLD/
VOUT[1],
CAM_FLD/
CAMERA_I/F,
CAM_WE/ IPD UART2 Clear to Send Input. Functions as SD
AB23 I/O GPMC, GP0
GPMC_A[11]/ DVDD_C transceiver control output in IrDA and CIR modes.
PINCNTL174
UART2_CTS/
DSIS: 1
GP0[28]
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown
resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

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Table 3-39. UART3 Terminal Functions

SIGNAL OTHER (2)
TYPE (1) (3) MUXED DESCRIPTION
NAME NO.
UART3
VOUT[1],
VOUT[1]_B_CB_C[6]/
EMAC[1], VIN[1]A,
EMAC[1]_MRXD[2]/
IPD GP3
VIN[1]A_D[3]/ AD25 I
DVDD PINCNTL211
UART3_RXD/
DSIS: 1
GP3[3]
MM: MUX1 UART3 Receive Data Input. Functions as IrDA receive input
UART0_DCD/ in IrDA modes and CIR receive input in CIR mode.
UART0, SPI[0],
UART3_RXD/
I2C[2], SD1, GP1
SPI[0]_SCS[3]/ IPU
AH4 I PINCNTL74
I2C[2]_SCL/ DVDD
DSIS: 1
SD1_POW/
MM: MUX0
GP1[2]
VOUT[1],
VOUT[1]_B_CB_C[7]/
EMAC[1], VIN[1]A,
EMAC[1]_MRXD[3]/
IPD GP3
VIN[1]A_D[4]/ AC25 O
DVDD PINCNTL212
UART3_TXD/
DSIS: PIN
GP3[4]
MM: MUX1 UART3 Transmit Data Output. Functions as CIR transmit
UART0_DSR/ output in CIR mode.
UART0, SPI[0],
UART3_TXD/
I2C[2], SD1, GP1
SPI[0]_SCS[2]/ IPU
AG4 O PINCNTL75
I2C[2]_SDA/ DVDD
DSIS: PIN
SD1_SDWP/
MM: MUX0
GP1[3]
VOUT[1]_HSYNC/ VOUT[1],
EMAC[1]_MCOL/ EMAC[1], VIN[1]A,
VIN[1]A_VSYNC/ IPD SPI[3], GP2
AC24 O
SPI[3]_D[1]/ DVDD PINCNTL205
UART3_RTS/ DSIS: PIN UART3 Request to Send Output. Indicates module is ready
GP2[29] MM: MUX1 to receive data. Functions as transmit data output in IrDA
UART0, UART1, modes.
UART0_RIN/
GP1
UART3_RTS/ IPU
AF4 O PINCNTL77
UART1_RXD/ DVDD
DSIS: PIN
GP1[5]
MM: MUX0
VOUT[1]_VSYNC/
VOUT[1],
EMAC[1]_MCRS/
EMAC[1], VIN[1]A,
VIN[1]A_FLD/
IPD SPI[3], GP2
VIN[1]A_DE/ AA23 I/O
DVDD PINCNTL206
SPI[3]_D[0]/
DSIS: 1
UART3_CTS/ UART3 Clear to Send Input. Functions as SD transceiver
MM: MUX1
GP2[30] control output in IrDA and CIR modes.
UART3, UART1,
UART0_DTR/
GP1
UART3_CTS/ IPU
AG2 I/O PINCNTL76
UART1_TXD/ DVDD
DSIS: 1
GP1[4]
MM: MUX0
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown
resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

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Table 3-40. UART4 Terminal Functions

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
UART4
UART0_CTS/ UART0, DCAN1,
UART4_RXD/ SPI[1], SD0
IPU
DCAN1_TX/ AE6 I PINCNTL72
DVDD
SPI[1]_SCS[3]/ DSIS: 1
SD0_SDCD MM: MUX3
VOUT[1],
VOUT[1]_B_CB_C[4]/
EMAC[1], VIN[1]A,
EMAC[1]_MRXD[0]/
IPD GP3
VIN[1]A_D[1]/ AG25 I
DVDD PINCNTL209
UART4_RXD/
DSIS: 1
GP3[1]
MM: MUX2 UART4 Receive Data Input. Functions as IrDA receive
EMAC[0], input in IrDA modes and CIR receive input in CIR mode.
EMAC[0]_MTXD[1]/
EMAC[1], GPMC
EMAC[1]_RGTXD[1]/ IPD
H25 I PINCNTL251
GPMC_A[8]/ DVDD_GPMC
DSIS: 1
UART4_RXD
MM: MUX1
VOUT[1],
VOUT[1]_G_Y_YC[1]/
CAMERA_I/F,
CAM_D[3]/
IPU GPMC, GP0
GPMC_A[5]/ AD18 I
DVDD_C PINCNTL168
UART4_RXD/
DSIS: 1
GP0[22]
MM: MUX0
UART0_RTS/ UART0, DCAN1,
UART4_TXD/ SPI[1], SD2
IPU
DCAN1_RX/ AF5 O PINCNTL73
DVDD
SPI[1]_SCS[2]/ DSIS: PIN
SD2_SDCD MM: MUX3
VOUT[1],
VOUT[1]_B_CB_C[5]/
EMAC[1], VIN[1]A,
EMAC[1]_MRXD[1]/
IPD GP3
VIN[1]A_D[2]/ AF25 O
DVDD PINCNTL210
UART4_TXD/
DSIS: PIN
GP3[2]
MM: MUX2 UART4 Transmit Data Output. Functions as CIR transmit
EMAC[0]_MTXD[2]/ EMAC[0], output in CIR mode.
EMAC[1]_RGTXCTL/ EMAC[1], GPMC
IPD
EMAC[1]_RMRXD[0]/ H22 O PINCNTL252
DVDD_GPMC
GPMC_A[9]/ DSIS: PIN
UART4_TXD MM: MUX1
VOUT[1],
VOUT[1]_G_Y_YC[0]/
CAMERA_I/F,
CAM_D[2]/
IPD GPMC, GP0
GPMC_A[6]/ AC18 O
DVDD_C PINCNTL169
UART4_TXD/
DSIS: PIN
GP0[23]
MM: MUX0

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown
resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal
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Table 3-40. UART4 Terminal Functions (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
VOUT[1]_AVID/ VOUT[1],
EMAC[1]_MRXER/ EMAC[1], VIN[1]A,
VIN[1]A_CLK/ IPD TIMER6, GP2
Y22 O
UART4_RTS/ DVDD PINCNTL207
TIM6_IO/ DSIS: PIN
GP2[31] MM: MUX2
EMAC[0]_MTXD[4]/ EMAC[0],
EMAC[1]_RGTXD[2]/ EMAC[1], GPMC UART4 Request to Send Output. Indicates module is
IPD
EMAC[1]_RMRXER/ G23 O PINCNTL254 ready to receive data. Functions as transmit data output
DVDD_GPMC
GPMC_A[11]/ DSIS: PIN in IrDA modes.
UART4_RTS MM: MUX1
VOUT[1],
VOUT[1]_R_CR[0]/
CAMERA_I/F,
CAM_D[0]/
IPD GPMC, GP0
GPMC_A[8]/ AA22 O
DVDD_C PINCNTL171
UART4_RTS/
DSIS: PIN
GP0[25]
MM: MUX0
VOUT[1],
VOUT[1]_B_CB_C[3]/
EMAC[1], VIN[1]A,
EMAC[1]_MRCLK/
IPD GP3
VIN[1]A_D[0]/ AH25 I/O
DVDD PINCNTL208
UART4_CTS/
DSIS: 1
GP3[0]
MM: MUX2
EMAC[0]_MTXD[3]/ EMAC[0],
EMAC[1]_RGTXD[0]/ EMAC[1], GPMC
IPD UART4 Clear to Send Input. Functions as SD transceiver
EMAC[1]_RMRXD[1]/ H23 I/O PINCNTL253
DVDD_GPMC control output in IrDA and CIR modes.
GPMC_A[10]/ DSIS: 1
UART4_CTS MM: MUX1
VOUT[1],
VOUT[1]_R_CR[1]/
CAMERA_I/F,
CAM_D[1]/
IPD GPMC, GP0
GPMC_A[7]/ AC19 I/O
DVDD_C PINCNTL170
UART4_CTS/
DSIS: 1
GP0[24]
MM: MUX0

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Table 3-41. UART5 Terminal Functions

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
UART5
MCA[2]_AXR[0]/ MCA[2], SD0, GP0
SD0_DAT[6]/ IPU PINCNTL41
N2 I
UART5_RXD/ DVDD DSIS: 1
GP0[12] MM: MUX3
VOUT[1]_R_CR[8]/ VOUT[1], EMAC[1],
EMAC[1]_MTXD[7]/ VIN[1]A, GP3
IPD
VIN[1]A_D[19]/ W23 I PINCNTL226
DVDD
UART5_RXD/ DSIS: 1
GP3[18] MM: MUX2
VIN[0]A_FLD/ VIN[0]A, I2C[2], UART5 Receive Data Input. Functions as IrDA receive
VIN[0]B_VSYNC/ GP2 input in IrDA modes and CIR receive input in CIR mode.
IPU
UART5_RXD/ AA20 I PINCNTL136
DVDD
I2C[2]_SCL/ DSIS: 1
GP2[1] MM: MUX1
EMAC[0]_MRXD[3]/
EMAC[1]_RGRXCTL EMAC[0],
/ EMAC[1], GPMC
IPD
GPMC_A[27]/ J25 I PINCNTL243
DVDD_GPMC
GPMC_A[26]/ DSIS: 1
GPMC_A[0]/ MM: MUX0
UART5_RXD
MCA[2]_AXR[1]/ MCA[2], SD0, GP0
SD0_DAT[7]/ IPU PINCNTL42
V6 O
UART5_TXD/ DVDD DSIS: PIN
GP0[13] MM: MUX3
VOUT[1]_R_CR[9]/ VOUT[1], EMAC[1],
EMAC[1]_MTXEN/ VIN[1]A, GP3
IPD
VIN[1]A_D[20]/ Y24 O PINCNTL227
DVDD
UART5_TXD/ DSIS: PIN
GP3[19] MM: MUX2
UART5 Transmit Data Output. Functions as CIR transmit
VIN[0]A_DE/ VIN[0]A, I2C[2], output in CIR mode.
VIN[0]B_HSYNC/ GP0
IPU
UART5_TXD/ AE21 O PINCNTL135
DVDD
I2C[2]_SDA/ DSIS: PIN
GP2[0] MM: MUX1
EMAC[0]_MRXD[4]/
EMAC[0], GPMC
EMAC[0]_RGRXD[3]
IPD PINCNTL244
/ T23 O
DVDD_GPMC DSIS: PIN
GPMC_A[1]/
MM: MUX0
UART5_TXD
VIN[0]A, GP2
VIN[0]A_HSYNC/
IPU PINCNTL138
UART5_RTS/ AC20 O
DVDD DSIS: PIN
GP2[3]
MM: MUX1 UART5 Request to Send Output. Indicates module is
EMAC[0]_MRXD[6]/ ready to receive data. Functions as transmit data output in
EMAC[0], GPMC IrDA modes.
EMAC[0]_RGTXD[2]
IPD PINCNTL246
/ F28 O
DVDD_GPMC DSIS: PIN
GPMC_A[3]/
MM: MUX0
UART5_RTS

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown
resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal
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Table 3-41. UART5 Terminal Functions (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
VIN[0]A, GP2
VIN[0]A_VSYNC/
IPU PINCNTL139
UART5_CTS/ AD20 I/O
DVDD DSIS: 1
GP2[4]
MM: MUX1
UART5 Clear to Send Input. Functions as SD transceiver
EMAC[0]_MRXD[5]/ control output in IrDA and CIR modes.
EMAC[0], GPMC
EMAC[0]_RGTXD[3]
IPD PINCNTL245
/ H26 I/O
DVDD_GPMC DSIS: 1
GPMC_A[2]/
MM: MUX0
UART5_CTS

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3.2.21 USB

Table 3-42. USB Terminal Functions

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
USB0
– USB0 bidirectional data differential signal pair
USB0_DP AG11 A I/O –
VDDA_USB_3P3 [plus/minus].
– When the USB0 PHY is powered down, these pins
USB0_DM AH11 A I/O –
VDDA_USB_3P3 should be left unconnected.
USB0 OTG identification input.
–
USB0_ID AG10 AI – When the USB0 PHY is powered down, this pin should
VDDA_USB_3P3
be left unconnected.
USB0 charger enable.
–
USB0_CE AH10 AO – When the USB0 PHY is powered down, this pin should
VDDA_USB_3P3
be left unconnected.
5-V USB0 VBUS comparator input.

– This analog input pin senses the level of the USB VBUS
USB0_VBUSIN AG12 AI – voltage and should connect directly to the USB VBUS
VDDA_USB_3P3
voltage. When the USB0 PHY is powered down, this pin
should be left unconnected.
When this pin is used as USB0_DRVVBUS and the
USB0 Controller is operating as a Host, this signal is
GP0 used by the USB0 Controller to enable the external
USB0_DRVVBUS/ IPD
AF11 O PINCNTL270 VBUS charge pump.
GP0[7] DVDD
DSIS: N/A
When the USB0 PHY is powered down, this pin should
be left unconnected.
USB1
– USB1 bidirectional data differential signal pair
USB1_DP AG13 A I/O –
VDDA_USB_3P3 [plus/minus].
– When the USB1 PHY is powered down, these pins
USB1_DM AH13 A I/O –
VDDA_USB_3P3 should be left unconnected.
USB1 OTG identification input.
–
USB1_ID AH12 AI – When the USB1 PHY is powered down, this pin should
VDDA_USB_3P3
be left unconnected.
USB1 charger enable.
–
USB1_CE AH14 AO – When the USB1 PHY is powered down, this pin should
VDDA_USB_3P3
be left unconnected.
5-V USB1 VBUS comparator input.

– This analog input pin senses the level of the USB VBUS
USB1_VBUSIN AG14 AI – voltage and should connect directly to the USB VBUS
VDDA_USB_3P3
voltage. When the USB1 PHY is powered down, this pin
should be left unconnected.
When this pin is used as USB1_DRVVBUS and the
AUD_CLKIN0/ USB1 Controller is operating as a Host, this signal is
AUD_CLKIN0,
MCA[0]_AXR[7]/ used by the USB1 Controller to enable the external
IPD MCA[0], MCA[3],
MCA[0]_AHCLKX/ L5 O VBUS charge pump.
DVDD PINCNTL14
MCA[3]_AHCLKX/
DSIS: N/A When the USB1 PHY is powered down, this pin should
USB1_DRVVBUS
be left unconnected.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown
resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal

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3.2.22 Video Input (Digital)

Table 3-43. Video Input 0 (Digital) Terminal Functions

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
Video Input 0 (Digital)
VIN[0]B_CLK/ CLKOUT0, GP1 Video Input 0 Port B Clock input. Input clock for 8-bit
IPD
CLKOUT0/ AE17 I PINCNTL134 Port B video capture. This signal is not used in 16-bit
DVDD
GP1[9] DSIS: 0 and 24-bit capture modes.
GP2
VIN[0]A_CLK/ IPD Video Input 0 Port A Clock input. Input clock for 8-bit ,
AB20 I PINCNTL137
GP2[2] DVDD 16-bit, or 24-bit Port A video capture.
DSIS: 0
VIN[0]A_D[23]/ CAM_IF,
CAM_D[15]/ EMAC[1]_RM,
IPD
EMAC[1]_RMTXEN/ AC16 I SPI[3], GP0
DVDD_C
SPI[3]_D[0]/ PINCNTL163
GP0[17] DSIS: PIN
VIN[0]A_D[22]/ CAM_IF,
CAM_D[14]/ EMAC[1]_RM,
IPD
EMAC[1]_RMTXD[1]/ AC21 I SPI[3], GP0
DVDD_C
SPI[3]_D[1]/ PINCNTL162
GP0[16] DSIS: PIN
VIN[0]A_D[21]/ CAM_IF,
CAM_D[13]/ EMAC[1]_RM,
IPD
EMAC[1]_RMTXD[0]/ AE18 I SPI[3], GP0
DVDD_C
SPI[3]_SCLK/ PINCNTL161
GP0[15] DSIS: PIN
VIN[0]A_D[20]/ CAM_IF,
CAM_D[12]/ EMAC[1]_RM,
IPD
EMAC[1]_RMCRSDV/ AC17 I SPI[3], GP0 Video Input 0 Data inputs. For 16-bit capture, D[7:0] are
DVDD_C
SPI[3]_SCS[0]/ PINCNTL160 Cb/Cr and [15:8] are Y Port A inputs. For 8-bit capture,
GP0[14] DSIS: PIN D[7:0] are Port A YCbCr data inputs and D[15:8] are Port
VIN[0]A_D[19]/ CAM_IF, B YCbCr data inputs. For RGB capture, D[23:16] are R,
CAM_D[11]/ EMAC[1]_RM, D[15:8] are G, and D[7:0] are B data inputs.
IPU
EMAC[1]_RMRXD[0]/ AF21 I I2C[3], GP0
DVDD_C
I2C[3]_SDA/ PINCNTL159
GP0[13] DSIS: PIN
VIN[0]A_D[18]/ CAM_IF,
CAM_D[10]/ EMAC[1]_RM,
IPU
EMAC[1]_RMRXD[1]/ AF20 I I2C[3], GP0
DVDD_C
I2C[3]_SCL/ PINCNTL158
GP0[12] DSIS: PIN
CAM_IF,
VIN[0]A_D[17]/
EMAC[1]_RM,
CAM_D[9]/ IPD
AB21 I I2C[3], GP0
EMAC[1]_RMRXER/ DVDD_C
PINCNTL157
GP0[11]
DSIS: PIN
VIN[0]A_D[16]/ CAM_IF, I2C[3],
CAM_D[8]/ IPU GP0
AA21 I
I2C[2]_SCL/ DVDD_C PINCNTL156
GP0[10] DSIS: PIN

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown
resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal.
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Table 3-43. Video Input 0 (Digital) Terminal Functions (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
VIN[0]A_D[15]_BD[7]/ CAM_IF, GP2
IPD
CAM_SHUTTER/ AC14 I PINCNTL155
DVDD
GP2[20] DSIS: PIN
VIN[0]A_D[14]_BD[6]/ CAM_IF, GP2
IPD
CAM_STROBE/ AC12 I PINCNTL154
DVDD
GP2[19] DSIS: PIN
VIN[0]A_D[13]_BD[5]/ CAM_IF, GP2
IPD
CAM_RESET/ AF17 I PINCNTL153
DVDD
GP2[18] DSIS: PIN
VIN[0]A_D[12]_BD[4]/ CLKOUT1, GP2
IPD Video Input 0 Data inputs. For 16-bit capture, D[7:0] are
CLKOUT1/ AG17 I PINCNTL152
DVDD Cb/Cr and [15:8] are Y Port A inputs. For 8-bit capture,
GP2[17] DSIS: PIN
D[7:0] are Port A YCbCr data inputs and D[15:8] are Port
VIN[0]A_D[11]_BD[3]/ CAM_IF, GP2 B YCbCr data inputs. For RGB capture, D[23:16] are R,
IPD
CAM_WE/ AH17 I PINCNTL151 D[15:8] are G, and D[7:0] are B data inputs.
DVDD
GP2[16] DSIS: PIN
GP2
VIN[0]A_D[10]_BD[2]/ IPD
AH9 I PINCNTL150
GP2[15] DVDD
DSIS: PIN
GP2
VIN[0]A_D[9]_BD[1]/ IPD
AG9 I PINCNTL149
GP2[14] DVDD
DSIS: PIN
GP2
VIN[0]A_D[8]_BD[0]/ IPD
AB15 I PINCNTL148
GP2[13] DVDD
DSIS: PIN
GP2
VIN[0]A_D[7]/ IPD
AA11 I PINCNTL147
GP2[12] DVDD
DSIS: PIN
GP2
VIN[0]A_D[6]/ IPD
AH16 I PINCNTL146
GP2[11] DVDD
DSIS: PIN
GP2
VIN[0]A_D[5]/ IPD
AG16 I PINCNTL145
GP2[10] DVDD
DSIS: PIN
GP2
VIN[0]A_D[4]/ IPD Video Input 0 Data inputs. For 16-bit capture, D[7:0] are
AH8 I PINCNTL144
GP2[9] DVDD Cb/Cr and [15:8] are Y Port A inputs. For 8-bit capture,
DSIS: PIN
D[7:0] are Port A YCbCr data inputs and D[15:8] are Port
GP2 B YCbCr data inputs. For RGB capture, D[23:16] are R,
VIN[0]A_D[3]/ IPD
AE12 I PINCNTL143 D[15:8] are G, and D[7:0] are B data inputs.
GP2[8] DVDD
DSIS: PIN
GP2
VIN[0]A_D[2]/ IPD
AC9 I PINCNTL142
GP2[7] DVDD
DSIS: PIN
GP1
VIN[0]A_D[1]/ IPD
AB11 I PINCNTL141
GP1[12] DVDD
DSIS: PIN
GP1
VIN[0]A_D[0]/ IPD
AF9 I PINCNTL140
GP1[11] DVDD
DSIS: PIN
VIN[0]A_DE/
VIN[0]A, UART5, Video Input 0 Port B Horizontal Sync input. Discrete
VIN[0]B_HSYNC/
IPU I2C[2], GP2 horizontal synchronization signal for Port B 8-bit YCbCr
UART5_TXD/ AE21 I
DVDD PINCNTL135 capture without embedded syncs (“BT.601” modes). Not
I2C[2]_SDA/
DSIS: 0 used in RGB or 16-bit YCbCr capture modes
GP2[0]
Video Input 0 Port A Horizontal Sync0 input. Discrete
VIN[0]A_HSYNC/ UART5, GP2
IPU horizontal synchronization signal for Port A RGB capture
UART5_RTS/ AC20 I PINCNTL138
DVDD mode or YCbCr capture without embedded syncs
GP2[3] DSIS: 0
(“BT.601” modes).

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Table 3-43. Video Input 0 (Digital) Terminal Functions (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
VIN[0]A_FLD/
VIN[0]A, UART5, Video Input 0 Port B Vertical Sync1 input. Discrete
VIN[0]B_VSYNC/
IPU I2C[2], GP2 vertical synchronization signal for Port B 8-bit YCbCr
UART5_RXD/ AA20 I
DVDD PINCNTL136 capture without embedded syncs (“BT.601” modes). Not
I2C[2]_SCL/
DSIS:0 used in RGB or 16-bit YCbCr capture modes.
GP2[1]
Video Input 0 Port A Vertical Sync0 input. Discrete
VIN[0]A_VSYNC/ UART5, GP2
IPU vertical synchronization signal for Port A RGB capture
UART5_CTS/ AD20 I PINCNTL139
DVDD mode or YCbCr capture without embedded syncs
GP2[4] DSIS: 0
(“BT.601” modes).
CAMERA_I/F, Video Input 0 Port B Field ID input. Discrete field
VIN[0]B_FLD/
IPU GP0 identification signal for Port B 8-bit YCbCr capture
CAM_D[4]/ AD17 I
DVDD_C PINCNTL167 without embedded syncs (“BT.601” modes). Not used in
GP0[21]
DSIS: 0 RGB or 16-bit YCbCr capture modes.
CAMERA_I/F,
VIN[0]A_FLD/ GP0
IPU
CAM_D[5]/ AC22 I PINCNTL166
DVDD_C
GP0[20] DSIS: 0 Video Input 0 Port A Field ID input. Discrete field
MM: MUX1 identification signal for Port A RGB capture mode or
VIN[0]A_FLD/ VIN[0]B, UART5, YCbCr capture without embedded syncs (“BT.601”
VIN[0]B_VSYNC/ I2C[2], GP2 modes).
IPU
UART5_RXD/ AA20 I PINCNTL136
DVDD
I2C[2]_SCL/ DSIS: 0
GP2[1] MM: MUX0
CAMERA_I/F,
VIN[0]B_DE/ Video Input 0 Port B Data Enable input. Discrete data
IPU GP0
CAM_D[6]/ AC15 I valid signal for Port B RGB capture mode or YCbCr
DVDD_C PINCNTL165
GP0[19] capture without embedded syncs (“BT.601” modes).
DSIS: 0
CAMERA_I/F,
VIN[0]A_DE/ GP0
IPU
CAM_D[7]/ AB17 I PINCNTL164
DVDD_C
GP0[18] DSIS: 0
MM: MUX1 Video Input 0 Port A Data Enable input. Discrete data
valid signal for Port A RGB capture mode or YCbCr
VIN[0]A_DE/ VIN[0]B, UART5, capture without embedded syncs ("BT.601" modes).
VIN[0]B_HSYNC/ I2C[2], GP2
IPU
UART5_TXD/ AE21 I PINCNTL135
DVDD
I2C[2]_SDA/ DSIS: 0
GP2[0] MM: MUX0

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Table 3-44. Video Input 1 (Digital) Terminal Functions

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
Video Input 1 (Digital)
GPMC_CS[3]/ GPMC, SPI[2], Video Input 1 Port B Clock input. Input clock for 8-bit
VIN[1]B_CLK/ IPU GP1 Port B video capture. Input data is sampled on the CLK1
P26 I
SPI[2]_SCS[0]/ DVDD_GPMC PINCNTL125 edge. This signal is not used in 16-bit and 24-bit capture
GP1[26] DSIS: 0 modes.
VOUT[1]_AVID/ VOUT[1],
EMAC[1]_MRXER/ EMAC[1],
Video Input 1 Port A Clock input. Input clock for 8-bit ,
VIN[1]A_CLK/ IPD UART4, TIMER
Y22 I 16-bit, or 24-bit Port A video capture. Input data is
UART4_RTS/ DVDD 6, GP2
sampled on the CLK0 edge.
TIM6_IO/ PINCNTL207
GP2[31] DSIS: 0
VOUT[1]_R_CR[2]/
VOUT[1], GPMC,
GPMC_A[15]/
HDMI, SPI[2],
VIN[1]A_D[23]/ IPD
AE27 I GP3
HDMI_HPDET/ DVDD
PINCNTL230
SPI[2]_D[1]/
DSIS: PIN
GP3[22]
VOUT[1]_R_CR[3]/
GPMC_A[14]/ VOUT[1], GPMC,
VIN[1]A_D[22]/ HDMI, SPI[2],
IPU
HDMI_SDA/ AG28 I I2C[2], GP3
DVDD
SPI[2]_SCLK/ PINCNTL229 Video Input 1 Data inputs. For 16-bit capture, D[7:0] are
I2C[2]_SDA/ DSIS: PIN Cb/Cr and [15:8] are Y Port A inputs. For 8-bit capture,
GP3[21] D[7:0] are Port A YCbCr data inputs. For RGB capture,
VOUT[1]_G_Y_YC[2]/ D[23:16] are R, D[15:8] are G, and D[7:0] are B Port A
GPMC_A[13]/ VOUT[1], GPMC, data inputs.
VIN[1]A_D[21]/ HDMI, SPI[2],
IPU
HDMI_SCL/ AF27 I I2C[2], GP3
DVDD
SPI[2]_SCS[2]/ PINCNTL228
I2C[2]_SCL/ DSIS: PIN
GP3[20]
VOUT[1]_R_CR[9]/ VOUT[1],
EMAC[1]_MTXEN/ EMAC[1],
IPD
VIN[1]A_D[20]/ Y24 I UART5, GP3
DVDD
UART5_TXD/ PINCNTL227
GP3[19] DSIS: PIN
VOUT[1]_R_CR[8]/ VOUT[1],
EMAC[1]_MTXD[7]/ EMAC[1],
IPD
VIN[1]A_D[19]/ W23 I UART5, GP3
DVDD
UART5_RXD/ PINCNTL226
GP3[18] DSIS: PIN
VOUT[1]_R_CR[7]/ VOUT[1],
EMAC[1]_MTXD[6]/ EMAC[1], SPI[3],
IPD
VIN[1]A_D[18]/ V22 I GP3
DVDD Video Input 1 Data inputs. For 16-bit capture, D[7:0] are
SPI[3]_D[0]/ PINCNTL225
GP3[17] DSIS: PIN Cb/Cr and [15:8] are Y Port A inputs. For 8-bit capture,
D[7:0] are Port A YCbCr data inputs. For RGB capture,
VOUT[1]_R_CR[6]/ VOUT[1], D[23:16] are R, D[15:8] are G, and D[7:0] are B Port A
EMAC[1]_MTXD[5]/ EMAC[1], SPI[3], data inputs.
IPD
VIN[1]A_D[17]/ AA25 I GP3
DVDD
SPI[3]_D[1]/ PINCNTL224
GP3[16] DSIS: PIN
VOUT[1]_R_CR[5]/ VOUT[1],
EMAC[1]_MTXD[4]/ EMAC[1], SPI[3],
IPD
VIN[1]A_D[16]/ AC26 I GP3
DVDD
SPI[3]_SCLK/ PINCNTL223
GP3[15] DSIS: PIN

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown
resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal
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Table 3-44. Video Input 1 (Digital) Terminal Functions (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
VOUT[1]_R_CR[4]/ VOUT[1],
EMAC[1]_MTXD[3]/ EMAC[1], SPI[3],
IPD
VIN[1]A_D[15]/ AG27 I GP3
DVDD
SPI[3]_SCS[1]/ PINCNTL222
GP3[14] DSIS: PIN
VOUT[1]_G_Y_YC[9]/ VOUT[1],
EMAC[1]_MTXD[2]/ IPD EMAC[1], GP3
AD26 I
VIN[1]A_D[14]/ DVDD PINCNTL221
GP3[13] DSIS: PIN
VOUT[1]_G_Y_YC[8]/ VOUT[1],
EMAC[1]_MTXD[1]/ IPD EMAC[1], GP3
AE26 I
VIN[1]A_D[13]/ DVDD PINCNTL220
GP3[12] DSIS: PIN
VOUT[1]_G_Y_YC[7]/ VOUT[1],
EMAC[1]_MTXD[0]/ IPD EMAC[1], GP3 Video Input 1 Data inputs. For 16-bit capture, D[7:0] are
AF26 I
VIN[1]A_D[12]/ DVDD PINCNTL219 Cb/Cr and [15:8] are Y Port A inputs. For 8-bit capture,
GP3[11] DSIS: PIN D[7:0] are Port A YCbCr data inputs. For RGB capture,
VOUT[1]_G_Y_YC[6]/ VOUT[1], D[23:16] are R, D[15:8] are G, and D[7:0] are B Port A
EMAC[1]_GMTCLK/ IPD EMAC[1], GP3 data inputs.
AH27 I
VIN[1]A_D[11]/ DVDD PINCNTL218
GP3[10] DSIS: PIN
VOUT[1]_G_Y_YC[5]/ VOUT[1],
EMAC[1]_MRXDV/ IPD EMAC[1], GP3
AG26 I
VIN[1]A_D[10]/ DVDD PINCNTL217
GP3[9] DSIS: PIN
VOUT[1]_G_Y_YC[4]/ VOUT[1],
EMAC[1]_MRXD[7]/ IPD EMAC[1], GP3
W22 I
VIN[1]A_D[9]/ DVDD PINCNTL216
GP3[8] DSIS: PIN
VOUT[1]_G_Y_YC[3]/ VOUT[1],
EMAC[1]_MRXD[6]/ IPD EMAC[1], GP3
Y23 I
VIN[1]A_D[8]/ DVDD PINCNTL215
GP3[7] DSIS: PIN

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Table 3-44. Video Input 1 (Digital) Terminal Functions (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
VOUT[1]_B_CB_C[2]/
VOUT[1], GPMC,
GPMC_A[0]/
HDMI, SPI[2],
VIN[1]A_D[7]/ IPU
AF28 I GP3
HDMI_CEC/ DVDD
PINCNTL231
SPI[2]_D[0]/
DSIS: PIN
GP3[30]
VOUT[1]_B_CB_C[9]/ VOUT[1],
EMAC[1]_MRXD[5]/ EMAC[1], I2C[3],
IPD
VIN[1]A_D[6]/ AA24 I GP3
DVDD
I2C[3]_SDA/ PINCNTL214
GP3[6] DSIS: PIN
VOUT[1]_B_CB_C[8]/ VOUT[1],
EMAC[1]_MRXD[4]/ EMAC[1], I2C[3],
IPD
VIN[1]A_D[5]/ AH26 I GP3
DVDD
I2C[3]_SCL/ PINCNTL213
GP3[5] DSIS: PIN
VOUT[1]_B_CB_C[7]/ VOUT[1],
EMAC[1]_MRXD[3]/ EMAC[1],
IPD
VIN[1]A_D[4]/ AC25 I UART3, GP3 Video Input 1 Data inputs. For 16-bit capture, D[7:0] are
DVDD
UART3_TXD/ PINCNTL212 Cb/Cr and [15:8] are Y Port A inputs. For 8-bit capture,
GP3[4] DSIS: PIN D[7:0] are Port A YCbCr data inputs. For RGB capture,
VOUT[1]_B_CB_C[6]/ VOUT[1], D[23:16] are R, D[15:8] are G, and D[7:0] are B Port A
EMAC[1]_MRXD[2]/ EMAC[1], data inputs.
IPD
VIN[1]A_D[3]/ AD25 I UART3, GP3
DVDD
UART3_RXD/ PINCNTL211
GP3[3] DSIS: PIN
VOUT[1]_B_CB_C[5]/ VOUT[1],
EMAC[1]_MRXD[1]/ EMAC[1],
IPD
VIN[1]A_D[2]/ AF25 I UART4, GP3
DVDD
UART4_TXD/ PINCNTL210
GP3[2] DSIS: PIN
VOUT[1]_B_CB_C[4]/ VOUT[1],
EMAC[1]_MRXD[0]/ EMAC[1],
IPD
VIN[1]A_D[1]/ AG25 I UART4, GP3
DVDD
UART4_RXD/ PINCNTL209
GP3[1] DSIS: PIN
VOUT[1]_B_CB_C[3]/ VOUT[1],
EMAC[1]_MRCLK/ EMAC[1],
IPD
VIN[1]A_D[0]/ AH25 I UART4, GP3
DVDD
UART4_CTS/ PINCNTL208
GP3[0] DSIS: PIN
EMAC[0]_MRXD[2]/
EMAC[0]_RGRXD[1]/ EMAC[0], GP3
IPD
VIN[1]B_D[7]/ R23 I PINCNTL242
DVDD_GPMC
EMAC[0]_RMTXEN/ DSIS: PIN
GP3[30]
EMAC[0]_MRXD[1]/
EMAC[0]_RGRXD[0]/ EMAC[0], GP3
IPD
VIN[1]B_D[6]/ P23 I PINCNTL241
DVDD_GPMC
EMAC[0]_RMTXD[1]/ DSIS: PIN
GP3[29]
Video Input 1 Port B Data inputs. For 8-bit capture,
EMAC[0]_MRXD[0]/ B_D[7:0] are Port B YCbCr data inputs.
EMAC[0]_RGTXD[0]/ EMAC[0], GP3
IPD
VIN[1]B_D[5]/ G28 I PINCNTL240
DVDD_GPMC
EMAC[0]_RMTXD[0]/ DSIS: PIN
GP3[28]
EMAC[0]_MRCLK/
EMAC[0]_RGTXC/ EMAC[0], SPI[3],
VIN[1]B_D[4]/ IPD GP3
H27 I
EMAC[0]_RMCRSDV/ DVDD_GPMC PINCNTL239
SPI[3]_SCS[2]/ DSIS: PIN
GP3[27]

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Table 3-44. Video Input 1 (Digital) Terminal Functions (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
MUXED DESCRIPTION
NAME NO.
EMAC[0]_MRXER/
EMAC[0]_RGTXCTL/ EMAC[0], GP3
IPD
VIN[1]B_D[3]/ J26 I PINCNTL238
DVDD_GPMC
EMAC[0]_RMRXER/ DSIS: PIN
GP3[26]
EMAC[0]_MCRS/
EMAC[0]_RGRXD[2]/ EMAC[0], GP3
IPD
VIN[1]B_D[2]/ R25 I PINCNTL237
DVDD_GPMC
EMAC[0]_RMRXD[1]/ DSIS: PIN
GP3[25]
Video Input Port B Data inputs. For 8-bit capture,
EMAC[0]_MCOL/ B_D[7:0] are Port B YCbCr data inputs.
EMAC[0]_RGRXCTL/ EMAC[0], GP3
IPD
VIN[1]B_D[1]/ L23 I PINCNTL236
DVDD_GPMC
EMAC[0]_RMRXD[0]/ DSIS: PIN
GP3[24]
EMAC[0]_MTCLK/
EMAC[0]_RGRXC/ EMAC[0], SPI[3],
VIN[1]B_D[0]/ IPD I2C[2], GP3
L24 I
SPI[3]_SCS[3]/ DVDD_GPMC PINCNTL235
I2C[2]_SDA/ DSIS: PIN
GP3[23]
VOUT[1]_CLK/ VOUT[1], Video Input 1 Port A Horizontal Sync input. Discrete
EMAC[1]_MTCLK/ IPD EMAC[1], GP2 horizontal synchronization signal forPort A YCbCr
AE24 I
VIN[1]A_HSYNC/ DVDD PINCNTL204 capture modes without embedded syncs (“BT.601”
GP2[28] DSIS: 0 modes).
VOUT[1]_HSYNC/
VOUT[1],
EMAC[1]_MCOL/
EMAC[1], SPI[3], Video Input 1 Port A Vertical Sync input. Discrete vertical
VIN[1]A_VSYNC/ IPD
AC24 I UART3, GP2 synchronization signal for Port A YCbCr capture modes
SPI[3]_D[1]/ DVDD
PINCNTL205 without embedded syncs (“BT.601” modes).
UART3_RTS/
DSIS: 0
GP2[29]
VOUT[1]_VSYNC/
VOUT[1],
EMAC[1]_MCRS/
EMAC[1],
VIN[1]A_FLD/ Video Input 1 Port A Data Enable input. Discrete data
IPD VIN[1]A, SPI[3],
VIN[1]A_DE/ AA23 I valid signal for Port A YCbCr capture modes without
DVDD UART3, GP2
SPI[3]_D[0]/ embedded syncs (“BT.601” modes).
PINCNTL206
UART3_CTS/
DSIS: 0
GP2[30]
VOUT[1]_VSYNC/
VOUT[1],
EMAC[1]_MCRS/
EMAC[1],
VIN[1]A_FLD/ Video Input 1 Port A Field ID input. Discrete field
IPD VIN[1]A, SPI[3],
VIN[1]A_DE/ AA23 I identification signal for Port A YCbCr capture modes
DVDD UART3, GP2
SPI[3]_D[0]/ without embedded syncs (“BT.601” modes).
PINCNTL206
UART3_CTS/
DSIS: 0
GP2[30]

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3.2.23 Video Output (Digital)

Table 3-45. Video Output 0 (Digital) Terminal Functions

SIGNAL OTHER (2)
TYPE (1) (3) MUXED DESCRIPTION
NAME NO.
Video Output 0
IPD –
VOUT[0]_CLK AD12 O Video Output Clock output.
DVDD PINCNTL176
IPD –
VOUT[0]_G_Y_YC[9] AF14 O
DVDD PINCNTL195
IPD –
VOUT[0]_G_Y_YC[8] AE14 O
DVDD PINCNTL194
IPD –
VOUT[0]_G_Y_YC[7] AD14 O
DVDD PINCNTL193
IPD – Video Output Data. These signals represent the 8 MSBs
VOUT[0]_G_Y_YC[6] AA8 O
DVDD PINCNTL192 of G/Y/YC video data. For RGB mode they are green
IPD – data bits, for YUV444 mode they are Y data bits, for Y/C
VOUT[0]_G_Y_YC[5] AB12 O mode they are Y (Luma) data bits and for BT.656 mode
DVDD PINCNTL191
they are multiplexed Y/Cb/Cr (Luma and Chroma) data
IPD – bits.
VOUT[0]_G_Y_YC[4] AB8 O
DVDD PINCNTL190
GP2
VOUT[0]_G_Y_YC[3]/ IPD
AH15 O PINCNTL189
GP2[25] DVDD
DSIS: PIN
VOUT[0]_G_Y_YC[2]/ EMU, GP2
IPD
EMU3/ AH7 O PINCNTL188
DVDD
GP2[24] DSIS: PIN
IPD –
VOUT[0]_B_CB_C[9] AG15 O
DVDD PINCNTL187
IPD –
VOUT[0]_B_CB_C[8] AF15 O
DVDD PINCNTL186
IPD –
VOUT[0]_B_CB_C[7] AB10 O
DVDD PINCNTL185
IPD –
VOUT[0]_B_CB_C[6] AC10 O Video Output Data. These signals represent the 8 MSBs
DVDD PINCNTL184
of B/CB/C video data. For RGB mode they are blue data
IPD – bits, for YUV444 mode they are Cb (Chroma) data bits,
VOUT[0]_B_CB_C[5] AD15 O
DVDD PINCNTL183 for Y/C mode they are multiplexed Cb/Cr (Chroma) data
IPD – bits and for BT.656 mode they are unused.
VOUT[0]_B_CB_C[4] AD11 O
DVDD PINCNTL182
GP2
VOUT[0]_B_CB_C[3]/ IPD
AE15 O PINCNTL181
GP2[23] DVDD
DSIS: PIN
VOUT[0]_B_CB_C[2]/ EMU2, GP2
IPD
EMU2/ AG7 O PINCNTL180
DVDD
GP2[22] DSIS: PIN

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown
resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal
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Table 3-45. Video Output 0 (Digital) Terminal Functions (continued)

SIGNAL OTHER (2)
TYPE (1) (3) MUXED DESCRIPTION
NAME NO.
IPD –
VOUT[0]_R_CR[9]/ AC13 O
DVDD PINCNTL203
IPD –
VOUT[0]_R_CR[8]/ AE8 O
DVDD PINCNTL202
IPD –
VOUT[0]_R_CR[7]/ AF12 O
DVDD PINCNTL201
IPD –
VOUT[0]_R_CR[6]/ AF6 O
DVDD PINCNTL200 Video Output Data. These signals represent the 8 MSBs
IPD – of R/CR video data. For RGB mode they are red data
VOUT[0]_R_CR[5]/ AF8 O bits, for YUV444 mode they are Cr (Chroma) data bits,
DVDD PINCNTL199
for Y/C mode and BT.656 modes they are unused.
IPD –
VOUT[0]_R_CR[4]/ AA9 O
DVDD PINCNTL198
GP2
VOUT[0]_R_CR[3]/ IPD
AB9 O PINCNTL197
GP2[27] DVDD
DSIS: PIN
VOUT[0]_R_CR[2]/ EMU4, GP2
IPD
EMU4/ AD9 O PINCNTL196
DVDD
GP2[26] DSIS: PIN
Video Output Vertical Sync output. This is the discrete
IPD –
VOUT[0]_VSYNC AB13 O vertical synchronization output. This signal is not used
DVDD PINCNTL178
for embedded sync modes.
Video Output Horizontal Sync output. This is the discrete
IPD –
VOUT[0]_HSYNC AC11 O horizontal synchronization output. This signal is not used
DVDD PINCNTL177
for embedded sync modes.
CAMERA_I/F,
VOUT[0]_FLD/
GPMC, UART2,
CAM_PCLK/
IPD GP2
GPMC_A[12]/ AF18 O
DVDD_C PINCNTL175
UART2_RTS/
DSIS: N/A Video Output Field ID output. This is the discrete field
GP2[2]
MM: MUX1 identification output. This signal is not used for
VOUT[0]_AVID/ VOUT[0], SPI[3], embedded sync modes.
VOUT[0]_FLD/ TIMER7, GP2
IPD
SPI[3]_SCLK/ AA10 O PINCNTL179
DVDD
TIM7_IO/ DSIS: N/A
GP2[21] MM: MUX0
VOUT[0]_AVID/
VOUT[0], SPI[3],
VOUT[0]_FLD/ Video Output Active Video output. This is the discrete
IPD TIMER7, GP2
SPI[3]_SCLK/ AA10 O active video indicator output. This signal is not used for
DVDD PINCNTL179
TIM7_IO/ embedded sync modes.
DSIS: N/A
GP2[21]

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Table 3-46. Video Output 1 Terminal Functions

SIGNAL OTHER (2)
TYPE (1) (3) MUXED DESCRIPTION
NAME NO.
Video Output 1
VOUT[1]_CLK/ EMAC[1],
EMAC[1]_MTCLK/ IPD VIN[1]A, GP2
AE24 O Video Output Clock output
VIN[1]A_HSYNC/ DVDD PINCNTL204
GP2[28] DSIS: N/A
VOUT[1]_G_Y_YC[9]/ EMAC[1],
EMAC[1]_MTXD[2]/ IPD VIN[1]A, GP3
AD26 O
VIN[1]A_D[14]/ DVDD PINCNTL221
GP3[13] DSIS: N/A
VOUT[1]_G_Y_YC[8]/ EMAC[1],
EMAC[1]_MTXD[1]/ IPD VIN[1]A, GP3 Video Output Data. These signals represent the 8 MSBs
AE26 O
VIN[1]A_D[13]/ DVDD PINCNTL220 of G/Y/YC video data. For RGB mode they are green
GP3[12] DSIS: N/A data bits, for YUV444 mode they are Y data bits, for Y/C
VOUT[1]_G_Y_YC[7]/ EMAC[1], mode they are Y (Luma) data bits and for BT.656 mode
EMAC[1]_MTXD[0]/ IPD VIN[1]A, GP3 they are multiplexed Y/Cb/Cr (Luma and Chroma) data
AF26 O bits.
VIN[1]A_D[12]/ DVDD PINCNTL219
GP3[11] DSIS: N/A
VOUT[1]_G_Y_YC[6]/ EMAC[1],
EMAC[1]_GMTCLK/ IPD VIN[1]A, GP3
AH27 O
VIN[1]A_D[11]/ DVDD PINCNTL218
GP3[10] DSIS: N/A
VOUT[1]_G_Y_YC[5]/ EMAC[1],
EMAC[1]_MRXDV/ IPD VIN[1]A, GP3
AG26 O
VIN[1]A_D[10]/ DVDD PINCNTL217
GP3[9] DSIS: N/A
VOUT[1]_G_Y_YC[4]/ EMAC[1],
EMAC[1]_MRXD[7]/ IPD VIN[1]A, GP3
W22 O
VIN[1]A_D[9]/ DVDD PINCNTL216
GP3[8] DSIS: N/A Video Output Data. These signals represent the 8 MSBs
of G/Y/YC video data. For RGB mode they are green
VOUT[1]_G_Y_YC[3] EMAC[1], data bits, for YUV444 mode they are Y data bits, for Y/C
EMAC[1]_MRXD[6]/ IPD VIN[1]A, GP3 mode they are Y (Luma) data bits and for BT.656 mode
Y23 O
VIN[1]A_D[8]/ DVDD PINCNTL215 they are multiplexed Y/Cb/Cr (Luma and Chroma) data
GP3[7] DSIS: N/A bits.
VOUT[1]_G_Y_YC[2]/
GPMC_A[13]/ GPMC, VIN[1]A,
VIN[1]A_D[21]/ HDMI, SPI[2],
IPU
HDMI_SCL/ AF27 O I2C[2], GP3
DVDD
SPI[2]_SCS[2]/ PINCNTL228
I2C[2]_SCL/ DSIS: N/A
GP3[20]
VOUT[1]_G_Y_YC[1]/ CAMERA_I/F,
CAM_D[3]/ GPMC, UART4,
IPU Video Output Data. These signals represent the 2 LSBs
GPMC_A[5]/ AD18 O GP0
DVDD_C of G/Y/YC video data for 10-bit, 20-bit, and 30-bit video
UART4_RXD/ PINCNTL168
GP0[22] DSIS: N/A modes (VOUT[1] only). For RGB mode they are green
data bits, for YUV444 mode they are Y data bits, for Y/C
VOUT[1]_G_Y_YC[0]/ CAMERA_I/F, mode they are Y (Luma) data bits and for BT-656 mode
CAM_D[2]/ GPMC, UART4, they are multiplexed Y/Cb/Cr (Luma and Chroma) data
IPD
GPMC_A[6]/ AC18 O GP0 bits. These signals are not used in 8/16/24-bit modes.
DVDD_C
UART4_TXD/ PINCNTL169
GP0[23] DSIS: N/A

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown
resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal
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Table 3-46. Video Output 1 Terminal Functions (continued)

SIGNAL OTHER (2)
TYPE (1) (3) MUXED DESCRIPTION
NAME NO.
VOUT[1]_B_CB_C[9]/ EMAC[1],
EMAC[1]_MRXD[5]/ VIN[1]A, I2C[3],
IPD
VIN[1]A_D[6]/ AA24 O GP3
DVDD
I2C[3]_SDA/ PINCNTL214
GP3[6] DSIS: N/A
VOUT[1]_B_CB_C[8]/ EMAC[1],
EMAC[1]_MRXD[4]/ VIN[1]A, I2C[3],
IPD
VIN[1]A_D[5]/ AH26 O GP3
DVDD Video Output Data. These signals represent the 8 MSBs
I2C[3]_SCL/ PINCNTL213
GP3[5] DSIS: N/A of B/CB/C video data. For RGB mode they are blue data
bits, for YUV444 mode they are Cb (Chroma) data bits,
VOUT[1]_B_CB_C[7]/ EMAC[1], for Y/C mode they are multiplexed Cb/Cr (Luma) data
EMAC[1]_MRXD[3]/ VIN[1]A, UART3, bits, and for BT.656 mode they are not used.
IPD
VIN[1]A_D[4]/ AC25 O GP3
DVDD
UART3_TXD/ PINCNTL212
GP3[4] DSIS: N/A
VOUT[1]_B_CB_C[6]/ EMAC[1],
EMAC[1]_MRXD[2]/ VIN[1]A, UART3,
IPD
VIN[1]A_D[3]/ AD25 O GP3
DVDD
UART3_RXD/ PINCNTL211
GP3[3] DSIS: N/A
VOUT[1]_B_CB_C[5]/ EMAC[1],
EMAC[1]_MRXD[1]/ VIN[1]A, UART4,
IPD
VIN[1]A_D[2]/ AF25 O GP3
DVDD
UART4_TXD/ PINCNTL210
GP3[2] DSIS: N/A
VOUT[1]_B_CB_C[4]/ EMAC[1],
EMAC[1]_MRXD[0]/ VIN[1]A, UART4,
IPD
VIN[1]A_D[1]/ AG25 O GP3
DVDD
UART4_RXD/ PINCNTL209 Video Output Data. These signals represent the 8 MSBs
GP3[1] DSIS: N/A of B/CB/C video data. For RGB mode they are blue data
VOUT[1]_B_CB_C[3]/ EMAC[1], bits, for YUV444 mode they are Cb (Chroma) data bits,
EMAC[1]_MRCLK/ VIN[1]A, UART4, for Y/C mode they are multiplexed Cb/Cr (Luma) data
IPD bits, and for BT.656 mode they are not used.
VIN[1]A_D[0]/ AH25 O GP3
DVDD
UART4_CTS/ PINCNTL208
GP3[0] DSIS: N/A
VOUT[1]_B_CB_C[2]/
GPMC, VIN[1]A,
GPMC_A[0]/
HDMI, SPI[2],
VIN[1]A_D[7]/ IPU
AF28 O GP3
HDMI_CEC/ DVDD
PINCNTL231
SPI[2]_D[0]/
DSIS: N/A
GP3[30]
VOUT[1]_B_CB_C[1]/ CAMERA_I/F,
CAM_HS/ GPMC, UART2,
IPD Video Output Data. These signals represent the 2 LSBs
GPMC_A[9]/ AE23 O GP0
DVDD_C of B/CB/C video data for 20-bit, and 30-bit video modes.
UART2_RXD/ PINCNTL172
GP0[26] DSIS: N/A For RGB mode they are blue data bits, for YUV444 mode
they are Cb (Chroma) data bits, for Y/C mode they are
VOUT[1]_B_CB_C[0]/ CAMERA_I/F, multiplexed Cb/Cr (Chroma) data bits and for BT.656
CAM_VS/ GPMC, UART2, mode they are unused. These signals are not used in
IPU
GPMC_A[10]/ AD23 O GP0 16/24-bit modes.
DVDD_C
UART2_TXD/ PINCNTL173
GP0[27] DSIS: N/A

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Table 3-46. Video Output 1 Terminal Functions (continued)

SIGNAL OTHER (2)
TYPE (1) (3) MUXED DESCRIPTION
NAME NO.
VOUT[1]_R_CR[9]/ EMAC[1],
EMAC[1]_MTXEN/ VIN[1]A, UART5,
IPD
VIN[1]A_D[20]/ Y24 O GP3
DVDD
UART5_TXD/ PINCNTL227
GP3[19] DSIS: N/A
VOUT[1]_R_CR[8]/ EMAC[1],
EMAC[1]_MTXD[7]/ VIN[1]A, UART5,
IPD
VIN[1]A_D[19]/ W23 O GP3
DVDD
UART5_RXD/ PINCNTL226 Video Output Data. These signals represent the 8 MSBs
GP3[18] DSIS: N/A of R/CR video data. For RGB mode they are red data
VOUT[1]_R_CR[7]/ EMAC[1], bits, for YUV444 mode they are Cr (Chroma) data bits,
EMAC[1]_MTXD[6]/ VIN[1]A, SPI[3], for Y/C mode and BT.656 mode they are not used.
IPD
VIN[1]A_D[18]/ V22 O GP3
DVDD
SPI[3]_D[0]/ PINCNTL225
GP3[17] DSIS: N/A
VOUT[1]_R_CR[6]/ EMAC[1],
EMAC[1]_MTXD[5]/ VIN[1]A, SPI[3],
IPD
VIN[1]A_D[17]/ AA25 O GP3
DVDD
SPI[3]_D[1]/ PINCNTL224
GP3[16] DSIS: N/A
VOUT[1]_R_CR[5]/ EMAC[1],
EMAC[1]_MTXD[4]/ VIN[1]A, SPI[3],
IPD
VIN[1]A_D[16]/ AC26 O GP3
DVDD
SPI[3]_SCLK/ PINCNTL223
GP3[15] DSIS: N/A
VOUT[1]_R_CR[4]/ EMAC[1],
EMAC[1]_MTXD[3]/ VIN[1]A, SPI[3],
IPD
VIN[1]A_D[15]/ AG27 O GP3
DVDD
SPI[3]_SCS[1]/ PINCNTL222
GP3[14] DSIS: N/A
Video Output Data. These signals represent the 8 MSBs
VOUT[1]_R_CR[3]/ of R/CR video data. For RGB mode they are red data
GPMC_A[14]/ GPMC, VIN[1]A, bits, for YUV444 mode they are Cr (Chroma) data bits,
VIN[1]A_D[22]/ HDMI, SPI[2], for Y/C mode and BT.656 mode they are not used.
IPU
HDMI_SDA/ AG28 O I2C[2], GP3
DVDD
SPI[2]_SCLK/ PINCNTL229
I2C[2]_SDA/ DSIS: N/A
GP3[21]
VOUT[1]_R_CR[2]/
GPMC, VIN[1]A,
GPMC_A[15]/
HDMI, SPI[2],
VIN[1]A_D[23]/ IPU
AE27 O I2C[2], GP3
HDMI_HPDET/ DVDD
PINCNTL230
SPI[2]_D[1]/
DSIS: N/A
GP3[22]
VOUT[1]_R_CR[1]/ CAMERA_I/F,
CAM_D[1]/ GPMC, UART4,
IPD
GPMC_A[7]/ AC19 O GP0 Video Output Data. These signals represent the 2 LSBs
DVDD_C
UART4_CTS/ PINCNTL170 of R/CR video data for 30-bit video modes. For RGB
GP0[24] DSIS: N/A mode they are red data bits, for YUV444 mode they are
VOUT[1]_R_CR[0]/ CAMERA_I/F, Cr (Chroma) data bits, for Y/C mode and BT.656 modes
CAM_D[0]/ GPMC, UART4, they are not used. These signals are not used in 24-bit
IPD mode.
GPMC_A[8]/ AA22 O GP0
DVDD_C
UART4_RTS/ PINCNTL171
GP0[25] DSIS: N/A
VOUT[1]_VSYNC/
EMAC[1]_MCRS/ EMAC[1],
VIN[1]A_FLD/ VIN[1]A, SPI[3], Video Output Vertical Sync output. This is the discrete
IPD
VIN[1]A_DE/ AA23 O UART3, GP2 vertical synchronization output. This signal is not used for
DVDD
SPI[3]_D[0]/ PINCNTL206 embedded sync modes
UART3_CTS/ DSIS: N/A
GP2[30]

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Table 3-46. Video Output 1 Terminal Functions (continued)

SIGNAL OTHER (2)
TYPE (1) (3) MUXED DESCRIPTION
NAME NO.
VOUT[1]_HSYNC/
EMAC[1],
EMAC[1]_MCOL/
VIN[1]A, SPI[3], Video Output Horizontal Sync output. This is the discrete
VIN[1]A_VSYNC/ IPD
AC24 O UART3, GP2 horizontal synchronization output. This signal is not used
SPI[3]_D[1]/ DVDD
PINCNTL205 for embedded sync modes.
UART3_RTS/
DSIS: N/A
GP2[29]
VOUT[1]_FLD/
CAMERA_I/F,
CAM_FLD/
GPMC, UART2, Video Output Field ID output. This is the discrete field
CAM_WE/ IPD
AB23 O GP0 identification output. This signal is not used for embedded
GPMC_A[11]/ DVDD_C
PINCNTL174 sync modes.
UART2_CTS/
DSIS: N/A
GP0[28]
VOUT[1]_AVID/
EMAC[1],
EMAC[1]_MRXER/
VIN[1]A, UART4, Video Output Active Video output. This is the discrete
VIN[1]A_CLK/ IPD
Y22 O TIMER6, GP2 active video indicator output. This signal is not used for
UART4_RTS/ DVDD
PINCNTL207 embedded sync modes.
TIM6_IO/
DSIS: N/A
GP2[31]

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3.2.24 Video Output (Analog, TV)

Table 3-47. Video Outupt (Analog, TV) Terminal Functions

SIGNAL
TYPE (1) OTHER (2) (3)
DESCRIPTION
NAME NO.
VIDEO INTERFACES (TV)
Composite/S-Video (Luminance) Amplifier Output.
In Normal mode (internal amplifier used), this pin drives the 75-Ω TV
load. An external resistor (Rout) should be connected between this pin
and the TV_VFB0 pin and be placed as close to the pins as possible.
– The nominal value of Rout is 2700 Ω.
TV_OUT0 AH24 O
VDDA_VDAC_1P8
In TVOUT Bypass mode (internal amplifier not used), this pin is not
used.
When this pin is not used or the TV output is powered-down, this pin
should be left unconnected.
S-Video (Chrominance) Amplifier Output.
In Normal mode (internal amplifier used), this pin drives the 75-Ω TV
load.
An external resistor (Rout) should be connected between this pin and
– the TV_VFB1 pin and be placed as close to the pins as possible. The
TV_OUT1 AH22 O
VDDA_VDAC_1P8 nominal value of Rout is 2700 Ω.
In TVOUT Bypass mode (internal amplifier not used), this pin is not
used.
When this pin is not used or the TV output is powered-down, this pin
should be left unconnected.
Composite/S-Video (Luminance) Feedback.
In Normal mode (internal amplifier used), this pin acts as the buffer
feedback node.
An external resistor (Rout) should be connected between this pin and
the TV_OUT0 pin.
–
TV_VFB0 AG23 AO
VDDA_VDAC_1P8 In TVOUT Bypass mode (internal amplifier not used), this pin acts as
the direct Video DAC output and should be connected to ground
through a load resistor (Rload) and to an external video amplifier. The
nominal value of Rload is 1500 Ω.
When this pin is not used or the TV output is powered-down, this pin
should be left unconnected.
S-Video (Chrominance) Feedback.
In Normal mode (internal amplifier used), this pin acts as the buffer
feedback node.
An external resistor (Rout) should be connected between this pin and
the TV_OUT1 pin.
–
TV_VFB1 AG22 AO
VDDA_VDAC_1P8 In TVOUT Bypass mode (internal amplifier not used), it acts as the
direct Video DAC output and should be connected to ground through
a load resistor (Rload) and to an external video amplifier. The nominal
value of Rload is 1500 Ω.
When this pin is not used or the TV output is powered-down, this pin
should be left unconnected.

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown
resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal
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Table 3-47. Video Outupt (Analog, TV) Terminal Functions (continued)

SIGNAL
TYPE (1) OTHER (2) (3)
DESCRIPTION
NAME NO.
TV Input Reference Current Setting.
An external resistor (Rset) should be connected between this pin and
VSSA_VDAC to set the reference current of the video DAC. The value
of the resistor depends on the mode of operation.

– In Normal mode (internal amplifier used), the nominal value for Rset
TV_RSET AH23 A
VDDA_VDAC_1P8 is 4700 Ω.
In TVOUT Bypass mode (internal amplifier not used), the nominal
value for Rset is 10000 Ω.
When the TV output is not used, this pin should be connected to
ground (VSS).

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3.2.25 Reserved Pins

Table 3-48. Reserved Terminal Functions

SIGNAL
TYPE (1) OTHER DESCRIPTION
NAME NO.
RSV1 AD8 O Reserved. (Leave unconnected, do not connect to power or ground.)
RSV2 U8 O Reserved. (Leave unconnected, do not connect to power or ground.)
RSV3 V8 O Reserved. (Leave unconnected, do not connect to power or ground.)
RSV4 Y14 I
Reserved. (Leave unconnected, do not connect to power or ground.)
RSV5 AC8 I
RSV6 L27 I
RSV7 L28 I
RSV8 M27 I
RSV9 M28 I
RSV10 N28 I
Reserved. (Leave unconnected, do not connect to power or ground.)
RSV11 N27 I
RSV12 P28 I
RSV13 P27 I
RSV14 R27 I
RSV15 R28 I
RSV16 U1 I Reserved. (Leave unconnected, do not connect to power or ground.)
RSV17 U2 I Reserved. (Leave unconnected, do not connect to power or ground.)
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State

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3.2.26 Supply Voltages

Table 3-49. Supply Voltages Terminal Functions

SIGNAL
TYPE (1) OTHER DESCRIPTION
NAME NO.
VREFSSTL_DDR[0] G15 S Reference Power Supply DDR[0]
VREFSSTL_DDR[1] G14 S Reference Power Supply DDR[1]
CVDD K9, K12, S Variable Voltage Supply for the CORE_L Core Logic Voltage
K18, L15, Domain
L17, L19, For actual voltage supply ranges, see Section 6.2, Recommended
M16, M18, Operating Conditions.
N17, N19,
P12, P14,
P16, R15,
R17, R19,
T12, U11,
U13, U17,
U19, W11
CVDD_ARM T14, T15, S Variable Voltage Supply for the ARM_L Core Logic Voltage
T16, U15, Domain
U16, V15, For actual voltage supply ranges, see Section 6.2, Recommended
V16 Operating Conditions.
CVDD_DSP K10, L9, L10, S Variable Voltage Supply for the DSP_L Core Logic Voltage
L11, L12, Domain
M10, M12, For actual voltage supply ranges, see Section 6.2, Recommended
N9 Operating Conditions.
CVDD_HDVICP L14, M13, S Variable Voltage Supply for the HDVICP_L Core Logic Voltage
M14, N13, Domain
N14 For actual voltage supply ranges, see Section 6.2, Recommended
Operating Conditions.
DVDD M8, N7, P8, S 3.3 V/1.8 V Power Supply for General I/Os
T7, U21,
U22,
V20,Y11,
Y16, AA15,
AA17, AB14,
AB16
DVDD_GPMC K20, L21, S 3.3 V/1.8 V Power Supply for GPMC I/Os (that is, GPMC, SD2,
M20 and so forth)
DVDD_GPMCB P20, T20 S 3.3 V/1.8 V Power Supply for GPMCB I/Os
DVDD_SD P7, P9 S 3.3 V/1.8 V Power Supply for MMC/SD/SDIO I/Os (specifically,
SD0, SD1, and pin W6)
DVDD_DDR[0] E20, E21, S 1.5 V/1.8 V Power Supply for DDR[0] I/Os
G16, H16,
H17, J15,
J16, J17, J18
DVDD_DDR[1] E8, E9, G13, S 1.5 V/1.8 V Power Supply for DDR[1] I/Os
H12, H13,
H14, J10,
J11, J13
DVDD_M R10 S 1.8 V Power Supply . For proper device operation, this pin must
always be connected to a 1.8-V Power Supply.
DVDD_C W19, W20 S 3.3 V/1.8 V Power Supply for Camera I/F I/Os
VDDA_ARMPLL_1P8 R13 S 1.8 V Analog Power Supply for PLL_ARM and PLL_SGX
VDDA_DSPPLL_1P8 P11 S 1.8 V Analog Power Supply for PLL_DSP and PLL_HDVICP
VDDA_VID0PLL_1P8 AB18 S 1.8 V Analog Power Supply for PLL_VIDEO0
VDDA_VID1PLL_1P8 AA18 S 1.8 V Analog Power Supply for PLL_VIDEO1
VDDA_AUDIOPLL_1P8 R18 S 1.8 V Analog Power Supply for PLL_AUDIO
VDDA_DDRPLL_1P8 H15 S 1.8 V Analog Power Supply for PLL_DDR

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
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Table 3-49. Supply Voltages Terminal Functions (continued)

SIGNAL
TYPE (1) OTHER DESCRIPTION
NAME NO.
VDDA_L3PLL_1P8 N18 S 1.8 V Analog Power Supply for PLL_L3, PLL_HDVPSS, and
PLL_MEDIACTL
VDDA_PCIE_1P8 W9, W10 S 1.8 V Analog Power Supply for PCIe.
For proper device operation, this pin must always be connected
to a 1.8-V Power Supply, even if the PCIe is not being used.
VDDA_SATA_1P8 U9, U10 S 1.8 V Analog Power Supply for SATA.
For proper device operation, this pin must always be connected
to a 1.8-V Power Supply, even if the SATA is not being used.
VDDA_HDMI_1P8 W18 S 1.8 V Analog Power Supply for HDMI.
For proper device operation, this pin must always be connected
to a 1.8-V Power Supply, even if the HDMI is not being used.
VDDA_USB0_1P8 AA12 S 1.8 V Analog Power Supply for USB0.
For proper device operation, this pin must always be connected
to a 1.8-V Power Supply, even if the USB0 is not being used.
VDDA_USB1_1P8 W13 S 1.8 V Analog Power Supply for USB1.
For proper device operation, this pin must always be connected
to a 1.8-V Power Supply, even if the USB1 is not being used.
VDDA_VDAC_1P8 AB19 S 1.8 V Reference Power Supply for VDAC.
For proper device operation, this pin must always be connected
to a 1.8-V Power Supply, even if the VDAC is not being used.
VDDA_USB_3P3 AA13 S 3.3 V Analog Power Supply for USB0 and USB1.
For proper device operation, this pin must always be connected
to a 3.3-V Power Supply, even if USB0 and USB1 are not being
used.
VDDA_1P8 L20, M7, S 1.8 V Power Supply for on-chip LDOs and I/O biasing
M22, R20,
U7, V10,
W15, Y13
LDOCAP_ARM W14 A ARM Cortex-A8 VBB LDO output.
This pin must always be connected via a 1-uF capacitor to VSS.
LDOCAP_ARMRAM V14 A ARM Cortex-A8 RAM LDO output.
This pin must always be connected via a 1-uF capacitor to VSS.
LDOCAP_RAM0 P18 A CORE RAM0 LDO output.
This pin must always be connected via a 1-uF capacitor to VSS.
LDOCAP_RAM1 R11 A CORE RAM1 LDO output.
This pin must always be connected via a 1-uF capacitor to VSS.
LDOCAP_RAM2 L18 A CORE RAM2 LDO output.
This pin must always be connected via a 1-uF capacitor to VSS.
LDOCAP_DSP P10 A C674x DSP VBB LDO output.
This pin must always be connected via a 1-uF capacitor to VSS.
LDOCAP_DSPRAM M11 A C674x DSP RAM LDO output.
This pin must always be connected via a 1-uF capacitor to VSS.
LDOCAP_HDVICP N10 A HDVICP2 VBB LDO output.
This pin must always be connected via a 1-uF capacitor to VSS.
LDOCAP_HDVICPRAM N11 A HDVICP2 RAM LDO output.
This pin must always be connected via a 1-uF capacitor to VSS.
LDOCAP_SGX T10 A SGX530 VBB LDO output.
This pin must always be connected via a 1-uF capacitor to VSS.
LDOCAP_SERDESCLK T11 A SERDES_CLKP/N Pins LDO output.
This pin must always be connected via a 1-uF capacitor to VSS.

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3.2.27 Ground Pins (VSS)

Table 3-50. Ground Terminal Functions

SIGNAL
TYPE (1) OTHER DESCRIPTION
NAME NO.
VSS A1, A12, GND Ground (GND)
A17, A28,
D9, D20, J12,
J14, J19,
K11, K13,
K14, K15,
K16, K17,
K19, L8, L13,
L16, L22, M9,
M15, M17,
M19, M21,
N8, N12,
N15, N16,
N20, N21,
N22, P13,
P15, P17,
P19, P21,
R8, R9, R12,
R14, R16,
R21, R22,
T8, T9, T13,
T17, T18,
T19, T21,
T22, U12,
U14, U18,
U20, V7, V9,
V11, V17,
V19, V21,
W12, W16,
W17, Y1, Y2,
Y10, Y12,
Y15, Y17,
Y18, Y19,
AA14, AA16,
AD21, AE1,
AE2, AE9,
AE20, AF23,
AG1, AH1,
AH28
VSSA_VDAC AA19 GND Analog GND for VDAC.
For proper device operation, this pin must always be connected to ground,
even if the VDAC is not being used.
VSSA_HDMI V18 GND Analog GND for HDMI
For proper device operation, this pin must always be connected to ground,
even if the HDMI is not being used.
VSSA_USB V12, V13 GND Analog GND for USB0 and USB1.
For proper device operation, this pin must always be connected to ground,
even if USB0 and USB1 are not being used.
VSSA_DEVOSC AG3 GND Ground for Device Oscillator
VSSA_AUXOSC R2 GND Ground for Auxiliary Oscillator
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State

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4 Device Configurations

4.1 Control Module Registers

4.2 Boot Modes

The state of the device after boot is determined by sampling the input states of the BTMODE[15:0] pins
when device reset (POR or RESET) is de-asserted. The sampled values are latched into the
CONTROL_STATUS register, which is part of the Control Module. The BTMODE[15:11] values determine
the following system boot settings:
• RSTOUT_WD_OUT Control
• GPMC CS0 Default Data Bus Width, Wait Enable, and Address/Data Multiplexing
For additional details on BTMODE[15:11] pin functions, see Table 3-1, Boot Configuration Terminal
Functions.
The BTMODE[4:0] values determine the boot mode order according to Table 4-1, Boot Mode Order. The
1st boot mode listed for each BTMODE[4:0] configuration is executed as the primary boot mode. If the
primary boot mode fails, the 2nd, 3rd, and 4th boot modes are executed in that order until a successful
boot is completed.
The BTMODE[7:5] pins are RESERVED and should be pulled down as indicated inTable 3-1, Boot
Configuration Terminal Functions.
When the EMAC bootmode is selected (see Table 4-1), the sampled value from BTMODE[9:8] pins are
used to determine the Ethernet PHY Mode selection (see Table 4-7).
When the XIP (MUX0), XIP (MUX1), XIP w/ WAiT (MUX0) or XIP w/ WAiT (MUX1) bootmode is selected
(see Table 4-1), the sampled value from BTMODE[10] pin is used to select between GPMC pin muxing
options shown in Table 4-2, XIP (on GPMC) Boot Options [Muxed or Non-Muxed].
For more detailed information on booting the device, see the ROM Code Memory and Peripheral Booting
chapter of the TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual (Literature
Number: SPRUGZ8).

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Table 4-1. Boot Mode Order

BTMODE[4:0] 1st 2nd 3rd 4th
00000 RESERVED RESERVED RESERVED RESERVED
00001 UART XIP w/WAIT (MUX0) (1) (2) MMC SPI
00010 UART SPI NAND NANDI2C
00011 UART SPI XIP (MUX0) (1) (2) MMC
(3)
00100 EMAC SPI NAND NANDI2C
00101 RESERVED RESERVED RESERVED RESERVED
00110 RESERVED RESERVED RESERVED RESERVED
00111 EMAC (3) MMC SPI XIP (MUX1) (1) (2)
01000 PCIE_32 (4) RESERVED RESERVED RESERVED
(4)
01001 PCIE_64 RESERVED RESERVED RESERVED
01010 RESERVED RESERVED RESERVED RESERVED
01011 RESERVED RESERVED RESERVED RESERVED
01100 RESERVED RESERVED RESERVED RESERVED
01101 RESERVED RESERVED RESERVED RESERVED
01110 RESERVED RESERVED RESERVED RESERVED
01111 Fast XIP (MUX0) (1) UART EMAC (3) PCIE_64 (4)
(1) (2) (3)
10000 XIP (MUX1) UART EMAC MMC
10001 XIP w/WAIT (MUX1) (1) (2) UART EMAC (3) MMC
10010 NAND NANDI2C SPI UART
10011 NAND NANDI2C MMC UART
10100 NAND NANDI2C SPI EMAC (3)
10101 NANDI2C MMC EMAC (3) UART
10110 SPI MMC UART EMAC (3)
10111 MMC SPI UART EMAC (3)
(4)
11000 SPI MMC PCIE_32 RESERVED
11001 SPI MMC PCIE_64 (4) RESERVED
(1) (2)
11010 XIP (MUX0) UART SPI MMC
11011 XIP w/WAIT (MUX0) (1) (2) UART SPI MMC
11100 RESERVED RESERVED RESERVED RESERVED
11101 RESERVED RESERVED RESERVED RESERVED
11110 RESERVED RESERVED RESERVED RESERVED
11111 Fast XIP (MUX0) (1) EMAC (3) UART PCIE_32 (4)
(1) GPMC CS0 eXecute In Place (XIP) boot for NOR/OneNAND/ROM. MUX0/1 refers to the multiplexing option for the GPMC_A[12:0] pins.
For more detailed information on booting the device, including which pins are used for each boot mode, see the ROM Code Memory
and Peripheral Booting chapter of the TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual (Literature
Number: SPRUGZ8).
(2) When the XIP (MUX0), XIP (MUX1), XIP w/ WAiT (MUX0) or XIP w/ WAiT (MUX1) bootmode is selected, the sampled value from
BTMODE[10] pin is used to select between GPMC pin configuration options shown in Table 4-2, XIP (on GPMC) Boot Options.
(3) When the EMAC bootmode is selected, the sampled value from BTMODE[9:8] pins are used to determine the Ethernet PHY Mode
Selection (see Table 4-7).
(4) When the PCIe bootmode is selected (PCIE_32 or PCI_64), the sampled value from BTMODE[15:12] pins are used to determine the
addressing options. For more detailed information on the PCIe addressing options, see the ROM Code Memory and Peripheral Booting
chapter of the TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual (Literature Number: SPRUGZ8).

4.2.1 XIP (NOR) Boot Options

Table 4-2 shows the XIP (NOR) boot mode GPMC pin configuration options (Option A: BTMODE[10] = 0
and Option B: BTMODE[10] = 1). For Option B, the pull state on select pins is reconfigured to IPD and
remains IPD after boot until the user software reconfigures it.

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Table 4-2. XIP (on GPMC) Boot Options

CONTROLLED I/O FUNCTION DURING XIP (NOR) BOOT
BTMODE[10] = 0 [OPTION A] BTMODE[10] = 1 [OPTION B]
SIGNAL NAME PIN NO. OTHER CONDITIONS
PULL PULL
PIN FUNCTION PIN FUNCTION
STATE STATE
GPMC_CS[0]/* T28 GPMC_CS[0] IPU GPMC_CS[0] IPU
M26 BTMODE[14:13] = 01b or 10b (Mux) GPMC_ADV_ALE IPU GPMC_ADV_ALE IPU
GPMC_ADV_ALE/*
BTMODE[14:13] = 00b (Non-Mux) Default
GPMC_OE_RE T27 GPMC_OE_RE IPU GPMC_OE_RE IPU
GPMC_BE[0]_CLE/GPMC_A[25]/* U27 GPMC_BE[0]_CLE IPD Default IPD
GPMC_BE[1]/GPMC_A[24]/* V28 Default IPD Default IPD
GPMC_WE U28 GPMC_WE IPU GPMC_WE IPU
W28 BTMODE[15] = 1b (WAIT Used/Enabled) GPMC_WAIT[0] IPU GPMC_WAIT[0] IPU
GPMC_WAIT[0]/GPMC_A[26]/* BTMODE[15] = 0b (WAIT Not Default IPD (1)
Used/Disabled)
GPMC_CLK/* R26 GPMC_CLK IPU Default IPU
Y25,V24,U23,U24,AA27,Y26,AB GPMC_D[15:0] Off GPMC_D[15:0] Off
GPMC_D[15:0]/* 28,Y27,V25,U25,AA28,V26,W27,
V27,Y28,U26
J25 BTMODE[12] = 0b (8-bit Mode) GPMC_A[0] IPD GPMC_A[0] IPD
*/GPMC_A[27]/GPMC_A[26]/GPMC_A[0]/*
BTMODE[12] = 1b (16-bit Mode) Default
T23,H26,F28,G27,K22,K23,J24, XIP_MUX0 Mode GPMC_A[1:12] IPD GPMC_A[1:12] IPD
*/GPMC_A[1:12]/* (M0) H25,H22,H23,G23,F27
XIP_MUX1 Mode Default IPD Default IPD
J28,K27,M24,L26,AD18,AC18,A XIP_MUX0 Mode Default Default Default Default
*/GPMC_A[1:12]/* (M1) C19,AA22,AE23,AD23,AB23,AF
XIP_MUX1 Mode GPMC_A[1:12] Default GPMC_A[1:12] Default
18
*/GPMC_A[13:15]/* (M0) J22,H24,J23 Default IPD Default IPD
AF28 BTMODE[12] = 0b (8-bit Mode) Default IPU Default IPU
*/GPMC_A[0]/* (M1)
BTMODE[12] = 1b (16-bit Mode)
AF27 BTMODE[14:13] = 01b or 10b (Mux) Default IPU Default IPU
*/GPMC_A[13]/* (M1)
BTMODE[14:13] = 00b (Non-Mux) IPD (1)
AG28 BTMODE[14:13] = 01b or 10b (Mux) Default IPU Default IPU
*/GPMC_A[14]/* (M1)
BTMODE[14:13] = 00b (Non-Mux) IPD (1)
*/GPMC_A[15]/* (M1) AE27 Default IPD Default IPD
GPMC_A[16:19]/* AD27,V23,AE28,AC27 Default IPD Default IPD
GPMC_A[20] (M0) AD28 Default IPU Default IPD (1)
GPMC_A[21] (M0) AC28 Default IPD Default IPD
GPMC_A[22] (M0) AB27 Default IPU Default IPD (1)
GPMC_A[23] (M0) AA26 Default IPD Default IPD

(1) After initial power-up the internal pullup (IPU) will be at its default configuration of IPU. During the boot ROM execution, the pull state is reconfigured to IPD and it remains IPD after boot
until the user software reconfigures it.

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Table 4-2. XIP (on GPMC) Boot Options (continued)

CONTROLLED I/O FUNCTION DURING XIP (NOR) BOOT
BTMODE[10] = 0 [OPTION A] BTMODE[10] = 1 [OPTION B]
SIGNAL NAME PIN NO. OTHER CONDITIONS
PULL PULL
PIN FUNCTION PIN FUNCTION
STATE STATE
*/GPMC_A[24]/GPMC_A[20]/* L25 Default IPU Default IPD (1)
*/GPMC_A[25]/GPMC_A[21]/* N23 Default IPU Default IPD (1)
*/GPMC_A[26]/GPMC_A[22]/* P22 Default IPU Default IPD (1)
*/GPMC_A[27]/GPMC_A[23]/* R24 Default IPU Default IPU
GPMC_A[24] (M1) M25 Default IPU Default IPU
GPMC_A[25] (M1) K28 Default IPU Default IPU

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4.2.2 NAND Flash Boot

Table 4-3 lists the device pins that are configured by the ROM for the NAND Flash boot mode.
NOTE: Table 4-3 lists the configuration of the GPMC_CLK pin (pin mux and pull state) in NAND
bootmodes.
The NAND flash memory is not XIP and requires shadowing before the code can be executed.

Table 4-3. Pins Used in NAND FLASH Bootmode

OTHER
SIGNAL NAME PIN NO. TYPE
CONDITIONS
GPMC_CS[0]/* T28 O
GPMC_ADV_ALE/* M26 O
BTMODE[12] = 0b
GPMC_OE_RE T27 O (8-bit Mode)
GPMC_BE[0]_CLE/GPMC_A[25]/* U27 O BTMODE[12] = 1b
(16-bit Mode)
GPMC_BE[1]/GPMC_A[24]/* V28 O
GPMC_WE U28 O
BTMODE[14:13] =
GPMC_WAIT[0]/GPMC_A[26]/* (1) W28 I 00b (GPMC CS0
GPMC_CLK/* R26 O not muxed)

Y25,V24,U23,U24,
AA27,Y26,AB28,Y2 BTMODE[15] = 0b
GPMC_D[15:0]/* 7, I/O (wait disabled)
V25,U25,AA28,V26
,W27,V27,Y28,U26
(1) GPMC_CLK/* is not configured in BTMODE[10] = 1 [OPTION B]

4.2.3 NAND I2C Boot (I2C EEPROM)

Table 4-4 lists the device pins that are configured by the ROM for the NAND I2C boot mode.

Table 4-4. Pins Used in NAND I2C Bootmode

SIGNAL NAME PIN NO. TYPE
I2C[0]_SCL AC4 I/O
I2C[0]_SDA AB6 I/O

4.2.4 MMC/SD Cards Boot

Table 4-5 lists the device pins that are configured by the ROM for the MMC/SD boot mode.

Table 4-5. Pins Used in MMC/SD Bootmode

SIGNAL NAME PIN NO. TYPE
SD1_CLK P3 O
SD1_CMD/GP0[0] [MUX0] P2 O
SD1_DAT[0] P1 I/O
SD1_DAT[1]_SDIRQ P5 I/O
SD_DAT[2]_SDRW P4 I/O
SD1_DAT[3] P6 I/O

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4.2.5 SPI Boot

Table 4-6 lists the device pins that are configured by the ROM for the SPI boot mode.

Table 4-6. Pins Used in SPI Bootmode

SIGNAL NAME PIN NO. TYPE
SPI[0]_SCS[0] AD6 I/O
SPI[0]_D[0] (MISO) AE3 I/O
SPI[0]_D[1] (MOSI) AF3 I/O
SPI[0]_SCLK AC7 I/O

4.2.6 Ethernet PHY Mode Selection

When the EMAC bootmode is selected, via the BTMODE[4:0] pins (see Table 4-1), Table 4-7 shows the
sampled value of BTMODE[9:8] pins and the Ethernet PHY Mode selection.
Table 4-8 shows the signal names (pin functions) and the associated pin numbers selected in each
particular EMAC mode.

Table 4-7. EMAC PHY Mode Selection

ETHERNET PHY MODE
BTMODE[9:8]
SELECTION
00b MII
01b RMII
10b RGMII
11b RESERVED

Table 4-8. Pins Used in EMAC[0] MII/GMII, RGMII, and RMII Boot Modes
SIGNAL NAMES
PIN NO.
MII/GMII TYPE RGMII TYPE RMII TYPE
Output
J27 DEFAULT DEFAULT EMAC_RMREFCLK
only
L23 EMAC[0]_MCOL I EMAC[0]_RGRXCTL I EMAC[0]_RMRXD[0] I
R25 EMAC[0]_MCRS I EMAC[0]_RGRXD[2] I EMAC[0]_RMRXD[1] I
K23 EMAC[0]_GMTCLK O DEFAULT DEFAULT
H27 EMAC[0]_MRCLK I EMAC[0]_RGTXC O EMC[0]_RMCRSDV I
G28 EMAC[0]_MRXD[0] I EMAC[0]_RGTXD[0] O EMAC[0]_RMTXD[0] O
P23 EMAC[0]_MRXD[1] I EMAC[0]_RGRXD[0] I EMAC[0]_RMTXD[1] O
R23 EMAC[0]_MRXD[2] I EMAC[0]_RGRXD[1] I EMAC[0]_RMTXEN O
J25 EMAC[0]_MRXD[3] I DEFAULT DEFAULT
T23 EMAC[0]_MRXD[4] I EMAC[0]_RGRXD[3] I DEFAULT
H26 EMAC[0]_MRXD[5] I EMAC[0]_RGTXD[3] O DEFAULT
F28 EMAC[0]_MRXD[6] I EMAC[0]_RGTXD[2] O DEFAULT
G27 EMAC[0]_MRXD[7] I EMAC[0]_RGTXD[1] O DEFAULT
K22 EMAC[0]_MRXDV I DEFAULT DEFAULT
J26 EMAC[0]_MRXER I EMAC[0]_RGTXCTL O EMAC[0]_RMRXER I
L24 EMAC[0]_MTCLK I EMAC[0]_RGRXC I DEFAULT
J24 EMAC[0]_MTXD[0] O DEFAULT DEFAULT
H25 EMAC[0]_MTXD[1] O DEFAULT DEFAULT
H22 EMAC[0]_MTXD[2] O DEFAULT DEFAULT

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Table 4-8. Pins Used in EMAC[0] MII/GMII, RGMII, and RMII Boot Modes (continued)
SIGNAL NAMES
PIN NO.
MII/GMII TYPE RGMII TYPE RMII TYPE
H23 EMAC[0]_MTXD[3] O DEFAULT DEFAULT
G23 EMAC[0]_MTXD[4] O DEFAULT DEFAULT
F27 EMAC[0]_MTXD[5] O DEFAULT DEFAULT
J22 EMAC[0]_MTXD[6] O DEFAULT DEFAULT
H24 EMAC[0]_MTXD[7] O DEFAULT DEFAULT
J23 EMAC[0]_MTXEN O DEFAULT DEFAULT
H28 MDCLK O MDCLK O MDCLK O
P24 MDIO I/O MDIO I/O MDIO I/O

4.2.7 PCIe Bootmode (PCIE_32 and PCIE_64)

Table 4-9 lists the device pins that are configured by the ROM for the PCIe boot mode.

Table 4-9. Pins Used in PCIe Bootmode

SIGNAL NAME PIN NO. TYPE
PCIE_TXP0 AD2 O
PCIE_TXN0 AD1 O
PCIE_RXP0 AC2 I
PCIE_RXN0 AC1 I
SERDES_CLKIP AF1 I
SERDES_CLKN AF2 I

4.2.8 UART Bootmode

Table 4-10 lists the device pins that are configured by the ROM for the UART boot mode.

Table 4-10. Pins Used in UART Bootmode

SIGNAL NAME PIN NO. TYPE
UART0_RXD AH5 I
UART0_TXD AG5 O

4.3 Pin Multiplexing Control

Device level pin multiplexing is controlled on a pin-by-pin basis by the MUXMODE bits of the PINCNTL1 –
PINCNTL270 registers in the Control Module.
Pin multiplexing selects which one of several peripheral pin functions controls the pin's I/O buffer output
data values. Table 4-11 shows the peripheral pin functions associated with each MUXMODE setting for all
multiplexed pins. The default pin multiplexing control for almost every pin is to select MUXMODE = 0x0, in
which case the pin's I/O buffer is 3-stated.
In most cases, the input from each pin is routed to all of the peripherals that share the pin, regardless of
the MUXMODE setting. However, in some cases a constant "0" or "1" value is routed to the associated
peripheral when its peripheral function is not selected to control any output pin. For more details on the
De-Selected Input State (DSIS), see the "MUXED" columns of each Terminal Functions table (Section 3.2,
Terminal Functions).

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Some peripheral pin functions can be routed to more than one device pin. These types of peripheral pin
functions are called Multimuxed (MM) and may have different Switching Characteristics and Timing
Requirements for each device pin option. The Multimuxed peripheral pin functions are labeled as "MM" in
Terminal Functions tables in Section 3.2, Terminal Functions and the associated timings for each MM pin
option are in Section 8, Peripheral Information and Timings.
For more detailed information on the Pin Control 1 through Pin Control 270 (PINCNTLx) registers
breakout, see Figure 4-1 and Table 4-11. For the register reset values of each PINCNTLx register, see
Table 4-13, PINCNTLx Registers MUXMODE Functions.

Figure 4-1. PINCNTL1 – PINCNTL270 (PINCNTLx) Registers Breakout

31 24 23 20 19 18 17 16
RESERVED RESERVED RSV RXAC PLLTY PLLU
TIVE PESE DEN
L
R - 0000 0000 R - 0000 R/W (see Table 4-13 for register
reset value)

15 8 7 0
RESERVED MUXMODE[7:0] (see Table 4-13)
R - 0000 0000 R/W - 0000 0000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-11. PINCNTL1 – PINCNTL270 (PINCNTLx) Registers Bit Descriptions

Bit Field Description Comments
31:20 RESERVED Reserved. Read only, writes have no effect.
Reserved. This bit must always be written with the
19 RSV reset (default) value.
(See Table 4-13 for full register reset value)
Receiver Enable
18 RXACTIVE 0 = Receiver Disabled
1 = Receiver Enabled
For PINCNTLx register reset value
Pullup/Pulldown Type Selection bit examples, see Table 4-12,
17 PLLTYPSEL 0 = Pulldown (PD) selected PNICNTLx Register Reset Value
1 = Pullup (PU) selected Examples.

Pullup/Pulldown Enable bit For the full register reset values of all
PINCNTLx registers, see Table 4-13,
16 PLLUDEN 0 = PU/PD enabled PINCNTLx Registers MUXMODE
1 = PU/PD disabled Functions.
15:8 RESERVED Reserved. Read only, writes have no effect.
MUXMODE Selection bits
These bits select the multiplexed mode pin function
7:0 MUXMODE[7:0] settings (seeTable 4-13, PINCNTLx Registers
MUXMODE Functions). A value of zero results in the
pin being tri-stated. Non-zero values other than those
shown in Table 4-13 are Reserved.

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Table 4-12. PINCNTLx Register Reset Value Examples

HEX PINCNTLx Bits 31:24 Bits 23:20 Bit 19 Bit 18 Bit 17 Bit 16 Bits 15:8 Bits 7:0 REGISTER
ADDRESS REGISTER RESET
RANGE NAME RESERVED RESERVED RSV RSV PLLTYPESEL PLLUDEN RESERVED MUXMODE[7:0] VALUE
0x4814 0800 PINCNTL1 00h 0h 0 1 1 0 00h 00h 0x0006 0000
0x4814 0804 PINCNTL2 00h 0h 1 1 1 0 00h 00h 0x000E 0000
0x4814 0808 PINCNTL3 00h 0h 1 1 1 0 00h 00h 0x000E 0000
…
0x4814 0C34 PINCNTL270 00h 0h 1 1 0 0 00h 00h 0x000C 0000

(1) "(M0)" represents multimuxed option "0" for this pin function, "(M1)" represents multimuxed option "1" for this pin function, ... etc.
(2) Within this MUXMODE setting, EMAC[x] GMII or RGMII pin functions are selected via the RGMII0_EN and/or RGMII1_EN bits (8 and 9, respectively) in the GMII_SEL register
[0x4814_0650] of the Control Module. "0" = GMII (default) and "1" = RGMII.

Table 4-13. PINCNTLx Registers MUXMODE Functions

HEX REGISTER MUXMODE[7:0] SETTINGS

REGISTER PIN
ADDRESS RESET
NAME NO. 0x1 0x2 0x4 0x8 0x10 0x20 0x40 0x80
VALUE
0x4814 0800 PINCNTL1 P3 0x0006 0000 SD1_CLK
0x4814 0804 PINCNTL2 P2 0x000E 0000 SD1_CMD(M0) GP0[0]

0x4814 0808 PINCNTL3 P1 0x000E 0000 SD1_DAT[0]

0x4814 080C PINCNTL4 P5 0x000E 0000 SD1_DAT[1]_SDIRQ
0x4814 0810 PINCNTL5 P4 0x000E 0000 SD1_DAT[2]_SDRW
0x4814 0814 PINCNTL6 P6 0x000E 0000 SD1_DAT[3]
0x4814 0818 PINCNTL7 W6 0x000E 0000 DEVOSC_WAKE SPI[1]_SCS[1] TIM5_IO(M1) GP1[7](M0)
0x4814 081C PINCNTL8 Y6 0x0006 0000 SD0_CLK GP0[1]
0x4814 0820 PINCNTL9 N1 0x000E 0000 SD0_CMD SD1_CMD(M1) GP0[2]

0x4814 0824 PINCNTL10 R7 0x000E 0000 SD0_DAT[0] SD1_DAT[4] GP0[3]

0x4814 0828 PINCNTL11 Y5 0x000E 0000 SD0_DAT[1]_SDIRQ SD1_DAT[5] GP0[4]
0x4814 082C PINCNTL12 Y3 0x000E 0000 SD0_DAT[2]_SDRW SD1_DAT[6] GP0[5]
0x4814 0830 PINCNTL13 Y4 0x000E 0000 SD0_DAT[3] SD1_DAT[7] GP0[6]
0x4814 0834 PINCNTL14 L5 0x000C 0000 AUD_CLKIN0 MCA[0]_AXR[7] (M1) MCA[0]_AHCLKX MCA[3]_AHCLKX USB1_DRVVBU
S
0x4814 0838 PINCNTL15 R5 0x000C 0000 AUD_CLKIN1 MCA[0]_AXR[8](M1) MCA[1]_AHCLKX MCA[4]_AHCLKX EDMA_EVT3(M1) TIM2_IO(M1) GP0[8]

0x4814 083C PINCNTL16 H1 0x000C 0000 AUD_CLKIN2 MCA[0]_AXR[9](M1) MCA[2]_AHCLKX MCA[5]_AHCLKX EDMA_EVT2(M1) TIM3_IO(M1) GP0[9]

0x4814 0840 PINCNTL17 R4 0x0004 0000 MCA[0]_ACLKX

0x4814 0844 PINCNTL18 L3 0x000C 0000 MCA[0]_AFSX
0x4814 0848 PINCNTL19 K2 0x0004 0000 MCA[0]_ACLKR MCA[5]_AXR[2]
0x4814 084C PINCNTL20 K1 0x000C 0000 MCA[0]_AFSR MCA[5]_AXR[3]

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Table 4-13. PINCNTLx Registers MUXMODE Functions (continued)

HEX REGISTER MUXMODE[7:0] SETTINGS
REGISTER PIN
ADDRESS RESET
NAME NO. 0x1 0x2 0x4 0x8 0x10 0x20 0x40 0x80
VALUE
0x4814 0850 PINCNTL21 J2 0x000C 0000 MCA[0]_AXR[0]
0x4814 0854 PINCNTL22 J1 0x000E 0000 MCA[0]_AXR[1] I2C[3]_SCL(M0)
0x4814 0858 PINCNTL23 L4 0x000E 0000 MCA[0]_AXR[2] I2C[3]_SDA(M0)
0x4814 085C PINCNTL24 M5 0x000C 0000 MCA[0]_AXR[3]
0x4814 0860 PINCNTL25 R6 0x000C 0000 MCA[0]_AXR[4] MCA[1]_AXR[8](M0)
0x4814 0864 PINCNTL26 M3 0x000C 0000 MCA[0]_AXR[5] MCA[1]_AXR[9](M0)
0x4814 0868 PINCNTL27 M4 0x000C 0000 MCA[0]_AXR[6] MCB_DR
0x4814 086C PINCNTL28 L2 0x000C 0000 MCA[0]_AXR[7](M0) MCB_DX

0x4814 0870 PINCNTL29 L1 0x000C 0000 MCA[0]_AXR[8] (M0) MCB_FSX MCB_FSR(M1)

0x4814 0874 PINCNTL30 M6 0x000C 0000 MCA[0]_AXR[9] (M0) MCB_CLKX MCB_CLKR(M1)
0x4814 0878 PINCNTL31 U5 0x0004 0000 MCA[1]_ACLKX
0x4814 087C PINCNTL32 V3 0x000C 0000 MCA[1]_AFSX
0x4814 0880 PINCNTL33 M1 0x0004 0000 MCA[1]_ACLKR MCA[1]_AXR[4]
0x4814 0884 PINCNTL34 M2 0x000C 0000 MCA[1]_AFSR MCA[1]_AXR[5]
0x4814 0888 PINCNTL35 V4 0x000E 0000 MCA[1]_AXR[0] SD0_DAT[4]
0x4814 088C PINCNTL36 T6 0x000E 0000 MCA[1]_AXR[1] SD0_DAT[5]
0x4814 0890 PINCNTL37 R3 0x000C 0000 MCA[1]_AXR[2] MCB_FSR(M0)
0x4814 0894 PINCNTL38 N6 0x000C 0000 MCA[1]_AXR[3] MCB_CLKR(M0)
0x4814 0898 PINCNTL39 U6 0x0006 0000 MCA[2]_ACLKX GP0[10](M1)
0x4814 089C PINCNTL40 AA5 0x000E 0000 MCA[2]_AFSX GP0[11](M1)
0x4814 08A0 PINCNTL41 N2 0x000E 0000 MCA[2]_AXR[0] SD0_DAT[6] UART5_RXD(M3) GP0[12](M1)
0x4814 08A4 PINCNTL42 V6 0x000E 0000 MCA[2]_AXR[1] SD0_DAT[7] UART5_TXD (M3)
GP0[13](M1)
0x4814 08A8 PINCNTL43 V5 0x000C 0000 MCA[2]_AXR[2] MCA[1]_AXR[6] TIM2_IO (M0)
GP0[14](M1)
0x4814 08AC PINCNTL44 H2 0x000C 0000 MCA[2]_AXR[3] MCA[1]_AXR[7] TIM3_IO(M0) GP0[15](M1)
0x4814 08B0 PINCNTL45 G6 0x0004 0000 MCA[3]_ACLKX GP0[16](M1)
0x4814 08B4 PINCNTL46 H4 0x000C 0000 MCA[3]_AFSX GP0[17](M1)
0x4814 08B8 PINCNTL47 G1 0x000C 0000 MCA[3]_AXR[0] TIM4_IO (M0)
GP0[18](M1)
0x4814 08BC PINCNTL48 G2 0x000C 0000 MCA[3]_AXR[1] TIM5_IO(M0) GP0[19](M1)
0x4814 08C0 PINCNTL49 F2 0x000C 0000 MCA[3]_AXR[2] MCA[1]_AXR[8] (M1)
GP0[20](M1)
0x4814 08C4 PINCNTL50 J6 0x000C 0000 MCA[3]_AXR[3] MCA[1]_AXR[9] (M1)

0x4814 08C8 PINCNTL51 K7 0x0004 0000 MCA[4]_ACLKX GP0[21](M1)

0x4814 08CC PINCNTL52 H3 0x000C 0000 MCA[4]_AFSX GP0[22](M1)
0x4814 08D0 PINCNTL53 H6 0x000C 0000 MCA[4]_AXR[0] GP0[23](M1)
0x4814 08D4 PINCNTL54 J4 0x000C 0000 MCA[4]_AXR[1] TIM6_IO(M0) GP0[24](M1)

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Table 4-13. PINCNTLx Registers MUXMODE Functions (continued)

HEX REGISTER MUXMODE[7:0] SETTINGS
REGISTER PIN
ADDRESS RESET
NAME NO. 0x1 0x2 0x4 0x8 0x10 0x20 0x40 0x80
VALUE
0x4814 08D8 PINCNTL55 J3 0x000C 0000 MCA[5]_ACLKX GP0[25](M1)
0x4814 08DC PINCNTL56 H5 0x000C 0000 MCA[5]_AFSX GP0[26](M1)
0x4814 08E0 PINCNTL57 L7 0x000C 0000 MCA[5]_AXR[0] MCA[4]_AXR[2] GP0[27](M1)
0x4814 08E4 PINCNTL58 L6 0x000C 0000 MCA[5]_AXR[1] MCA[4]_AXR[3] TIM7_IO (M0)
GP0[28](M1)
0x4814 08E8 PINCNTL59 U4 0x0004 0000 UART2_RXD (M1) GP0[29]

0x4814 08EC PINCNTL60 T2 0x0004 0000 TCLKIN GP0[30]

0x4814 08F0 PINCNTL61 U3 0x000C 0000 UART2_TXD(M1) GP0[31]

0x4814 08F4 PINCNTL62 W1 0x000C 0000 GP1[7](M1)

0x4814 08F8 PINCNTL63 W2 0x000E 0000 GP1[8](M1)
0x4814 08FC PINCNTL64 V1 0x000C 0000 GP1[9](M1)
0x4814 0900 PINCNTL65 V2 0x000E 0000 GP1[10](M1)
0x4814 0904 PINCNTL66 – 0x000C 0000 Reserved. Do Not Program this Register.
0x4814 0908 PINCNTL67 – 0x000E 0000 Reserved. Do Not Program this Register.
0x4814 090C PINCNTL68 AH6 0x000E 0000 DCAN0_TX UART2_TXD(M2) I2C[3]_SDA(M1) GP1[0]

0x4814 0910 PINCNTL69 AG6 0x000E 0000 DCAN0_RX UART2_RXD(M2) I2C[3]_SCL(M1) GP1[1]

0x4814 0914 PINCNTL70 AH5 0x000E 0000 UART0_RXD

0x4814 0918 PINCNTL71 AG5 0x000E 0000 UART0_TXD
0x4814 091C PINCNTL72 AE6 0x000E 0000 UART0_CTS UART4_RXD(M3) DCAN1_TX SPI[1]_SCS[3] SD0_SDCD

0x4814 0920 PINCNTL73 AF5 0x000E 0000 UART0_RTS UART4_TXD (M3) DCAN1_RX SPI[1]_SCS[2] SD2_SDCD

0x4814 0924 PINCNTL74 AH4 0x000E 0000 UART0_DCD UART3_RXD (M0) SPI[0]_SCS[3] I2C[2]_SCL (M0) SD1_POW GP1[2]

0x4814 0928 PINCNTL75 AG4 0x000E 0000 UART0_DSR UART3_TXD(M0) SPI[0]_SCS[2] I2C[2]_SDA(M0) SD1_SDWP GP1[3]

0x4814 092C PINCNTL76 AG2 0x000E 0000 UART0_DTR UART3_CTS (M0)

UART1_TXD (M0) GP1[4]

0x4814 0930 PINCNTL77 AF4 0x000E 0000 UART0_RIN UART3_RTS (M0)

UART1_RXD (M0) GP1[5]

0x4814 0934 PINCNTL78 AF24 0x000E 0000 I2C[1]_SCL HDMI_SCL(M0)

0x4814 0938 PINCNTL79 AG24 0x000E 0000 I2C[1]_SDA HDMI_SDA(M0)
0x4814 093C PINCNTL80 AE5 0x0006 0000 SPI[0]_SCS[1] SD1_SDCD SATA_ACT0_LED EDMA_EVT1(M1) TIM4_IO(M1) GP1[6]

0x4814 0940 PINCNTL81 AD6 0x0006 0000 SPI[0]_SCS[0]

0x4814 0944 PINCNTL82 AC7 0x0006 0000 SPI[0]_SCLK
0x4814 0948 PINCNTL83 AF3 0x0006 0000 SPI[0]_D[1]
0x4814 094C PINCNTL84 AE3 0x0006 0000 SPI[0]_D[0]
0x4814 0950 PINCNTL85 AD3 0x0006 0000 SPI[1]_SCS[0] GP1[16](M1)
0x4814 0954 PINCNTL86 AC3 0x0006 0000 SPI[1]_SCLK GP1[17](M1)
0x4814 0958 PINCNTL87 AA3 0x0006 0000 SPI[1]_D[1] GP1[18](M1)
0x4814 095C PINCNTL88 AA6 0x0006 0000 SPI[1]_D[0] GP1[26](M1)

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Table 4-13. PINCNTLx Registers MUXMODE Functions (continued)

HEX REGISTER MUXMODE[7:0] SETTINGS
REGISTER PIN
ADDRESS RESET
NAME NO. 0x1 0x2 0x4 0x8 0x10 0x20 0x40 0x80
VALUE
0x4814 0960 PINCNTL89 U26 0x0005 0000 GPMC_D[0] BTMODE[0]
0x4814 0964 PINCNTL90 Y28 0x0005 0000 GPMC_D[1] BTMODE[1]
0x4814 0968 PINCNTL91 V27 0x0005 0000 GPMC_D[2] BTMODE[2]
0x4814 096C PINCNTL92 W27 0x0005 0000 GPMC_D[3] BTMODE[3]
0x4814 0970 PINCNTL93 V26 0x0005 0000 GPMC_D[4] BTMODE[4]
0x4814 0974 PINCNTL94 AA28 0x0005 0000 GPMC_D[5] BTMODE[5]
0x4814 0978 PINCNTL95 U25 0x0005 0000 GPMC_D[6] BTMODE[6]
0x4814 097C PINCNTL96 V25 0x0005 0000 GPMC_D[7] BTMODE[7]
0x4814 0980 PINCNTL97 Y27 0x0005 0000 GPMC_D[8] BTMODE[8]
0x4814 0984 PINCNTL98 AB28 0x0005 0000 GPMC_D[9] BTMODE[9]
0x4814 0988 PINCNTL99 Y26 0x0005 0000 GPMC_D[10] BTMODE[10]
0x4814 098C PINCNTL100 AA27 0x0005 0000 GPMC_D[11] BTMODE[11]
0x4814 0990 PINCNTL101 U24 0x0005 0000 GPMC_D[12] BTMODE[12]
0x4814 0994 PINCNTL102 U23 0x0005 0000 GPMC_D[13] BTMODE[13]
0x4814 0998 PINCNTL103 V24 0x0005 0000 GPMC_D[14] BTMODE[14]
0x4814 099C PINCNTL104 Y25 0x0005 0000 GPMC_D[15] BTMODE[15]
0x4814 09A0 PINCNTL105 AD27 0x0004 0000 GPMC_A[16] GP2[5](M0)
0x4814 09A4 PINCNTL106 V23 0x0004 0000 GPMC_A[17] GP2[6](M0)
0x4814 09A8 PINCNTL107 AE28 0x0004 0000 GPMC_A[18] TIM2_IO(M2) GP1[13](M0)
0x4814 09AC PINCNTL108 AC27 0x0004 0000 GPMC_A[19] TIM3_IO(M2) GP1[14](M0)
0x4814 09B0 PINCNTL109 AD28 0x0006 0000 GPMC_A[20] (M0) SPI[2]_SCS[1] GP1[15](M0)
0x4814 09B4 PINCNTL110 AC28 0x0004 0000 GPMC_A[21] (M0)
SPI[2]_D[0](M0)
GP1[16](M0)
0x4814 09B8 PINCNTL111 AB27 0x0006 0000 GPMC_A[22](M0) SPI[2]_D[1](M0) HDMI_CEC(M0) TIM4_IO(M2) GP1[17](M0)
0x4814 09BC PINCNTL112 AA26 0x0004 0000 GPMC_A[23] (M0)
SPI[2]_SCLK (M0)
HDMI_HPDET (M0)
TIM5_IO (M2)
GP1[18](M0)
0x4814 09C0 PINCNTL113 L25 0x0006 0000 SD2_DAT[7] GPMC_A[24] (M0)
GPMC_A[20] (M1)
UART2_RXD (M3) GP1[19]

0x4814 09C4 PINCNTL114 N23 0x0006 0000 SD2_DAT[6] GPMC_A[25](M0) GPMC_A[21](M1) UART2_TXD(M3) GP1[20]

0x4814 09C8 PINCNTL115 P22 0x0006 0000 SD2_DAT[5] GPMC_A[26] (M0)

GPMC_A[22] (M1)
TIM6_IO (M2) GP1[21]

0x4814 09CC PINCNTL116 R24 0x0006 0000 SD2_DAT[4] GPMC_A[27] (M0)

GPMC_A[23] (M1) GPMC_CS[7] EDMA_EVT0 (M1)
TIM7_IO (M2) GP1[22]

0x4814 09D0 PINCNTL117 J28 0x0006 0000 SD2_DAT[3] GPMC_A[1](M1) GP2[5](M1)

0x4814 09D4 PINCNTL118 K27 0x0006 0000 SD2_DAT[2]_SDRW GPMC_A[2](M1) GP2[6](M1)
0x4814 09D8 PINCNTL119 M24 0x0006 0000 SD2_DAT[1]_SDIRQ GPMC_A[3] (M1)
GP1[13](M1)
0x4814 09DC PINCNTL120 L26 0x0006 0000 SD2_DAT[0] GPMC_A[4] (M1)
GP1[14](M1)
0x4814 09E0 PINCNTL121 M23 0x0006 0000 SD2_CLK GP1[15](M1)
0x4814 09E4 PINCNTL122 T28 0x0006 0000 GPMC_CS[0] GP1[23]
0x4814 09E8 PINCNTL123 K28 0x0006 0000 GPMC_CS[1] GPMC_A[25](M1) GP1[24]

164 Device Configurations Copyright © 2011–2013, Texas Instruments Incorporated

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Table 4-13. PINCNTLx Registers MUXMODE Functions (continued)

HEX REGISTER MUXMODE[7:0] SETTINGS
REGISTER PIN
ADDRESS RESET
NAME NO. 0x1 0x2 0x4 0x8 0x10 0x20 0x40 0x80
VALUE
0x4814 09EC PINCNTL124 M25 0x0006 0000 GPMC_CS[2] GPMC_A[24] (M1) GP1[25]

0x4814 09F0 PINCNTL125 P26 0x0006 0000 GPMC_CS[3] VIN[1]B_CLK SPI[2]_SCS[0] GP1[26](M0)
0x4814 09F4 PINCNTL126 P25 0x0006 0000 GPMC_CS[4] SD2_CMD GP1[8](M0)
0x4814 09F8 PINCNTL127 R26 0x0006 0000 GPMC_CLK GPMC_CS[5] GPMC_WAIT[1] CLKOUT1 EDMA_EVT3 (M0)
TIM4_IO (M3) GP1[27]

0x4814 09FC PINCNTL128 M26 0x0006 0000 GPMC_ADV_ALE GPMC_CS[6] TIM5_IO (M3) GP1[28]

0x4814 0A00 PINCNTL129 T27 0x0006 0000 GPMC_OE_RE

0x4814 0A04 PINCNTL130 U28 0x0006 0000 GPMC_WE
0x4814 0A08 PINCNTL131 U27 0x0004 0000 GPMC_BE[0]_CLE GPMC_A[25](M2) EDMA_EVT2(M0) TIM6_IO(M3) GP1[29]

0x4814 0A0C PINCNTL132 V28 0x0004 0000 GPMC_BE[1] GPMC_A[24](M2) EDMA_EVT1(M0) TIM7_IO(M3) GP1[30]

0x4814 0A10 PINCNTL133 W28 0x0006 0000 GPMC_WAIT[0] GPMC_A[26](M2) EDMA_EVT0(M0) GP1[31]

0x4814 0A14 PINCNTL134 AE17 0x0004 0000 VIN[0]B_CLK CLKOUT0 GP1[9](M0)

0x4814 0A18 PINCNTL135 AE21 0x000E 0000 VIN[0]A_DE (M0) VIN[0]B_HSYNC UART5_TXD (M1)
I2C[2]_SDA (M1) GP2[0]

0x4814 0A1C PINCNTL136 AA20 0x000E 0000 VIN[0]A_FLD(M0) VIN[0]B_VSYNC UART5_RXD(M1) I2C[2]_SCL(M3) GP2[1]

0x4814 0A20 PINCNTL137 AB20 0x000C 0000 VIN[0]A_CLK GP2[2](M1)

0x4814 0A24 PINCNTL138 AC20 0x000E 0000 VIN[0]A_HSYNC UART5_RTS (M1) GP2[3]

0x4814 0A28 PINCNTL139 AD20 0x000E 0000 VIN[0]A_VSYNC UART5_CTS(M1) GP2[4]

0x4814 0A2C PINCNTL140 AF9 0x000C 0000 VIN[0]A_D[0] GP1[11](M1)

0x4814 0A30 PINCNTL141 AB11 0x000C 0000 VIN[0]A_D[1] GP1[12](M1)
0x4814 0A34 PINCNTL142 AC9 0x000C 0000 VIN[0]A_D[2] GP2[7]
0x4814 0A38 PINCNTL143 AE12 0x000C 0000 VIN[0]A_D[3] GP2[8]
0x4814 0A3C PINCNTL144 AH8 0x000C 0000 VIN[0]A_D[4] GP2[9]
0x4814 0A40 PINCNTL145 AG16 0x000C 0000 VIN[0]A_D[5] GP2[10]
0x4814 0A44 PINCNTL146 AH16 0x000C 0000 VIN[0]A_D[6] GP2[11]
0x4814 0A48 PINCNTL147 AA11 0x000C 0000 VIN[0]A_D[7] GP2[12]
0x4814 0A4C PINCNTL148 AB15 0x000C 0000 VIN[0]A_D[8]_BD[0] GP2[13]
0x4814 0A50 PINCNTL149 AG9 0x000C 0000 VIN[0]A_D[9]_BD[1] GP2[14]
0x4814 0A54 PINCNTL150 AH9 0x000C 0000 VIN[0]A_D[10]_BD[2] GP2[15]
0x4814 0A58 PINCNTL151 AH17 0x000C 0000 VIN[0]A_D[11]_BD[3] CAM_WE(M1) GP2[16]

0x4814 0A5C PINCNTL152 AG17 0x0004 0000 VIN[0]A_D[12]_BD[4] CLKOUT1 GP2[17]

0x4814 0A60 PINCNTL153 AF17 0x000C 0000 VIN[0]A_D[13]_BD[5] CAM_RESET GP2[18]
0x4814 0A64 PINCNTL154 AC12 0x000C 0000 VIN[0]A_D[14]_BD[6] CAM_STROBE GP2[19]
0x4814 0A68 PINCNTL155 AC14 0x000C 0000 VIN[0]A_D[15]_BD[7] CAM_SHUTTER GP2[20]
0x4814 0A6C PINCNTL156 AA21 0x000E 0000 VIN[0]A_D[16] CAM_D[8] I2C[2]_SCL(M1) GP0[10](M0)
0x4814 0A70 PINCNTL157 AB21 0x000C 0000 VIN[0]A_D[17] CAM_D[9] EMAC[1]_RMRXER(M GP0[11](M0)
1)

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Table 4-13. PINCNTLx Registers MUXMODE Functions (continued)

HEX REGISTER MUXMODE[7:0] SETTINGS
REGISTER PIN
ADDRESS RESET
NAME NO. 0x1 0x2 0x4 0x8 0x10 0x20 0x40 0x80
VALUE
0x4814 0A74 PINCNTL158 AF20 0x000E 0000 VIN[0]A_D[18] CAM_D[10] EMAC[1]_RMRXD[1] (
I2C[3]_SCL (M2)
GP0[12](M0)
M1)

0x4814 0A78 PINCNTL159 AF21 0x000E 0000 VIN[0]A_D[19] CAM_D[11] EMAC[1]_RMRXD[0]( I2C[3]_SDA(M2) GP0[13](M0)
M1)

0x4814 0A7C PINCNTL160 AC17 0x000C 0000 VIN[0]A_D[20] CAM_D[12] EMAC[1]_RMCRSDV( SPI[3]_SCS[0] GP0[14](M0)
M1)

0x4814 0A80 PINCNTL161 AE18 0x0004 0000 VIN[0]A_D[21] CAM_D[13] EMAC[1]_RMTXD[0]( SPI[3]_SCLK(M0) GP0[15](M0)
M1)

0x4814 0A84 PINCNTL162 AC21 0x0004 0000 VIN[0]A_D[22] CAM_D[14] EMAC[1]_RMTXD[1]( SPI[3]_D[1](M0) GP0[16](M0)
M1)

0x4814 0A88 PINCNTL163 AC16 0x0004 0000 VIN[0]A_D[23] CAM_D[15] EMAC[1]_RMTXEN(M1 SPI[3]_D[0](M0) GP0[17](M0)
)

0x4814 0A8C PINCNTL164 AB17 0x0006 0000 VIN[0]A_DE(M1) CAM_D[7] GP0[18](M0)

0x4814 0A90 PINCNTL165 AC15 0x0006 0000 VIN[0]B_DE CAM_D[6] GP0[19](M0)
0x4814 0A94 PINCNTL166 AC22 0x0006 0000 VIN[0]A_FLD (M1) CAM_D[5] GP0[20](M0)
0x4814 0A98 PINCNTL167 AD17 0x0006 0000 VIN[0]B_FLD CAM_D[4] GP0[21](M0)
0x4814 0A9C PINCNTL168 AD18 0x0006 0000 VOUT[1]_G_Y_YC[1] CAM_D[3] GPMC_A[5](M1) UART4_RXD(M0) GP0[22](M0)
0x4814 0AA0 PINCNTL169 AC18 0x0004 0000 VOUT[1]_G_Y_YC[0] CAM_D[2] GPMC_A[6] (M1)
UART4_TXD (M0)
GP0[23](M0)
0x4814 0AA4 PINCNTL170 AC19 0x0004 0000 VOUT[1]_R_CR[1] CAM_D[1] GPMC_A[7] (M1)
UART4_CTS (M0)
GP0[24](M0)
0x4814 0AA8 PINCNTL171 AA22 0x0004 0000 VOUT[1]_R_CR[0] CAM_D[0] GPMC_A[8](M1) UART4_RTS(M0) GP0[25](M0)
0x4814 0AAC PINCNTL172 AE23 0x0004 0000 VOUT[1]_B_CB_C[1] CAM_HS GPMC_A[9](M1) UART2_RXD(M0) GP0[26](M0)
0x4814 0AB0 PINCNTL173 AD23 0x0006 0000 VOUT[1]_B_CB_C[0] CAM_VS GPMC_A[10] (M1)
UART2_TXD (M0)
GP0[27](M0)
0x4814 0AB4 PINCNTL174 AB23 0x0004 0000 VOUT[1]_FLD CAM_FLD CAM_WE (M0)
GPMC_A[11] (M1) UART2_CTS GP0[28](M0)
0x4814 0AB8 PINCNTL175 AF18 0x0004 0000 VOUT[0]_FLD(M1) CAM_PCLK GPMC_A[12](M1) UART2_RTS GP2[2](M0)
0x4814 0ABC PINCNTL176 AD12 0x000C 0000 VOUT[0]_CLK
0x4814 0AC0 PINCNTL177 AC11 0x000C 0000 VOUT[0]_HSYNC
0x4814 0AC4 PINCNTL178 AB13 0x000C 0000 VOUT[0]_VSYNC
0x4814 0AC8 PINCNTL179 AA10 0x000C 0000 VOUT[0]_AVID VOUT[0]_FLD(M0) SPI[3]_SCLK(M2) TIM7_IO(M1) GP2[21]

0x4814 0ACC PINCNTL180 AG7 0x000C 0000 VOUT[0]_B_CB_C[2] EMU2 GP2[22]

Reset by GCR
Only
0x4814 0AD0 PINCNTL181 AE15 0x000C 0000 VOUT[0]_B_CB_C[3] GP2[23]
0x4814 0AD4 PINCNTL182 AD11 0x000C 0000 VOUT[0]_B_CB_C[4]
0x4814 0AD8 PINCNTL183 AD15 0x000C 0000 VOUT[0]_B_CB_C[5]
0x4814 0ADC PINCNTL184 AC10 0x000C 0000 VOUT[0]_B_CB_C[6]
0x4814 0AE0 PINCNTL185 AB10 0x000C 0000 VOUT[0]_B_CB_C[7]
0x4814 0AE4 PINCNTL186 AF15 0x000C 0000 VOUT[0]_B_CB_C[8]

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Table 4-13. PINCNTLx Registers MUXMODE Functions (continued)

HEX REGISTER MUXMODE[7:0] SETTINGS
REGISTER PIN
ADDRESS RESET
NAME NO. 0x1 0x2 0x4 0x8 0x10 0x20 0x40 0x80
VALUE
0x4814 0AE8 PINCNTL187 AG15 0x000C 0000 VOUT[0]_B_CB_C[9]
0x4814 0AEC PINCNTL188 AH7 0x000C 0000 VOUT[0]_G_Y_YC[2] EMU3 GP2[24]
Reset by GCR
Only
0x4814 0AF0 PINCNTL189 AH15 0x000C 0000 VOUT[0]_G_Y_YC[3] GP2[25]
0x4814 0AF4 PINCNTL190 AB8 0x000C 0000 VOUT[0]_G_Y_YC[4]
0x4814 0AF8 PINCNTL191 AB12 0x000C 0000 VOUT[0]_G_Y_YC[5]
0x4814 0AFC PINCNTL192 AA8 0x000C 0000 VOUT[0]_G_Y_YC[6]
0x48140B00 PINCNTL193 AD14 0x000C 0000 VOUT[0]_G_Y_YC[7]
0x48140B04 PINCNTL194 AE14 0x000C 0000 VOUT[0]_G_Y_YC[8]
0x48140B08 PINCNTL195 AF14 0x000C 0000 VOUT[0]_G_Y_YC[9]
0x48140B0C PINCNTL196 AD9 0x000C 0000 VOUT[0]_R_CR[2] EMU4 GP2[26]
Reset by GCR
Only
0x4814 0B10 PINCNTL197 AB9 0x000C 0000 VOUT[0]_R_CR[3] GP2[27]
0x4814 0B14 PINCNTL198 AA9 0x000C 0000 VOUT[0]_R_CR[4]
0x4814 0B18 PINCNTL199 AF8 0x000C 0000 VOUT[0]_R_CR[5]
0x4814 0B1C PINCNTL200 AF6 0x000C 0000 VOUT[0]_R_CR[6]
0x4814 0B20 PINCNTL201 AF12 0x000C 0000 VOUT[0]_R_CR[7]
0x4814 0B24 PINCNTL202 AE8 0x000C 0000 VOUT[0]_R_CR[8]
0x4814 0B28 PINCNTL203 AC13 0x000C 0000 VOUT[0]_R_CR[9]
0x4814 0B2C PINCNTL204 AE24 0x0004 0000 VOUT[1]_CLK EMAC[1]_MTCLK VIN[1]A_HSYNC GP2[28]
0x4814 0B30 PINCNTL205 AC24 0x0004 0000 VOUT[1]_HSYNC EMAC[1]_MCOL VIN[1]A_VSYNC SPI[3]_D[1](M2) UART3_RTS(M1) GP2[29]

0x4814 0B34 PINCNTL206 AA23 0x0004 0000 VOUT[1]_VSYNC EMAC[1]_MCRS VIN[1]A_FLD VIN[1]A_DE SPI[3]_D[0](M2) UART3_CTS(M1) GP2[30]

0x4814 0B38 PINCNTL207 Y22 0x0004 0000 VOUT[1]_AVID EMAC[1]_MRXER VIN[1]A_CLK UART4_RTS (M2) (M1)
TIM6_IO GP2[31]

0x4814 0B3C PINCNTL208 AH25 0x0004 0000 VOUT[1]_B_CB_C[3] EMAC[1]_MRCLK VIN[1]A_D[0] UART4_CTS (M2) GP3[0]

0x4814 0B40 PINCNTL209 AG25 0x0004 0000 VOUT[1]_B_CB_C[4] EMAC[1]_MRXD[0] VIN[1]A_D[1] UART4_RXD(M2) GP3[1]

0x4814 0B44 PINCNTL210 AF25 0x0004 0000 VOUT[1]_B_CB_C[5] EMAC[1]_MRXD[1] VIN[1]A_D[2] UART4_TXD (M2) GP3[2]

0x4814 0B48 PINCNTL211 AD25 0x0004 0000 VOUT[1]_B_CB_C[6] EMAC[1]_MRXD[2] VIN[1]A_D[3] UART3_RXD (M1) GP3[3]

0x48140B4C PINCNTL212 AC25 0x0004 0000 VOUT[1]_B_CB_C[7] EMAC[1]_MRXD[3] VIN[1]A_D[4] UART3_TXD(M1) GP3[4]

0x4814 0B50 PINCNTL213 AH26 0x0004 0000 VOUT[1]_B_CB_C[8] EMAC[1]_MRXD[4] VIN[1]A_D[5] I2C[3]_SCL (M3) GP3[5]

0x4814 0B54 PINCNTL214 AA24 0x0004 0000 VOUT[1]_B_CB_C[9] EMAC[1]_MRXD[5] VIN[1]A_D[6] I2C[3]_SDA (M3) GP3[6]

0x4814 0B58 PINCNTL215 Y23 0x0004 0000 VOUT[1]_G_Y_YC[3] EMAC[1]_MRXD[6] VIN[1]A_D[8] GP3[7]
0x4814 0B5C PINCNTL216 W22 0x0004 0000 VOUT[1]_G_Y_YC[4] EMAC[1]_MRXD[7] VIN[1]A_D[9] GP3[8]
0x4814 0B60 PINCNTL217 AG26 0x0004 0000 VOUT[1]_G_Y_YC[5] EMAC[1]_MRXDV VIN[1]A_D[10] GP3[9]
0x4814 0B64 PINCNTL218 AH27 0x0004 0000 VOUT[1]_G_Y_YC[6] EMAC[1]_GMTCLK VIN[1]A_D[11] GP3[10]
0x4814 0B68 PINCNTL219 AF26 0x0004 0000 VOUT[1]_G_Y_YC[7] EMAC[1]_MTXD[0] VIN[1]A_D[12] GP3[11]
0x4814 0B6C PINCNTL220 AE26 0x0004 0000 VOUT[1]_G_Y_YC[8] EMAC[1]_MTXD[1] VIN[1]A_D[13] GP3[12]

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Table 4-13. PINCNTLx Registers MUXMODE Functions (continued)

HEX REGISTER MUXMODE[7:0] SETTINGS
REGISTER PIN
ADDRESS RESET
NAME NO. 0x1 0x2 0x4 0x8 0x10 0x20 0x40 0x80
VALUE
0x4814 0B70 PINCNTL221 AD26 0x0004 0000 VOUT[1]_G_Y_YC[9] EMAC[1]_MTXD[2] VIN[1]A_D[14] GP3[13]
0x4814 0B74 PINCNTL222 AG27 0x0004 0000 VOUT[1]_R_CR[4] EMAC[1]_MTXD[3] VIN[1]A_D[15] SPI[3]_SCS[1] GP3[14]
0x4814 0B78 PINCNTL223 AC26 0x0004 0000 VOUT[1]_R_CR[5] EMAC[1]_MTXD[4] VIN[1]A_D[16] SPI[3]_SCLK(M1) GP3[15]

0x4814 0B7C PINCNTL224 AA25 0x0004 0000 VOUT[1]_R_CR[6] EMAC[1]_MTXD[5] VIN[1]A_D[17] SPI[3]_D[1](M1) GP3[16]

0x4814 0B80 PINCNTL225 V22 0x0004 0000 VOUT[1]_R_CR[7] EMAC[1]_MTXD[6] VIN[1]A_D[18] SPI[3]_D[0](M1) GP3[17]

0x4814 0B84 PINCNTL226 W23 0x0004 0000 VOUT[1]_R_CR[8] EMAC[1]_MTXD[7] VIN[1]A_D[19] UART5_RXD(M2) GP3[18]

0x4814 0B88 PINCNTL227 Y24 0x0004 0000 VOUT[1]_R_CR[9] EMAC[1]_MTXEN VIN[1]A_D[20] UART5_TXD (M2) GP3[19]

0x4814 0B8C PINCNTL228 AF27 0x0006 0000 VOUT[1]_G_Y_YC[2] GPMC_A[13] (M1) VIN[1]A_D[21] HDMI_SCL (M1) SPI[2]_SCS[2] I2C[2]_SCL (M2) GP3[20]

0x4814 0B90 PINCNTL229 AG28 0x0006 0000 VOUT[1]_R_CR[3] GPMC_A[14](M1) VIN[1]A_D[22] HDMI_SDA(M1) SPI[2]_SCLK(M1) I2C[2]_SDA(M2) GP3[21]

0x4814 0B94 PINCNTL230 AE27 0x0004 0000 VOUT[1]_R_CR[2] GPMC_A[15](M1) VIN[1]A_D[23] HDMI_HPDET(M1) SPI[2]_D[1](M1) GP3[22]

0x4814 0B98 PINCNTL231 AF28 0x0006 0000 VOUT[1]_B_CB_C[2] GPMC_A[0] (M1) VIN[1]A_D[7] HDMI_CEC (M1)
SPI[2]_D[0](M1)
GP3[30](M1)
0x4814 0B9C PINCNTL232 J27 0x0004 0000 EMAC_RMREFCLK TIM2_IO (M3)
GP1[10](M0)
0x4814 0BA0 PINCNTL233 H28 0x000E 0000 MDCLK GP1[11](M0)
0x4814 0BA4 PINCNTL234 P24 0x000E 0000 MDIO GP1[12](M0)
0x4814 0BA8 PINCNTL235 L24 0x000C 0000 EMAC[0]_MTCLK/ VIN[1]B_D[0] SPI[3]_SCS[3] I2C[2]_SDA (M3) GP3[23]
EMAC[0]_RGRXC
0x4814 0BAC PINCNTL236 L23 0x000C 0000 EMAC[0]_MCOL/ VIN[1]B_D[1] EMAC[0]_RMRXD[0] GP3[24]
EMAC[0]_RGRXCTL
0x4814 0BB0 PINCNTL237 R25 0x000C 0000 EMAC[0]_MCRS/ VIN[1]B_D[2] EMAC[0]_RMRXD[1] GP3[25]
EMAC[0]_RGRXD[2]
0x4814 0BB4 PINCNTL238 J26 0x000C 0000 EMAC[0]_MRXER/ VIN[1]B_D[3] EMAC[0]_RMRXER GP3[26]
EMAC[0]_RGTXCTL
0x4814 0BB8 PINCNTL239 H27 0x000C 0000 EMAC[0]_MRCLK/ VIN[1]B_D[4] EMAC[0]_RMCRSDV SPI[3]_SCS[2] GP3[27]
EMAC[0]_RGTXC
0x4814 0BBC PINCNTL240 G28 0x0004 0000 EMAC[0]_MRXD[0]/ VIN[1]B_D[5] EMAC[0]_RMTXD[0] GP3[28]
EMAC[0]_RGTXD[0]
0x4814 0BC0 PINCNTL241 P23 0x0004 0000 EMAC[0]_MRXD[1]/ VIN[1]B_D[6] EMAC[0]_RMTXD[1] GP3[29]
EMAC[0]_RGRXD[0]
0x4814 0BC4 PINCNTL242 R23 0x0004 0000 EMAC[0]_MRXD[2]/ VIN[1]B_D[7] EMAC[0]_RMTXEN GP3[30](M0)
EMAC[0]_RGRXD[1]
0x4814 0BC8 PINCNTL243 J25 0x0004 0000 EMAC[0]_MRXD[3]/ GPMC_A[27](M1) GPMC_A[26](M1) GPMC_A[0](M0) UART5_RXD(M0)
EMAC[1]_RGRXCTL
0x4814 0BCC PINCNTL244 T23 0x0004 0000 EMAC[0]_MRXD[4]/ GPMC_A[1](M0) UART5_TXD(M0)
EMAC[0]_RGRXD[3]
0x4814 0BD0 PINCNTL245 H26 0x0004 0000 EMAC[0]_MRXD[5]/ GPMC_A[2](M0) UART5_CTS(M0)
EMAC[0]_RGTXD[3]
0x4814 0BD4 PINCNTL246 F28 0x0004 0000 EMAC[0]_MRXD[6]/ GPMC_A[3](M0) UART5_RTS(M0)
EMAC[0]_RGTXD[2]
0x4814 0BD8 PINCNTL247 G27 0x0004 0000 EMAC[0]_MRXD[7]/ GPMC_A[4](M0) SPI[2]_SCS[3]
EMAC[0]_RGTXD[1]

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Table 4-13. PINCNTLx Registers MUXMODE Functions (continued)

HEX REGISTER MUXMODE[7:0] SETTINGS
REGISTER PIN
ADDRESS RESET
NAME NO. 0x1 0x2 0x4 0x8 0x10 0x20 0x40 0x80
VALUE
0x4814 0BDC PINCNTL248 K22 0x0004 0000 EMAC[0]_MRXDV/ GPMC_A[5] (M0)
SPI[2]_SCLK (M2)
EMAC[1]_RGRXD[1]
0x4814 0BE0 PINCNTL249 K23 0x0004 0000 EMAC[0]_GMTCLK/ GPMC_A[6](M0) SPI[2]_D[1](M2)
EMAC[1]_RGRXC
0x4814 0BE4 PINCNTL250 J24 0x0004 0000 EMAC[0]_MTXD[0]/ GPMC_A[7](M0) SPI[2]_D[0](M2)
EMAC[1]_RGRXD[3]
0x4814 0BE8 PINCNTL251 H25 0x0004 0000 EMAC[0]_MTXD[1]/ GPMC_A[8](M0) UART4_RXD(M1)
EMAC[1]_RGTXD[1]
0x4814 0BEC PINCNTL252 H22 0x0004 0000 EMAC[0]_MTXD[2]/ EMAC[1]_RMRXD[0](M0) GPMC_A[9](M0) UART4_TXD(M1)
EMAC[1]_RGTXCTL
0x4814 0BF0 PINCNTL253 H23 0x0004 0000 EMAC[0]_MTXD[3]/ EMAC[1]_RMRXD[1](M0) GPMC_A[10](M0) UART4_CTS(M1)
EMAC[1]_RGTXD[0]
0x4814 0BF4 PINCNTL254 G23 0x0004 0000 EMAC[0]_MTXD[4]/ EMAC[1]_RMRXER GPMC_A[11](M0) UART4_RTS(M1)
EMAC[1]_RGTXD[2]
0x4814 0BF8 PINCNTL255 F27 0x0004 0000 EMAC[0]_MTXD[5]/ EMAC[1]_RMCRSDV(M0) GPMC_A[12](M0) UART1_RXD(M1)
EMAC[1]_RGTXC
0x4814 0BFC PINCNTL256 J22 0x0004 0000 EMAC[0]_MTXD[6]/ EMAC[1]_RMTXD[0](M0) GPMC_A[13](M0) UART1_TXD(M1)
EMAC[1]_RGRXD[0]
0x4814 0C00 PINCNTL257 H24 0x0004 0000 EMAC[0]_MTXD[7]/ EMAC[1]_RMTXD[1](M0) GPMC_A[14](M0) UART1_CTS
EMAC[1]_RGTXD[3]
0x4814 0C04 PINCNTL258 J23 0x0004 0000 EMAC[0]_MTXEN/ EMAC[1]_RMTXEN(M0) GPMC_A[15](M0) UART1_RTS
EMAC[1]_RGRXD[2]
0x4814 0C08 PINCNTL259 J7 0x0004 0000 CLKIN32 CLKOUT0 TIM3_IO(M3) GP3[31]

0x4814 0C0C PINCNTL260 J5 0x000E 0000 RESET

0x4814 0C10 PINCNTL261 H7 0x000E 0000 NMI
0x4814 0C14 PINCNTL262 K6 0x0005 0000 RSTOUT_WD_OUT
0x4814 0C18 PINCNTL263 AC4 0x000D 0000 I2C[0]_SCL
0x4814 0C1C PINCNTL264 AB6 0x000D 0000 I2C[0]_SDA
0x4814 0C20 PINCNTL265 – Undetermined Reserved. Do Not Program this Register.
0x4814 0C24 PINCNTL266 – Undetermined Reserved. Do Not Program this Register.
0x4814 0C28 PINCNTL267 – Undetermined Reserved. Do Not Program this Register.
0x4814 0C2C PINCNTL268 – Undetermined Reserved. Do Not Program this Register.
0x4814 0C30 PINCNTL269 – Undetermined Reserved. Do Not Program this Register.
0x4814 0C34 PINCNTL270 AF11 0x000C 0000 USB0_DRVVBUS GP0[7]

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4.4 Handling Unused Pins

When device signal pins are unused in the system, they can be left unconnected unless otherwise noted
in the Terminal Functions tables (see Section 3.2). For unused input pins, the internal pull resistor should
be enabled, or an external pull resistor should be used, to prevent floating inputs. Unless otherwise noted,
all supply pins must always be connected to the correct voltage, even when their associated signal pins
are unused.

4.5 DeBugging Considerations

4.5.1 Pullup/Pulldown Resistors

Proper board design should ensure that input pins to the TMS320DM814x DaVinci™ Digital Media
Processsors device always be at a valid logic level and not floating. This may be achieved via
pullup/pulldown resistors. The device features internal pullup (IPU) and internal pulldown (IPD) resistors
on most pins to eliminate the need, unless otherwise noted, for external pullup/pulldown resistors.
An external pullup/pulldown resistor needs to be used in the following situations:
• Boot Configuration Pins: If the pin is both routed out and 3-stated (not driven), an external
pullup/pulldown resistor is strongly recommended, even if the IPU/IPD matches the desired
value/state.
• Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external
pullup/pulldown resistor to pull the signal to the opposite rail.
For the boot configuration pins (listed in Table 3-1, Boot Configuration Terminal Functions), if they are
both routed out and 3-stated (not driven), it is strongly recommended that an external pullup/pulldown
resistor be implemented. Although, internal pullup/pulldown resistors exist on these pins and they may
match the desired configuration value, providing external connectivity can help ensure that valid logic
levels are latched on these device boot configuration pins. In addition, applying external pullup/pulldown
resistors on the boot and configuration pins adds convenience to the user in debugging and flexibility in
switching operating modes.
Tips for choosing an external pullup/pulldown resistor:
• Consider the total amount of current that may pass through the pullup or pulldown resistor. Make sure
to include the leakage currents of all the devices connected to the net, as well as any internal pullup or
pulldown resistors.
• Decide a target value for the net. For a pulldown resistor, this should be below the lowest VIL level of
all inputs connected to the net. For a pullup resistor, this should be above the highest VIH level of all
inputs on the net. A reasonable choice would be to target the VOL or VOH levels for the logic family of
the limiting device; which, by definition, have margin to the VIL and VIH levels.
• Select a pullup/pulldown resistor with the largest possible value; but, which can still ensure that the net
will reach the target pulled value when maximum current from all devices on the net is flowing through
the resistor. The current to be considered includes leakage current plus, any other internal and
external pullup/pulldown resistors on the net.
• For bidirectional nets, there is an additional consideration which sets a lower limit on the resistance
value of the external resistor. Verify that the resistance is small enough that the weakest output buffer
can drive the net to the opposite logic level (including margin).
• Remember to include tolerances when selecting the resistor value.
• For pullup resistors, also remember to include tolerances on the DVDD rail.
For most systems, a 1-kΩ resistor can be used to oppose the IPU/IPD while meeting the above criteria.
Users should confirm this resistor value is correct for their specific application.
For most systems, a 20-kΩ resistor can be used to compliment the IPU/IPD on the boot and configuration
pins while meeting the above criteria. Users should confirm this resistor value is correct for their specific
application.

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For most systems, a 20-kΩ resistor can also be used as an external PU/PD on the pins that have
IPUs/IPDs disabled and require an external PU/PD resistor while still meeting the above criteria. Users
should confirm this resistor value is correct for their specific application.
For more detailed information on input current (II), and the low-/high-level input voltages (VIL and VIH) for
the device, see Section 6.4, Electrical Characteristics Over Recommended Ranges of Supply Voltage and
Operating Temperature.
For the internal pullup/pulldown resistors for all device pins, see the peripheral/system-specific terminal
functions table.

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5 System Interconnect
The device’s various processors, subsystems, and peripherals are interconnected through a switch fabric
architecture. The switch fabric is composed of an L3 and L4 interconnect, a switched central resource
(SCR), and multiple bridges (for an overview, see Figure 5-1). Not all Initiators in the switch fabric are
connected to all Target peripherals. The supported initiator and target connections are designated by a "X"
in Table 5-1, Target/Initiator Connectivity.
For more detailed information on the device System Interconnect Architecture, see the TMS320DM814x
DaVinci Digital Media Processors Technical Reference Manual (Literature Number: SPRUGZ8).

EDMATC RD 0/1
DSP MDMA
EDMATC WR 0/1

Note1
L3F L3F L3F
Initiators Initiators L3S Initiators
Initiators USB2.0 (2 I/F)
ARM Cortex PCIe
EDMATC RD 2/3 System MEDIACTL DSP CFG
A8 EDMATC WR 2/3 EMAC SW
HDVICP2 MMU
SATA
HDVPSS (2 I/F) DAP
ISS
SGX530

128b 64b 128b 128b 128b 64b 32b 32b

1 I/F 9 I/F 1 I/F 4 I/F 2 I/F 7 I/F 4 I/F

L3F/L3Mid
L3S Interconnect
Interconnect
100 MHz (Note 2)
200 MHz (Note 2)

2 I/F 2 I/F 5 I/F 11 I/F 2 I/F 8 I/F 2 I/F

128b 128b 128b 64b 32b 32b 32b 32b

DMM L3F L3F L3F L3S Targets

Targets Targets Targets L4F L4S
Interconnect MCASP 0/1 / 2 Data Interconnect
PCIe ISS
200 MHz MCBSP 100 MHz
MEDIACTL MMCSD 2
DDR0 DDR1 DSP SDMA GPMC
SGX530 HDVICP2 CFG
HDVICP2 SL2 (Note 2) HDMI (Note2)
OCMC SRAM EDMATC 0/1/2/3 USB
EDMACC
DEBUGSS 11 I/F 58 I/F

32b 32b

L4S Targets
L4F Targets
MMU
UART 0/1/2/3/4/5
EMAC SW I2C 0/1/2/3
SATA
DMTimer 0/1/2/3/4/5/6/7/8
MCASP 3/4/5 CFG
SPI 0/1/2/3
MCASP 3/4/5 DATA
GPIO 0/1/2/3
MCASP 0/1/2 CFG
MMCSD 0 /1
ELM
RTC
WDT 0/1
Mailbox
Spinlock
HDVPSS
HDMIPHY
PLLSS
Control Module
PRCM
DCAN 0/1
OCPWP
Note 1 : TPTC 0/1 RD/WR transactions can optionally be routed through System MMU using chip control module SYNCTIMER32K
Note 2 : The frequencies specified are for 100% OPP

Figure 5-1. System Interconnect

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Table 5-1. L3 Master/Slave Connectivity (1)

(1) X = Connection exists.
S = Selectable path based on thirty-third address bit from control module register for System MMU accessible targets. Non-System
MMU accessible targets (such as, C674x SDMA) will always be direct mapped.
SLAVES

EDMA DMM Tiler/Lisa0

EDMA DMM Tiler/Lisa1

EDMA TPTC0 - 3 CFG

L4 Std Periph Port 0

L4 Std Periph Port 1

L4 HS Periph Port 0

L4 HS Periph Port 1
HDMI 1.3 Tx Audio
EDMA DMM ELLA

PCIe Gen2 Slave

Media Controller
HDVICP2 SL2
System MMU

HDVICP2 Hst

C674x SDMA

L3 Registers
McASP 0/1/2

EDMA TPCC

USB2.0 CFG
OCMC RAM

Imaging SS
SGX530

McBSP
GPMC
MASTERS SD2
ARM M1 (128-bit) X
ARM M2 (64-bit) X X X X X X X X X X X X X X X X X X X X
C674x MDMA X
System MMU X X X X X X X X X
C674x CFG X X X X X
HDVICP2 VDMA X X
HDVPSS Mstr0 X X X X
HDVPSS Mstr1 X X X X
SGX530 BIF X X X X X
SATA X X X X X
EMAC SW X X X X
USB2.0 DMA X X X
USB2.0 Queue Mgr X X X X X
PCIe Gen2 X X X X X X X X X X X X X X X X X X
Media Controller X X X X X X X X X X X X X X X X X
DeBug Access Port (DAP) X X X X X X X X X X X X X X X X X X
EDMA TPTC0 RD S X X X X X X X X X X X X X X X X X X
EDMA TPTC0 WR S X X X X X X X X X X X X X X X X X X
EDMA TPTC1 RD S X X X X X X X X X X X X X X X X X X
EDMA TPTC1 WR S X X X X X X X X X X X X X X X X X X
EDMA TPTC2 RD X X X X X X X X X X X X X X X X X X
EDMA TPTC2 WR X X X X X X X X X X X X X X X X X X
EDMA TPTC3 RD X X X X X X X X X X X X X X X X X X
EDMA TPTC3 WR X X X X X X X X X X X X X X X X X X
ISS X X X X

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The L4 interconnect is a non-blocking peripheral interconnect that provides low-latency access to a large
number of low-bandwidth, physically-dispersed target cores. The L4 can handle incoming traffic from up to
four initiators and can distribute those communication requests to and collect related responses from up to
63 targets.
The device provides two interfaces with L3 interconnect for high-speed peripheraland standard peripheral.

Table 5-2. L4 Peripheral Connectivity (1)

MASTERS
L4 PERIPHERALS ARM Cortex- EDMA EDMA EDMA EDMA C674x System
PCIe
A8 M2 (64-bit) TPTC0 TPTC1 TPTC2 TPTC3 CONFIG MMU
L4 Fast Peripherals Port 0/1
EMAC SW Port0 Port1 Port0 Port1 Port0 Port0 Port0 Port1
SATA Port0 Port1 Port0 Port1 Port0 Port1
McASP3 CFG Port0 Port1 Port0 Port1 Port0 Port0 Port0 Port1
McASP4 CFG Port0 Port1 Port0 Port1 Port0 Port0 Port0 Port1
McASP5 CFG Port0 Port1 Port0 Port1 Port0 Port0 Port0 Port1
McASP3 DATA Port0 Port1 Port0 Port1 Port0 Port0 Port0 Port1
McASP4 DATA Port0 Port1 Port0 Port1 Port0 Port0 Port0 Port1
McASP5 DATA Port0 Port1 Port0 Port1 Port0 Port0 Port0 Port1
L4 Slow Peripherals Port 0/1
I2C0 Port0 Port1 Port0 Port1 Port0 Port0 Port0 Port1
I2C1 Port0 Port1 Port0 Port1 Port0 Port0 Port0 Port1
I2C2 Port0 Port1 Port0 Port1 Port0 Port0 Port0 Port1
I2C3 Port0 Port1 Port0 Port1 Port0 Port0 Port0 Port1
SPI0 Port0 Port1 Port0 Port1 Port0 Port0 Port0 Port1
SPI1 Port0 Port1 Port0 Port1 Port0 Port0 Port0 Port1
SPI2 Port0 Port1 Port0 Port1 Port0 Port0 Port0 Port1
SPI3 Port0 Port1 Port0 Port1 Port0 Port0 Port0 Port1
UART0 Port0 Port1 Port0 Port1 Port0 Port0 Port0 Port1
UART1 Port0 Port1 Port0 Port1 Port0 Port0 Port0 Port1
UART2 Port0 Port1 Port0 Port1 Port0 Port0 Port0 Port1
UART3 Port0 Port1 Port0 Port1 Port0 Port0 Port0 Port1
UART4 Port0 Port1 Port0 Port1 Port0 Port0 Port0 Port1
UART5 Port0 Port1 Port0 Port1 Port0 Port0 Port0 Port1
Timer1 Port0 Port1 Port0 Port1 Port0 Port0 Port0 Port1
Timer2 Port0 Port1 Port0 Port1 Port0 Port0 Port0 Port1
Timer3 Port0 Port1 Port0 Port1 Port0 Port0 Port0 Port1
Timer4 Port0 Port1 Port0 Port1 Port0 Port0 Port0 Port1
Timer5 Port0 Port1 Port0 Port1 Port0 Port0 Port0 Port1
Timer6 Port0 Port1 Port0 Port1 Port0 Port0 Port0 Port1
Timer7 Port0 Port1 Port0 Port1 Port0 Port0 Port0 Port1
Timer8 Port0 Port1 Port0 Port1 Port0 Port0 Port0 Port1
GPIO0 Port0 Port1 Port0 Port1 Port0 Port0 Port0 Port1
GPIO1 Port0 Port1 Port0 Port1 Port0 Port0 Port0 Port1
MMC/SD0/SDIO Port0 Port1 Port0 Port1 Port0 Port1
MMC/SD1/SDIO Port0 Port1 Port0 Port1 Port0 Port1
MMC/SD2/SDIO Port0 Port1 Port0 Port1 Port0 Port1
WDT0 Port0 Port1 Port0 Port1 Port0 Port1
RTC Port0 Port1 Port0 Port1 Port0 Port1

(1) X, Port0, Port1 = Connection exists.

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Table 5-2. L4 Peripheral Connectivity(1) (continued)

MASTERS
L4 PERIPHERALS ARM Cortex- EDMA EDMA EDMA EDMA C674x System
PCIe
A8 M2 (64-bit) TPTC0 TPTC1 TPTC2 TPTC3 CONFIG MMU
System MMU Port0 Port1 Port0 Port1 Port0 Port0 Port0 Port1
Mailbox Port0 Port0 Port0
Spinlock Port0 Port0 Port0
HDVPSS Port0 Port1 Port0 Port1 Port0 Port1
PLLSS Port0 Port1
Control/Top Regs Port0 Port1
(Control Module)
PRCM Port0 Port1
ELM Port0 Port1
HDMIPHY Port0 Port1
DCAN0 Port0 Port1 Port0 Port1 Port0 Port1
DCAN1 Port0 Port1 Port0 Port1 Port0 Port1
OCPWP Port0 Port0
McASP0 CFG Port0 Port1 Port0 Port1 Port0 Port0 Port0 Port1
McASP1 CFG Port0 Port1 Port0 Port1 Port0 Port0 Port0 Port1
McASP2 CFG Port0 Port1 Port0 Port1 Port0 Port0 Port0 Port1
SYNCTIMER32K Port0 Port1 Port0 Port1 Port0 Port1

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6 Device Operating Conditions

(1) (2)
6.1 Absolute Maximum Ratings
Core (CVDD, CVDD_ARM, CVDD_DSP, CVDD_HDVICP) -0.3 V to 1.5 V
I/O, 1.8 V (DVDD_M, DVDD_DDR[0], DVDD_DDR[1], VDDA_1P8, VDDA_ARMPLL_1P8, -0.3 V to 2.1 V
VDDA_DSPPLL_1P8, VDDA_VID0PLL_1P8, VDDA_VID1PLL_1P8,
Supply voltage ranges VDDA_AUDIOPLL_1P8, VDDA_DDRPLL_1P8, VDDA_L3PLL_1P8, VDDA_PCIE_1P8,
(Steady State): VDDA_SATA_1P8, VDDA_HDMI_1P8, VDDA_USB0_1P8, VDDA_USB1_1P8,
VDDA_VDAC_1P8)
I/O 3.3 V (DVDD, DVDD_GPMC, DVDD_GPMCB, DVDD_SD, DVDD_C) -0.3 V to 4.0 V
DDR Reference Voltage (VREFSSTL_DDR[0], VREFSSTL_DDR[1]) -0.3 V to 1.1 V
V I/O, 1.5-V pins (Steady State) -0.3 V to
DVDD_DDR[x] + 0.3
V
V I/O, 1.8-V pins (Steady State) -0.3 V to DVDD +
0.3 V
Input and Output voltage
-0.3 V to DVDD_x +
ranges:
0.3 V
V I/O, 3.3-V pins (Steady State) -0.3 V to DVDD +
0.3 V
-0.3 V to DVDD_x +
0.3 V
Commercial Temperature 0°C to 90°C
Operating junction
Industrial -40°C to 90°C
temperature range, TJ:
Extended -40°C to 105°C
Storage temperature -55°C to 150°C
range, Tstg:
I-test: Silicon Revision 3.0, All I/O pins (3) ±100 mA
Latch-up Performance: I-test: Silicon Revision 2.1, All I/O pins (3) ±70 mA
(4)
Over-Voltage Test, All Supply pins 1.5xVddmax V
Electrostatic Discharge ESD-HBM (Human Body Model) (5) ±1000 V
(ESD) Performance: ESD-CDM (Charged-Device Model) (6) ±250 V
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to their associated VSS or VSSA_x.
(3) Pins stressed per JEDEC JESD78 at 90°C (Class II) and passed with specified I/O pin injection current and clamp voltage of 1.5 times
maximum recommended I/O voltage and negative 0.5 times maximum recommended I/O voltage.
(4) Supplies stressed per JEDEC JESD78 at 90°C (Class II) and passed specified voltage injection.
(5) Level listed is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows safe
manufacturing with a standard ESD control process, and manufacturing with less than 500-V HBM is possible if necessary precautions
are taken. Pins listed as 1000 V may actually have higher performance.
(6) Level listed is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250-V CDM allows safe
manufacturing with a standard ESD control process, and manufacturing with less than 250-V CDM is possible if necessary precautions
are taken. Pins listed as 250 V may actually have higher performance.

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6.2 Recommended Operating Conditions

PARAMETER MIN NOM MAX UNIT
Supply voltage, Core (Scalable) 166% OPP 1.28 1.35 1.42
DVFS only, No AVS
120% OPP 1.14 1.20 1.26
CVDD 100% OPP 1.05 1.10 1.16 V
Supply voltage, Core ARM 166% OPP 1.28 1.35 1.42
(Scalable)
120% OPP 1.14 1.20 1.26
DVFS only, No AVS
CVDD_ARM 100% OPP 1.05 1.10 1.16 V
Supply voltage, Core, DSP 166% OPP 1.28 1.35 1.42
(Scalable)
120% OPP 1.14 1.20 1.26
DVFS only, No AVS
CVDD_DSP 100% OPP 1.05 1.10 1.16 V
Supply voltage, Core, HDVICP2 166% OPP 1.28 1.35 1.42
(Scalable)
120% OPP 1.14 1.20 1.26
DVFS only, No AVS
CVDD_HDVICP 100% OPP 1.05 1.10 1.16 V
Supply voltage, I/O, standard 3.3 V 3.14 3.3 3.47
DVDD pins (1) V
1.8 V 1.71 1.8 1.89
Supply voltage, I/O, GPMC pin 3.3 V 3.14 3.3 3.47
DVDD_GPMC group V
1.8 V 1.71 1.8 1.89
Supply voltage, I/O, GPMCB pin 3.3 V 3.14 3.3 3.47
DVDD_GPMCB group V
1.8 V 1.71 1.8 1.89
Supply voltage, I/O, SD pin group 3.3 V 3.14 3.3 3.47
DVDD_SD V
1.8 V 1.71 1.8 1.89
Supply voltage, I/O, C pin group 3.3 V 3.14 3.3 3.47
DVDD_C V
1.8 V 1.71 1.8 1.89
DVDD_M Supply voltage, I/O, M pin group 1.8 V 1.71 1.8 1.89 V
DVDD_DDR[0] Supply voltage, I/O, DDR[0] and DDR2 1.71 1.8 1.89
DDR[1] V
DVDD_DDR[1] DDR3 mode 1.43 1.5 1.58
VDDA_USB_3P Supply voltage, I/O, Analog, USB 3.3 V
3.14 3.3 3.47 V
3
Supply Voltage, I/O, Analog, (VDDA_1P8,
VDDA_ARMPLL_1P8, VDDA_DSPPLL_1P8,
VDDA_VID0PLL_1P8, VDDA_VID1PLL_1P8,
VDDA_AUDIOPLL_1P8, VDDA_DDRPLL_1P8,
VDDA_1P8
VDDA_L3PLL_1P8, VDDA_PCIE_1P8, VDDA_SATA_1P8, 1.71 1.8 1.89 V
VDDA_x_1P8
VDDA_HDMI_1P8, VDDA_USB0_1P8, VDDA_USB1_1P8,
VDDA_VDAC_1P8)
Note: HDMI, USB0/1, and VDAC relative to their respective
VSSA.
Supply Ground (VSS, VSSA_HDMI, VSSA_USB,
VSS 0 V
VSSA_VDAC, VSSA_DEVOSC (2), VSSA_AUXOSC (2))
IO Reference Voltage, (VREFSSTL_DDR[0], 0.49 *
0.50 * 0.51 *
VREFSSTL_DDR[x] VREFSSTL_DDR[1]) DVDD_DDR[ V
DVDD_DDR[x] DVDD_DDR[x]
x]
USBx_VBUSIN USBx VBUS Comparator Input 4.75 5 5.25 V
High-level input voltage, LVCMOS (JTAG[TCK] pins), 3.3
2 V
V (1)
High-level input voltage, JTAG[TCK], 3.3 V 2.15 V
VIH
High-level input voltage, JTAG[TCK], 1.8 V 1.45 V
High-level input voltage, I2C (I2C[0] and I2C[1]) 0.7DVDD V
High-level input voltage, LVCMOS (1), 1.8 V 0.65DVDDx V

(1) LVCMOS pins are all I/O pins powered by DVDD, DVDD_GPMC, DVDD_GPMCB, DVDD_SD, DVDD_C supplies except for I2C[0] and
I2C[1] pins.
(2) When using the internal Oscillators, the oscillator grounds (VSSA_DEVOSC, VSSA_AUXOSC) must be kept separate from other
grounds and connected directly to the crystal load capacitor ground.
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Recommended Operating Conditions (continued)

PARAMETER MIN NOM MAX UNIT
Low-level input voltage, LVCMOS (1), 3.3 V 0.8 V
Low-level input voltage, JTAG[TCK] 0.45 V
VIL
Low-level input voltage, I2C (I2C[0] and I2C[1]) 0.3DVDDx V
Low-level input voltage, LVCMOS (1), 1.8 V 0.35DVDDx V
High-level output current 6 mA I/O buffers -6 mA
IOH DDR[0], DDR[1] buffers
@ 50-Ω impedance -8 mA
setting
Low-level output current 6 mA I/O buffers 6 mA
IOL DDR[0], DDR[1] buffers
@ 50-Ω impedance 8 mA
setting
VID Differential input voltage (SERDES_CLKN/P), [AC coupled] 0.250 2.0 V
Transition time, 10% - 90%, All inputs (unless otherwise
tt specified in the Electrical Data/Timing sections of each 0.25P or 10 (3) ns
peripheral)
Commercial
0 90 °C
Temperature (default)
Operating junction temperature
TJ
range (4) Industrial -40 90 °C
Extended -40 105 °C
(3) Whichever is smaller. P = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve
noise immunity on input signals.
(4) For more detailed information on estimating junction temps within systems, see the IC Package Thermal Metrics Application Report
(Literature Number: SPRA953).

6.3 Power-On Hours (POH)

The POH information in Table 6-1 is provided solely for convenience and does not extend or modify the warranty
provided under TI’s standard terms and conditions for TI Semiconductor Products. To avoid significant device
degradation, the device POH must be limited to those shown in Table 6-1.

Table 6-1. Power-On Hour Limits

Junction
Operating Condition Nominal CVDD Voltage (V) Lifetime POH (1)
Temperature (Tj)
100% OPP 1.1 -40 to 105 °C 100K
120% OPP 1.2 -40 to 105 °C 100K
166% OPP 1.35 -40 to 105 °C 49K
(1) POH represent device operation under the specified nominal conditions continuously for the duration of the calculated lifetime.

Logic functions and parameter values are not ensured out of the range specified in Section 6.2,
Recommended Operating Conditions.
The above notations cannot be deemed a warranty or deemed to extend or modify the warranty under TI’s
standard terms and conditions for semiconductor products.

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6.4 Electrical Characteristics Over Recommended Ranges of Supply Voltage and

Operating Temperature (Unless Otherwise Noted)
PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT
Low/Full speed: USB_DM 2.8 VDD_USB_3P V
and USB_DP 3
High speed: USB_DM and 360 440 mV
USB_DP
VOH
High-level output voltage, 3.3 V, DVDDx = MIN, IOH = 2.4 V
LVCMOS (2) (3.3-V I/O) MAX
High-level output voltage, 1.8 V, DVDDx = MIN, IOH = 1.26 V
LVCMOS (2) (1.8-V I/O) MAX
Low/Full speed: USB_DM 0.0 0.3 V
and USB_DP
High speed: USB_DM and -10 10 mV
USB_DP
Low-level output voltage, 3.3 V, DVDDx = MAX, IOL = 0.4 V
VOL
LVCMOS (2) (3.3-V I/O) MAX
Low-level output voltage, 1.8 V, DVDDx = MAX, IOL = 0.4 V
LVCMOS (2) (1.8-V I/O) MAX
Low-level output voltage, 1.8/3.3 V, IOL = 4mA
0.4 V
I2C (I2C[0], I2C[1])
LDOs (applies to all
1.5 V
LDOCAP_x pins)
Input current, LVCMOS (2), 0 < VI < DVDDx, 3.3 V pull
-20 20 µA
3.3 V mode disabled
0 < VI < DVDDx, 3.3 V
20 100 300 µA
pulldown enabled (4)
0 < VI < DVDDx, 3.3 V
-20 -100 -300 µA
pullup enabled (4)
Input current, LVCMOS (2), 0 < VI < DVDDx, 1.8 V pull
II (3) -5 5 µA
1.8 V mode disabled
0 < VI < DVDDx, 1.8 V
50 100 200 µA
pulldown enabled (4)
0 < VI < DVDDx, 1.8 V
-50 -100 -200 µA
pullup enabled (4)
Input current, I2C (I2C[0], 3.3 V mode -20 20 µA
I2C[1])
1.8 V mode -5 5 µA
3.3 V mode, pull enabled -300 300 µA
3.3 V mode, pull disabled -20 20 µA
IOZ (5) I/O Off-state output current
1.8 V mode, pull enabled -200 200 µA
1.8 V mode, pull disabled -5 5 µA
(6)
ICDD Core (CVDD) supply current (scalable) see note mA
(6)
ARM Core Current see note mA
ICVDD_ARM
(Scalable)
(6)
DSP Core Current see note mA
ICVDD_DSP
(Scalable)
(6)
HDVICP2 Core Current see note mA
ICVDD_HDVICP
(Scalable)

(1) For test conditions shown as MIN, MAX, or TYP, use the appropriate value specified in the recommended operating conditions table.
(2) LVCMOS pins are all I/O pins powered by DVDD, DVDD_GPMC, DVDD_GPMCB, DVDD_SD, DVDD_C supplies except for I2C[0] and
I2C[1] pins.
(3) II applies to input-only pins and bi-directional pins. For input-only pins, II indicates the input leakage current. For bi-directional pins, II
indicates the input leakage current and off-state (Hi-Z) output leakage current.
(4) Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.
(5) IOZ applies to output-only pins, indicating off-state (Hi-Z) output leakage current.
(6) The actual current draw varies across manufacturing processes and is highly application-dependent. For more details on core and I/O
activity, as well as information relevant to board power supply design, see the TMS320DM814x/AM387x Power Estimation Spreadsheet
Application Report (Literature Number: SPRABO3). To determine the worst-case power consumption values, use the
TMS320DM814x/AM387x Power Estimation Spreadsheet Application Report.
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Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Temperature
(Unless Otherwise Noted) (continued)
PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT
(6)
3.3-V I/O (DVDD, see note mA
DVDD_GPMC,
DVDD_GPMCB,
DVDD_SD, DVDD_C,
VDDA_USB_3P3) supply
current
(6)
1.8-V I/O (DVDD, see note mA
DVDD_GPMC,
IDDD DVDD_GPMCB,
DVDD_SD, DVDD_C
DVDD_M, DVDD_DDR[0],
DVDD_DDR[1] [for DDR2],
VDDA_x_1P8) supply
current
(6)
1.5-V I/O (DVDD_DDR[0], see note mA
DVDD_DDR[1] [for DDR3
SDRAM]) supply current
Input capacitance 12 pF
CI
LVCMOS (2)
Output capacitance 12 pF
Co
LVCMOS (2)

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7 Power, Reset, Clocking, and Interrupts

7.1 Power, Reset and Clock Management (PRCM) Module

The PRCM module is the centralized management module for the power, reset, and clock control signals
of the device. The PRCM interfaces with all the components on the device for power, clock, and reset
management through power-control signals. The PRCM module inTiming Requirements for
AUD_CLKINxtegrates enhanced features to allow the device to adapt energy consumption dynamically,
according to changing application and performance requirements. The innovative hardware architecture
allows a substantial reduction in leakage current.
The PRCM module is composed of two main entities:
• Power reset manager (PRM): Handles the power, reset, wake-up management, and system clock
source control (oscillator)
• Clock manager (CM): Handles the clock generation, distribution, and management.
For more details on the PRCM, see the Power, Reset, and Clock Management (PRCM) Module chapter of
the TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual (Literature Number:
SPRUGZ8).

7.2 Power

7.2.1 Voltage and Power Domains

Every Module within the device belongs to a Core Logic Voltage Domain, Memory Voltage Domain, and a
Power Domain (see Table 7-1).

Table 7-1. Voltage and Power Domains

CORE LOGIC MEMORY VOLTAGE POWER
MODULES
VOLTAGE DOMAIN DOMAIN DOMAIN
ARM_L ARM_M ARM Cortex-A8 Subsystem
DCAN0/1, DMM, EDMA, ELM, DDR0/1, EMAC Switch,
GPIO Banks 0/1/2/3,GPMC, I2C0/1/2/3, IPC,
ALWAYS ON MCASP0/1/2/3/4/5, MCBSP, OCMC SRAM, PCIE,
CORE_L CORE_M PRCM, RTC, SATA, SD/MMC0/1/2, SPI01/2/3,
Timer1/2/3/4/5/6/7/8, UART0/1/2/3/4/5, USB0/1,
WDT0, System Interconnect, JTAG, Media Controller,
ISS
GFX SGX530
HDVPSS HDVPSS, HDMI, SD-DAC
DSP_L DSP_M DSP C674x DSP and L2 SRAM
HDVICP_L HDVICP_M HDVICP HDVICP2

7.2.1.1 Core Logic Voltage Domains

The device contains four Core Logic Voltage Domains. These domains define groups of Modules that
share the same supply voltage for their core logic. Each Core Logic Voltage Domain is powered by a
dedicated supply voltage rail. Table 7-2 shows the mapping between the Core Logic Voltage Domains and
their associated supply pins.

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Table 7-2. Core Logic Voltage Domains and Supply Pin Associations
CORE LOGIC SUPPLY PIN NAME
VOLTAGE DOMAIN
ARM_L CVDD_ARM
CORE_L CVDD
DSP_L CVDD_DSP
HDVICP_L CVDD_HDVICP

Note: A regulated supply voltage must be supplied to each Core Logic Voltage Domain at all times,
regardless of the Core Logic Power Domain states.

7.2.1.2 Memory Voltage Domains

The SRAM within each Device Module is assigned to one of four Memory Voltage Domains. The voltage
of each Memory Voltage Domain is independently controlled by internal LDO regulators, which are
supplied by the VDDA_1P8 pins.
The voltage level output by each of these LDO regulators is controlled through software by programming
the RAMLDO_CTRLx registers in the Control Module. The Memory Voltage Domain voltage must be
programmed based on the Core Logic Voltage Domain voltage for that domain (that is, the corresponding
Core Logic Voltage Domain for the ARM_M Voltage Domain is ARM_C, and so on). Table 7-3 shows the
Memory Voltage Domain voltage requirements.

Table 7-3. Memory Voltage Domain LDO Requirements

CORE LOGIC VOLTAGE MEMORY VOLTAGE DOMAIN
DOMAIN VOLTAGE (V) VOLTAGE (V)
0.83 – 1.20 1.20

7.2.1.3 Power Domains

The device contains six Power Domains which supply power to both the Core Logic and SRAM within their
associated modules. Each Power Domain, except for the ALWAYS ON domain, has an internal power
switch that can completely remove power from that domain. All power switches are turned "OFF" by
default after reset, and software can individually turn them "ON/OFF" via Control Module registers.
Note: All Modules within a Power Domain are unavailable when the domain is powered "OFF". For
instructions on powering "ON/OFF" the Power domains, see the Power, Reset, and Clock Management
(PRCM) Module chapter of the TMS320DM814x DaVinci Digital Media Processors Technical Reference
Manual (Literature Number: SPRUGZ8).

7.2.2 SmartReflex [Not Supported]

The device contains SmartReflex modules that help to minimize power consumption on the Core Logic
Voltage Domains by using external variable-voltage power supplies. Based on the device process,
temperature, and desired performance, the SmartReflex modules advise the host processor to raise or
lower the supply voltage to each domain for minimal power consumption.
The communication link between the host processor and the external regulators is a system-level decision
and can be accomplished using GPIOs, I2C, SPI, or other methods. The following sections briefly
describe the two major techniques employed by SmartReflex: Dynamic Voltage Frequency Scaling
(DVFS) and Adaptive Voltage Scaling (AVS).

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7.2.2.1 Dynamic Voltage Frequency Scaling (DVFS)

Each device Core Logic Voltage Domain can be run independently at one of several Operating
Performance Points (OPPs). An OPP for a specific Core Logic Voltage Domain is defined by: (1)
maximum frequencies of operation for Modules within the Domain and (2) an associated supply voltage
range. Trading off power versus performance, OPPs with lower maximum frequencies also have lower
voltage ranges for power savings.
The OPP for a domain can be changed in real-time without requiring a reset. This feature is called
Dynamic Voltage Frequency Scaling (DVFS). Table 7-4 contains a list of voltage ranges and maximum
module frequencies for the OPPs of each Core Logic Voltage Domain.

Table 7-4. Device Operating Points (OPPs)

CORE LOGIC VOLTAGE DOMAINS
ARM DSP HDVICP CORE
L3/L4,
Cortex A8 DSP HDVICP2 HDVPSS SGX ISS Media Ctlr. DDR
OPP Core
(MHz) (MHz) (MHz) (MHz) (MHz) (MHz) (MHz) (MHz) (1)
(MHz)
100%
600 500 266 200 200 400 200 200 400
(1.1 V)
120%
720 600 306 200 250 400 200 220 400
(1.2 V)
166%
700
(CYE1) 1000 410 220 280 480 240 220 533
750 (2)
(1.35 V)
166%
(CYE2) 1000 750 450 220 280 560 280 220 533
(1.35 V)

(1) All DDR access must be suspended prior to changing the DDR frequency of operation.
(2) Only DM814x SR3.0 devices support a DSP Frequency of 750-MHz. For more details on device silicon revisions, see Figure 9-1, Device
Nomenclature.

Although the OPP for each Core Logic Voltage Domain is independently selectable, not all combinations
of OPPs are supported. Table 7-5 marks the supported ARM, DSP, and HDVICP2 OPPs for a given
CORE OPP.

Table 7-5. Supported OPP Combinations (1) (2)

ARM DSP HDVICP2
CORE OPP166 OPP120 OPP100 OPP166 OPP120 OPP100 OPP166 OPP120 OPP100
OPP166 X X X
OPP120 X X X X X X
OPP100 X X X X X X

(1) "X" denotes supported combinations.

(2) The maximum voltage differences between CVDD and any other CVDD_x voltage domain must be < 150 mV.

7.2.2.2 Adaptive Voltage Scaling [Not Supported]

As mentioned in Section 7.2.2.1, Dynamic Voltage Frequency Scaling (DVFS) above, every OPP has an
associated voltage range. Based on the silicon process, temperature, and chosen OPP, the SmartReflex
modules guide software in adjusting the Core Logic Voltage Domain supply voltages within these ranges.
This technique is called Adaptive Voltage Scaling (AVS). AVS occurs continuously and in real-time,
helping to minimize power consumption in response to changing operating conditions.

7.2.3 Memory Power Management

To reduce SRAM leakage, many SRAM blocks can be switched from ACTIVE mode to SHUTDOWN
mode. When SRAM is put in SHUTDOWN mode, the voltage supplied to it is automatically removed and
all data in that SRAM is lost.

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All SRAM located in a switchable power domain (all domains except ALWAYS_ON) automatically enters
SHUTDOWN mode whenever its associated power domain goes into the "OFF" state. The SRAM returns
to the ACTIVE state when the corresponding Power Domain returns to the "ON" state.
In addition, the following SRAM within the ALWAYS_ON Power Domain can also be independently put
into SHUTDOWN by programming the x_MEM_PWRDN registers in the Control Module:
• Media Controller SRAM
• OCMC SRAM
For detailed instructions on powering up/down the various device SRAM, see the Control Module chapter
of the TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual (Literature
Number: SPRUGZ8).

7.2.4 SERDES_CLKP and SERDES_CLKN LDO

The SERDES_CLKP and SERDES_CLKN input buffers are powered by an internal LDO which is
programmed through the REFCLK_LJCBLDO_CTRL register in the Control Module.
For more information on programming the SERDES_CLKP and SERDES_CLKN LDO, see PCI Express
(PCIe) Module and Serial ATA (SATA) Controller chapters of the TMS320DM814x DaVinci Digital Media
Processors Technical Reference Manual (Literature Number: SPRUGZ8).

7.2.5 Dual Voltage I/Os

The device supports dual voltages on some of its I/Os. These I/Os are partitioned into the following
groups, and each group has its own dedicated supply pins: DVDD, DVDD_GPMC, DVDD_C, and
DVDD_SD. The supply voltage for each group can be independently powered with either 1.8 V or 3.3 V.
For the mapping between pins and power groups, see Section 3.2, Terminal Functions of the datasheet.
In addition, the I/O voltage on each DDR interface is independently selectable between either 1.5 V or 1.8
V to support various DDR device types. The I/O supplies for each DDR interface are separate and isolated
to allow populating different memory types on each interface.

7.2.6 I/O Power-Down Modes

On the device, there are power-down modes available for the following PHYs:
• Video DAC
• DDR
• USB
• HDMI
• PCIE
• SATA
When a PHY controller is in a power domain that is to be turned "OFF", software must configure the
corresponding PHY into power-down mode, prior to putting the power domain in the "OFF" state.

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7.2.7 Standby Mode

The device supports Low-Power Standby Mode as described below.
Standby Mode is defined as a state in which:
• All switchable power domains are in "OFF" state
• The ARM Cortex-A8 is executing an IDLE loop at its lowest frequency of operation
• All functional blocks not needed for a given application are clock gated
For detailed instructions on entering and exiting from Standby Mode see the Power, Reset, and Clock
Management (PRCM) Module chapter of the TMS320DM814x DaVinci Digital Media Processors Technical
Reference Manual (Literature Number: SPRUGZ8).

7.2.8 Supply Sequencing

The device power supplies are organized into four Supply Sequencing Groups:
1. All CVDD supplies (CVDD, CVDD_x)
2. All 1.5-/1.8-V DVDD_DDR[x] Supplies (1.5 V for DDR3, 1.8 V for DDR2)
3. All 1.8-V Supplies (DVDD_x, DVDD_M, VDDA_x_1P8, VDDA_1P8)
4. All 3.3-V Supplies (DVDD, DVDD_x, DVDD_C, VDDA_x_3P3)
To ensure proper device operation, a specific power-up and power-down sequence must be followed.
Some TI power-supply devices include features that facilitate these power sequencing requirements — for
example, TI’s TPS659113 integrated PMIC. For more information on TI power supplies and their features,
visit www.ti.com/processorpower.
For more detailed information on the actual power supply names and their descriptions, see Table 3-49,
Supply Voltages Terminal Functions.

7.2.8.1 Power-Up Sequence

For proper device operation, the following power-up sequence in Table 7-6 and must be followed.

Table 7-6. Power-Up Sequence Ramping Values

NO. DESCRIPTION MIN MAX UNIT
1.8 V and DVDD_DDR[x] supplies stable to 3.3 V supplies
1 0 ms
ramp start
(1)
2 1.8 V supplies to 1.5-/1.8- V DVDD_DDR[x] supplies 0 ms
1.8 V supplies stable to CVDD, CVDD_x variable supplies
3 0 (1) ms
ramp start
CVDD variable supply ramp start to CVDD_x variable
13 0 ms
supplies ramp start
Master
4 All supplies valid to power-on-reset (POR high) 4 096
Clocks
(1) The 1.8 V supplies must be ≥ 1.5-/1.8-V DVDD_DDR[x] supplies.

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1.8 V Supplies
(DVDD, DVDD_x, DVDD_M, VDDA_x_1P8,
VDDA_1P8)

3.3 V Supplies
(DVDD, DVDD_x, DVDD_C, VDDA_x_3P3)

1.5 V/1.8 V DVDD_DDR[x]

CVDD

Figure 7-1. Power-Up Sequence

7.2.8.2 Power-Down Sequence

For proper device operation, the following power-down sequence in Table 7-7 and Figure 7-2 must be
followed. Ramping down all supplies at the same time is allowed, provided the requirements in Table 7-7
are met.

Table 7-7. Power-Down Sequence Ramping Values

NO. DESCRIPTION MIN MAX UNIT
(1) (1)
8 CVDD, CVDD_x variable supply to 1.8 V supplies See See ms
(1) (1)
9 1.5-/1.8-V DVDD_DDR[x] supplies to 1.8 V supplies See See ms
(2) (2)
10 3.3 V supplies to 1.8 V supplies See See ms
CVDD_x variable supplies ramp-down start to CVDD
14 0 ms
variable supply ramp-down start
(1) The 1.5-/1.8-V DVDD_DDR[x] and CVDD, CVDD_x variable supplies can be powered down prior to or simultaneously with the 1.8-V
supplies.
(2) The 3.3 V supplies must never be more than 2 V above the 1.8 V supplies (see Figure 7-3).

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1.8 V Supplies
(DVDD, DVDD_x, DVDD_M, VDDA_x_1P8,
VDDA_1P8

3.3 V Supplies
(DVDD, DVDD_x, DVDD_C, VDDA_x_3P3)

Figure 7-2. Power-Down Sequence

Figure 7-3. 1.8 V Supplies Falling Before 3.3 V Supplies Delta

7.2.9 Power-Supply Decoupling

7.2.9.1 Analog and PLL

PLL and Analog supplies benefit from filters or ferrite beads to keep the noise from causing problems. The
minimum recommendation is a ferrite bead along with at least one capacitor on the device side of the
bead. An additional recommendation is to add one capacitor just before the bead to form a Pi filter. The
filter needs to be as close as possible to the device pin, with the device side capacitor being the most
important component to be close to the device pin. PLL pins close together can be combined on the same
supply, but analog pins should all have their own filters. PLL pins farther away from each other may need
their own filtered supply.

7.2.9.2 Digital
Recommended capacitors for power supply decoupling are all 0.1uF in the smallest body size that can be
used. Capacitors are more effective in the smallest physical size to limit lead inductance. For example,
0201 sized capacitors are better than 0402 sized capacitors, and so on. TI recommends using capacitors
no larger than 0402. Place at least one capacitor for every two power pins. For those power pins that have
only one pin, a capacitor is still required. Place one bulk (10 uF or larger) capacitor for every 10 or so
power pins as closely as possible to the chip. These larger caps do not need to be under the chip
footprint.

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Pay special attention not to put so much capacitance on the supply that it slows the start-up voltage ramp
enough to change the power sequencing order. Also be sure to verify that the main chip reset is low until
after all supplies are at their correct voltage and stable.
DDR peripheral related supply capacitor numbers are provided in Section 8.13, DDR2/DDR3 Memory
Controller.

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7.3 Reset

7.3.1 System-Level Reset Sources

The device has several types of system-level resets. Table 7-8 lists these reset types, along with the reset
initiator, and the effects of each reset on the device.

Table 7-8. System-Level Reset Types

RESETS ALL
MODULES,
EXCLUDING EMAC ASSERTS
RESETS EMAC RESETS PLL AND CLOCK LATCHES
TYPE INITIATOR SWITCH, RSTOUT_WD_OUT
SWITCH EMULATION CONFIG BOOT PINS
EMULATION, PLL PIN
AND CLOCK
CONFIG
Power-on Reset (POR) POR pin Yes Yes Yes Yes Yes Optional (1) (2)
(3)
External Warm Reset RESET pin Yes Optional No No Yes Optional (1) (2)
On-Chip Emulation
Emulation Warm Reset Yes Optional (3) No No No Optional (1)
Logic
Watchdog Reset Watchdog Timer Yes Optional (3) No No No Yes
Software Global Cold Reset Software Yes Optional (3) Yes Yes No Optional (1)
Software Global Warm Reset Software Yes Optional (3) No No No Optional (1)
Test Reset TRST pin No No Yes No No No

(1) RSTOUT_WD_OUT pin asserted only if BTMODE[11] was latched as "0" when coming out of reset.
(2) While POR and/or RESET is asserted, the RSTOUT_WD_OUT pin is 3-stated and the internal pull resistor is disabled; therefore, an
external pullup/pulldown can be used to set the state of this pin (high/low) while POR and/or RESET is asserted. For more detailed
information on external PUs/PDs, see Section 4.5.1, Pullup/Pulldown Resistors.
(3) EMAC Switch is NOT reset when the ISO_CONTROL bit in the RESET_ISO Control Module register is set to "1".

7.3.2 Power-on Reset (POR pin)

Power-on Reset (POR) is initiated by the POR pin and is used to reset the entire chip, including the Test
and Emulation logic, and the EMAC Switch. POR is also referred to as a cold reset since it is required to
be asserted when the device goes through a power-up cycle. However, a device power-up cycle is not
required to initiate a Power-on Reset.
The following sequence must be followed during a Power-on Reset:
1. Wait for the power supplies to reach normal operating conditions while keeping the POR pin asserted.
2. Wait for the input clock sources DEV_CLKIN, AUX_CLKIN, and SERDES_CLKN/P to be stable (if
used by the system) while keeping the POR pin asserted (low).
3. Once the power supplies and the input clock sources are stable, the POR pin must remain asserted
(low) [see Section 7.3.18, Reset Electrical Data/Timing]. Within the low period of the POR pin, the
following happens:
(a) All pins except Emulation pins enter a Hi-Z mode and the associated pulls, if applicable, will be
enabled.
(b) The PRCM asserts reset to all modules within the device.
(c) The PRCM begins propagating these clocks to the chip with the PLLs in BYPASS mode.
4. The POR pin may now be de-asserted (driven high). When the POR pin is de-asserted (high):
(a) The BTMODE[15:0] pins are latched.
(b) Reset to the ARM Cortex-A8 and Modules without a local processor is de-asserted.
(c) RSTOUT_WD_OUT is briefly asserted if BTMODE[11] was latched as "0".
(d) The clock, reset, and power-down state of each peripheral is determined by the default settings of
the PRCM.
(e) The ARM Cortex-A8 begins executing from the Boot ROM.

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7.3.3 External Warm Reset (RESET pin)

An external warm reset is activated by driving the RESET pin active-low. This resets everything in the
device, except for the Test and Emulation logic, and the EMAC Switch (optional). An emulator session
stays alive during warm reset.
The following sequence must be followed during a warm reset:
1. Power supplies and input clock sources should already be stable.
2. The RESET pin must be asserted (low)[see Section 7.3.18, Reset Electrical Data/Timing]. Within the
low period of the RESET pin, the following happens:
(a) All pins, except Test and Emulation pins, enter a Hi-Z mode and the associated pulls, if applicable,
will be enabled.
(b) The PRCM asserts reset to all modules within the device, except for the Test and Emulation logic,
EMAC Switch (optional), PLL, and Clock configuration.
3. The RESET pin may now be de-asserted (driven high). When the RESET pin is de-asserted (high):
(a) The BTMODE[15:0] pins are latched.
(b) Reset to the ARM Cortex-A8 and modules without a local processor is de-asserted, with the
exception of Test and Emulation logic, EMAC Switch (optional), PLL, and Clock configuration.
(c) RSTOUT_WD_OUT is asserted [see Section 7.3.18, Reset Electrical Data/Timing], if BTMODE[11]
was latched as "0".
(d) The clock, reset, and power-down state of each peripheral is determined by the default settings of
the PRCM.
(e) The ARM Cortex-A8 begins executing from the Boot ROM.

7.3.4 Emulation Warm Reset

An Emulation Warm Reset is activated by the on-chip Emulation Module and has the same effect and
requirements as an External Warm Reset (RESET), with the following exceptions:
• BTMODE[15:0] pins are not re-latched
• RSTOUT_WD_OUT is not 3-stated and is actively driven based on the value previously latched on the
BTMODE[11] pin.
The emulator initiates an Emulation Warm Reset via the ICEPICK module. To invoke the Emulation Warm
Reset via the ICEPICK module, the user can perform the following from the Code Composer Studio™ IDE
menu: Target -> Reset -> System Reset.

7.3.5 Watchdog Reset

A Watchdog Reset is initiated when the Watchdog Timer counter reaches zero and has the same effect
and requirements as an External Warm Reset (RESET pin), with the following exceptions:
• BTMODE[15:0] pins are not re-latched
• RSTOUT_WD_OUT is not 3-stated and is actively driven based on the value previously latched on the
BTMODE[11] pin.
In addition, a Watchdog Reset always results in RSTOUT_WD_OUT being asserted, regardless of
whether the BTMODE[11] pin was latched as "0" or "1".

7.3.6 Software Global Cold Reset

A Software Global Cold Reset is initiated under software control and has the same effect and
requirements as a POR Reset, with the following exceptions:
• BTMODE[15:0] pins are not re-latched and EMAC Switch (optional) is not reset
• RSTOUT_WD_OUT is not 3-stated and is actively driven based on the value previously latched on the
BTMODE[11] pin.

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Software initiates a Software Global Cold Reset by writing a "1" to the RST_GLOBAL_COLD_SW bit in
the PRM_RSTCTRL register in the PRCM.
For more detailed information on the PRM_RSTCTRL register, see the PRCM Registers section of the
Power, Reset, and Clock Management (PRCM) Module chapter of the TMS320DM814x DaVinci Digital
Media Processors Technical Reference Manual (Literature Number: SPRUGZ8).

7.3.7 Software Global Warm Reset

A Software Global Warm Reset is initiated under software control and has the same effect and
requirements as a External Warm Reset (RESET pin), with the following exceptions:
• BTMODE[15:0] pins are not re-latched
• RSTOUT_WD_OUT is not 3-stated and is actively driven based on the value previously latched on the
BTMODE[11] pin.
Software initiates a Software Global Warm Reset by writing a "1" to the RST_GLOBAL_WARM_SW bit in
the PRM_RSTCTRL register in the PRCM.
For more detailed information on the PRM_RSTCTRL register, see the PRCM Registers section of the
Power, Reset, and Clock Management (PRCM) Module chapter of the TMS320DM814x DaVinci Digital
Media Processors Technical Reference Manual (Literature Number: SPRUGZ8).

7.3.8 Test Reset (TRST pin)

A Test Reset is activated by the emulator asserting the TRST pin. The only effect a Test Reset has is to
reset the Test and Emulation Logic.

7.3.9 Local Reset

The Local Reset for various Modules within the device is controlled by programming the PRCM and/or the
Peripheral Module’s internal registers. Only the associated Module is reset when a Local Reset is
asserted, leaving the rest of the device unaffected.
For more details on Peripheral Local Resets, see the Reset Management section of the Power, Reset,
and Clock Management (PRCM) Module chapter of the TMS320DM814x DaVinci Digital Media
Processors Technical Reference Manual (Literature Number: SPRUGZ8).

7.3.10 Reset Priority

If any of the above reset sources occur simultaneously, the device only processes the highest-priority
reset request. The reset request priorities, from high-to-low, are as follows:
1. Power-on Reset (POR)
2. Test Reset (TRST)
3. External Warm Reset (RESET pin)
4. Emulation Warm Resets
5. Watchdog Reset
6. Software Global Cold/Warm Resets

7.3.11 Reset Status Register

The Reset Status Register (PRM_RSTST) contains information about the last reset that occurred in the
system. For more information on this register, see the Power, Reset, and Clock Management (PRCM)
Module chapter of the TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual
(Literature Number: SPRUGZ8).

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7.3.12 PCIE Reset Isolation

The device supports reset isolation for the PCI Express (PCIE) module. This means that the PCI Express
Subsystem can be reset without resetting the rest of the device.
When the devcie is a PCI Express Root Complex (RC), the PCIE Subsystem can be reset by software
through the PRCM. Software should ensure that there are no ongoing PCIE transactions before asserting
this reset by first taking the PCIE Subsystem into the IDLE state. After bringing the PCIE Subsystem out
of reset, bus enumeration should be performed again and should treat all Endpoints (EP) as if they had
just been connected.
When the device is a PCI Express Endpoint (EP), the PCIE Subsystem will generate an interrupt when an
in-band reset is received. Software should process this interrupt by putting the PCIE Subsystem in the
IDLE state and then asserting the PCIE local reset through the PRCM.
All device level resets mentioned in the previous sections, except Test Reset, will also reset the PCIE
Subsystem. Therefore, the PCIE peripheral should issue a Hot Reset to all downstream devices and re-
enumerate the bus upon coming out of reset.
For more detailed information on reset isolation procedures, see the PCIe Reset Isolation section of the
Power, Reset, and Clock Management (PRCM) Module chapter of the TMS320DM814x DaVinci Digital
Media Processors Technical Reference Manual (Literature Number: SPRUGZ8).

7.3.13 EMAC Switch Reset Isolation

The device supports reset isolation for the Ethernet Switch (EMAC Switch). This allows the device to
undergo all resets listed in Section 7.3.1, System-Level Reset Sources, with the exception of POR Reset,
without disrupting the Ethernet Switch or the traffic being routed through the switch during the reset
condition. The following reset types can optionally provide an EMAC Switch reset isolation by setting the
ISO_CONTROL bit in the RESET_ISO Control Module register to a "1":
• External Warm Reset
• Emulation Warm Reset
• Watchdog Reset
• Software Global Cold Reset
• Software Global Warm Reset
When one of above resets occurs and the Ethernet Switch (EMAC Switch) is programmed to be isolated:
• The switch function of the EMAC Switch and the PLL embedded in the SATA SERDES Module (which
provides the reference clocks to the EMAC Switch) will not be reset.
• Several Control Module registers are not reset. For more details, see the description of the
RESET_ISO register in the Control Module chapter of the TMS320DM814x DaVinci Digital Media
Processors Technical Reference Manual (Literature Number: SPRUGZ8).
• The pin multiplexing of some of the EMAC Switch pins is unaffected. For more details, see the
description of the RESET_ISO register in the Control Module chapter of the TMS320DM814x DaVinci
Digital Media Processors Technical Reference Manual (Literature Number: SPRUGZ8).
The EMAC Switch is always reset when:
• One of the above resets occurs and the Ethernet Switch is programmed to be “not isolated”
• A POR Reset occurs

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7.3.14 RSTOUT_WD_OUT Pin

The RSTOUT_WD_OUT pin reflects device reset status and is de-asserted (high) when the device is out
reset. This output will always be asserted when a Watchdog Timer reset (Watchdog Reset) occurs. In
addition, this output is always 3-stated and the internal pull resistor is disabled on this pin while POR
and/or RESET is asserted; therefore, an external pullup/pulldown can be used to set the state of this pin
(high/low) while POR and/or RESET is asserted. For more detailed information on external PUs/PDs, see
Section 4.5.1, Pullup/Pulldown Resistors.
If the BTMODE[11] pin is latched as a "0" at the rising edge of POR or RESET, then RSTOUT_WD_OUT
is also asserted when any of the below resets occur:
• Power-On Reset (asserted after the BTMODE[11] pin is latched)
• External Warm Reset (asserted after the BTMODE[11] pin is latched)
• Emulation Warm Reset
• Software Global Cold/Warm Reset
The RSTOUT_WD_OUT pin remains asserted until the PRCM releases the host ARM Cortex-A8
processor for reset.

7.3.15 Effect of Reset on Emulation and Trace

The device Emulation and Trace Logic will only be reset by the following sources:
• Power-On Reset
• Software Global Cold Reset
• Test Reset
Other than these three reset types, none of the other resets will affect the Emulation and Trace Logic.
However, the multiplexing of the EMU[4:2] pins is reset by all system reset types except Test Reset.

7.3.16 Reset During Power Domain Switching

Each Power Domain has a dedicated Warm Reset and Cold Reset. Warm Reset for a Power Domain is
asserted under either of the following two conditions:
1. An External Warm Reset, Emulation Warm Reset, or Software Global Warm Reset occurs
2. When that Power Domain switches from the "ON" state to the "OFF" state
Cold Reset for a Power Domain is asserted under either of the following two conditions:
1. Power-On Reset or Software Global Cold Reset occurs
2. When that Power Domain switches from the "OFF" state to the "ON" state

7.3.17 Pin Behaviors at Reset

When any reset, other than Test Reset, (all described in Section 7.3.1, System-Level Reset Sources) is
asserted, all device I/O pins are reset into a Hi-Z state except for:
• Emulation Pins. These pins are only put into a Hi-Z state when Test Reset (TRST) is asserted.
• EMAC Switch Pins. These pins are always put into a Hi-Z state during Power-On Reset. However,
some EMAC Switch pins will not be put into a Hi-Z state during the other reset modes when the
ISO_CONTROL bit in the RESET_ISO register of the Control Module is programmed as a "1". For
more details, see the description of the RESET_ISO register in the Control Module chapter of the
TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual (Literature Number:
SPRUGZ8).
• RSTOUT_WD_OUT Pin during any reset types except for POR and RESET. For more detailed
information on RSTOUT_WD_OUT pin behavior, see Section 7.3.14, RSTOUT_WD_OUT Pin.

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• DDR[0]/[1] Address/Control Pins (CLK, CLK, CKE, WE, CS[1]/[0], RAS, CAS, ODT[1]/[0], RST,
BA[2:0], A[14:0]). These pins are 3-stated during reset. However, these pins are then driven to the
same value as their internal pull resistor reset value when reset is released (For the direction of the
internal pull during reset, see the DDR[0]/[1] Terminal Functions tables in the Section 3.2.4,
DDR2/DDR3 Memory Controller of this document).
In addition, the PINCNTL registers, which control pin multiplexing, enabling the IPUs/IPDs, and enabling
the receiver, are reset to their default state. Again, enabling the EMAC Switch reset isolation prevents
some PINCNTL registers from being reset.
For details on EMAC Switch reset isolation, see the descriptions of the RESET_ISO register and the
PINCNTL registers in the Control Module chapter of the TMS320DM814x DaVinci Digital Media
Processors Technical Reference Manual (Literature Number: SPRUGZ8).
Internal pull-up/down (IPU/IPD) resistors are enabled during and immediately after reset as described in
Section 3.2, Terminal Functions of this document.

NOTE
Upon coming out of reset, the ARM Cortex-A8 starts executing code from the internal Boot
ROM. The Boot ROM code modifies the PINCNTLx registers to configure the associated
pins for the chosen primary and backup Bootmodes. For more details on the Boot ROM
effects on pin multiplexing, see the ROM Code Memory and Peripheral Booting and Control
Module chapters of the TMS320DM814x DaVinci Digital Media Processors Technical
Reference Manual (Literature Number: SPRUGZ8).

7.3.18 Reset Electrical Data/Timing

Table 7-9. Timing Requirements for Reset (see Figure 7-4 and Figure 7-5)
OPP100
NO. UNIT
MIN MAX
1 tw(RESET) Pulse duration, POR low or RESET low 12P (1) ns
(2)
Setup time, BTMODE[15:0] pins valid before POR high or POR 2P ns
2 tsu(BOOT)
RESET high RESET 2P (2) ns
3 th(BOOT) Hold time, BTMODE[15:0] pins valid after POR high or RESET high 0 ns
(1) The device clock source must be stable and at a valid frequency prior to meeting the tw(RESET) requirement.
(2) P = 1/(DEV Clock) frequency in ns.

Table 7-10. Switching Characteristics Over Recommended Operating Conditions During Reset
(see Figure 7-5)
OPP100
NO. PARAMETER UNIT
MIN MAX
td(RSTL-
4 Delay time, RESET low or POR low to all I/Os entering their reset state 14 ns
IORST)
td(RSTH-
5 Delay time, RESET high or POR high to all I/Os exiting their reset state 14 ns
IOFUNC)
RESET assertion tw(RESET)
0 2P ns
td(RSTH- (1) (2)
≥ 30P
6 Delay time, RESET high to RSTOUT_WD_OUT high
RSTOUTH) RESET assertion tw(RESET) 32P -
0 ns
< 30P tw(RESET)
td(PORH-
7 Delay time, POR high to RSTOUT_WD_OUT high (1) (2) 0 12500P ns
RSTOUTH)
td(RSTL-
8 Delay time, RESET low to RSTOUT_WD_OUT Hi-Z (1) (2) 0 2P ns
RSTOUTZ)

(1) For more detailed information on RSTOUT_WD_OUT pin behavior, see Section 7.3.14, RSTOUT_WD_OUT Pin.
(2) P = 1/(DEV Clock) frequency in ns.
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Table 7-10. Switching Characteristics Over Recommended Operating Conditions During Reset
(see Figure 7-5) (continued)
OPP100
NO. PARAMETER UNIT
MIN MAX
td(PORH- Delay time, POR high to RSTOUT_WD_OUT driven based on latched BTMODE[11]
9 0 2P ns
RSTOUTL) value (1) (2)
td(RSTH- Delay time, RESET high to RSTOUT_WD_OUT driven based on latched BTMODE[11]
10 0 2P ns
RSTOUTD) value (1) (2)

Figure 7-4 shows the Power-Up Timing. Figure 7-5 shows the Warm Reset (RESET) Timing. Max Reset
Timing is identical to Warm Reset Timing, except the BTMODE[15:0] pins are not re-latched.

Power
Supplies Power Supplies Stable
Ramping
Clock Source Stable
DEV_CLKIN/
(A)
AUX_CLKIN
1

POR

RESET
7
9
Hi-Z (B)
RSTOUT_WD_OUT BTMODE[11]

5
2 3
Hi-Z
BTMODE[15:0] Config

(C)
Other I/O Pins RESET STATE

A. Power supplies and DEV_CLKIN/AUX_CLKIN must be stable before the start of tw(RESET).
B. RSTOUT_WD_OUT only asserted if BTMODE[11] was latched as a "0" when coming out of reset.
C. For more detailed information on the RESET STATE of each pin, see Section 7.3.17, Pin Behaviors at Reset. Also
see Section 3.2, Terminal Functions for the IPU/IPD settings during reset.

Figure 7-4. Power-Up Timing

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Power Supplies Stable

DEV_CLKIN/
AUX_CLKIN

POR
1

RESET

8 6
10
Hi-Z (A)
RSTOUT_WD_OUT BTMODE[11]

4 5
2 3
Hi-Z
BTMODE[15:0] Config
4 5

(B)
Other I/O Pins RESET STATE

A. RSTOUT_WD_OUT only asserted if BTMODE[11] was latched as a "0" when coming out of reset.
B. For more detailed information on the RESET STATE of each pin, see Section 7.3.17, Pin Behaviors at Reset. Also
see Section 3.2, Terminal Functions for the IPU/IPD settings during reset.

Figure 7-5. Warm Reset (RESET) Timing

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7.4 Clocking
The device clocks are generated from several reference clocks that are fed to on-chip PLLs and dividers
(both inside and outside of the PRCM Module). Figure 7-6 shows a high-level overview of the device
system clocking structure (Note: to reduce complexity, not all clocking connections are shown). For
detailed information on the device clocks, see the Clock Generation and Management section of the
Power, Reset, and Clock Management (PRCM) Module chapter of the TMS320DM814x DaVinci Digital
Media Processors Technical Reference Manual (Literature Number: SPRUGZ8).

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PLL_DSP DSP

PLL_HDVPSS HDVPSS

PLL_MEDIACTL ISS, Media Controller

SYSCLK3
PLL_HDVICP PRCM HDVICP2

SYSCLK4 L3 Fast/Medium, L4 Fast,

EDMA, OCMC, MMU
PLL_L3 PRCM
L3/L4 Slow, GPMC, ELM,
SYSCLK6 McASP, McBSP,
UART3/4/5 (opt),
Mailbox, Spinlock

SYSCLK23
PLL_SGX PRCM SGX530

CLKDCO USB0/1

PLL_USB
DEVOSC/ SYSCLK10 SPI0/1/2/3, I2C0/1/2/3,
DEV_CLKIN M UART0/1/2, HDMI CEC
U CLKOUT PRCM
SYSCLK8
AUXOSC/ X MMC0/1/2
AUX_CLKIN
(Note: Separate MUX M
exists for each PLL) U UART3/4/5
From SYSCLK6 X
PLL_DDR DDR0/1
/2 DMM

PLL_VIDEO0 HDVPSS SD VENC

HDMI

PLL_VIDEO2 HDVPSS VOUT1

M
U
HDMI PHY X

M
U HDVPSS VOUT0
PLL_VIDEO1 X

PLL_AUDIO SYSCLK20
PRCM M
U MCASP0/1/2 AUX_CLK
SYSCLK21 X
From PLL_VIDEO0/1/2 PRCM
M MCBSP CLKS,
U
X HDMI I2S
From AUX Clock, AUD_CLK0/1/2

From PLL_AUDIO, PLL_VIDEO0/1/2, AUX Clock, AUD_CLK0/1/2 MCASP3/4/5 AUX_CLK

PLL_ARM
(Embedded PLL) M
U Cortex-A8
X
RTCDIVIDER SYSCLK18 RTC, GPIO, SyncTimer,
PRCM Cortex-A8 (Optional)
From CLKIN32 Pin
M
U TIMER1/2/3/4/5/6/7/8
From DEV/AUX Clock, AUD_CLK0/1/2, TCLKIN X
WDT0 (Optional)
DCAN0/1
M
U SATA SERDES
X (Embedded PLL)
SERDES_CLK

EMAC Switch

PCIE SERDES
(Embedded PLL)

RCOSC32K WDT0 (Optional)

Figure 7-6. System Clocking Overview

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7.4.1 Device (DEV) and Auxiliary (AUX) Clock Inputs

The device provides two clock inputs, Device (DEVOSC_MXI/DEV_CLKIN) and Auxiliary
(AUXOSC_MXI/AUX_CLKIN). The Device (DEV) clock is used to generate the majority of the internal
reference clocks, while the Auxiliary (AUX) clock can optionally be used as a source for the Audio and/or
Video PLLs.
The DEV and AUX clocks can be sourced in two ways:
1. Using an external crystal in conjunction with the internal oscillator or
2. Using an external 1.8-V LVCMOS-compatible clock input
Note: The external crystals used with the internal oscillators must operate in fundamental parallel
resonant mode only. There is no overtone support.
The DEV Clock should in most cases be 20 MHz. However, it can optionally range anywhere from 20 - 30
MHz if the following are true:
• The DEV Clock is not used to source the SATA reference clock
• A precise 32768-Hz clock is not needed for Real-Time Clock functionality
• If the boot mode is FAST XIP
The AUX Clock is optional and can range from 20-30 MHz. AUX Clock can be used to source the Audio
and/or Video PLLs when a very precise audio or video frequency is required.

7.4.1.1 Using the Internal Oscillators

When the internal oscillators are used to generate the DEV and AUX clocks, external crystals are required
to be connected across the DEVOSC or AUXOSC oscillator MXI and MXO pins, along with two load
capacitors (see Figure 7-7 and Figure 7-8). The external crystal load capacitors should also be connected
to the associated oscillator ground pin (VSSA_DEVOSC or VSSA_AUXOSC). The capacitors should not
be connected to board ground (VSS).

Figure 7-7. Device Oscillator

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AUXOSC_MXI/
AUX_CLKIN AUXOSC_MXO VSSA_AUXOSC

Crystal Rd
(Optional)

C1 C2

Figure 7-8. Auxiliary Oscillator

The load capacitors, C1 and C2 in the above pictures, should be chosen such that the below equation is
satisfied. CL in the equation is the load specified by the crystal manufacturer. All discrete components
used to implement the oscillator circuit should be placed as close as possible to the associated oscillator
MXI, MXO, and VSS pins.
C1 C2
CL =
(C1 + C2 )

Table 7-11. Input Requirements for Crystal Circuit on the Device Oscillator (DEVOSC)
PARAMETER MIN TYP MAX UNIT
Start-up time (from power up until oscillating at stable frequency) 4 ms
(1)
Crystal Oscillation frequency 20 20 30 MHz
Parallel Load Capacitance (C1 and C2) 12 24 pF
Crystal ESR 50 Ω
Crystal Shunt Capacitance 5 pF
Crystal Oscillation Mode Fundamental Only n/a
If Ethernet not used ±200
If MII is used and
Crystal Frequency Stability ±100 ppm
RGMII, RMII not used
If RGMII, or RMII used ±50
(1) 20-MHz DEV clock is required for all bootmodes other than Fast XIP. For more detailed information on boot modes, see the ROM Code
Memory and Peripheral Booting chapter of the TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual
(Literature Number: SPRUGZ8).

Table 7-12. Input Requirements for Crystal Circuit on the Auxiliary Oscillator (AUXOSC)
PARAMETER MIN MAX UNIT
Start-up time (from power up until oscillating at stable frequency) 4 ms
Crystal Oscillation frequency 20 30 MHz
Parallel Load Capacitance (C1 and C2) 12 24 pF
Crystal ESR 50 Ω
Crystal Shunt Capacitance 5 pF
Crystal Oscillation Mode Fundamental Only n/a
Crystal Frequency stability (1) ±50 ppm
(1) Applies only when sourcing the HDMI or HDVPSS DAC clocks from the AUXOSC

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7.4.1.2 Using a 1.8V LVCMOS-Compatible Clock Input

A 1.8-V LVCMOS-Compatible Clock Input can be used instead of the internal oscillators as the DEV and
AUX clock inputs to the system. The external connections to support this are shown in Figure 7-9 and
Figure 7-10. The DEV_CLKIN and AUX_CLKIN pins are connected to the 1.8-V LVCMOS-Compatible
clock sources. The DEV_MXO and AUX_MXO pins are left unconnected. The VSSA_DEVOSC and
VSSA_AUXOSC pins are connected to board ground (VSS).

DEVOSC_MXI/
DEV_CLKIN DEVOSC_MXO VSSA_DEVOSC

NC

Figure 7-9. 1.8-V LVCMOS-Compatible Clock Input (DEV_OSC)

AUXOSC_MXI/
AUX_CLKIN AUXOSC_MXO VSSA_AUXOSC

NC

Figure 7-10. 1.8-V LVCMOS-Compatible Clock Input (AUX_OSC)

The clock source must meet the DEVOSC_MXI/DEV_CLKIN timing requirements shown in Table 7-15,
Timing Requirements for DEVOSC_MXI/DEV_CLKIN.

The clock source must meet the AUXOSC_MXI/AUX_CLKIN timing requirements shown in Table 7-16,
Timing Requirements for AUXOSC_MXI/AUX_CLKIN.

7.4.2 SERDES_CLKN/P Input Clock

A high-quality, low-jitter differential clock source is required for the PCIE PHY and is an optional clock
source for the SATA PHY. The clock is required to be AC coupled to the SERDES_CLKP and
SERDES_CLKN device pins according to the specifications in Table 7-13. Both the clock source and the
coupling capacitors should be placed physically as close to the processor as possible. In addition, make
sure to follow any PCB routing and termination recommendations that the clock source manufacturer
recommends.

Table 7-13. SERDES_CLKN/P AC Coupling Capacitors Recommendations

PARAMETER MIN TYP MAX UNIT
SERDES_CLKN/P AC coupling capacitor value 0.24 0.27 1.0 nF

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Table 7-13. SERDES_CLKN/P AC Coupling Capacitors Recommendations (continued)

PARAMETER MIN TYP MAX UNIT
SERDES_CLKN/P AC coupling capacitor package size (1) (2) 0402 0603 EIA
(1) L x W, 10 Mil units, that is, a 0402 is a 40 x 20 Mil surface mount capacitor.
(2) The physical size of the capacitor should be as small as practical. Use the same size on both lines in each pair placed side-by-side.

The differential clock source is required to meet the REFCLK AC Specifications outlined in the PCI
EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 2.0, at the input to the AC coupling
capacitors.
In addition, LVDS clock sources that are compliant to the above specification, but with the following
exceptions, are also acceptable:

Table 7-14. Acceptable Exceptions to the REFCLK AC Specifications for LVDS Clock Sources
PARAMETER MIN MAX UNIT
VIH Differential High-Level Input Voltage 125 1000 mV
VIL Differential Low-Level Input Voltage -1000 -125 mV

7.4.3 AUD_CLKINx Input Clocks

External clock inputs can optionally be provided at the AUD_CLKIN0/1/2 pins to serve as a reference
clocks for the following modules:
• McASP3/4/5
• McBSP
• TIMER1/2/3/4/5/6/7/8

7.4.4 CLKIN32 Input Clock

An external 32768-Hz clock input can optionally be provided at the CLKIN32 pin to serve as a reference
clock in place of the RTCDIVIDER clock for the following Modules:
• RTC
• GPIO0/1/2/3
• TIMER1/2/3/4/5/6/7/8
• ARM Cortex-A8
• SYNCTIMER
The CLKIN32 source must meet the timing requirements shown in Table 7-18.

7.4.5 External Input Clocks

There are three pins referred to as AUD_CLKIN0,1,2 which are used as optional sources for HDMI I2S,
McASP, McBSP and TIMER1-8. The maximum IO pin frequency for these three input clocks is 50MHz.

7.4.6 Output Clocks Select Logic

The device includes two selectable general-purpose clock outputs (CLKOUT0 and CLKOUT1). The source
for these output clocks is controlled by the CLKOUT_MUX register in the Control Module (see Figure 7-
11).

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CLKOUT_MUX

RESERVED
1011-1111

RCOSC32K Output
1010
PLL_SGX Output
1001
DEV_OSC Clock Input
1000
AUX Clock CLKOUT0
0111
DEV Clock
0110 CLKOUT1
PLL_L3 Output
0101
PLL_MEDIACTL Output / 2
0100
PLL_DSS Output / 2
0011
PCIE SERDES Observation Clock
0010
SATA SERDES Observation Clock
0001
PRCM SYSCLK Output (A)
0000

A. Muxed output of DEVOSC clock, USBPLL clock output, VIDEO0 PLL Clock output, and RTC DIVIDER output.

Figure 7-11. CLKOUTx Source Selection Logic

For detailed information on the CLKOUTx switching characteristics, see Table 7-19.

7.4.7 Input/Output Clocks Electrical Data/Timing

Note: If an external clock oscillator is used, a single clean power supply should be used to power both the
device and the external clock oscillator circuit.

Table 7-15. Timing Requirements for DEVOSC_MXI/DEV_CLKIN (1) (2) (3)

(see Figure 7-12)
NO OPP100
UNIT
. MIN NOM MAX
1 tc(DMXI) Cycle time, DEVOSC_MXI/DEV_CLKIN 33.33 50 50 ns
2 tw(DMXIH) Pulse duration, DEVOSC_MXI/DEV_CLKIN high 0.45C 0.55C ns
3 tw(DMXIL) Pulse duration, DEVOSC_MXI/DEV_CLKIN low 0.45C 0.55C ns
4 tt(DMXI) Transition time, DEVOSC_MXI/DEV_CLKIN 7 ns
5 tJ(DMXI) Period jitter, DEVOSC_MXI/DEV_CLKIN 0.02C ns
If Ethernet not used ±200
Frequency Stability If MII is used and RGMII, RMII not used ±100 ppm
If RGMII, or RMII used ±50
(1) The DEVOSC_MXI/DEV_CLKIN frequency and PLL settings should be chosen such that the resulting SYSCLKs and Module Clocks are
within the specific ranges shown in the Section 7.4.9, SYSCLKs and Section 7.4.10, Module Clocks.
(2) The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
(3) C = DEV_CLKIN cycle time in ns. For example, when DEVOSC_MXI/DEV_CLKIN frequency is 20 MHz, use C = 50 ns.

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5 1
4
1 2

DEVOSC_MXI/
DEV_CLKIN

3
4

Figure 7-12. DEV_MXI/DEV_CLKIN Timing

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(1) (2)
Table 7-16. Timing Requirements for AUX_MXI/AUX_CLKIN (see Figure 7-13)
OPP100
NO. UNIT
MIN NOM MAX
1 tc(AMXI) Cycle time, AUXOSC_MXI/AUX_CLKIN 33.3 50 50 ns
2 tw(AMXIH) Pulse duration, AUXOSC_MXI/AUX_CLKIN high 0.45C 0.55C ns
3 tw(AMXIL) Pulse duration, AUXOSC_MXI/AUX_CLKIN low 0.45C 0.55C ns
4 tt(AMXI) Transition time, AUXOSC_MXI/AUX_CLKIN 7 ns
5 tJ(AMXI) Period jitter, AUXOSC_MXI/AUX_CLKIN 0.02C ns
6 Sf Frequency stability, AUXOSC_MXI/AUX_CLKIN (3) ± 50 ppm
(1) The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
(2) C = AUX_CLKIN cycle time in ns. For example, when AUXOSC_MXI/AUX_CLKIN frequency is 20 MHz, use C = 50 ns.
(3) Applies only when sourcing the HDMI or HDVPSS DAC clocks from the AUXOSC.

5 1
4
1 2

AUXOSC_MXI/
AUX_CLKIN

3
4

Figure 7-13. AUX_MXI/AUX_CLKIN Timing

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(1)
Table 7-17. Timing Requirements for AUD_CLKINx (see Figure 7-14)
OPP100/120/166
NO. UNIT
MIN NOM MAX
1 tc(AUD_CLKINx) Cycle time, AUD_CLKINx 20 ns
0.55
2 tw(AUD_CLKINxH) Cycle time, AUD_CLKINx 0.45A ns
A
0.55
3 tw(AUD_CLKINxL) Cycle time, AUD_CLKINx 0.45A ns
A
(1) A = AUD_CLKINx cycle time in ns.

AUD_CLKINx

Figure 7-14. AUD_CLKINx Timing

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(1) (2)
Table 7-18. Timing Requirements for CLKIN32 (see Figure 7-15)
OPP100
NO. UNIT
MIN NOM MAX
1 tc(CLKIN32) Cycle time, CLKIN32 1/32768 s
2 tw(CLKIN32H) Pulse duration, CLKIN32 high 0.45C 0.55C ns
3 tw(CKIN32L) Pulse duration, CLKIN32 low 0.45C 0.55C ns
4 tt(CLKIN32) Transition time, CLKIN32 7 ns
5 tJ(CLKIN32) Period jitter, CLKIN32 0.02C ns
(1) The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
(2) C = CLKIN32 cycle time in ns. For example, when CLKIN32 frequency is 32768 Hz, use C = 1/32768 s.

5 1
4
1 2

CLKIN32

3
4

Figure 7-15. CLKIN32 Timing

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Table 7-19. Switching Characteristics Over Recommended Operating Conditions for CLKOUTx (CLKOUT0
and CLKOUT1) (1) (2)
(see Figure 7-16)
OPP100
NO. PARAMETER UNIT
MIN MAX
1 tc(CLKOUTx) Cycle time, CLKOUTx 5 ns
2 tw(CLKOUTxH) Pulse duration, CLKOUTx high 0.45P 0.55P ns
3 tw(CLKOUTxL) Pulse duration, CLKOUTx low 0.45P 0.55P ns
4 tt(CLKOUTx) Transition time, CLKOUTx 0.05P ns
(1) The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
(2) P = 1/CLKOUTx clock frequency in nanoseconds (ns). For example, when CLKOUTx frequency is 200 MHz, use P = 5 ns.

2
1 4

CLKOUTx
(Divide-by-1)

Figure 7-16. CLKOUTx Timing

7.4.8 PLLs
The device contains 12 top-level PLLs, and 4 embedded PLLs (within the ARM Cortex-A8, PCIE, SATA,
and CSI) that provide clocks to different parts of the system. Figure 7-17 and Figure 7-18 show simplified
block diagrams of the Top-Level PLL and PLL_ARM. In addition, see the System Clocking Overview
(Figure 7-6) for a high-level view of the device clock architecture including the PLL reference clock
sources and connections.

DEV/AUX
Clock 1 REFCLK xM CLKDCO 1
(N + 1) Multiplier M2
CLKOUT

1
(N 2 + 1)

Figure 7-17. Top-Level PLL Simplified Block Diagram

DEV Clock 1 REFCLK x2M DCOCLK 1 1

(N + 1) Multiplier M2 2
CLKOUT

1
(N 2 + 1)

Figure 7-18. PLL_ARM Simplified Block Diagram

The reference clock for most of the PLLs comes from the DEV input clock, with select PLLs also having
the option to use the AUX input clock as a reference. Also, each PLL supports a Bypass mode in which
the reference clock can be directly passed to the PLL CLKOUT through a divider. All device PLL’s will
come-up in Bypass mode after reset.
For details on programming the device PLLs, see the Control Module chapter of the TMS320DM814x
DaVinci Digital Media Processors Technical Reference Manual (Literature Number: SPRUGZ8).

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7.4.8.1 PLL Power Supply Filtering

The device PLLs are supplied externally via the VDDA_xPLL_1P8 power-supply pins (where "x"
represents ARM, DSP, VID0, VID1, AUDIO, DDR, and/or L3). External filtering must be added on the PLL
supply pins to ensure that the requirements in Table 7-20 are met.

Table 7-20. PLL Power Supply Requirements

PARAMETER MIN MAX UNIT
Dynamic noise at VDDA_xPLL_1P8 pins 50 mV p-p

7.4.8.2 PLL Multipliers and Dividers

The Top-Level and PLL_ARM PLLs support the internal multiplier and divider values shown in Table 7-21,
Top-Level PLL Multiplier and Divider Limits and Table 7-22, PLL_ARM Multiplier and Divider Limits. The
PLLs must be programmed to conform to the various REFCLK, CLKDCO, DCOCLK, and CLKOUT limits
described in Section 7.4.8.3, PLL Frequency Limits.

Table 7-21. Top-Level PLL Multiplier and Divider Limits

PARAMETER MIN MAX
N Pre-Divider 0 255
PLL Multiplier (M) 2 4095 (1)
M2 Post Divider 1 127
N2 Bypass Divider 0 15
(1) The PLL Multiplier supports fractional values (up to 18-bits of fraction) except when the PLL Multiplier is > 4093.

Table 7-22. PLL_ARM Multiplier and Divider Limits

PARAMETER MIN MAX
N Pre-Divider 0 127
PLL Multiplier (M) (1) 2 2047 (2)
M2 Post Divider 1 31
N2 Bypass Divider 0 15
(1) This parameter describes the limits on the programmable multiplier value M. The multiplication factor for the PLL_ARM is equal to 2 * M
(also see Figure 7-18).
(2) The PLL Multiplier supports fractional values (up to 18-bits of fraction) except when the PLL Multiplier is < 20 OR > 2045.

7.4.8.3 PLL Frequency Limits

Each PLL supports a minimum and maximum operating frequency for its REFCLK, CKLDCO, and
CLKOUT values. The PLLs must be configured not to exceed any of the constraints placed on these
values shown in Table 7-23 through Table 7-25. Care must be taken to stay within these limits when
selecting external clock input frequencies, internal divider values, and PLL multiply ratios. In addition,
limits shown in these tables may be further restricted by the clock frequency limitations of the device
modules using these clocks. For more detailed information on the SYSCLK and Module Clock frequency
limits, see Section 7.4.9, SYSCLKs and Section 7.4.10, Module Clocks.

Table 7-23. Top-Level PLL Frequency Ranges (ALL OPPs)

CLOCK MIN MAX UNIT
REFCLK 0.5 2.5 MHz
(1)
CLKDCO (HS1) 1000 2000 MHz
CLKDCO (HS2) (2) 500 1000 MHz

(1) The PLL has two modes of operation: HS1 and HS2. The mode of operation should be set, according to the desired CLKDCO
frequency, by programming the SELFREQDCO field of the ADPLLLJx_CLKCTRL registers in the Control Module.
(2) CLKDCO of the PLL_USB is used undivided by the USB modules; therefore, CLKDCO for the PLL_USB PLL must be programmed to
960 MHz for proper operation.
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Table 7-23. Top-Level PLL Frequency Ranges (ALL OPPs) (continued)

CLOCK MIN MAX UNIT
CLKOUT see Table 7-25 see Table 7-25 MHz

Table 7-24. ARM Cortex-A8 Embedded PLL (PLL_ARM) Frequency Ranges (ALL OPPs)
CLOCK MIN MAX UNIT
REFCLK 0.032 52 MHz
DCOCLK 20 2000 MHz
CLKOUT see Table 7-25 see Table 7-25 MHz

Table 7-25. PLL CLKOUT Frequency Ranges

OPP100
PLL UNIT
MIN MAX
PLL_ARM 10 600 MHz
PLL_DSP 10 500 MHz
PLL_SGX 10 200 MHz
PLL_HDVICP 10 266 MHz
PLL_L3 10 200 MHz
PLL_DDR 10 400 MHz
PLL_HDVPSS 10 200 MHz
PLL_AUDIO 10 200 MHz
PLL_MEDIACTL 10 400 MHz
PLL_USB 10 (1) 960 MHz
PLL_VIDEO0 10 200 MHz
PLL_VIDEO1 10 200 MHz
PLL_VIDEO2 10 200 MHz
(1) When the USB is used, PLL_USB must be fixed at 960 MHz.

7.4.8.4 PLL Register Descriptions

The PLL Control Registers reside in the Control Module and are listed in Section 4.1, Control Module of
this datasheet.

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7.4.9 SYSCLKs
In some cases, the system clock inputs and PLL outputs are sent to the PRCM Module for division and
multiplexing before being routed to the various device Modules. These clock outputs from the PRCM
Module are called SYSCLKs. Table Table 7-26 lists the device SYSCLKs along with their maximum
supported clock frequencies. In addition, limits shown in these tables may be further restricted by the clock
frequency limitations of the device modules using these clocks. For more details on Module Clock
frequency limits, see Section 7.4.10 Module Clocks.

Table 7-26. Maximum SYSCLK Clock Frequencies (1)

MAX CLOCK FREQUENCY
SYSCLK
OPP100 (MHz)
SYSCLK1 RSV
SYSCLK2 RSV
SYSCLK3 266
SYSCLK4 200
SYSCLK5 RSV
SYSCLK6 100
SYSCLK7 RSV
SYSCLK8 192
SYSCLK9 RSV
SYSCLK10 48
SYSCLK11 RSV
SYSCLK12 RSV
SYSCLK13 RSV
SYSCLK14 27
SYSCLK15 RSV
SYSCLK16 27
SYSCLK17 RSV
SYSCLK18 0.032768
SYSCLK19 192
SYSCLK20 192
SYSCLK21 192
SYSCLK22 RSV
SYSCLK23 200
(1) The maximum frequencies listed in this table are valid for OPP100. Some of these frequencies have
higher maximum values when OPP120 or OPP166 is used, see Table 7-4

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7.4.10 Module Clocks

Device Modules either receive their clock directly from an external clock input, directly from a PLL, or from
a PRCM SYSCLK output. Table 7-27 lists the clock source options for each Module on this device, along
with the maximum frequency that Module can accept. To ensure proper Module functionality, the device
PLLs and dividers must be programmed not to exceed the maximum frequencies listed in this table.

Table 7-27. Maximum Module Clock Frequencies (1)

MAX FREQUENCY
MODULE CLOCK SOURCES
OPP100 (MHz)
PLL_ARM
Cortex-A8 600
SYSCLK18
DCAN0/1 DEV Clock 30
DDR0/1 PLL_DDR 400
DMM PLL_DDR/2 200
DSP PLL_DSP 500
System MMU SYSCLK4 200
EDMA SYSCLK4 200
EMAC Switch (GMII) SATA SERDES Fixed 125
PLL_VIDEO0
PLL_VIDEO1
EMAC Switch (RGMII) Fixed 250
PLL_VIDEO02
PLL_L3
SATA SERDES
EMAC Switch (RMII and MII) Fixed 50
EMAC_RMREFCLK Pin
GPIO SYSCLK6 100
GPIO Debounce SYSCLK18 Fixed 0.032768
GPMC SYSCLK6 100
HDMI PLL_VIDEO2 186
HDMI CEC SYSCLK10 Fixed 48
SYSCLK20
SYSCLK21
HDMI I2S 50
AUD_CLK0/1/2
AUX Clock
HDVICP2 SYSCLK3 266
HDVPSS PLL_HDVPSS 200
PLL_VIDEO2
HDVPSS VOUT1 186
HDMI PHY
PLL_VIDEO1
HDVPSS VOUT0 165
PLL_VIDEO2
HDVPSS SD VENC PLL_VIDEO0 Fixed 54
I2C0/1/2/3 SYSCLK10 48
ISS PLL_ MEDIACTL 400
L3 Fast SYSCLK4 200
L3 Medium SYSCLK4 200
L3 Slow SYSCLK6 100
L4 Fast SYSCLK4 200
L4 Slow SYSCLK6 100
Mailbox SYSCLK6 100
McASP SYSCLK6 100
SYSCLK20
McASP0/1/2 AUX_CLK 192
SYSCLK21

(1) The maximum frequencies listed in this table are valid for OPP100. Some of these frequencies have higher maximum values when
OPP120 or OPP166 is used, see Table 7-4
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Table 7-27. Maximum Module Clock Frequencies(1) (continued)

MAX FREQUENCY
MODULE CLOCK SOURCES
OPP100 (MHz)
PLL_AUDIO
PLL_VIDEO0/1/2
McASP3/4/5 AUX_CLK 192
AUD_CLK0/1/2
AUX Clock
SYSCLK20
SYSCLK21
McBSP CLKS 192
AUD_CLK0/1/2
AUX Clock
Media Controller PLL_MEDIACTL/2 200
MMCSD0/1/2 SYSCLK8 192
OCMC RAM SYSCLK4 200
PCIe SERDES SERDES_CLKx Pins 100
DEV Clock
SATA SERDES 20 or 100
SERDES_CLKx Pins
SGX530 SYSCLK23 200
SPI0/1/2/3 SYSCLK10 48
Spinlock SYSCLK6 100
Sync Timer SYSCLK18 Fixed 0.032768
SYSCLK18
DEV Clock
TIMER1/2/3/4/5/6/7/8 AUX Clock 30
AUD_CLK0/1/2
TCLKIN
UART0/1/2 SYSCLK10 48
SYSCLK6
UART3/4/5 SYSCLK8 192
SYSCLK10
USB PLL_USB CLKDCO Fixed 960
RTCDIVIDER
WDT0 Fixed 0.032768
RCOSC32K

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7.5 Interrupts
The device has a large number of interrupts to service the needs of its many peripherals and subsystems.
The ARM Cortex-A8, C674x DSP, and Media Controller are capable of servicing these interrupts.
However, the C674x DSP require additional system-level interrupt multiplexors to receive their interrupts.
The following sections list the device interrupt mapping and multiplexing schemes.

7.5.1 ARM Cortex-A8 Interrupts

The ARM Cortex-A8 Interrupt Controller (AINTC) is responsible for prioritizing all service requests from the
System peripherals and generating either IRQs or FIQs to the Cortex-A8. The AINTC has the capability to
handle up to 128 requests, and the priority of the interrupt inputs are programmable. Table 7-28 lists the
interrupt sources for the AINTC.
Note: For General-Purpose devices, the AINTC does not support the generation of FIQs to the ARM
processor.
For more details on ARM Cortex-A8 interrupt control, see the ARM Interrupt Controller (AINTC) chapter of
the TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual (Literature Number:
SPRUGZ8).

Table 7-28. ARM Cortex-A8 Interrupt Controller (AINTC) Interrupt Sources

Cortex-A8
ACRONYM SOURCE
INTERRUPT NUMBER
0 EMUINT Cortex-A8 Emulation
1 COMMTX Cortex-A8 Emulation
2 COMMRX Cortex-A8 Emulation
3 BENCH Cortex-A8 Emulation
4 ELM_IRQ ELM
5 – Reserved
6 – Reserved
7 NMI NMIn Pin
8 – Reserved
9 L3DEBUG L3 Interconnect
10 L3APPINT L3 Interconnect
11 TINT8 TIMER8
12 EDMACOMPINT EDMA CC Completion
13 EDMAMPERR EDMA Memory Protection Error
14 EDMAERRINT EDMA CC Error
15 WDTINT0 Watchdog Timer 0
16 SATAINT SATA
17 USBSSINT USB Subsystem
18 USBINT0 USB0
19 USBINT1 USB1
20-27 – Reserved
28 SDINT1 MMC/SD1
29 SDINT2 MMC/SD2
30 I2CINT2 I2C2
31 I2CINT3 I2C3
32 GPIOINT2A GPIO2 A
33 GPIOINT2B GPIO2 B
34 USBWAKEUP USB Subsystem Wakeup
35 PCIeWAKEUP PCIe Wakeup

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Table 7-28. ARM Cortex-A8 Interrupt Controller (AINTC) Interrupt Sources (continued)
Cortex-A8
ACRONYM SOURCE
INTERRUPT NUMBER
36 DSSINT HDVPSS
37 GFXINT SGX530
38 HDMIINT HDMI
39 ISS_IRQ_5 ISS
40 3PGSWRXTHR0 EMAC Switch RX Threshold
41 3PGSWRXINT0 EMAC Switch Receive
42 3PGSWTXINT0 EMAC Switch Transmit
43 3PGSWMISC0 EMAC Switch Miscellaneous
44 UARTINT3 UART3
45 UARTINT4 UART4
46 UARTINT5 UART5
47 - Reserved
48 PCIINT0 PCIe
49 PCIINT1 PCIe
50 PCIINT2 PCIe
51 PCIINT3 PCIe
52 DCAN0_INT0 DCAN0
53 DCAN0_INT1 DCAN0
54 DCAN0_PARITY DCAN0 Parity
55 DCAN1_INT0 DCAN1
56 DCAN1_INT1 DCAN1
57 DCAN1_PARITY DCAN1 Parity
58-61 – Reserved
62 GPIOINT3A GPIO3
63 GPIOINT3B GPIO3
64 SDINT0 MMC/SD0
65 SPIINT0 SPI0
66 - Reserved
67 TINT1 TIMER1
68 TINT2 TIMER2
69 TINT3 TIMER3
70 I2CINT0 I2C0
71 I2CINT1 I2C1
72 UARTINT0 UART0
73 UARTINT1 UART1
74 UARTINT2 UART2
75 RTCINT RTC
76 RTCALARMINT RTC Alarm
77 MBINT Mailbox
78 – Reserved
79 PLLINT PLL Recalculation Interrupt
80 MCATXINT0 McASP0 Transmit
81 MCARXINT0 McASP0 Receive
82 MCATXINT1 McASP1 Transmit
83 MCARXINT1 McASP1 Receive
84 MCATXINT2 McASP2 Transmit
85 MCARXINT2 McASP2 Receive

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Table 7-28. ARM Cortex-A8 Interrupt Controller (AINTC) Interrupt Sources (continued)
Cortex-A8
ACRONYM SOURCE
INTERRUPT NUMBER
86 MCBSPINT McBSP
87 – Reserved
88 – Reserved
91 – Reserved
92 TINT4 TIMER4
93 TINT5 TIMER5
94 TINT6 TIMER6
95 TINT7 TIMER7
96 GPIOINT0A GPIO0
97 GPIOINT0B GPIO0
98 GPIOINT1A GPIO1
99 GPIOINT1B GPIO1
100 GPMCINT GPMC
101 DDRERR0 DDR0
102 DDRERR1 DDR1
103 HDVICPCONT1SYNC HDVICP2
104 HDVICPCONT2SYNC HDVICP2
105 MCATXINT3 McASP3 Transmit
106 MCARXINT3 McASP3 Receive
107 IVA0MBOXINT HDVICP2 Mailbox
108 MCATXINT4 McASP4 Transmit
109 MCARXINT4 McASP4 Receive
110 MCATXINT5 McASP5 Transmit
111 MCARXINT5 McASP5 Receive
112 TCERRINT0 EDMA TC 0 Error
113 TCERRINT1 EDMA TC 1 Error
114 TCERRINT2 EDMA TC 2 Error
115 TCERRINT3 EDMA TC 3 Error
116-119 – Reserved
122 MMUINT System MMU
123 MCMMUINT Media Controller
124 DMMINT DMM
125 SPIINT1 SPI1
126 SPIINT2 SPI2
127 SPIINT3 SPI3

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7.5.2 C674x DSP Interrupts

The C674x DSP interrupt controller combines up to 128 device events into 12 prioritized interrupts
presented to the CPU. The default sources of the 128 device events are shown in Table 7-29. In addition,
device events 15 through 95 can alternatively be sourced from one of the 24 Multiplexed device events
shown in Table 7-30. The DSP_INTMUX_x registers in the Control Module are used to select between the
default event and the multiplexed event. The interrupt controller also controls the generation of the CPU
exceptions, NMI, and emulation interrupts.

Table 7-29. Default C674x Event Sources

C674x DEFAULT
ACRONYM SOURCE
EVENT NUMBER
0 EVT0 C674x Interrupt Controller 0
1 EVT1 C674x Interrupt Controller 1
2 EVT2 C674x Interrupt Controller 2
3 EVT3 C674x Interrupt Controller 3
4 - Reserved
5 - Reserved
6 - Reserved
7 - Reserved
8 - Reserved
9 EMU_DTDMA C674x-ECM
10 - Reserved
11 EMU_RTDXRX C674x-RTDX
12 EMU_RTDXTX C674x-RTDX
13 IDMAINT0 C674x-ECM
14 C674x C674x-ECM
15 SDINT0 MMC/SD0
16 SPIINT0 SPI0
17 – Reserved
18 ELM_IRQ ELM
19 – Reserved
20 EDMAINT EDMA CC
21 EDMAERRINT EDMA CC Error
22 TCERRINT0 EDMA TC0 Error
23 ISS_IRQ4 ISS
24 – Reserved
25 – Reserved
26 – Reserved
27 TCERRINT1 EDMA TC1 Error
28 TCERRINT2 EDMA TC2 Error
29 TCERRINT3 EDMA TC3 Error
30 SDINT1 MMC/SD1
31 SDINT2 MMC/SD2
32 3PGSWRXTHR0 EMAC Switch RX Threshold
33 3PGSWRXINT0 EMAC Switch RX
34 3PGSWTXINT0 EMAC Switch TX
35 3PGSWMISC0 EMAC Switch Miscellaneous
36 PCIINT0 PCIe
37 PCIINT1 PCIe
38 PCIINT2 PCIe

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Table 7-29. Default C674x Event Sources (continued)

C674x DEFAULT
ACRONYM SOURCE
EVENT NUMBER
39 PCIINT3 PCIe
40 DSSINT DSS
41 HDMIINT HDMI
42 SATAINT SATA
43 GFXINT SGX530
46 - Reserved
47-48 - Reserved
49 TINT1 TIMER1
50 TINT2 TIMER2
51 TINT3 TIMER3
52 TINT4 TIMER4
53 TINT5 TIMER5
54 TINT6 TIMER6
55 TINT7 TIMER7
56 MBINT Mailbox
57 GPIOINT3A GPIO3
58 I2CINT0 I2C0
59 I2CINT1 I2C1
60 UARTINT0 UART0
61 UARTINT1 UART1
62 UARTINT2 UART2
63 GPIOINT3B GPIO3
64 GPIOINT0A GPIO0
65 GPIOINT0B GPIO0
66 GPIOINT1A GPIO1
67 GPIOINT1B GPIO1
68 GPIOINT2A GPIO2
69 GPIOINT2B GPIO2
70 MCATXINT0 McASP0 Transmit
71 MCARXINT0 McASP0 Receive
72 MCATXINT1 McASP1 Transmit
73 MCARXINT1 McASP1 Receive
74 MCATXINT2 McASP2 Transmit
75 MCARXINT2 McASP2 Receive
76 MCBSPINT McBSP
77 UARTINT3 UART3
78 UARTINT4 UART4
79 UARTINT5 UART5
80 MCATXINT3 McASP3 Transmit
81 MCARXINT3 McASP3 Receive
82 MCATXINT4 McASP4 Transmit
83 MCARXINT4 McASP4 Receive
84 MCATXINT5 McASP5 Transmit
85 MCARXINT5 McASP5 Receive
86 SPIINT1 SPI1
87 SPIINT2 SPI2
88 SPIINT3 SPI3

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Table 7-29. Default C674x Event Sources (continued)

C674x DEFAULT
ACRONYM SOURCE
EVENT NUMBER
89 I2CINT2 I2C2
90 HDVICPCONT1SYNC HDVICP2
91 HDVICPCONT2SYNC HDVICP2
92 I2CINT3 I2C3
93 MMUINT System MMU
94 HDVICPMBOXINT HDVICP2 Mailbox
95 GPMCINT GPMC
96 INTERR C674x-Int Ctl
97 EMC_IDMAERR C674x-EMC
98 - Reserved
99 - Reserved
100 EFIINTA C674x-EFIA
101 EFIINTB C674x-EFIB
102 - Reserved
103 - Reserved
104 - Reserved
105 - Reserved
106 - Reserved
107 - Reserved
108 - Reserved
109 - Reserved
110 - Reserved
111 - Reserved
112 - Reserved
113 PMC_ED C674x-PMC
114 - Reserved
115 - Reserved
116 UMC_ED1 C674x-UMC
117 UMC_ED2 C674x-UMC
118 PDC_INT C674x-PDC
119 SYS_CMPA C674x-SYS
120 PMC_CMPA C674x-PMC
121 PMC_DMPA C674x-PMC
122 DMC_CMPA C674x-DMC
123 DMC_DMPA C674x-DMC
124 UMC_CMPA C674x-UMC
125 UMC_DMPA C674x-UMC
126 EMC_CMPA C674x-EMC
127 EMC_BUSERR C674x-EMC

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Table 7-30. Multiplexed C674x Event Sources

C674x MULTIPLEXED
ACRONYM SOURCE
EVENT NUMBER
0 - Default Event
1 DCAN0_INT0 DCAN0
2 DCAN0_INT1 DCAN0
3 DCAN1_PARITY DCAN0 Parity
4 DCAN1_INT0 DCAN1
5 DCAN1_INT1 DCAN1
6 DCAN1_PARITY DCAN1 Parity
7 – Reserved
8 – Reserved
9 – Reserved
10 - Reserved
11 L3DEBUG L3 Interconnect
12 L3APPINT L3 Interconnect
13 EDMAMPERR EDMA Memory Protection Error
14 TINT8 TIMER8
15 WDTINT0 Watchdog Timer 0
16 USBSSINT USB Subsystem
17 USBINT0 USB0
18 USBINT1 USB1
19 RTCINT RTC
20 RTCALARMINT RTC Alarm
21 - Reserved
22 - Reserved
23 DDRERR0 DDR0
24 DDRERR1 DDR1

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8 Peripheral Information and Timings

8.1 Parameter Information

Tester Pin Electronics Data Sheet Timing Reference Point

42 Ω 3.5 nH Output
Transmission Line Under
Test
Z0 = 50 Ω
(see Note) Device Pin
4.0 pF 1.85 pF (see Note)

NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be
taken into account. A transmission line with a delay of 2 ns can be used to produce the desired transmission line effect. The transmission line is
intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns) from the data sheet timings.

Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.

Figure 8-1. Test Load Circuit for AC Timing Measurements

The load capacitance value stated is only for characterization and measurement of AC timing signals. This
load capacitance value does not indicate the maximum load the device is capable of driving.

8.1.1 1.8-V and 3.3-V Signal Transition Levels

All input and output timing parameters are referenced to Vref for both "0" and "1" logic levels. For 3.3-V I/O,
Vref = 1.5 V. For 1.8-V I/O, Vref = 0.9 V.

Vref

Figure 8-2. Input and Output Voltage Reference Levels for AC Timing Measurements

All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL
MAX and VOH MIN for output clocks.

Vref = VIH MIN (or VOH MIN)

Vref = VIL MAX (or VOL MAX)

Figure 8-3. Rise and Fall Transition Time Voltage Reference Levels

8.1.2 3.3-V Signal Transition Rates

All timings are tested with an input edge rate of 4 volts per nanosecond (4 V/ns).

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8.1.3 Timing Parameters and Board Routing Analysis

The timing parameter values specified in this data manual do not include delays by board routings. As a
good board design practice, such delays must always be taken into account. Timing values may be
adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer
information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS
models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing
Analysis application report (Literature Number: SPRA839). If needed, external logic hardware such as
buffers may be used to compensate any timing differences.

8.2 Recommended Clock and Control Signal Transition Behavior

All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner.

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8.3 Controller Area Network Interface (DCAN)

The device provides two DCAN interfaces for supporting distributed realtime control with a high level of
security. The DCAN interfaces implement the following features:
• Supports CAN protocol version 2.0 part A, B
• Bit rates up to 1 MBit/s
• 64 message objects
• Individual identifier mask for each message object
• Programmable FIFO mode for message objects
• Programmable loop-back modes for self-test operation
• Suspend mode for debug support
• Software module reset
• Automatic bus on after Bus-Off state by a programmable 32-bit timer
• Message RAM parity check mechanism
• Direct access to Message RAM during test mode
• CAN Rx/Tx pins are configurable as general-purpose IO pins
• Two interrupt lines (plus additional parity-error interrupts line)
• RAM initialization
• DMA support
For more detailed information on the DCAN peripheral, see the DCAN Controller Area Network chapter of
the TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual (Literature Number:
SPRUGZ8).

8.3.1 DCAN Peripheral Register Descriptions

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8.3.2 DCAN Electrical Data/Timing

Table 8-1. Timing Requirements for DCANx Receive (1) (see Figure 8-4)
OPP100/120/166
NO. UNIT
MIN NOM MAX
f(baud) Maximum programmable baud rate 1 Mbps
1 tw(DCANRX) Pulse duration, receive data bit (DCANx_RX) H-2 H+2 ns
(1) H = period of baud rate, 1/programmed baud rate.

Table 8-2. Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit
(1)
(see Figure 8-4)
OPP100/120/166
NO. PARAMETER UNIT
MIN MAX
f(baud) Maximum programmable baud rate 1 Mbps
2 tw(DCANTX) Pulse duration, transmit data bit (DCANx_TX) H-2 H+2 ns
(1) H = period of baud rate, 1/programmed baud rate.

DCANx_RX

DCANx_TX

Figure 8-4. DCANx Timings

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8.4 EDMA
The EDMA controller handles all data transfers between memories and the device slave peripherals on
the device. These data transfers include cache servicing, non-cacheable memory accesses, user-
programmed data transfers, and host accesses.

8.4.1 EDMA Channel Synchronization Events

The EDMA Channel controller supports up to 64 channels that service peripherals and memory. Each
EDMA channel is mapped to a defaul EDMA synchronization event as shown in Table 8-3. By default,
each event uses the parameter entry that matches its event number. However, because the device
includes a channel mapping feature, each event may be mapped to any of 512 parameter table entries.
For more detailed information, see the Enhanced Direct Memory Access Controller chapter of the
TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual (Literature Number:
SPRUGZ8).

Table 8-3. EDMA Default Synchronization Events

EVENT DEFAULT
DEFAULT EVENT DESCRIPTION
NUMBER EVENT NAME
0-1 – Reserved
2 SDTXEVT1 SD1 Transmit
3 SDRXEVT1 SD1 Receive
4-7 – Reserved
8 AXEVT0 McASP0 Transmit
9 AREVT0 McASP0 Receive
10 AXEVT1 McASP1 Transmit
11 AREVT1 McASP1 Receive
12 AXEVT2 McASP2 Transmit
13 AREVT2 McASP2 Receive
14 BXEVT McBSP Transmit
15 BREVT McBSP Receive
16 SPI0XEVT0 SPI0 Transmit 0
17 SPI0REVT0 SPI0 Receive 0
18 SPI0XEVT1 SPI0 Transmit 1
19 SPI0REVT1 SPI0 Receive 1
20 SPI0XEVT2 SPI0 Transmit 2
21 SPI0REVT2 SPI0 Receive 2
22 SPI0XEVT3 SPI0 Transmit 3
23 SPI0REVT3 SPI0 Receive 3
24 SDTXEVT0 SD0 Transmit
25 SDRXEVT0 SD0 Receive
26 UTXEVT0 UART0 Transmit
27 URXEVT0 UART0 Receive
28 UTXEVT1 UART1 Transmit
29 URXEVT1 UART1 Receive
30 UTXEVT2 UART2 Transmit
31 URXEVT2 UART2 Receive
32-35 – Reserved
36 ISS_DMA_REQ1 ISS Event 1
37 ISS_DMA_REQ2 ISS Event 2
38 ISS_DMA_REQ3 ISS Event 3
39 ISS_DMA_REQ4 ISS Event 4

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Table 8-3. EDMA Default Synchronization Events (continued)

EVENT DEFAULT
DEFAULT EVENT DESCRIPTION
NUMBER EVENT NAME
40 CAN_IF1DMA DCAN0 IF1
41 CAN_IF2DMA DCAN0 IF2
42 SPI1XEVT0 SPI1 Transmit 0
43 SPI1REVT0 SPI1 Receive 0
44 SPI1XEVT1 SPI1 Transmit 1
45 SPI1REVT1 SPI1 Receive 1
46 – Reserved
47 CAN_IF3DMA DCAN0 IF3
48 TINT4 TIMER4
49 TINT5 TIMER5
50 TINT6 TIMER6
51 TINT7 TIMER7
52 GPMCEVT GPMC
53 HDMIEVT HDMI
54 – Reserved
55 – Reserved
56 AXEVT3 McASP3 Transmit
57 AREVT3 McASP3 Receive
58 I2CTXEVT0 I2C0 Transmit
59 I2CRXEVT0 I2C0 Receive
60 I2CTXEVT1 I2C1 Transmit
61 I2CRXEVT1 I2C1 Receive
62 AXEVT4 McASP4 Transmit
63 AREVT4 McASP4 Receive

Table 8-4. EDMA Multiplexed Synchronization Events

EVT_MUX_x MULTIPLEXED
MULTIPLEXED EVENT DESCRIPTION
VALUE EVENT NAME
0 - Default Event
1 SDTXEVT2 SD2 Transmit
2 SDRXEVT2 SD2 Receive
3 I2CTXEVT2 I2C2 Transmit
4 I2CRXEVT2 I2C2 Receive
5 I2CTXEVT3 I2C3 Transmit
6 I2CRXEVT3 I2C3 Receive
7 UTXEVT3 UART3 Transmit
8 URXEVT3 UART3 Receive
9 UTXEVT4 UART4 Transmit
10 URXEVT4 UART4 Receive
11 UTXEVT5 UART5 Transmit
12 URXEVT5 UART5 Receive
13 CAN_IF1DMA DCAN1 IF1
14 CAN_IF2DMA DCAN1 IF2
15 CAN_IF3DMA DCAN1 IF3
16 SPI2XEVT0 SPI2 Transmit 0
17 SPI2REVT0 SPI2 Receive 0
18 SPI2XEVT1 SPI2 Transmit 1

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Table 8-4. EDMA Multiplexed Synchronization Events (continued)

EVT_MUX_x MULTIPLEXED
MULTIPLEXED EVENT DESCRIPTION
VALUE EVENT NAME
19 SPI2REVT1 SPI2 Receive 1
20 SPI3XEVT0 SPI3 Transmit 0
21 SPI3REVT0 SPI3 Receive 0
22 – Reserved
23 TINT1 TIMER1
24 TINT2 TIMER2
25 TINT3 TIMER3
26 AXEVT5 McASP5 Transmit
27 AREVT5 McASP5 Receive
28 EDMAEVT0 EDMA_EVT0 Pin
29 EDMAEVT1 EDMA_EVT1 Pin
30 EDMAEVT2 EDMA_EVT2 Pin
31 EDMAEVT3 EDMA_EVT3 Pin

8.4.2 EDMA Peripheral Register Descriptions

Table 8-5. EDMA Channel Controller (EDMA TPCC) Control Registers

HEX ADDRESS ACRONYM REGISTER NAME
0x4900 0000 PID Peripheral Identification
0x4900 0004 CCCFG EDMA3CC Configuration
0x4900 0100 - 0x4900 01FC DCHMAP0-63 DMA Channel 0-63 Mappings
0x4900 0200 QCHMAP0 QDMA Channel 0 Mapping
0x4900 0204 QCHMAP1 QDMA Channel 1 Mapping
0x4900 0208 QCHMAP2 QDMA Channel 2 Mapping
0x4900 020C QCHMAP3 QDMA Channel 3 Mapping
0x4900 0210 QCHMAP4 QDMA Channel 4 Mapping
0x4900 0214 QCHMAP5 QDMA Channel 5 Mapping
0x4900 0218 QCHMAP6 QDMA Channel 6 Mapping
0x4900 021C QCHMAP7 QDMA Channel 7 Mapping
0x4900 0240 DMAQNUM0 DMA Queue Number 0
0x4900 0244 DMAQNUM1 DMA Queue Number 1
0x4900 0248 DMAQNUM2 DMA Queue Number 2
0x4900 024C DMAQNUM3 DMA Queue Number 3
0x4900 0250 DMAQNUM4 DMA Queue Number 4
0x4900 0254 DMAQNUM5 DMA Queue Number 5
0x4900 0258 DMAQNUM6 DMA Queue Number 6
0x4900 025C DMAQNUM7 DMA Queue Number 7
0x4900 0260 QDMAQNUM QDMA Queue Number
0x4900 0284 QUEPRI Queue Priority
0x4900 0300 EMR Event Missed
0x4900 0304 EMRH Event Missed High
0x4900 0308 EMCR Event Missed Clear
0x4900 030C EMCRH Event Missed Clear High
0x4900 0310 QEMR QDMA Event Missed
0x4900 0314 QEMCR QDMA Event Missed Clear
0x4900 0318 CCERR EDMA3CC Error

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Table 8-5. EDMA Channel Controller (EDMA TPCC) Control Registers (continued)
HEX ADDRESS ACRONYM REGISTER NAME
0x4900 031C CCERRCLR EDMA3CC Error Clear
0x4900 0320 EEVAL Error Evaluate
0x4900 0340 DRAE0 DMA Region Access Enable for Region 0
0x4900 0344 DRAEH0 DMA Region Access Enable High for Region 0
0x4900 0348 DRAE1 DMA Region Access Enable for Region 1
0x4900 034C DRAEH1 DMA Region Access Enable High for Region 1
0x4900 0350 DRAE2 DMA Region Access Enable for Region 2
0x4900 0354 DRAEH2 DMA Region Access Enable High for Region 2
0x4900 0358 DRAE3 DMA Region Access Enable for Region 3
0x4900 035C DRAEH3 DMA Region Access Enable High for Region 3
0x4900 0360 DRAE4 DMA Region Access Enable for Region 4
0x4900 0364 DRAEH4 DMA Region Access Enable High for Region 4
0x4900 0368 DRAE5 DMA Region Access Enable for Region 5
0x4900 036C DRAEH5 DMA Region Access Enable High for Region 5
0x4900 0370 DRAE6 DMA Region Access Enable for Region 6
0x4900 0374 DRAEH6 DMA Region Access Enable High for Region 6
0x4900 0378 DRAE7 DMA Region Access Enable for Region 7
0x4900 037C DRAEH7 DMA Region Access Enable High for Region 7
0x4900 0380 - 0x4900 039C QRAE0-7 QDMA Region Access Enable for Region 0-7
0x4900 0400 - 0x4900 04FC Q0E0-Q3E15 Event Queue Entry Q0E0-Q3E15
0x4900 0600 - 0x4900 060C QSTAT0-3 Queue Status 0-3
0x4900 0620 QWMTHRA Queue Watermark Threshold A
0x4900 0640 CCSTAT EDMA3CC Status
0x4900 0800 MPFAR Memory Protection Fault Address
0x4900 0804 MPFSR Memory Protection Fault Status
0x4900 0808 MPFCR Memory Protection Fault Command
0x4900 080C MPPAG Memory Protection Page Attribute Global
0x4900 0810 - 0x4900 082C MPPA0-7 Memory Protection Page Attribute 0-7
0x4900 1000 ER Event
0x4900 1004 ERH Event High
0x4900 1008 ECR Event Clear
0x4900 100C ECRH Event Clear High
0x4900 1010 ESR Event Set
0x4900 1014 ESRH Event Set High
0x4900 1018 CER Chained Event
0x4900 101C CERH Chained Event High
0x4900 1020 EER Event Enable
0x4900 1024 EERH Event Enable High
0x4900 1028 EECR Event Enable Clear
0x4900 102C EECRH Event Enable Clear High
0x4900 1030 EESR Event Enable Set
0x4900 1034 EESRH Event Enable Set High
0x4900 1038 SER Secondary Event
0x4900 103C SERH Secondary Event High
0x4900 1040 SECR Secondary Event Clear
0x4900 1044 SECRH Secondary Event Clear High
0x4900 1050 IER Interrupt Enable

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Table 8-5. EDMA Channel Controller (EDMA TPCC) Control Registers (continued)
HEX ADDRESS ACRONYM REGISTER NAME
0x4900 1054 IERH Interrupt Enable High
0x4900 1058 IECR Interrupt Enable Clear
0x4900 105C IECRH Interrupt Enable Clear High
0x4900 1060 IESR Interrupt Enable Set
0x4900 1064 IESRH Interrupt Enable Set High
0x4900 1068 IPR Interrupt Pending
0x4900 106C IPRH Interrupt Pending High
0x4900 1070 ICR Interrupt Clear
0x4900 1074 ICRH Interrupt Clear High
0x4900 1078 IEVAL Interrupt Evaluate
0x4900 1080 QER QDMA Event
0x4900 1084 QEER QDMA Event Enable
0x4900 1088 QEECR QDMA Event Enable Clear
0x4900 108C QEESR QDMA Event Enable Set
0x4900 1090 QSER QDMA Secondary Event
0x4900 1094 QSECR QDMA Secondary Event Clear
Shadow Region 0 Channel Registers
0x4900 2000 ER Event
0x4900 2004 ERH Event High
0x4900 2008 ECR Event Clear
0x4900 200C ECRH Event Clear High
0x4900 2010 ESR Event Set
0x4900 2014 ESRH Event Set High
0x4900 2018 CER Chained Event
0x4900 201C CERH Chained Event High
0x4900 2020 EER Event Enable
0x4900 2024 EERH Event Enable High
0x4900 2028 EECR Event Enable Clear
0x4900 202C EECRH Event Enable Clear High
0x4900 2030 EESR Event Enable Set
0x4900 2034 EESRH Event Enable Set High
0x4900 2038 SER Secondary Event
0x4900 203C SERH Secondary Event High
0x4900 2040 SECR Secondary Event Clear
0x4900 2044 SECRH Secondary Event Clear High
0x4900 2050 IER Interrupt Enable
0x4900 2054 IERH Interrupt Enable High
0x4900 2058 IECR Interrupt Enable Clear
0x4900 205C IECRH Interrupt Enable Clear High
0x4900 2060 IESR Interrupt Enable Set
0x4900 2064 IESRH Interrupt Enable Set High
0x4900 2068 IPR Interrupt Pending
0x4900 206C IPRH Interrupt Pending High
0x4900 2070 ICR Interrupt Clear
0x4900 2074 ICRH Interrupt Clear High
0x4900 2078 IEVAL Interrupt Evaluate
0x4900 2080 QER QDMA Event

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Table 8-5. EDMA Channel Controller (EDMA TPCC) Control Registers (continued)
HEX ADDRESS ACRONYM REGISTER NAME
0x4900 2084 QEER QDMA Event Enable
0x4900 2088 QEECR QDMA Event Enable Clear
0x4900 208C QEESR QDMA Event Enable Set
0x4900 2090 QSER QDMA Secondary Event
0x4900 2094 QSECR QDMA Secondary Event Clear
0x4900 2200 - 0x4900 2294 - Shadow Region 1 Channels
0x4900 2400 - 0x4900 2494 - Shadow Region 2 Channels
... ...
0x4900 2E00 - 0x4900 2E94 - Shadow Channels for MP Space 7

Table 8-6. EDMA Transfer Controller (EDMA TPTC) Control Registers

TPTC0 HEX TPTC1 HEX TPTC2 HEX TPTC3 HEX
ACRONYM REGISTER NAME
ADDRESS ADDRESS ADDRESS ADDRESS
0x4980 0000 0x4990 0000 0x49A0 0000 0x49B0 0000 PID Peripheral Identification
0x4980 0004 0x4990 0004 0x49A0 0004 0x49B0 0004 TCCFG EDMA3TC Configuration
0x4980 0100 0x4990 0100 0x49A0 0100 0x49B0 0100 TCSTAT EDMA3TC Channel Status
0x4980 0120 0x4990 0120 0x49A0 0120 0x49B0 0120 ERRSTAT Error Status
0x4980 0124 0x4990 0124 0x49A0 0124 0x49B0 0124 ERREN Error Enable
0x4980 0128 0x4990 0128 0x49A0 0128 0x49B0 0128 ERRCLR Error Clear
0x4980 012C 0x4990 012C 0x49A0 012C 0x49B0 012C ERRDET Error Details
0x4980 0130 0x4990 0130 0x49A0 0130 0x49B0 0130 ERRCMD Error Interrupt Command
0x4980 0140 0x4990 0140 0x49A0 0140 0x49B0 0140 RDRATE Read Rate Register
0x4980 0240 0x4990 0240 0x49A0 0240 0x49B0 0240 SAOPT Source Active Options
0x4980 0244 0x4990 0244 0x49A0 0244 0x49B0 0244 SASRC Source Active Source Address
0x4980 0248 0x4990 0248 0x49A0 0248 0x49B0 0248 SACNT Source Active Count
0x4980 024C 0x4990 024C 0x49A0 024C 0x49B0 024C SADST Source Active Destination
Address
0x4980 0250 0x4990 0250 0x49A0 0250 0x49B0 0250 SABIDX Source Active Source B-Index
0x4980 0254 0x4990 0254 0x49A0 0254 0x49B0 0254 SAMPPRXY Source Active Memory
Protection Proxy
0x4980 0258 0x4990 0258 0x49A0 0258 0x49B0 0258 SACNTRLD Source Active Count Reload
0x4980 025C 0x4990 025C 0x49A0 025C 0x49B0 025C SASRCBREF Source Active Source Address
B-Reference
0x4980 0260 0x4990 0260 0x49A0 0260 0x49B0 0260 SADSTBREF Source Active Destination
Address B-Reference
0x4980 0280 0x4990 0280 0x49A0 0280 0x49B0 0280 DFCNTRLD Destination FIFO Set Count
Reload
0x4980 0284 0x4990 0284 0x49A0 0284 0x49B0 0284 DFSRCBREF Destination FIFO Set
Destination Address B
Reference
0x4980 0288 0x4990 0288 0x49A0 0288 0x49B0 0288 DFDSTBREF Destination FIFO Set
Destination Address B
Reference
0x4980 0300 0x4990 0300 0x49A0 0300 0x49B0 0300 DFOPT0 Destination FIFO Options 0
0x4980 0304 0x4990 0304 0x49A0 0304 0x49B0 0304 DFSRC0 Destination FIFO Source
Address 0
0x4980 0308 0x4990 0308 0x49A0 0308 0x49B0 0308 DFCNT0 Destination FIFO Count 0
0x4980 030C 0x4990 030C 0x49A0 030C 0x49B0 030C DFDST0 Destination FIFO Destination
Address 0
0x4980 0310 0x4990 0310 0x49A0 0310 0x49B0 0310 DFBIDX0 Destination FIFO BIDX 0

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Table 8-6. EDMA Transfer Controller (EDMA TPTC) Control Registers (continued)
TPTC0 HEX TPTC1 HEX TPTC2 HEX TPTC3 HEX
ACRONYM REGISTER NAME
ADDRESS ADDRESS ADDRESS ADDRESS
0x4980 0314 0x4990 0314 0x49A0 0314 0x49B0 0314 DFMPPRXY0 Destination FIFO Memory
Protection Proxy 0
0x4980 0340 0x4990 0340 0x49A0 0340 0x49B0 0340 DFOPT1 Destination FIFO Options 1
0x4980 0344 0x4990 0344 0x49A0 0344 0x49B0 0344 DFSRC1 Destination FIFO Source
Address 1
0x4980 0348 0x4990 0348 0x49A0 0348 0x49B0 0348 DFCNT1 Destination FIFO Count 1
0x4980 034C 0x4990 034C 0x49A0 034C 0x49B0 034C DFDST1 Destination FIFO Destination
Address 1
0x4980 0350 0x4990 0350 0x49A0 0350 0x49B0 0350 DFBIDX1 Destination FIFO BIDX 1
0x4980 0354 0x4990 0354 0x49A0 0354 0x49B0 0354 DFMPPRXY1 Destination FIFO Memory
Protection Proxy 1
0x4980 0380 0x4990 0380 0x49A0 0380 0x49B0 0380 DFOPT2 Destination FIFO Options 2
0x4980 0384 0x4990 0384 0x49A0 0384 0x49B0 0384 DFSRC2 Destination FIFO Source
Address 2
0x4980 0388 0x4990 0388 0x49A0 0388 0x49B0 0388 DFCNT2 Destination FIFO Count 2
0x4980 038C 0x4990 038C 0x49A0 038C 0x49B0 038C DFDST2 Destination FIFO Destination
Address 2
0x4980 0390 0x4990 0390 0x49A0 0390 0x49B0 0390 DFBIDX2 Destination FIFO BIDX 2
0x4980 0394 0x4990 0394 0x49A0 0394 0x49B0 0394 DFMPPRXY2 Destination FIFO Memory
Protection Proxy 2
0x4980 03C0 0x4990 03C0 0x49A0 03C0 0x49B0 03C0 DFOPT3 Destination FIFO Options 3
0x4980 03C4 0x4990 03C4 0x49A0 03C4 0x49B0 03C4 DFSRC3 Destination FIFO Source
Address 3
0x4980 03C8 0x4990 03C8 0x49A0 03C8 0x49B0 03C8 DFCNT3 Destination FIFO Count 3
0x4980 03CC 0x4990 03CC 0x49A0 03CC 0x49B0 03CC DFDST3 Destination FIFO Destination
Address 3
0x4980 03D0 0x4990 03D0 0x49A0 03D0 0x49B0 03D0 DFBIDX3 Destination FIFO BIDX 3
0x4980 03D4 0x4990 03D4 0x49A0 03D4 0x49B0 03D4 DFMPPRXY3 Destination FIFO Memory
Protection Proxy 3

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8.5 Emulation Features and Capability

8.5.1 Advanced Event Triggering (AET)

The device supports Advanced Event Triggering (AET). This capability can be used to debug complex
problems as well as understand performance characteristics of user applications. AET provides the
following capabilities:
• Hardware Program Breakpoints: specify addresses or address ranges that can generate events such
as halting the processor or triggering the trace capture.
• Data Watchpoints: specify data variable addresses, address ranges, or data values that can generate
events such as halting the processor or triggering the trace capture.
• Counters: count the occurrence of an event or cycles for performance monitoring.
• State Sequencing: allows combinations of hardware program breakpoints and data watchpoints to
precisely generate events for complex sequences.
For more information on AET, see the following documents:
• Using Advanced Event Triggering to Find and Fix Intermittent Real-Time Bugs application report
(Literature Number: SPRA753)
• Using Advanced Event Triggering to Debug Real-Time Problems in High Speed Embedded
Microprocessor Systems application report (Literature Number: SPRA387)

8.5.2 Trace
The device supports Trace at the Cortex™-A8, C674x, and System levels. Trace is a debug technology
that provides a detailed, historical account of application code execution, timing, and data accesses. Trace
collects, compresses, and exports debug information for analysis. The debug information can be exported
to the Embedded Trace Buffer (ETB), or to the 5-pin Trace Interface (system trace only). Trace works in
real-time and does not impact the execution of the system.
For more information on board design guidelines for Trace Advanced Emulation, see the Emulation and
Trace Headers Technical Reference Manual (Literature Number: SPRU655).

8.5.3 IEEE 1149.1 JTAG

The JTAG (IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture)
interface is used for BSDL testing and emulation of the device. The TRST pin only needs to be released
when it is necessary to use a JTAG controller to debug the device or exercise the boundary scan
functionality of the device. For maximum reliability, the device includes an internal pulldown (IPD) on the
TRST pin to ensure that TRST is always asserted upon power up and the internal emulation logic of the
device is always properly initialized. JTAG controllers from Texas Instruments actively drive TRST high.
However, some third-party JTAG controllers may not drive TRST high but expect the use of a pullup
resistor on TRST. When using this type of JTAG controller, assert TRST to initialize the device after
powerup and externally drive TRST high before attempting any emulation or boundary-scan operations.
The main JTAG features include:
• 32KB embedded trace buffer (ETB)
• 5-pin system trace interface for debug
• Supports Advanced Event Triggering (AET)
• All processors can be emulated via JTAG ports
• All functions on EMU pins of the device:
– EMU[1:0] - cross-triggering, boot mode (WIR), STM trace
– EMU[4:2] - STM trace only (single direction)

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8.5.3.1 JTAG ID (JTAGID) Register Description

Table 8-7. JTAG ID Register (1)

HEX ADDRESS ACRONYM REGISTER NAME
0x4814 0600 JTAGID JTAG Identification Register (2)
(1) IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
(2) Read-only. Provides the device 32-bit JTAG ID.

The JTAG ID register is a read-only register that identifies to the customer the JTAG/device ID. For this
device, the JTAG ID register resides at address location 0x4814 0600. The register hex value for the
device is: 0x0B8F 202F. For the actual register bit names and their associated bit field descriptions, see
Figure 8-5 and Table 8-8.

31 28 27 12 11 1 0
VARIANT (4-
PART NUMBER (16-bit) MANUFACTURER (11-bit) LSB
bit)
R-xxxx R-1011 1000 1111 0010 R-0000 0010 111 R-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Figure 8-5. JTAG ID Register Description - Device Register Value: 0x0B8F 202F

Table 8-8. JTAG ID Register Selection Bit Descriptions

Bit Field Description
31:28 VARIANT Variant (4-bit) value. Device value: xxxx. This value reflects the device silicon revision [For example, 0x0
(0000) for initial silicon revision (SR) 1.0].
• SR2.1, 0011, register value: 0x3B8F 202F
• SR3.0, 0100, register value: 0x4B8F 202F
For more detailed information on the current device silicon revision, see the TMS320DM814x DaVinci™
Digital Media Processors Silicon Errata (Silicon Revisions 3.0, 2.1) (Literature Number: SPRZ343).
27:12 PART NUMBER Part Number (16-bit) value. Device value: 0xB8F2 (1011 1000 1111 0010)
11:1 MANUFACTURER Manufacturer (11-bit) value. Device value: 0x017 (0000 0010 111)
0 LSB LSB. This bit is read as a ""1 for this device.

8.5.3.2 JTAG Electrical Data/Timing

Table 8-9. Timing Requirements for IEEE 1149.1 JTAG

(see Figure 8-6)
OPP100/120/166
NO. UNIT
MIN MAX
1 tc(TCK) Cycle time, TCK 51.15 ns
1a tw(TCKH) Pulse duration, TCK high (40% of tc) 20.46 ns
1b tw(TCKL) Pulse duration, TCK low (40% of tc) 20.46 ns
3 tsu(TDI-TCK) Input setup time, TDI valid to TCK high (20% of (tc * 0.5)) 5.115 ns
3 tsu(TMS-TCK) Input setup time, TMS valid to TCK high (20% of (tc * 0.5)) 5.115 ns
th(TCK-TDI) Input hold time, TDI valid from TCK high 10 ns
4
th(TCK-TMS) Input hold time, TMS valid from TCK high 10 ns

Table 8-10. Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
(see Figure 8-6)
OPP100/120/166
NO. PARAMETER UNIT
MIN MAX
2 td(TCKL-TDOV) Delay time, TCK low to TDO valid 0 23.575 (1) ns
(1) (0.5 * tc) - 2

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1
1a 1b

TCK

TDO

3 4

TDI/TMS

Figure 8-6. JTAG Timing

Table 8-11. Timing Requirements for IEEE 1149.1 JTAG With RTCK
(see Figure 8-6)
OPP100/120/166
NO. UNIT
MIN MAX
1 tc(TCK) Cycle time, TCK 51.15 ns
1a tw(TCKH) Pulse duration, TCK high (40% of tc) 20.46 ns
1b tw(TCKL) Pulse duration, TCK low (40% of tc) 20.46 ns
3 tsu(TDI-TCK) Input setup time, TDI valid to TCK high (20% of (tc * 0.5)) 5.115 ns
3 tsu(TMS-TCK) Input setup time, TMS valid to TCK high (20% of (tc * 0.5)) 5.115 ns
th(TCK-TDI) Input hold time, TDI valid from TCK high 10 ns
4
th(TCK-TMS) Input hold time, TMS valid from TCK high 10 ns

Table 8-12. Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
With RTCK
(see Figure 8-7)
OPP100/120/166
NO. PARAMETER UNIT
MIN MAX
Delay time, TCK to RTCK with no selected subpaths (that is,
5 td(TCK-RTCK) ICEPick is the only tap selected - when the ARM is in the scan 0 21 ns
chain, the delay time is a function of the ARM functional clock.)
6 tc(RTCK) Cycle time, RTCK 51.15 ns
7 tw(RTCKH) Pulse duration, RTCK high (40% of tc) 20.46 ns
8 tw(RTCKL) Pulse duration, RTCK low (40% of tc) 20.46 ns

TCK

6
7 8

RTCK

Figure 8-7. JTAG With RTCK Timing

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Table 8-13. Switching Characteristics Over Recommended Operating Conditions for STM Trace
(see Figure 8-8)
OPP100/120/166
NO. PARAMETER UNIT
MIN MAX
Pulse duration, EMUx high detected at 50% VOH with 60/40 duty
tw(EMUH50) 4 (1) ns
1 cycle
tw(EMUH90) Pulse duration, EMUx high detected at 90% VOH 3.5 ns
Pulse duration, EMUx low detected at 50% VOH with 60/40 duty
tw(EMUL50) 4 (1) ns
2 cycle
tw(EMUL10) Pulse duration, EMUx low detected at 10% VOH 3.5 ns
Output skew time, time delay difference between EMUx pins
3 tsko(EMU) -2 0.5 ns
configured as trace.
Pulse skew, magnitude of difference between high-to-low (tPHL)
tskp(EMU) 1 (1) ns
and low-to-high (tPLH) propagation delays
tsldp_o(EMU) Output slew rate EMUx 3.3 V/ns
(1) This parameter applies to the maximum trace export frequency operating in a 40/60 duty cycle.

A
Buffer
Inputs Buffers EMUx Pins
tPLH tPHL
1
2
B B
A
C 3

Figure 8-8. STM Trace Timing

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8.6 Ethernet MAC Switch (EMAC SW)

The EMAC SW controls the flow of packet data between the device and two external Ethernet PHYs, with
hardware flow control and quality-of-service (QOS) support. The EMAC SW contains a 3-port gigabit
switch, where one port is internally connected and the other two ports are brought out externally. Each of
the external EMAC ports supports 10Base-T (10 Mbits/second [Mbps]), and 100BaseTX (100 Mbps), in
either half- or full-duplex mode, and 1000BaseT (1000 Mbps) in full-duplex mode.
The EMAC SW controls the flow of packet data from the device to the external PHYs. The EMAC0/1 ports
on the device support four interface modes: Media Independent Interface (MII), Gigabit Media
Independent Interface (GMII), Reduced Media Independent Interface (RMII) and Reduced Gigabit Media
Independent Interface (RGMII). In addition, a single MDIO interface is pinned out to control the PHY
configuration and status monitoring. Multiple external PHYs can be controlled by the MDIO interface.
The EMAC SW module conforms to the IEEE 802.3-2002 standard, describing the “Carrier Sense Multiple
Access with Collision Detection (CSMA/CD) Access Method and Physical Layer” specifications. The IEEE
802.3 standard has also been adopted by ISO/IEC and re-designated as ISO/IEC 8802-3:2000(E).
Deviating from this standard, the EMAC SW module does not use the Transmit Coding Error signal
MTXER. Instead of driving the error pin when an underflow condition occurs on a transmitted frame, the
EMAC SW will intentionally generate an incorrect checksum by inverting the frame CRC, so that the
transmitted frame will be detected as an error by the network. In addition, the EMAC SW I/Os operate at
3.3 V and are not compatible with 2.5-V I/O signaling. Therefore, only Ethernet PHYs with 3.3-V I/O
interface should be used.
In networking systems, packet transmission and reception are critical tasks. The communications port
programming interface (CPPI) protocol maximizes the efficiency of interaction between the host software
and communications modules. The CPPI block contains 2048 words of 32-bit buffer descriptor memory
that holds up to 512 buffer descriptors.
For more detailed information on the EMAC SW module, see the 3PSW Ethernet Subsystem chapter of
the TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual (Literature Number:
SPRUGZ8).

8.6.1 EMAC Peripheral Register Descriptions

Table 8-14. Ethernet MAC Switch Registers

ARM/L3 MASTERS
EMAC HEX ACRONYM REGISTER NAME
ADDRESS RANGE
0x4A10 0000 CPSW_ID_VER CPSW ID Version Register
0x4A10 0004 CPSW_CONTROL CPSW Switch Control Register
0x4A10 0008 CPSW_SOFT_RESET CPSW Soft Reset Register
0x4A10 000C CPSW_STAT_PORT_EN CPSW Statistics Port Enable Register
0x4A10 0010 CPSW_PTYPE CPSW Transmit Priority Type Register
0x4A10 0014 CPSW_SOFT_IDLE CPSW Software Idle
0x4A10 0018 CPSW_THRU_RATE CPSW Throughput Rate
0x4A10 001C CPSW_GAP_THRESH CPSW CPGMAC_SL Short Gap Threshold
0x4A10 0020 CPSW_TX_START_WDS CPSW Transmit Start Words
0x4A10 0024 CPSW_FLOW_CONTROL CPSW Flow Control
0x4A10 0028 P0_MAX_BLKS CPSW Port 0 Maximum FIFO Blocks Register
0x4A10 002C P0_BLK_CNT CPSW Port 0 FIFO Block Usage Count Register (Read Only)
0x4A10 0030 P0_TX_IN_CTL CPSW Port 0 Transmit FIFO Control
0x4A10 0034 P0_PORT_VLAN CPSW Port 0 VLAN Register
0x4A10 0038 P0_TX_PRI_MAP CPSW Port 0 Tx Header Priority to Switch Priority Mapping Register

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Table 8-14. Ethernet MAC Switch Registers (continued)

ARM/L3 MASTERS
EMAC HEX ACRONYM REGISTER NAME
ADDRESS RANGE
0x4A10 003C CPDMA_TX_PRI_MAP CPSW CPDMA TX (Port 0 Rx) Packet Priority to Header Priority Mapping
Register
0x4A10 0040 CPDMA_RX_CH_Map CPSW CPDMA RX (Port 0 Tx) Switch Priority to DMA Channel Mapping
Register
0x4A10 0050 P1_MAX_BLKS CPSW Port 1 Maximum FIFO Blocks Register
0x4A10 0054 P1_BLK_CNT CPSW Port 1 FIFO Block Usage Count (Read Only)
0x4A10 0058 P1_TX_IN_CTL CPSW Port 1 Transmit FIFO Control
0x4A10 005C P1_PORT_VLAN CPSW Port 1 VLAN Register
0x4A10 0060 P1_TX_PRI_MAP CPSW Port 1 Tx Header Priority to Switch Priority Mapping Register
0x4A10 0064 P1_TS_CTL CPSW_3GF Port 1 Time Sync Control Register
0x4A10 0068 P1_TS_SEQ_LTYPE CPSW_3GF Port 1 Time Sync LTYPE (and SEQ_ID_OFFSET)
0x4A10 006C P1_TS_VLAN CPSW_3GF Port 1 Time Sync VLAN2 and VLAN2 Register
0x4A10 0070 SL1_SA_LO CPSW CPGMAC_SL1 Source Address Low Register
0x4A10 0074 SL1_SA_HI CPSW CPGMAC_SL1 Source Address High Register
0x4A10 0078 P1_SEND_PERCENT CPSW Port 1 Transmit Queue Send Percentages
0x4A10 007C – 0x4A10 008C – Reserved
0x4A10 0090 P2_MAX_BLKS CPSW Port 2 Maximum FIFO Blocks Register
0x4A10 0094 P2_BLK_CNT CPSW Port 2 FIFO Block Usage Count (Read Only)
0x4A10 0098 P2_TX_IN_CTL CPSW Port 2 Transmit FIFO Control
0x4A10 009C P2_PORT_VLAN CPSW Port 2 VLAN Register
0x4A10 00A0 P2_TX_PRI_MAP CPSW Port 2 Tx Header Priority to Switch Priority Mapping Register
0x4A10 00A4 P2_TS_CTL CPSW_3GF Port 2 Time Sync Control Register
0x4A10 00A8 P2_TS_SEQ_LTYPE CPSW_3GF Port 2 Time Sync LTYPE (and SEQ_ID_OFFSET)
0x4A10 00AC P2_TS_VLAN CPSW_3GF Port 2 Time Sync VLAN2 and VLAN2 Register
0x4A10 00B0 SL2_SA_LO CPSW CPGMAC_SL2 Source Address Low Register
0x4A10 00B4 SL2_SA_HI CPSW CPGMAC_SL2 Source Address High Register
0x4A10 00B8 P2_SEND_PERCENT CPSW Port 2 Transmit Queue Send Percentages
0x4A10 00BC – 0x4A10 00FC – Reserved
0x4A10 0100 TX_IDVER CPDMA_REGS TX Identification and Version Register
0x4A10 0104 TX_CONTROL CPDMA_REGS TX Control Register
0x4A10 0108 TX_TEARDOWN CPDMA_REGS TX Teardown Register
0x4A10 010C – Reserved
0x4A10 0110 RX_IDVER CPDMA_REGS RX Identification and Version Register
0x4A10 0114 RX_CONTROL CPDMA_REGS RX Control Register
0x4A10 0118 RX_TEARDOWN CPDMA_REGS RX Teardown Register
0x4A10 011C SOFT_RESET CPDMA_REGS Soft Reset Register
0x4A10 0120 DMACONTROL CPDMA_REGS CPDMA Control Register
0x4A10 0124 DMASTATUS CPDMA_REGS CPDMA Status Register
0x4A10 0128 RX_BUFFER_OFFSET CPDMA_REGS Receive Buffer Offset
0x4A10 012C EMCONTROL CPDMA_REGS Emulation Control
0x4A10 0130 TX_PRI0_RATE CPDMA_REGS Transmit (Ingress) Priority 0 Rate
0x4A10 0134 TX_PRI1_RATE CPDMA_REGS Transmit (Ingress) Priority 1 Rate
0x4A10 0138 TX_PRI2_RATE CPDMA_REGS Transmit (Ingress) Priority 2 Rate
0x4A10 013C TX_PRI3_RATE CPDMA_REGS Transmit (Ingress) Priority 3 Rate
0x4A10 0140 TX_PRI4_RATE CPDMA_REGS Transmit (Ingress) Priority 4 Rate
0x4A10 0144 TX_PRI5_RATE CPDMA_REGS Transmit (Ingress) Priority 5 Rate

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Table 8-14. Ethernet MAC Switch Registers (continued)

ARM/L3 MASTERS
EMAC HEX ACRONYM REGISTER NAME
ADDRESS RANGE
0x4A10 0148 TX_PRI6_RATE CPDMA_REGS Transmit (Ingress) Priority 6 Rate
0x4A10 014C TX_PRI7_RATE CPDMA_REGS Transmit (Ingress) Priority 7 Rate
0x4A10 0150 – 0x4A10 017C – Reserved
0x4A10 0180 TX_INTSTAT_RAW CPDMA_INT TX Interrupt Status Register (Raw Value)
0x4A10 0184 TX_INTSTAT_MASKED CPDMA_INT TX Interrupt Status Register (Masked Value)
0x4A10 0188 TX_INTMASK_SET CPDMA_INT TX Interrupt Mask Set Register
0x4A10 018C TX_INTMASK_CLEAR CPDMA_INT TX Interrupt Mask Clear Register
0x4A10 0190 CPDMA_IN_VECTOR CPDMA_INT Input Vector (Read Only)
0x4A10 0194 CPDMA_EOI_VECTOR CPDMA_INT End Of Interrupt Vector
0x4A10 0198 – 0x4A10 019C – Reserved
0x4A10 01A0 RX_INTSTAT_RAW CPDMA_INT RX Interrupt Status Register (Raw Value)
0x4A10 01A4 RX_INTSTAT_MASKED CPDMA_INT RX Interrupt Status Register (Masked Value)
0x4A10 01A8 RX_INTMASK_SET CPDMA_INT RX Interrupt Mask Set Register
0x4A10 01AC RX_INTMASK_CLEAR CPDMA_INT RX Interrupt Mask Clear Register
0x4A10 01B0 DMA_INTSTAT_RAW CPDMA_INT DMA Interrupt Status Register (Raw Value)
0x4A10 01B4 DMA_INTSTAT_MASKED CPDMA_INT DMA Interrupt Status Register (Masked Value)
0x4A10 01B8 DMA_INTMASK_SET CPDMA_INT DMA Interrupt Mask Set Register
0x4A10 01BC DMA_INTMASK_CLEAR CPDMA_INT DMA Interrupt Mask Clear Register
0x4A10 01C0 RX0_PENDTHRESH CPDMA_INT Receive Threshold Pending Register Channel 0
0x4A10 01C4 RX1_PENDTHRESH CPDMA_INT Receive Threshold Pending Register Channel 1
0x4A10 01C8 RX2_PENDTHRESH CPDMA_INT Receive Threshold Pending Register Channel 2
0x4A10 01CC RX3_PENDTHRESH CPDMA_INT Receive Threshold Pending Register Channel 3
0x4A10 01D0 RX4_PENDTHRESH CPDMA_INT Receive Threshold Pending Register Channel 4
0x4A10 01D4 RX5_PENDTHRESH CPDMA_INT Receive Threshold Pending Register Channel 5
0x4A10 01D8 RX6_PENDTHRESH CPDMA_INT Receive Threshold Pending Register Channel 6
0x4A10 01DC RX7_PENDTHRESH CPDMA_INT Receive Threshold Pending Register Channel 7
0x4A10 01E0 RX0_FREEBUFFER CPDMA_INT Receive Free Buffer Register Channel 0
0x4A10 01E4 RX1_FREEBUFFER CPDMA_INT Receive Free Buffer Register Channel 1
0x4A10 01E8 RX2_FREEBUFFER CPDMA_INT Receive Free Buffer Register Channel 2
0x4A10 01EC RX3_FREEBUFFER CPDMA_INT Receive Free Buffer Register Channel 3
0x4A10 01F0 RX4_FREEBUFFER CPDMA_INT Receive Free Buffer Register Channel 4
0x4A10 01F4 RX5_FREEBUFFER CPDMA_INT Receive Free Buffer Register Channel 5
0x4A10 01F8 RX6_FREEBUFFER CPDMA_INT Receive Free Buffer Register Channel 6
0x4A10 01FC RX7_FREEBUFFER CPDMA_INT Receive Free Buffer Register Channel 7
(1)
0x4A10 0200 TX0_HDP CPDMA_STATERAM TX Channel 0 Head Desc Pointer
(1)
0x4A10 0204 TX1_HDP CPDMA_STATERAM TX Channel 1 Head Desc Pointer
(1)
0x4A10 0208 TX2_HDP CPDMA_STATERAM TX Channel 2 Head Desc Pointer
(1)
0x4A10 020C TX3_HDP CPDMA_STATERAM TX Channel 3 Head Desc Pointer
(1)
0x4A10 0210 TX4_HDP CPDMA_STATERAM TX Channel 4 Head Desc Pointer
(1)
0x4A10 0214 TX5_HDP CPDMA_STATERAM TX Channel 5 Head Desc Pointer
(1)
0x4A10 0218 TX6_HDP CPDMA_STATERAM TX Channel 6 Head Desc Pointer
(1)
0x4A10 021C TX7_HDP CPDMA_STATERAM TX Channel 7 Head Desc Pointer
(1)
0x4A10 0220 RX0_HDP CPDMA_STATERAM RX 0 Channel 0 Head Desc Pointer
(1)
0x4A10 0224 RX1_HDP CPDMA_STATERAM RX 1 Channel 1 Head Desc Pointer
(1)
0x4A10 0228 RX2_HDP CPDMA_STATERAM RX 2 Channel 2 Head Desc Pointer

(1) Denotes CPPI 3.0 registers.

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Table 8-14. Ethernet MAC Switch Registers (continued)

ARM/L3 MASTERS
EMAC HEX ACRONYM REGISTER NAME
ADDRESS RANGE
(1)
0x4A10 022C RX3_HDP CPDMA_STATERAM RX 3 Channel 3 Head Desc Pointer
(1)
0x4A10 0230 RX4_HDP CPDMA_STATERAM RX 4 Channel 4 Head Desc Pointer
(1)
0x4A10 0234 RX5_HDP CPDMA_STATERAM RX 5 Channel 5 Head Desc Pointer
(1)
0x4A10 0238 RX6_HDP CPDMA_STATERAM RX 6 Channel 6 Head Desc Pointer
(1)
0x4A10 023C RX7_HDP CPDMA_STATERAM RX 7 Channel 7 Head Desc Pointer
0x4A10 0240 TX0_CP CPDMA_STATERAM TX Channel 0 Completion Pointer Register (1)
(1)
0x4A10 0244 TX1_CP CPDMA_STATERAM TX Channel 1 Completion Pointer Register
(1)
0x4A10 0248 TX2_CP CPDMA_STATERAM TX Channel 2 Completion Pointer Register
(1)
0x4A10 024C TX3_CP CPDMA_STATERAM TX Channel 3 Completion Pointer Register
(1)
0x4A10 0250 TX4_CP CPDMA_STATERAM TX Channel 4 Completion Pointer Register
(1)
0x4A10 0254 TX5_CP CPDMA_STATERAM TX Channel 5 Completion Pointer Register
(1)
0x4A10 0258 TX6_CP CPDMA_STATERAM TX Channel 6 Completion Pointer Register
(1)
0x4A10 025C TX7_CP CPDMA_STATERAM TX Channel 7 Completion Pointer Register
(1)
0x4A10 0260 RX0_CP CPDMA_STATERAM RX Channel 0 Completion Pointer Register
(2)
0x4A10 0264 RX1_CP CPDMA_STATERAM RX Channel 1 Completion Pointer Register
(2)
0x4A10 0268 RX2_CP CPDMA_STATERAM RX Channel 2 Completion Pointer Register
(2)
0x4A10 026C RX3_CP CPDMA_STATERAM RX Channel 3 Completion Pointer Register
(2)
0x4A10 0270 RX4_CP CPDMA_STATERAM RX Channel 4 Completion Pointer Register
(2)
0x4A10 0274 RX5_CP CPDMA_STATERAM RX Channel 5 Completion Pointer Register
(2)
0x4A10 0278 Rx6_CP CPDMA_STATERAM RX Channel 6 Completion Pointer Register
(2)
0x4A10 027C Rx7_CP CPDMA_STATERAM RX Channel 7 Completion Pointer Register
0x4A10 02C0 - 0x4A10 03FC – Reserved
0x4A10 0400 RXGOODFRAMES CPSW_STATS Total Number of Good Frames Received
0x4A10 0404 RXBROADCASTFRAMES CPSW_STATS Total Number of Good Broadcast Frames Received
0x4A10 0408 RXMULTICASTFRAMES CPSW_STATS Total Number of Good Multicast Frames Received
0x4A10 040C RXPAUSEFRAMES CPSW_STATS PauseRxFrames
0x4A10 0410 RXCRCERRORS CPSW_STATS Total Number of CRC Errors Frames Received
0x4A10 0414 RXALIGNCODEERRORS CPSW_STATS Total Number of Alignment/Code Errors Received
0x4A10 0418 RXOVERSIZEDFRAMES CPSW_STATS Total Number of Oversized Frames Received
0x4A10 041C RXJABBERFRAMES CPSW_STATS Total number of Jabber Frames Received
0x4A10 0420 RXUNDERSIZEDFRAMES CPSW_STATS Total Number of Undersized Frames Received
0x4A10 0424 RXFRAGMENTS CPSW_STATS RxFragments Received
0x4A10 0428 - 0x4A10 042C – Reserved. Read as Zero
0x4A10 0430 RXOCTETS CPSW_STATS Total Number of Received Bytes in Good Frames
0x4A10 0434 TXGOODFRAMES CPSW_STATS GoodTxFrames
0x4A10 0438 TXBROADCASTFRAMES CPSW_STATS BroadcastTxFrames
0x4A10 043C TXMULTICASTFRAMES CPSW_STATS MulticastTxFrames
0x4A10 0440 TXPAUSEFRAMES CPSW_STATS PauseTxFrames
0x4A10 0444 TXDEFERREDFRAMES CPSW_STATS Deferred Frames
0x4A10 0448 TXCOLLISIONFRAMES CPSW_STATS Collisions
0x4A10 044C TXSINGLECOLLFRAMES CPSW_STATS SingleCollisionTxFrames
0x4A10 0450 TXMULTCOLLFRAMES CPSW_STATS MultipleCollisionTxFrames
0x4A10 0454 TXEXCESSIVECOLLISION CPSW_STATS ExcessiveCollisions
S
0x4A10 0458 TXLATECOLLISIONS CPSW_STATS LateCollisions

(2) Denotes CPPI 3.0 registers.

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Table 8-14. Ethernet MAC Switch Registers (continued)

ARM/L3 MASTERS
EMAC HEX ACRONYM REGISTER NAME
ADDRESS RANGE
0x4A10 045C TXUNDERRUN CPSW_STATS Transmit Underrun Error
0x4A10 0460 TXCARRIERSENSEERRO CPSW_STATS CarrierSenseErrors
RS
0x4A10 0464 TXOCTETS CPSW_STATS TxOctets
0x4A10 0468 64OCTETFRAMES CPSW_STATS 64octetFrames
0x4A10 046C 65T127OCTETFRAMES CPSW_STATS 65-127octetFrames
0x4A10 0470 128T255OCTETFRAMES CPSW_STATS 128-255octetFrames
0x4A10 0474 256T511OCTETFRAMES CPSW_STATS 256-511octetFrames
0x4A10 0478 512T1023OCTETFRAMES CPSW_STATS 512-1023octetFrames
0x4A10 047C 1024TUPOCTETFRAMES CPSW_STATS 1023-1518octetFrames
0x4A10 0480 NETOCTETS CPSW_STATS NetOctets
0x4A10 0484 RXSOFOVERRUNS CPSW_STATS Receive FIFO or DMA Start of Frame Overruns
0x4A10 0488 RXMOFOVERRUNS CPSW_STATS Receive FIFO or DMA Mid of Frame Overruns
0x4A10 048C RXDMAOVERRUNS CPSW_STATS Receive DMA Start of Frame and Middle of Frame
Overruns
0x4A10 0490 - 0x4A10 04FC – Reserved
0x4A10 0500 CPTS_IDVER Identification and Version Register
0x4A10 0504 CPTS_CONTROL Time Sync Control Register
0x4A10 0508 CPTS_RFTCLK_SEL Reference Clock Select Register
0x4A10 050C CPTS_TS_PUSH Time Stamp Event Push Register
0x4A10 0510 CPTS_TS_LOAD_VAL Time Stamp Load Value Register
0x4A10 0514 CPTSTS_LOAD_EN Time Stamp Load Enable Register
0x4A10 0518 - 0x4A10 051C – Reserved
0x4A10 0520 CPTS_INTSTAT_RAW Time Sync Interrupt Status Raw Register
0x4A10 0524 CPTS_INTSTAT_MASKED Time Sync Interrupt Status Masked Register
0x4A10 0528 CPTS_INT_ENABLE Time Sync Interrupt Enable Register
0x4A10 052C – Reserved
0x4A10 0530 CPTS_EVENT_POP Event Interrupt Pop Register
0x4A10 0534 CPTS_EVENT_LOW Lower 32-Bits of the Event Value
0x4A10 0538 CPTS_EVENT_HIGH Upper 32-Bits of the Event Value
0x4A10 053C - 0x4A10 05FC – Reserved
0x4A10 0600 ALE_IDVER Address Lookup Engine ID/Version Register
0x4A10 0604 – Reserved
0x4A10 0608 ALE_CONTROL Address Lookup Engine Control Register
0x4A10 060C – Reserved
0x4A10 0610 ALE_PRESCALE Address Lookup Engine Prescale Register
0x4A10 0614 – Reserved
0x4A10 0618 ALE_UNKNOWN_VLAN Address Lookup Engine Unknown VLAN Register
0x4A10 061C – Reserved
0x4A10 0620 ALE_TBLCTL Address Lookup Engine Table Control
0x4A10 0624 - 0x4A10 0630 – Reserved
0x4A10 0634 ALE_TBLW2 Address Lookup Engine Table Word 2 Register
0x4A10 0638 ALE_TBLW1 Address Lookup Engine Table Word 1 Register
0x4A10 063C ALE_TBLW0 Address Lookup Engine Table Word 0 Register
0x4A10 0640 ALE_PORTCTL0 Address Lookup Engine Port 0 Control Register
0x4A10 0644 ALE_PORTCTL1 Address Lookup Engine Port 1 Control Register

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Table 8-14. Ethernet MAC Switch Registers (continued)

ARM/L3 MASTERS
EMAC HEX ACRONYM REGISTER NAME
ADDRESS RANGE
0x4A10 0648 ALE_PORTCTL2 Address Lookup Engine Port 2 Control Register
0x4A10 064C – Reserved
0x4A10 0650 – Reserved
0x4A10 0654 – Reserved
0x4A10 0658 - 0x4A10 06FF – Reserved
0x4A10 0700 SL1_IDVER CPGMAC_SL1 ID/Version Register
0x4A10 0704 SL1_MACCONTROL CPGMAC_SL1 Mac Control Register
0x4A10 0708 SL1_MACSTATUS CPGMAC_SL1 Mac Status Register
0x4A10 070C SL1_SOFT_RESET CPGMAC_SL1 Soft Reset Register
0x4A10 0710 SL1_RX_MAXLEN CPGMAC_SL1 RX Maximum Length Register
0x4A10 0714 SL1_BOFFTEST CPGMAC_SL1 Backoff Test Register
0x4A10 0718 SL1_RX_PAUSE CPGMAC_SL1 Receive Pause Timer Register
0x4A10 071C SL1_TX_PAUSE CPGMAC_SL1 Transmit Pause Timer Register
0x4A10 0720 SL1_EMCONTROL CPGMAC_SL1 Emulation Control Register
0x4A10 0724 SL1_RX_PRI_MAP CPGMAC_SL1 Rx Pkt Priority to Header Priority Mapping Register
0x4A10 0728 - 0x4A10 073C – Reserved
0x4A10 0740 SL2_IDVER CPGMAC_SL2 ID/Version Register
0x4A10 0744 SL2_MACCONTROL CPGMAC_SL2 Mac Control Register
0x4A10 0748 SL2_MACSTATUS CPGMAC_SL2 Mac Status Register
0x4A10 074C SL2_SOFT_RESET CPGMAC_SL2 Soft Reset Register
0x4A10 0750 SL2_RX_MAXLEN CPGMAC_SL2 RX Maximum Length Register
0x4A10 0754 SL2_BOFFTEST CPGMAC_SL2 Backoff Test Register
0x4A10 0758 SL2_RX_PAUSE CPGMAC_SL2 Receive Pause Timer Register
0x4A10 075C SL2_TX_PAUSE CPGMAC_SL2 Transmit Pause Timer Register
0x4A10 0760 SL2_EMCONTROL CPGMAC_SL2 Emulation Control
0x4A10 0764 SL2_RX_PRI_MAP CPGMAC_SL2 Rx Pkt Priority to Header Priority Mapping Register
0x4A10 0768 - 0x4A10 07FF – Reserved
0x4A10 0800 - 0x4A10 08FF see Table 8-27 MDIO Registers
0x4A10 0900 IDVER Subsystem ID Version Register
0x4A10 0904 SOFT_RESET Subsystem Soft Reset Register
0x4A10 0908 CONTROL Subsystem Control Register
0x4A10 090C INT_CONTROL Subsystem Interrupt Control
0x4A10 0910 C0_RX_THRESH_EN Subsystem Core 0 Receive Threshold Int Enable Register
0x4A10 0914 C0_RX_EN Subsystem Core 0 Receive Interrupt Enable Register
0x4A10 0918 C0_TX_EN Subsystem Core 0 Transmit Interrupt Enable Register
0x4A10 091C C0_MISC_EN Subsystem Core 0 Misc Interrupt Enable Register
0x4A10 0920 C1_RX_THRESH_EN Subsystem Core 1 Receive Threshold Int Enable Register
0x4A10 0924 C1_RX_EN Subsystem Core 1 Receive Interrupt Enable Register
0x4A10 0928 C1_TX_EN Subsystem Core 1 Transmit Interrupt Enable Register
0x4A10 092C C1_MISC_EN Subsystem Core 1 Misc Interrupt Enable Register
0x4A10 0930 C2_RX_THRESH_EN Subsystem Core 2 Receive Threshold Int Enable Register
0x4A10 0934 C2_RX_EN Subsystem Core 2 Receive Interrupt Enable Register
0x4A10 0938 C2_TX_EN Subsystem Core 2 Transmit Interrupt Enable Register
0x4A10 093C C2_MISC_EN Subsystem Core 2 Misc Interrupt Enable Register
0x4A10 0940 C0_RX_THRESH_STAT Subsystem Core 0 Rx Threshold Masked Int Status Register
0x4A10 0944 C0_RX_STAT Subsystem Core 0 Rx Interrupt Masked Int Status Register

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Table 8-14. Ethernet MAC Switch Registers (continued)

ARM/L3 MASTERS
EMAC HEX ACRONYM REGISTER NAME
ADDRESS RANGE
0x4A10 0948 C0_TX_STAT Subsystem Core 0 Tx Interrupt Masked Int Status Register
0x4A10 094C C0_MISC_STAT Subsystem Core 0 Misc Interrupt Masked Int Status Register
0x4A10 0950 C1_RX_THRESH_STAT Subsystem Core 1 Rx Threshold Masked Int Status Register
0x4A10 0954 C1_RX_STAT Subsystem Core 1 Receive Masked Interrupt Status Register
0x4A10 0958 C1_TX_STAT Subsystem Core 1 Transmit Masked Interrupt Status Register
0x4A10 095C C1_MISC_STAT Subsystem Core 1 Misc Masked Interrupt Status Register
0x4A10 0960 C2_RX_THRESH_STAT Subsystem Core 2 Rx Threshold Masked Int Status Register
0x4A10 0964 C2_RX_STAT Subsystem Core 2 Receive Masked Interrupt Status Register
0x4A10 0968 C2_TX_STAT Subsystem Core 2 Transmit Masked Interrupt Status Register
0x4A10 096C C2_MISC_STAT Subsystem Core 2 Misc Masked Interrupt Status Register
0x4A10 0970 C0_RX_IMAX Subsystem Core 0 Receive Interrupts Per Millisecond
0x4A10 0974 C0_TX_IMAX Subsystem Core 0 Transmit Interrupts Per Millisecond
0x4A10 0978 C1_RX_IMAX Subsystem Core 1 Receive Interrupts Per Millisecond
0x4A10 097C C1_TX_IMAX Subsystem Core 1 Transmit Interrupts Per Millisecond
0x4A10 0980 C2_RX_IMAX Subsystem Core 2 Receive Interrupts Per Millisecond
0x4A10 0984 C2_TX_IMAX Subsystem Core 2 Transmit Interrupts Per Millisecond
0x4A10 2000 -0x4A10 3FFF CPPI_RAM CPPI RAM (3)
(3) Denotes CPPI 3.0 registers.

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8.6.2 EMAC Electrical Data/Timing

8.6.2.1 EMAC MII and GMII Electrical Data/Timing

Table 8-15. Timing Requirements for EMAC[x]_MRCLK - [G]MII Operation

(see Figure 8-9)
OPP100/120/166
1000 Mbps (1 Gbps) 100 Mbps 10 Mbps
NO. UNIT
(GMII Only)
MIN MAX MIN MAX MIN MAX
1 tc(MRCLK) Cycle time, EMAC[x]_MRCLK 8 40 400 ns
Pulse duration,
2 tw(MRCLKH) 2.8 14 140 ns
EMAC[x]_MRCLK high
Pulse duration,
3 tw(MRCLKL) 2.8 14 140 ns
EMAC[x]_MRCLK low
Transition time,
4 tt(MRCLK) 1 3 3 ns
EMAC[x]_MRCLK

1 4

2 3

EMAC[x]_MRCLK

Figure 8-9. EMAC[x]_MRCLK Timing (EMAC Receive) - [G]MII Operation

Table 8-16. Timing Requirements for EMAC[x]_MTCLK - [G]MII Operation

(see Figure 8-14)
OPP100/120/166
1000 Mbps (1 Gbps) 100 Mbps 10 Mbps
NO. UNIT
(GMII Only)
MIN MAX MIN MAX MIN MAX
1 tc(MTCLK) Cycle time, EMAC[x]_MTCLK 8 40 400 ns
Pulse duration,
2 tw(MTCLKH) 2.8 14 140 ns
EMAC[x]_MTCLK high
Pulse duration,
3 tw(MTCLKL) 2.8 14 140 ns
EMAC[x]_MTCLK low
Transition time,
4 tt(MTCLK) 1 3 3 ns
EMAC[x]_MTCLK

1 4

2 3

EMAC[x]_MTCLK

Figure 8-10. EMAC[x]_MTCLK Timing (EMAC Transmit) - [G]MII Operation

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Table 8-17. Timing Requirements for EMAC [G]MII Receive 10/100/1000 Mbit/s
(see Figure 8-11)
OPP100/120/166
1000 Mbps (1 100/10 Mbps
NO. UNIT
Gbps)
MIN MAX MIN MAX
tsu(MRXD-MRCLK)
Setup time, receive selected signals valid before
1 tsu(MRXDV-MRCLK) 2 8 ns
EMAC[1:0]_MRCLK
tsu(MRXER-MRCLK)
th(MRCLK-MRXD)
Hold time, receive selected signals valid after
2 th(MRCLK-MRXDV) 0 8 ns
EMAC[1:0]_MRCLK
th(MRCLK-MRXER)

1
2

EMAC[x]_MRCLK (Input)

EMAC[x]_MRXD3−EMAC[x]_MRXD0,
EMAC[x]_MRXDV, EMAC[x]_MRXER (Inputs)

Figure 8-11. EMAC Receive Interface Timing [G]MII Operation

Table 8-18. Switching Characteristics Over Recommended Operating Conditions for EMAC [G]MII
Transmit 10/100 Mbits/s
(see Figure 8-12)
OPP100/120/166
NO. PARAMETER 100/10 Mbps UNIT
MIN MAX
td(MTXCLK-MTXD)
1 Delay time, EMAC[x]_MTCLK to transmit selected signals valid 2.5 25 ns
td(MTCLK-MTXEN)

Table 8-19. Switching Characteristics Over Recommended Operating Conditions for EMAC [G]MII
Transmit 1000 Mbits/s
(see Figure 8-12)
OPP100/120/166
NO. PARAMETER 1000 Mbps (1 Gbps) UNIT
MIN MAX
td(GMTCLK-MTXD)
1 Delay time, EMAC[x]_GMTCLK to transmit selected signals valid 0 5 ns
td(GMTCLK-MTXEN)

EMAC[x]_MTCLK (Input)

EMAC[x]_MTXD3−EMAC[x]_MTXD0,
EMAC[x]_MTXEN (Outputs)

Figure 8-12. EMAC Transmit Interface Timing [G]MII Operation

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8.6.2.2 EMAC RMII Electrical Data/Timing

Table 8-20. Timing Requirements for EMAC[x]_RMREFCLK - RMII Operation

(see Figure 8-13)
OPP100/120/166
NO. UNIT
MIN MAX
1 tc(RMREFCLK) Cycle time, EMAC[x]_RMREFCLK 19.999 20.001 ns
2 tw(RMREFCLKH) Pulse duration, EMAC[x]_RMREFCLK high 7 13 ns
3 tw(RMREFCLKL) Pulse duration, EMAC[x]_RMREFCLK low 7 13 ns
4 tt(RMREFCLK) Transition time, EMAC[x]_RMREFCLK 3 ns

1
2
4

RMREFCLK
(Input)
3
4

Figure 8-13. RMREFCLK Timing RMII Operation

Table 8-21. Timing Requirements for EMAC RMII Receive

(see Figure 8-13)
OPP100/120/166
NO. UNIT
MIN MAX
tsu(RMRXD-RMREFCLK)
Setup time, receive selected signals valid before
1 tsu(RMCRSDV-RMREFCLK) 4 ns
EMAC[x]_RMREFCLK
tsu(RMRXER-RMREFCLK)
th(RMREFCLK-RMRXD)
Hold time, receive selected signals valid after
2 th(RMREFCLK-RMCRSDV) 2 ns
EMAC[x]_RMREFCLK
th(RMREFCLK-RMRXER)

1
2

RMREFCLK

RMRXD1−RMRXD0,
RMCRSDV, RMRXER (inputs)

Figure 8-14. EMAC Receive Interface Timing RMII Operation

Table 8-22. Switching Characteristics Over Recommended Operating Conditions for EMAC RMII Transmit
10/100 Mbits/s
(see Figure 8-15)
OPP100/120/166
NO. PARAMETER UNIT
MIN MAX
Delay time, EMAC[x]_RMREFCLK high to EMAC[x]_RMTXD[x]
1 td(RMREFCLK-RMTXD) 2.5 13 ns
valid
Delay time, EMAC[x]_RMREFCLK high to EMAC[x]_RMTXEN
2 tdd(RMREFCLK-RMTXEN) 2.5 13
valid

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RMREFCLK

RMTXD1−RMTXD0,
RMTXEN (Outputs)

Figure 8-15. EMAC Transmit Interface Timing RMII Operation

8.6.2.3 EMAC RGMII Electrical Data/Timing

Table 8-23. Timing Requirements for EMAC[x]_RGRXC - RGMII Operation

(see Figure 8-16)
OPP100/120/166
NO. UNIT
MIN MAX
10 Mbps 360 440
1 tc(RGRXC) Cycle time, EMAC[x]_RGRXC 100 Mbps 36 44 ns
1000 Mbps 7.2 8.8
10 Mbps 0.40*tc(RGRXC) 0.60*tc(RGRXC)
2 tw(RGRXCH) Pulse duration, EMAC[x]_RGRXC high 100 Mbps 0.40*tc(RGRXC) 0.60*tc(RGRXC) ns
1000 Mbps 0.45*tc(RGRXC) 0.55*tc(RGRXC)
10 Mbps 0.40*tc(RGRXC) 0.60*tc(RGRXC)
3 tw(RGRXCL) Pulse duration, EMAC[x]_RGRXC low 100 Mbps 0.40*tc(RGRXC) 0.60*tc(RGRXC) ns
1000 Mbps 0.45*tc(RGRXC) 0.55*tc(RGRXC)
10 Mbps 0.75
4 tt(RGRXC) Transition time, EMAC[x]_RGRXC 100 Mbps 0.75 ns
1000 Mbps 0.75

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Table 8-24. Timing Requirements for EMAC RGMII Input Receive for 10/100/1000 Mbps (1)
(see Figure 8-16)
OPP100/120/166
NO. UNIT
MIN MAX
tsu(RGRXD- Setup time, receive selected signals valid before EMAC[x]_RGRXC (at device)
5 1.0 ns
RGRXCH) high/low
th(RGRXCH- Hold time, receive selected signals valid after EMAC[x]_RGRXC (at device)
6 1.0 ns
RGRXD) high/low
(1) For RGMII, receive selected signals include: EMAC[x]_RGRXD[3:0] and EMAC[x]_RGRXCTL.

1
4
2
3 4
EMAC[x]_RGRXC
(A)
(at device)
5
1st Half-byte
2nd Half-byte 6
(B)
EMAC[x]_RGRXD[3:0] RGRXD[3:0] RGRXD[7:4]

(B)
EMAC[x]_RGRXCTL RXDV RXERR

A. EMAC[x]_RGRXC must be externally delayed relative to the data and control pins. The internal delay can be enabled
or disabled via the EMAC RGMIIx_ID_MODE register.
B. Data and control information is received using both edges of the clocks. EMAC[x]_RGRXD[3:0] carries data bits 3-0
on the rising edge of EMAC[x]_RGRXC and data bits 7-4 on the falling edge of EMAC[x]_RGRXC. Similarly,
EMAC[x]_RGRXCTL carries RXDV on rising edge of EMAC[x]_RGRXC and RXERR on falling edge of
EMAC[x]_RGRXC.

Figure 8-16. EMAC Receive Interface Timing [RGMII Operation]

Table 8-25. Switching Characteristics Over Recommended Operating Conditions for RGTXC - RGMII
Operation for 10/100/1000 Mbit/s
(see Figure 8-17)
OPP100/120/166
NO. UNIT
MIN MAX
10 Mbps 360 440
1 tc(RGTXC) Cycle time, EMAC[x]_RGTXC 100 Mbps 36 44 ns
1000 Mbps 7.2 8.8
10 Mbps 0.40*tc(RGTXC) 0.60*tc(RGTXC)
2 tw(RGTXCH) Pulse duration, EMAC[x]_RGTXC high 100 Mbps 0.40*tc(RGTXC) 0.60*tc(RGTXC) ns
1000 Mbps 0.45*tc(RGTXC) 0.55*tc(RGTXC)
10 Mbps 0.40*tc(RGTXC) 0.60*tc(RGTXC)
3 tw(RGTXCL) Pulse duration, EMAC[x]_RGTXC low 100 Mbps 0.40*tc(RGTXC) 0.60*tc(RGTXC) ns
1000 Mbps 0.45*tc(RGTXC) 0.55*tc(RGTXC)
10 Mbps 0.75
4 tt(RGTXC) Transition time, EMAC[x]_RGTXC 100 Mbps 0.75 ns
1000 Mbps 0.75

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Table 8-26. Switching Characteristics Over Recommended Operating Conditions for EMAC RGMII
Transmit (1)
(see Figure 8-17)
OPP100/120/166
NO. PARAMETER UNIT
MIN MAX
tsu(RGTXD- Setup time, transmit selected signals valid before
5 Internal delay enabled 1.2 ns
RGTXCH) EMAC[x]_RGTXC (at device) high/low
th(RGTXCH- Hold time, transmit selected signals valid after
6 Internal delay enabled 1.2 ns
RGTXD) EMAC[x]_RGTXC (at device) high/low
tsk(RGTXD- Transmit selected signals to EMAC[x]_RGTXC (at device)
7 Internal delay disabled -0.5 0.5 ns
RGTXCH) output skew
(1) For RGMII, transmit selected signals include: EMAC[x]_RGTXD[3:0] and EMAC[x]_RGTXCTL.

1
4
2
3 4
(A)
EMAC[x]_RGTXC (at device)
[internal delay enabled]

5
(A)
EMAC[x]_RGTXC (at device)
[internal delay disabled]
7

(B)
EMAC[x]_RGTXD[3:0] 1st Half-byte 2nd Half-byte

6
(B)
EMAC[x]_RGTXCTL TXEN TXERR

A. RGTXC is delayed internally before being driven to the EMAC[x]_RGTXC pin. The internal delay can be enabled or
disabled via the EMAC RGMIIx_ID_MODE register.
B. Data and control information is transmitted using both edges of the clocks. EMAC[x]_RGTXD[3:0] carries data bits 3-0
on the rising edge of EMAC[x]_RGTXC and data bits 7-4 on the falling edge of EMAC[x]_RGTXC. Similarly,
EMAC[x]_RGTXCTL carries TXEN on rising edge of EMAC[x]_RGTXC and TXERR of falling edge of
EMAC[x]_RGTXC.

Figure 8-17. EMAC Transmit Interface Timing [RGMII Operation]

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8.6.3 Management Data Input/Output (MDIO)

The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to
enumerate all PHY devices in the system.
The MDIO module implements the 802.3 serial management interface to interrogate and control Ethernet
PHYs using a shared two-wire bus. Host software uses the MDIO module to configure the auto-
negotiation parameters of each PHY attached to the EMAC SW, retrieve the negotiation results, and
configure required parameters in the EMAC SW module for correct operation. The module is designed to
allow almost transparent operation of the MDIO interface, with very little maintenance from the core
processor. A single MDIO interface is pinned out to control the PHY configuration and status monitoring.
Multiple external PHYs can be controlled by the MDIO interface.
For more detailed information on the MDIO peripheral, see the 3PSW Ethernet Subsystem chapter of the
TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual (Literature Number:
SPRUGZ8).

8.6.3.1 MDIO Peripheral Register Descriptions

Table 8-27. MDIO Registers

HEX ADDRESS ACRONYM REGISTER NAME
0x4A10 0800 VERSION MDIO Version
0x4A10 0804 CONTROL MDIO Control
0x4A10 0808 ALIVE PHY Alive Status
0x4A10 080C LINK PHY Link Status
0x4A10 0810 LINKINTRAW MDIO Link Status Change Interrupt (Unmasked)
0x4A10 0814 LINKINTMASKED MDIO Link Status Change Interrupt (Masked)
0x4A10 0818 - 0x4A10 081C - Reserved
0x4A10 0820 USERINTRAW MDIO User Command Complete Interrupt (Unmasked)
0x4A10 0824 USERINTMASKED MDIO User Command Complete Interrupt (Masked)
0x4A10 0828 USERINTMASKSET MDIO User Command Complete Interrupt Mask Set
0x4A10 082C USERINTMASKCLEAR MDIO User Command Complete Interrupt Mask Clear
0x4A10 0830 - 0x4A10 087C - Reserved
0x4A10 0880 USERACCESS0 MDIO User Access 0
0x4A10 0884 USERPHYSEL0 MDIO User PHY Select 0
0x4A10 0888 USERACCESS1 MDIO User Access 1
0x4A10 088C USERPHYSEL1 MDIO User PHY Select 1
0x4A10 0990 - 0x4A10 08FF - Reserved

8.6.3.2 MDIO Electrical Data/Timing

Table 8-28. Timing Requirements for MDIO Input

(see Figure 8-18)
OPP100/122/166
NO. UNIT
MIN MAX
1 tc(MDCLK) Cycle time, MDCLK 400 ns
tw(MDCLK) Pulse duration, MDCLK high or low 180 ns
4 tsu(MDIO-MDCLKH) Setup time, MDIO data input valid before MDCLK high 20 ns
5 th(MDCLKH-MDIO) Hold time, MDIO data input valid after MDCLK high 0 ns

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MDCLK

4
5

MDIO
(input)

Figure 8-18. MDIO Input Timing

Table 8-29. Switching Characteristics Over Recommended Operating Conditions for MDIO Output
(see Figure 8-19)
OPP100/122/1166
NO. PARAMETER UNIT
MIN MAX
7 td(MDCLKL-MDIO) Delay time, MDCLK low to MDIO data output valid 100 ns

MDCLK

MDIO
(output)

Figure 8-19. MDIO Output Timing

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8.7 General-Purpose Input/Output (GPIO)

The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs.
When configured as an output, a write to an internal register controls the state driven on the output pin.
When configured as an input, the state of the input is detectable by reading the state of an internal
register. In addition, the GPIO peripheral can produce CPU interrupts in different interrupt generation
modes. The GPIO peripheral provides generic connections to external devices.
The device contains four GPIO modules and each GPIO module is made up of 32 identical channels.
The device GPIO peripheral supports the following:
• Up to 128 1.8-V/3.3-V GPIO pins, GP0[0:31], GP1[0:31], GP2[0:31], and GP3[0:31] (the exact number
available varies as a function of the device configuration). Each channel can be configured to be used
in the following applications:
– Data input/output
– Keyboard interface with a de-bouncing cell
– Synchronous interrupt generation (in active mode) upon the detection of external events (signal
transitions and/or signal levels).
• Synchronous interrupt requests from each channel are processed by four identical interrupt generation
sub-modules to be used independently by the ARM, DSP, or Media Controller. Interrupts can be
triggered by rising and/or falling edge, specified for each interrupt-capable GPIO signal.
• Shared registers can be accessed through "Set and Clear" protocol. Software writes 1 to
corresponding bit position or positions to set or to clear the GPIO signal. This allows multiple software
processes to toggle GPIO output signals without critical section protection (disable interrupts, program
GPIO, re-enable interrupts, to prevent context switching to another process during GPIO
programming).
• Separate input/output registers.
• Output register in addition to set/clear so that, if preferred by software, some GPIO output signals can
be toggled by direct write to the output register.
• Output register, when read, reflects output drive status. This, in addition to the input register reflecting
pin status and open-drain I/O cell, allows wired logic to be implemented.
For more detailed information on GPIOs, see the General-Purpose I/O (GPIO) Interface chapter of the
TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual (Literature Number:
SPRUGZ8).

8.7.1 GPIO Peripheral Register Descriptions

Table 8-30. GPIO Registers
HEX ADDRESS
GPIO0 GPIO1 GPIO2 GPIO3 ACRONYM REGISTER NAME
0x4803 2000 0x4804 C000 0x481A C000 0x481A E000 GPIO_REVISION GPIO Revision
0x4803 2010 0x4804 C010 0x481A C010 0x481A E010 GPIO_SYSCONFIG System Configuration
0x4803 2020 0x4804 C020 0x481A C020 0x481A E020 GPIO_EOI End of Interrupt
0x4803 2024 0x4804 C024 0x481A C024 0x481A E024 GPIO_IRQSTATUS Status Raw for Interrupt 1
_RAW_0
0x4803 2028 0x4804 C028 0x481A C028 0x481A E028 GPIO_IRQSTATUS Status Raw for Interrupt 2
_RAW_1
0x4803 202C 0x4804 C02C 0x481A C02C 0x481A E02C GPIO_IRQSTATUS Status for Interrupt 1
_0
0x4803 2030 0x4804 C030 0x481A C030 0x481A E030 GPIO_IRQSTATUS Status for Interrupt 2
_1
0x4803 2034 0x4804 C034 0x481A C034 0x481A E034 GPIO_IRQSTATUS Enable Set for Interrupt 1
_SET_0

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Table 8-30. GPIO Registers (continued)

HEX ADDRESS
GPIO0 GPIO1 GPIO2 GPIO3 ACRONYM REGISTER NAME
0x4803 2038 0x4804 C038 0x481A C038 0x481A E038 GPIO_IRQSTATUS Enable Set for Interrupt 2
_SET_1
0x4803 203C 0x4804 C03C 0x481A C03C 0x481A E03C GPIO_IRQSTATUS Enable Clear for Interrupt 1
_CLR_0
0x4803 2040 0x4804 C040 0x481A C040 0x481A E040 GPIO_IRQSTATUS Enable Clear for Interrupt 2
_CLR_1
0x4803 2044 0x4804 C044 0x481A C044 0x481A E044 GPIO_IRQWAKEN_ Wakeup Enable for Interrupt
0 1
0x4803 2048 0x4804 C048 0x481A C048 0x481A E048 GPIO_IRQWAKEN_ Wakeup Enable for Interrupt
1 2
0x4803 2114 0x4804 C114 0x481A C114 0x481A E114 GPIO_SYSSTATUS System Status
0x4803 2130 0x4804 C130 0x481A C130 0x481A E130 GPIO_CTRL Module Control
0x4803 2134 0x4804 C134 0x481A C134 0x481A E134 GPIO_OE Output Enable
0x4803 2138 0x4804 C138 0x481A C138 0x481A E138 GPIO_DATAIN Data Input
0x4803 213C 0x4804 C13C 0x481A C13C 0x481A E13C GPIO_DATAOUT Data Output
0x4803 2140 0x4804 C140 0x481A C140 0x481A E140 GPIO_LEVELDETE Detect Low Level
CT0
0x4803 2144 0x4804 C144 0x481A C144 0x481A E144 GPIO_LEVELDETE Detect High Level
CT1
0x4803 2148 0x4804 C148 0x481A C148 0x481A E148 GPIO_RISINGDETE Detect Rising Edge
CT
0x4803 214C 0x4804 C14C 0x481A C14C 0x481A E14C GPIO_FALLINGDET Detect Falling Edge
ECT
0x4803 2150 0x4804 C150 0x481A C150 0x481A E150 GPIO_DEBOUNCE Debouncing Enable
NABLE
0x4803 2154 0x4804 C154 0x481A C154 0x481A E154 GPIO_DEBOUNCIN Debouncing Value
GTIME
0x4803 2190 0x4804 C190 0x481A C190 0x481A E190 GPIO_CLEARDATA Clear Data Output
OUT
0x4803 2194 0x4804 C194 0x481A C194 0x481A E194 GPIO_SETDATAOU Set Data Output
T

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8.7.2 GPIO Electrical Data/Timing

Table 8-31. Timing Requirements for GPIO Inputs

(see Figure 8-20)
OPP100/122/166
NO. UNIT
MIN MAX
1 tw(GPIH) Pulse duration, GPx[31:0] input high 12P (1) ns
(1)
2 tw(GPIL) Pulse duration, GPx[31:0] input low 12P ns
(1) P = Module clock.

Table 8-32. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs
(see Figure 8-20)
OPP100/122/166
NO. PARAMETER UNIT
MIN MAX
3 tw(GPOH) Pulse duration, GPx[31:0] output high 36P-8 (1) ns
(1)
4 tw(GPOL) Pulse duration, GPx[31:0] output low 36P-8 ns
(1) P = Module clock.

2
1
GPx[31:0]
input
4
3
GPx[31:0]
output

Figure 8-20. GPIO Port Timing

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8.8 General-Purpose Memory Controller (GPMC) and Error Location Module (ELM)
The GPMC is a device memory controller used to provide a glueless interface to external memory devices
such as NOR Flash, NAND Flash (with BCH and Hamming Error Code Detection for 8-bit or 16-bit NAND
Flash), SRAM, and Pseudo-SRAM. The GPMC includes flexible asynchronous protocol control for
interface to SRAM-like memories and custom logic (FPGA, CPLD, ASICs, etc.).
Other supported features include:
• 8-/16-bit wide multiplexed address/data bus
• 512 MBytes maximum addressing capability divided among up to eight chip selects
• Non-multiplexed address/data mode
• Pre-fetch and write posting engine associated with system DMA to get full performance from NAND
device with minimum impact on NOR/SRAM concurrent access.
The device also contains an Error Locator Module (ELM) which is used to extract error addresses from
syndrome polynomials generated using a BCH algorithm. Each of these polynomials gives a status of the
read operations for a 512 bytes block from a NAND flash and its associated BCH parity bits, plus
optionally spare area information. The ELM has the following features:
• 4-bit, 8-bit and 16-bit per 512byte block error location based on BCH algorithms
• Eight simultaneous processing contexts
• Page-based and continuous modes
• Interrupt generation on error location process completion
– When the full page has been processed in page mode
– For each syndrome polynomial in continuous mode

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8.8.1 GPMC and ELM Peripherals Register Descriptions

Table 8-33. GPMC Registers

HEX ADDRESS ACRONYM REGISTER NAME
0x5000 0000 GPMC_REVISION GPMC Revision
0x5000 0010 GPMC_SYSCONFIG System Configuration
0x5000 0014 GPMC_SYSSTATUS System Status
0x5000 0018 GPMC_IRQSTATUS Status for Interrupt
0x5000 001C GPMC_IRQENABLE Interrupt Enable
0x5000 0040 GPMC_TIMEOUT_CONTROL Timeout Counter Start Value
0x5000 0044 GPMC_ERR_ADDRESS Error Address
0x5000 0048 GPMC_ERR_TYPE Error Type
0x5000 0050 GPMC_CONFIG GPMC Global Configuration
0x5000 0054 GPMC_STATUS GPMC Global Status
(1)
0x5000 0060 + (0x0000 0030 * i) GPMC_CONFIG1_0 - Parameter Configuration 1_0-7
GPMC_CONFIG1_7
0x5000 0064 + (0x0000 0030 * i) (1) GPMC_CONFIG2_0 - Parameter Configuration 2_0-7
GPMC_CONFIG2_7
0x5000 0068 + (0x0000 0030 * i) (1) GPMC_CONFIG3_0 - Parameter Configuration 3_0-7
GPMC_CONFIG3_7
0x5000 006C + (0x0000 0030 * i) (1) GPMC_CONFIG4_0 - Parameter Configuration 4_0-7
GPMC_CONFIG4_7
0x5000 0070 + (0x0000 0030 * i) (1) GPMC_CONFIG5_0 - Parameter Configuration 5_0-7
GPMC_CONFIG5_7
0x5000 0074 + (0x0000 0030 * i) (1) GPMC_CONFIG6_0 - Parameter Configuration 6_0-7
GPMC_CONFIG6_7
0x5000 0078 + (0x0000 0030 * i) (1) GPMC_CONFIG7_0 - Parameter Configuration 7_0-7
GPMC_CONFIG7_7
0x5000 007C + (0x0000 0030 * i) (1) GPMC_NAND_COMMAND_0 - NAND Command 0-7
GPMC_NAND_COMMAND_7
0x5000 0080 + (0x0000 0030 * i) (1) GPMC_NAND_ADDRESS_0 - NAND Address 0-7
GPMC_NAND_ADDRESS_7
0x5000 0084 + (0x0000 0030 * i) (1) GPMC_NAND_DATA_0 - NAND Data 0-7
GPMC_NAND_DATA_7
0x5000 01E0 GPMC_PREFETCH_CONFIG1 Prefetch Configuration 1
0x5000 01E4 GPMC_PREFETCH_CONFIG2 Prefetch Configuration 2
0x5000 01EC GPMC_PREFETCH_CONTROL Prefetch Control
0x5000 01F0 (1) GPMC_PREFETCH_STATUS Prefetch Status
0x5000 01F4 GPMC_ECC_CONFIG ECC Configuration
0x5000 01F8 GPMC_ECC_CONTROL ECC Control
0x5000 01FC GPMC_ECC_SIZE_CONFIG ECC Size Configuration
0x5000 0200 + (0x0000 0004 * j) (2) GPMC_ECC0_RESULT - ECC0-8 Result
GPMC_ECC8_RESULT
0x5000 0240 + (0x0000 0010 * i) (1) GPMC_BCH_RESULT0_0 - BCH Result 0_0-7
GPMC_BCH_RESULT0_7
0x5000 0244 + (0x0000 0010 * i) (1) GPMC_BCH_RESULT1_0 - BCH Result 1_0-7
GPMC_BCH_RESULT1_7
0x5000 0248 + (0x0000 0010 * i) (1) GPMC_BCH_RESULT2_0 - BCH Result 2_0-7
GPMC_BCH_RESULT2_7
0x5000 024C + (0x0000 0010 * i) (1) GPMC_BCH_RESULT3_0 - BCH Result 3_0-7
GPMC_BCH_RESULT3_7
0x5000 0300 + (0x0000 0010 * i) (1) GPMC_BCH_RESULT4_0 - BCH Result 4_0-7
GPMC_BCH_RESULT4_7

(1) i = 0 to 7
(2) j = 0 to 8
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Table 8-33. GPMC Registers (continued)

HEX ADDRESS ACRONYM REGISTER NAME
0x5000 0304 + (0x0000 0010 * i) (1) GPMC_BCH_RESULT5_0 - BCH Result 5_0-7
GPMC_BCH_RESULT5_7
0x5000 0308 + (0x0000 0010 * i) (1) GPMC_BCH_RESULT6_0 - BCH Result 6_0-7
GPMC_BCH_RESULT6_7
0x5000 02D0 GPMC_BCH_SWDATA BCH Data

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8.8.2 GPMC Electrical Data/Timing

8.8.2.1 GPMC/NOR Flash Interface Synchronous Mode Timing (Non-Multiplexed and Multiplexed Modes)

Table 8-34. Timing Requirements for GPMC/NOR Flash Interface - Synchronous Mode
(see Figure 8-21, Figure 8-22, Figure 8-23 for Non-Multiplexed Modes)
(see Figure 8-24, Figure 8-25, Figure 8-26 for Multiplexed Modes)
OPP100/120/166
NO. UNIT
MIN MAX
13 tsu(DV-CLKH) Setup time, read GPMC_D[15:0] valid before GPMC_CLK high 4 ns
14 th(CLKH-DV) Hold time, read GPMC_D[15:0] valid after GPMC_CLK high 3 ns
22 tsu(WAITV-CLKH) Setup time, GPMC_WAIT[x] valid before GPMC_CLK high 4 ns
23 th(CLKH-WAITV) Hold time, GPMC_WAIT[x] valid after GPMC_CLK high 3 ns

Table 8-35. Switching Characteristics Over Recommended Operating Conditions for GPMC/NOR Flash
Interface - Synchronous Mode
(see Figure 8-21, Figure 8-22, Figure 8-23 for Non-Multiplexed Modes)
(see Figure 8-24, Figure 8-25, Figure 8-26 for Multiplexed Modes)
NO OPP100/120/166
PARAMETER UNIT
. MIN MAX
1 tc(CLK) Cycle time, output clock GPMC_CLK period 20 (1) ns
tw(CLKH) Pulse duration, output clock GPMC_CLK high 0.5P (2)
2 ns
tw(CLKL) Pulse duration, output clock GPMC_CLK low 0.5P (2)
3 td(CLKH-nCSV) Delay time, GPMC_CLK rising edge to GPMC_CS[x] transition F - 3 (3) F + 6 (3) ns
(4) (4)
4 td(CLKH-nCSIV) Delay time, GPMC_CLK rising edge to GPMC_CS[x] invalid E-3 E+6 ns
MUX0 and Non-Multi (5) (5)
B-6 B+6
Muxed pins
MUX1 for
Delay time, GPMC_A[27:0] address bus valid to B - 10 (5) B + 6 (5)
5 td(ADDV-CLK) GPMC_A[15:0] ns
GPMC_CLK first edge
MUX1/2 for (5) (5)
B - 10 B+6
GPMC_A[27:20]
GPMC_AD[15:0] B - 10 (5) B + 6 (5)
MUX0 and Non-Multi
-3
Muxed pins
MUX1 for
Delay time, GPMC_CLK rising edge to GPMC_A[27:0] GPMC_A[15:0] -6
6 td(CLKH-ADDIV) ns
GPMC address bus invalid
MUX1/2 for
-6
GPMC_A[27:20]
GPMC_AD[15:0] -6
7 td(nBEV-CLK) Delay time, GPMC_BE0_CLE, GPMC_BE1 valid to GPMC_CLK first edge B - 3 (5) B + 3 (5) ns

(1) Sync mode can operate at 50 MHz max.

(2) P = GPMC_CLK period.
(3) For nCS falling edge (CS activated):
• For GpmcFCLKDivider = 0:
F = 0.5 * CSExtraDelay * GPMC_FCLK
• For GpmcFCLKDivider = 1:
F = 0.5 * CSExtraDelay * GPMC_FCLK if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and CSOnTime are
even)
F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK otherwise
• For GpmcFCLKDivider = 2:
F = 0.5 * CSExtraDelay * GPMC_FCLK if ((CSOnTime – ClkActivationTime) is a multiple of 3)
F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime – ClkActivationTime – 1) is a multiple of 3)
F = (2 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime – ClkActivationTime – 2) is a multiple of 3)
(4) For single read: E = (CSRdOffTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst read: E = (CSRdOffTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst write: E = (CSWrOffTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(5) B = ClkActivationTime * GPMC_FCLK
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Table 8-35. Switching Characteristics Over Recommended Operating Conditions for GPMC/NOR Flash
Interface - Synchronous Mode (continued)
(see Figure 8-21, Figure 8-22, Figure 8-23 for Non-Multiplexed Modes)
(see Figure 8-24, Figure 8-25, Figure 8-26 for Multiplexed Modes)
NO OPP100/120/166
PARAMETER UNIT
. MIN MAX
8 td(CLKH-nBEIV) Delay time, GPMC_CLK rising edge to GPMC_BE0_CLE, GPMC_BE1 invalid D - 3 (6) D + 3 (6) ns
(7) (7)
9 td(CLKH-nADV) Delay time, GPMC_CLK rising edge to GPMC_ADV_ALE transition G-3 G+6 ns
10 td(CLKH-nADVIV) Delay time, GPMC_CLK rising edge to GPMC_ADV_ALE invalid D - 3 (6) D + 6 (6) ns
11 td(CLKH-nOE) Delay time, GPMC_CLK rising edge to GPMC_OE_RE transition H - 3 (8) H + 5 (8) ns

(6) For single read: D = (RdCycleTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For burst read: D = (RdCycleTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst write: D = (WrCycleTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(7) For ADV falling edge (ADV activated):
• Case GpmcFCLKDivider = 0:
G = 0.5 * ADVExtraDelay * GPMC_FCLK
• Case GpmcFCLKDivider = 1:
G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and ADVOnTime are
even)
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise
• Case GpmcFCLKDivider = 2:
G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVOnTime – ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVOnTime – ClkActivationTime – 1) is a multiple of 3)
G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVOnTime – ClkActivationTime – 2) is a multiple of 3)
For ADV rising edge (ADV deactivated) in Reading mode:
• Case GpmcFCLKDivider = 0:
G = 0.5 * ADVExtraDelay * GPMC_FCLK
• Case GpmcFCLKDivider = 1:
G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and
ADVRdOffTime are even)
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise
• Case GpmcFCLKDivider = 2:
G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime – 1) is a multiple of 3)
G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime – 2) is a multiple of 3)
For ADV rising edge (ADV deactivated) in Writing mode:
• Case GpmcFCLKDivider = 0:
G = 0.5 * ADVExtraDelay * GPMC_FCLK
• Case GpmcFCLKDivider = 1:
G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and
ADVWrOffTime are even)
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise
• Case GpmcFCLKDivider = 2:
G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime – 1) is a multiple of 3)
G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime – 2) is a multiple of 3)
(8) For OE falling edge (OE activated) / IO DIR rising edge (IN direction) :
• Case GpmcFCLKDivider = 0:
H = 0.5 * OEExtraDelay * GPMC_FCLK
• Case GpmcFCLKDivider = 1:
H = 0.5 * OEExtraDelay * GPMC_FCLK if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and OEOnTime are
even)
H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK otherwise
• Case GpmcFCLKDivider = 2:
H = 0.5 * OEExtraDelay * GPMC_FCLK if ((OEOnTime – ClkActivationTime) is a multiple of 3)
H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOnTime – ClkActivationTime – 1) is a multiple of 3)
H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOnTime – ClkActivationTime – 2) is a multiple of 3)
For OE rising edge (OE deactivated):
• Case GpmcFCLKDivider = 0:
H = 0.5 * OEExtraDelay * GPMC_FCLK
• Case GpmcFCLKDivider = 1:
H = 0.5 * OEExtraDelay * GPMC_FCLK if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and OEOffTime are
even)
H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK otherwise
• Case GpmcFCLKDivider = 2:
H = 0.5 * OEExtraDelay * GPMC_FCLK if ((OEOffTime – ClkActivationTime) is a multiple of 3)
H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOffTime – ClkActivationTime – 1) is a multiple of 3)
H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOffTime – ClkActivationTime – 2) is a multiple of 3)
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Table 8-35. Switching Characteristics Over Recommended Operating Conditions for GPMC/NOR Flash
Interface - Synchronous Mode (continued)
(see Figure 8-21, Figure 8-22, Figure 8-23 for Non-Multiplexed Modes)
(see Figure 8-24, Figure 8-25, Figure 8-26 for Multiplexed Modes)
NO OPP100/120/166
PARAMETER UNIT
. MIN MAX
12 td(CLKH-nOEIV) Delay time, GPMC_CLK rising edge to GPMC_OE_RE invalid E - 3 (4) E + 5 (4) ns
(9) (9)
15 td(CLKH-nWE) Delay time, GPMC_CLK rising edge to GPMC_WE transition I-3 I+6 ns
16 td(CLKH-Data) Delay time, GPMC_CLK rising edge to GPMC_D[15:0] data bus transition J - 3 (10) J + 3 (10) ns
18 td(CLKH-nBE) Delay time, GPMC_CLK rising edge to GPMC_BE0_CLE, GPMC_BE1 transition J - 3 (10) J + 3 (10) ns
(11)
19 tw(nCSV) Pulse duration, GPMC_CS[x] low A ns
20 tw(nBEV) Pulse duration, GPMC_BE0_CLE, GPMC_BE1 low C (12) ns
21 tw(nADVV) Pulse duration, GPMC_ADV_ALE low K (13) ns
(9) For WE falling edge (WE activated):
• Case GpmcFCLKDivider = 0:
I = 0.5 * WEExtraDelay * GPMC_FCLK
• Case GpmcFCLKDivider = 1:
I = 0.5 * WEExtraDelay * GPMC_FCLK if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and WEOnTime are
even)
I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK otherwise
• Case GpmcFCLKDivider = 2:
I = 0.5 * WEExtraDelay * GPMC_FCLK if ((WEOnTime – ClkActivationTime) is a multiple of 3)
I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOnTime – ClkActivationTime – 1) is a multiple of 3)
I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOnTime – ClkActivationTime – 2) is a multiple of 3)
For WE rising edge (WE deactivated):
• Case GpmcFCLKDivider = 0:
I = 0.5 * WEExtraDelay * GPMC_FCLK
• Case GpmcFCLKDivider = 1:
I = 0.5 * WEExtraDelay * GPMC_FCLK if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and WEOffTime are
even)
I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK otherwise
• Case GpmcFCLKDivider = 2:
I = 0.5 * WEExtraDelay * GPMC_FCLK if ((WEOffTime – ClkActivationTime) is a multiple of 3)
I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime – ClkActivationTime – 1) is a multiple of 3)
I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime – ClkActivationTime – 2) is a multiple of 3)
(10) J = GPMC_FCLK period.
(11) For single read: A = (CSRdOffTime - CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK period
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK period [n
= page burst access number]
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK period [n
= page burst access number]
(12) For single read: C = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK
For burst read: C = (RdCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK [n = page burst
access number]
For Burst write: C = (WrCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK [n = page burst
access number]
(13) For read: K = (ADVRdOffTime - ADVOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For write: K = (ADVWrOffTime - ADVOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK

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2
1 2
GPMC_CLK
3 4
19
GPMC_CS[x]
5
GPMC_A[27:0] Address
7 8
20
GPMC_BE1
7 8
20
GPMC_BE0_CLE
9 9
21 10
GPMC_ADV_ALE
11 12
GPMC_OE
14
13
GPMC_AD[15:0] D0
23 22
GPMC_WAIT[x]

Figure 8-21. GPMC Non-Multiplexed NOR Flash - Synchronous Single Read (GPMCFCLKDIVIDER = 0)

2
1
2
GPMC_CLK
3 4
19
GPMC_CS[x]

5
GPMC_A[27:0] Address
7 8
20
GPMC_BE1 Valid
7 8
20
GPMC_BE0_CLE Valid
9 9
21 10
GPMC_ADV_ALE
11 12
GPMC_OE
14
13 13
13 13
GPMC_D[15:0]
(Non-Multplexed Mode) D0 D1 D2 D3

23 22
GPMC_WAIT[x]

Figure 8-22. GPMC Non-Multiplexed NOR Flash - 14x16-bit Synchronous Burst Read
(GPMCFCLKDIVIDER = 0)

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2
2 1
GPMC_CLK
3 4
19
GPMC_CS[x]

5
GPMC_A[27:0] Address
7 18
18 18
GPMC_BE1
7 18
18 18
GPMC_BE0_CLE
9
9
21 10
GPMC_ADV_ALE
15
15
GPMC_WE
16
16 16 16
GPMC_D[15:0]
(Non-Multiplexed Mode) D0 D1 D2 D3

23 22
GPMC_WAIT[x]

Figure 8-23. GPMC Non-Multiplexed NOR Flash - Synchronous Burst Write (GPMCFCLKDIVIDER = 0)

2
1 2
GPMC_CLK
3 4
19
GPMC_CS[x]
5
GPMC_A[27:16] Address
7 8
20
GPMC_BE1
7 8
20
GPMC_BE0_CLE
9 9
21 10
GPMC_ADV_ALE
11 12
GPMC_OE
5 6 13
14
GPMC_D[15:0]
(Multiplexed Mode) Address (LSB) D0

23 22
GPMC_WAIT[x]

Figure 8-24. GPMC Multiplexed NOR Flash - Synchronous Single Read (GPMCFCLKDIVIDER = 0)

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2
1
2
GPMC_CLK
3 4
19
GPMC_CS[x]

5
GPMC_A[27:16] Address (MSB)
7 8
20
GPMC_BE1 Valid
7 8
20
GPMC_BE0_CLE Valid
9 9
21 10
GPMC_ADV_ALE
11 12
GPMC_OE
14
13 13
5 6 13 13
GPMC_D[15:0]
(Multplexed Mode) Address (LSB) D0 D1 D2 D3

23 22
GPMC_WAIT[x]

Figure 8-25. GPMC Multiplexed NOR Flash - 14x16-bit Synchronous Burst Read (GPMCFCLKDIVIDER = 0)

2
2 1
GPMC_CLK
3 4
19
GPMC_CS[x]

5 6
GPMC_A[27:16] Address (MSB)
7 18
18 18
GPMC_BE1
7 18
18 18
GPMC_BE0_CLE
9
9
21 10
GPMC_ADV_ALE
15
15
GPMC_WE
16
5 6,16 16 16
GPMC_D[15:0]
(Multiplexed Mode) Address (LSB) D0 D1 D2 D3

23 22
GPMC_WAIT[x]

Figure 8-26. GPMC Non-Multiplexed NOR Flash - Synchronous Burst Write (GPMCFCLKDIVIDER = 0)

8.8.2.2 GPMC/NOR Flash Interface Asynchronous Mode Timing (Non-Multiplexed and Multiplexed
Modes)

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Table 8-36. Timing Requirements for GPMC/NOR Flash Interface - Asynchronous Mode (1)
(see Figure 8-27, Figure 8-28 for Non-Multiplexed Mode )
(see Figure 8-29, Figure 8-31 for Multiplexed Mode)
OPP100/120/166
NO. UNIT
MIN MAX
6 tacc(DAT) Data maximum access time (GPMC_FCLK cycles) H (2) cycles
Page mode successive data maximum access time (GPMC_FCLK
21 tacc1-pgmode(DAT) P (3) cycles
cycles)
(2)
22 tacc2-pgmode(DAT) Page mode first data maximum access time (GPMC_FCLK cycles) H cycles
(1) The internal GPMC_FCLK is equal to SYSCLK6, and is nominally 100 MHz or 10 ns. For any additional constraints, see the Clocking
section of this document.
(2) H = AccessTime * (TimeParaGranularity + 1)
(3) P = PageBurstAccessTime * (TimeParaGranularity + 1).

Table 8-37. Switching Characteristics Over Recommended Operating Conditions for GPMC/NOR Flash
Interface - Asynchronous Mode
(see Figure 8-27, Figure 8-28, Figure 8-29, Figure 8-30 for Non-Multiplexed Modes)
(see Figure 8-31, Figure 8-32 for Multiplexed Modes)
NO OPP100/120/166
PARAMETER UNIT
. MIN MAX
1 tw(nBEV) Pulse duration, GPMC_BE0_CLE, GPMC_BE1 valid time N (1) ns
2 tw(nCSV) Pulse duration, GPMC_CS[x] low A (2) ns
4 td(nCSV-nADVIV) Delay time, GPMC_CS[x] valid to GPMC_NADV_ALE invalid B - 2 (3) B + 4 (3) ns
(4) (4)
5 td(nCSV-nOEIV) Delay time, GPMC_CS[x] valid to GPMC_OE_RE invalid (single read) C-2 C+4 ns
MUX0 and Non-Multi (5) (5)
J-2 J+4 ns
Muxed pins
Delay time, GPMC_A[27:0] address bus valid to MUX1 for
10 td(AV-nCSV) J - 2 (5) J + 4 (5) ns
GPMC_CS[x] valid GPMC_A[15:0]
MUX1/2 for
J - 2 (5) J + 4 (5) ns
GPMC_A[27:20]
11 td(nBEV-nCSV) Delay time, GPMC_BE0_CLE, GPMC_BE1 valid to GPMC_CS[x] valid J - 2 (5) J + 4 (5) ns
(6)
13 td(nCSV-nADVV) Delay time, GPMC_CS[x] valid to GPMC_ADV_ALE valid K-2 K + 4 (6) ns
14 td(nCSV-nOEV) Delay time, GPMC_CS[x] valid to GPMC_OE_RE valid L - 2 (7) L + 4 (7) ns

(1) For single read: N = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK

For single write: N = WrCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK
For burst read: N = (RdCycleTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst write: N = (WrCycleTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(2) For single read: A = (CSRdOffTime - CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For single write: A = (CSWrOffTime - CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(3) = B - nCS Max Delay + nADV Min Delay
For reading: B = ((ADVRdOffTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay - CSExtraDelay)) * GPMC_FCLK
For writing: B = ((ADVWrOffTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay - CSExtraDelay)) * GPMC_FCLK
(4) = C - nCS Max Delay + nOE Min Delay
C = ((OEOffTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay - CSExtraDelay)) * GPMC_FCLK
(5) = J - Address Max Delay + nCS Min Delay
J = (CSOnTime * (TimeParaGranularity + 1) + 0.5 * CSExtraDelay) * GPMC_FCLK
(6) = K - nCS Max Delay + nADV Min Delay
K = ((ADVOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay - CSExtraDelay)) * GPMC_FCLK
(7) = L - nCS Max Delay + nOE Min Delay
L = ((OEOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay - CSExtraDelay)) * GPMC_FCLK
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Table 8-37. Switching Characteristics Over Recommended Operating Conditions for GPMC/NOR Flash
Interface - Asynchronous Mode (continued)
(see Figure 8-27, Figure 8-28, Figure 8-29, Figure 8-30 for Non-Multiplexed Modes)
(see Figure 8-31, Figure 8-32 for Multiplexed Modes)
NO OPP100/120/166
PARAMETER UNIT
. MIN MAX
MUX0 and Non-Multi
G (8) ns
Muxed pins
MUX1 for
Pulse duration, GPMC_A[27:0] address bus invalid G (8) ns
17 tw(AIV) GPMC_A[15:0]
between 2 successive R/W accesses
MUX1/2 for
G (8) ns
GPMC_A[27:20]
(8)
GPMC_D[15:0] G ns
19 td(nCSV-nOEIV) Delay time, GPMC_CS[x] valid to GPMC_OE_RE invalid (burst read) I - 2 (9) I + 4 (9) ns
MUX0 and Non-Multi
D (10) ns
Muxed pins
MUX1 for
Pulse duration, GPMC_A[27:0] address bus valid: D (10) ns
21 tw(AV) GPMC_A[15:0]
second, third and fourth accesses
MUX1/2 for
D (10) ns
GPMC_A[27:20]
GPMC_D[15:0] D (10) ns
(11) (11)
26 td(nCSV-nWEV) Delay time, GPMC_CS[x] valid to GPMC_WE valid E-2 E+4 ns
28 td(nCSV-nWEIV) Delay time, GPMC_CS[x] valid to GPMC_WE invalid F - 2 (12) F + 4 (12) ns
29 td(nWEV-DV) Delay time, GPMC_WE valid to GPMC_D[15:0] data bus valid 2.0 ns
(5) (5)
30 td(DV-nCSV) Delay time, GPMC_D[15:0] data bus valid to GPMC_CS[x] valid J-2 J+4 ns
Delay time, GPMC_ADV_ALE valid to GPMC_D[15:0] MUX0 and Non-Multi
37 td(ADVV-AIV) 2.0 ns
address invalid Muxed pins
MUX0 and Non-Multi
2.0 ns
Muxed pins
MUX1 for
Delay time, GPMC_OE_RE valid to GPMC_D[15:0] 2.0 ns
38 td(nOEV-AIV) GPMC_A[15:0]
address/data busses phase end
MUX1/2 for
2.0 ns
GPMC_A[27:20]
GPMC_D[15:0] 2.0 ns
Delay time, GPMC_D[15:0] address valid to MUX0 and Non-Multi
39 td(AIV-ADVV) 2.0 ns
GPMC_ADV_ALE invalid Muxed pins
(8) G = Cycle2CycleDelay * GPMC_FCLK
(9) = I - nCS Max Delay + nOE Min Delay
I = ((OEOffTime + (n - 1) * PageBurstAccessTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay - CSExtraDelay)) *
GPMC_FCLK
(10) D = PageBurstAccessTime * (TimeParaGranularity + 1) * GPMC_FCLK
(11) = E - nCS Max Delay + nWE Min Delay
E = ((WEOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay - CSExtraDelay)) * GPMC_FCLK
(12) = F - nCS Max Delay + nWE Min Delay
F = ((WEOffTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay - CSExtraDelay)) * GPMC_FCLK

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GPMC_FCLK

GPMC_CLK
6
2
GPMC_CS[x]
10
GPMC_A[10:1] Valid Address
11
1
GPMC_BE1
11
1
GPMC_BE0_CLE
4
13
GPMC_ADV_ALE
5
14
GPMC_OE
GPMC_AD[15:0] Data In 0 Data In 0

GPMC_WAIT[x]

Figure 8-27. GPMC/Non-Multiplexed NOR Flash - Asynchronous Read - Single Word Timing

GPMC_FCLK

GPMC_CLK
6 6
2 2
GPMC_CS[x]
17
10 10
GPMC_A[10:1] Address 2 Address 1
11 11
1 1
GPMC_BE1
11 11
1 1
GPMC_BE0_CLE
4 4
13 13
GPMC_ADV_ALE
5 5
14 14
GPMC_OE
GPMC_AD[15:0]
Data Upper
GPMC_WAIT[x]

Figure 8-28. GPMC/Non-Multiplexed NOR Flash - Asynchronous Read - 32-Bit Access Timing

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GPMC_FCLK

GPMC_CLK
22 21
21 21
2
GPMC_CS[x]
10
GPMC_A[10:1] Add0 Add1 Add2 Add3 Add4
11
1
GPMC_BE1
11
1
GPMC_BE0_CLE
13
GPMC_ADV_ALE
19
14
GPMC_OE
GPMC_AD[15:0] D0 D1 D2 D3 D3

GPMC_WAIT[x]

Figure 8-29. GPMC/Non-Multiplexed Only NOR Flash - Asynchronous Read - Page Mode 4x16-Bit Timing

GPMC_FCLK

GPMC_CLK
2
GPMC_CS[x]
10
GPMC_A[10:1] Valid Address
11
1
GPMC_BE1
11
1
GPMC_BE0_CLE
4
13
GPMC_ADV_ALE
28
26
GPMC_WE
30
GPMC_AD[15:0] Data OUT

GPMC_WAIT[x]

Figure 8-30. GPMC/Non-Multiplexed NOR Flash - Asynchronous Write - Single Word Timing

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GPMC_FCLK

GPMC_CLK
2
6
GPMC_CS[x]

10
GPMC_A[26:17] Address (MSB)
11
1
GPMC_BE1
11
1
GPMC_BE0_CLE
13
4
GPMC_ADV_ALE
5
14
GPMC_OE

30 38
GPMC_A[16:1]
Address (LSB) Data IN
GPMC_AD[15:0]
Data IN

GPMC_WAIT[x]

Figure 8-31. GPMC/Multiplexed NOR Flash - Asynchronous Read - Single Word Timing

GPMC_FCLK

GPMC_CLK

2
GPMC_CS[x]

10
GPMC_A[26:17] Address (MSB)
11
1
GPMC_BE1
11
1
GPMC_BE0_CLE
13
4
GPMC_ADV_ALE
28
26
GPMC_WE

30 29
GPMCA[16:1]
Valid Address (LSB) Data OUT
GPMC_AD[15:0]

GPMC_WAIT[x]

Figure 8-32. GPMC/Multiplexed NOR Flash - Asynchronous Write - Single Word Timing

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8.8.2.3 GPMC/NAND Flash and ELM Interface Timing

Table 8-38. Timing Requirements for GPMC/NAND Flash Interface

(see Figure 8-35)
OPP100/120/166
NO. UNIT
MIN MAX
13 tacc(DAT) Data maximum access time (GPMC_FCLK cycles) J (1) cycles
(1) J = AccessTime * (TimeParaGranularity + 1)

Table 8-39. Switching Characteristics Over Recommended Operating Conditions for GPMC/NAND Flash
Interface
(see Figure 8-33, Figure 8-34, Figure 8-35, Figure 8-36)
OPP100/120/166
NO. PARAMETER UNIT
MIN MAX
1 tw(nWEV) Pulse duration, GPMC_WE valid time A (1) ns
(2)
2 td(nCSV-nWEV) Delay time, GPMC_CS[X] valid to GPMC_WE valid B-2 B + 4 (2) ns
3 td(CLEH-nWEV) Delay time, GPMC_BE0_CLE high to GPMC_WE valid C - 2 (3) C + 4 (3) ns
(4) (4)
4 td(nWEV-DV) Delay time, GPMC_D[15:0] valid to GPMC_WE valid D-2 D+4 ns
5 td(nWEIV-DIV) Delay time, GPMC_WE invalid to GPMC_AD[15:0] invalid E - 2 (5) E + 4 (5) ns
6 td(nWEIV-CLEIV) Delay time, GPMC_WE invalid to GPMC_BE0_CLE invalid F - 2 (6) F + 4 (6) ns
(7) (7)
7 td(nWEIV-nCSIV) Delay time, GPMC_WE invalid to GPMC_CS[X] invalid G-2 G+4 ns
8 td(ALEH-nWEV) Delay time, GPMC_ADV_ALE High to GPMC_WE valid C - 2 (3) C + 4 (3) ns
9 td(nWEIV-ALEIV) Delay time, GPMC_WE invalid to GPMC_ADV_ALE invalid F - 2 (6) F + 4 (6) ns
10 tc(nWE) Cycle time, write cycle time H (8) ns
(9) (9)
11 td(nCSV-nOEV) Delay time, GPMC_CS[X] valid to GPMC_OE_RE valid I-2 I+4 ns
12 tw(nOEV) Pulse duration, GPMC_OE_RE valid time K (10) ns
13 tc(nOE) Cycle time, read cycle time L (11) ns
(12) (12)
14 td(nOEIV-nCSIV) Delay time, GPMC_OE_RE invalid to GPMC_CS[X] invalid M-2 M+4 ns
(1) A = (WEOffTime - WEOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(2) = B + nWE Min Delay - nCS Max Delay
B = ((WEOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay - CSExtraDelay)) * GPMC_FCLK
(3) = C + nWE Min Delay - CLE Max Delay
C = ((WEOnTime - ADVOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay - ADVExtraDelay)) * GPMC_FCLK
(4) = D + nWE Min Delay - Data Max Delay
D = (WEOnTime * (TimeParaGranularity + 1) + 0.5 * WEExtraDelay ) * GPMC_FCLK
(5) =E + Data Min Delay - nWE Max Delay
E = ((WrCycleTime - WEOffTime) * (TimeParaGranularity + 1) - 0.5 * WEExtraDelay ) * GPMC_FCLK
(6) = F + CLE Min Delay - nWE Max Delay
F = ((ADVWrOffTime - WEOffTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay - WEExtraDelay )) * GPMC_FCLK
(7) =G + nCS Min Delay - nWE Max Delay
G = ((CSWrOffTime - WEOffTime) * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay - WEExtraDelay )) * GPMC_FCLK
(8) H = WrCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK
(9) = I + nOE Min Delay - nCS Max Delay
I = ((OEOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay - CSExtraDelay)) * GPMC_FCLK
(10) K = (OEOffTime - OEOnTime) * (1 + TimeParaGranularity) * GPMC_FCLK
(11) L = RdCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK
(12) =M + nCS Min Delay - nOE Max Delay
M = ((CSRdOffTime - OEOffTime) * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay - OEExtraDelay ))* GPMC_FCLK

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GPMC_FCLK
2
7
GPMC_CS[x]
3 6
GPMC_BE0_CLE

GPMC_ADV_ALE

GPMC_OE
1
GPMC_WE
4 5
GPMC_A[16:1]
GPMC_AD[15:0] Command

Figure 8-33. GPMC/NAND Flash - Command Latch Cycle Timing

GPMC_FCLK
2
7
GPMC_CS[x]

GPMC_BE0_CLE

8 9
GPMC_ADV_ALE

GPMC_OE 10
1
GPMC_WE
4 5
GPMC_A[16:1]
GPMC_AD[15:0] Address

Figure 8-34. GPMC/NAND Flash - Address Latch Cycle Timing

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GPMC_FCLK

13
16
11
GPMC_CS[x]

GPMC_BE0_CLE

GPMC_ADV_ALE
15
14
GPMC_OE
GPMC_A[16:1]
GPMC_AD[15:0] Data

GPMC_WAIT[x]

Figure 8-35. GPMC/NAND Flash - Data Read Cycle Timing

GPMC_FCLK

2 7
GPMC_CS[x]

GPMC_BE0_CLE

GPMC_ADV_ALE

GPMC_OE
10
1
GPMC_WE

4 5
GPMC_A[16:1]
GPMC_AD[15:0] Data

Figure 8-36. GPMC/NAND Flash - Data Write Cycle Timing

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8.9 High-Definition Multimedia Interface (HDMI)

The device includes an HDMI 1.3a-compliant transmitter for digital video and audio data to display
devices. The HDMI interface consists of a digital HDMI transmitter core with TMDS encoder, a core
wrapper with interface logic and control registers, and a transmit PHY, with the following features:
• Hot-plug detection
• Consumer electronics control (CEC) messages
• DVI 1.0 compliant (only RGB pixel format)
• CEA 861-D and VESA DMT formats
• Supports up to 165-MHz pixel clock
– 1920 x 1080p @75 Hz with 8-bit/component color depth
– 1600 x 1200 @60 Hz with 8-bit/component color depth
• Support for deep-color mode:
– 10-bit/component color depth up to 1080p @60 Hz (Max pixel clock = 148.5 MHz)
– 12-bit/component color depth up to 720p/1080i @60 Hz (Max pixel clock = 123.75 MHz)
• TMDS clock to the HDMI-PHY is up to 185.625 MHz
• Maximum supported pixel clock:
– 165 MHz for 8-bit color depth
– 148.5 MHz for 10-bit color depth
– 123.75 MHz for 12-bit color depth
• Uncompressed multichannel (up to eight channels) audio (L-PCM) support
• Master I2C interface for display data channel (DDC) connection
For more details on the HDMI, see the High-Definition Multimedia Interface (HDMI) chapter of the
TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual (Literature Number:
SPRUGZ8).

8.9.1 HDMI Design Guidelines

This section provides PCB design and layout guidelines for the HDMI interface. The design rules constrain
PCB trace length, PCB trace skew, signal integrity, cross-talk, and signal timing. Simulation and system
design work has been done to ensure the HDMI interface requirements are met.

8.9.1.1 HDMI Interface Schematic

The HDMI bus is separated into three main sections:
1. Transition Minimized Differential Signaling (TMDS) high-speed digital video interface
2. Display Data Channel (I2C bus for configuration and status exchange between two devices)
3. Consumer Electronics Control (optional) for remote control of connected devices.
The DDC and CEC are low-speed interfaces, so nothing special is required for PCB layout of these
signals. Their connection is shown in Figure 8-37, HDMI Interface High-Level Schematic.
The TMDS channels are high-speed differential pairs and, therefore, require the most care in layout.
Specifications for TMDS layout are below.
Figure 8-37 shows the HDMI interface schematic. The specific pin numbers can be obtained from Table 3-
15, HDMI Terminal Functions.

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Device HDMI Connector

HDMI_DP0 TD0
TD0+
Shld
HDMI_DN0 TD0-

HDMI_DP1 TD1
TD1+
Shld
HDMI_DN1 TD1-
TPD12S521 TD2
HDMI_DP2 or other TD2+ Shld
HDMI_DN2 ESD Protection TD2-
w/I2C-Level
HDMI_CLKP Translation TCLK TCLK
HDMI_CLKN TCLK+ Shld
HDMI_CEC CEC
3.3 V DDC
Gnd
(A)
Rpullup
HDMI_SDA SDA
HDMI_SCL SCL
HDMI_HPDET HPDET

A. 5K-10K Ω pullup resistors are required if not integrated in the ESD protection chip.

Figure 8-37. HDMI Interface High-Level Schematic

8.9.1.2 TMDS Routing

The TMDS signals are high-speed differential pairs. Care must be taken in the PCB layout of these signals
to ensure good signal integrity.
The TMDS differential signal traces must be routed to achieve 100 Ω (±10%) differential impedance and
60 Ω (±10%) single-ended impedance. Single-ended impedance control is required because differential
signals are extremely difficult to closely couple on PCBs and, therefore, single-ended impedance becomes
important.
These impedances are impacted by trace width, trace spacing, distance to reference planes, and dielectric
material. Verify with a PCB design tool that the trace geometry for both data signal pairs results in as
close to 60 Ω impedance traces as possible. For best accuracy, work with your PCB fabricator to ensure
this impedance is met.
In general, closely coupled differential signal traces are not an advantage on PCBs. When differential
signals are closely coupled, tight spacing and width control is necessary. Very small width and spacing
variations affect impedance dramatically, so tight impedance control can be more problematic to maintain
in production.
Loosely coupled PCB differential signals make impedance control much easier. Wider traces and spacing
make obstacle avoidance easier, and trace width variations do not affect impedance as much; therefore, it
is easier to maintain an accurate impedance over the length of the signal. The wider traces also show
reduced skin effect and, therefore, often result in better signal integrity.
Table 8-40 shows the routing specifications for the TMDS signals.

Table 8-40. TMDS Routing Specifications

PARAMETER MIN TYP MAX UNIT
Processor-to-HDMI header trace length 7000 Mils
Number of stubs allowed on TMDS traces 0 Stubs
TX/RX pair differential impedance 90 100 110 Ω
TX/RX single ended impedance 54 60 66 Ω
Number of vias on each TMDS trace 2 Vias (1)

(1) Vias must be used in pairs with their distance minimized.

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Table 8-40. TMDS Routing Specifications (continued)

PARAMETER MIN TYP MAX UNIT
TMDS differential pair to any other trace spacing 2*DS (2)
(2) DS = differential spacing of the HDMI traces.

8.9.1.3 DDC Signals

As shown in Figure 8-37, HDMI Interface High-Level Schematic, the DDC connects just like a standard
I2C bus. As such, resistor pullups must be used to pull up the open drain buffer signals unless they are
integrated into the ESD protection chip used. If used, these pullup resistors should be connected to a 3.3-
V supply.

8.9.1.4 HDMI ESD Protection Device (Required)

Interfaces that connect to a cable such as HDMI generally require more ESD protection than can be built
into the outputs of the processor. Therefore, this HDMI interface requires the use of an ESD protection
chip to provide adequate ESD protection and to translate I2C voltage levels from the 3.3 V supplied by the
device to the 5 volts required by the HDMI specification.
When selecting an ESD protection chip, choose the lowest capacitance ESD protection available to
minimize signal degradation. In no case should the ESD protection circuit capacitance be more than 5 pF.
TI manufactures devices that provide ESD protection for HDMI signals such as the TPD12S521. For more
information see the www.ti.com website.

8.9.1.5 PCB Stackup Specifications

Table 8-41 shows the stackup and feature sizes required for HDMI.

Table 8-41. HDMI PCB Stackup Specifications

PARAMETER MIN TYP MAX UNIT
PCB routing/plane layers 4 6 - Layers
Signal routing layers 2 3 - Layers
Number of ground plane cuts allowed within HDMI routing region - - 0 Cuts
Number of layers between HDMI routing region and reference ground plane - - 0 Layers
PCB trace width - 4 - Mils
PCB BGA escape via pad size - 20 - Mils
PCB BGA escape via hole size - 10 Mils
(1) (2)
Processor device BGA pad size 0.4 mm
(1) Non-solder mask defined pad.
(2) Per IPC-7351A BGA pad size guideline.

8.9.1.6 Grounding
Each TMDS channel has its own shield pin which should be grounded to provide a return current path for
the TMDS signal.

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8.10 High-Definition Video Processing Subsystem (HDVPSS)

The device High-Definition Video Processing Subsystem (HDVPSS) provides a video input interface for
external imaging peripherals (that is, image sensors, video decoders, and so on) and a video output
interface for display devices, such as analog SDTV displays, digital HDTV displays, digital LCD panels,
and so on. The HDVPSS includes HD and SD video encoders and an HDMI transmitter interface.
The device HDVPSS features include:
• Two display processing pipelines with de-interlacing, scaling, alpha blending, chroma keying, color
space conversion, flicker filtering, and pixel format conversion.
• HD/SD compositor features for PIP support.
• Format conversions (up to 1080p 60 Hz) include scan format conversion, scan rate conversion, aspect-
ratio conversion, and frame size conversion.
• Supports additional video processing capabilities by using the memory-to-memory feature of the
subsystem.
• Two parallel video processing pipelines support HD (up to 1080p60) and SD (NTSC/PAL)
simultaneous outputs.
– SD analog output with OSD with embedded timing codes (BT.656)
• S-video or Composite output
• 2-channel SD-DAC with 10-bit resolution
• Options available to support MacroVision and CGMS-A (contact local TI Sales rep for
information).
– Digital HDMI 1.3a-compliant transmitter (for details, see Section 8.9, High-Definition Multimedia
Interface (HDMI)).
– One digital video output supporting up to 30-bits @ 165 MHz
– One digital video output supporting up to 24-bits @ 165 MHz
• Two independently configurable external video input capture ports (up to 165 MHz).
– 16/24-bit HD digital video input or dual clock independent 8-bit SD inputs on each capture port.
– 8/16/24-bit digital video input
– 8-bit digital video input
– Embedded sync and external sync modes are supported for all input configurations (VIN1 Port B
supports embedded sync only).
– De-multiplexing of both pixel-to-pixel and line-to-line multiplexed streams, effectively supporting up
to 16 simultaneous SD inputs with a glueless interface to an external multiplexer such as the
TVP5158.
– Additional features include: programmable color space conversion, scaler and chroma
downsampler, ancillary VANC/VBI data capture (decoded by software).
• Graphics features:
– Three independently-generated graphics layers.
– Each supports full-screen resolution graphics in HD, SD or both.
– Up/down scaler optimized for graphics.
– Global and pixel-level alpha blending supported.
For more detailed information on specific features and registers, see the High Definition Video Processing
Subsystem chapter of the TMS320DM814x DaVinci Digital Media Processors Technical Reference
Manual (Literature Number: SPRUGZ8).

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8.10.1 HDVPSS Electrical Data/Timing

Table 8-42. Timing Requirements for HDVPSS Input

(see Figure 8-38 and Figure 8-39)
OPP100/120/166
NO. UNIT
MIN MAX
VIN[X]A_CLK
1 tc(CLK) Cycle time, VIN[x]A_CLK 6.06 (1) ns
2 tw(CLKH) Pulse duration, VIN[x]A_CLK high (45% of tc) 2.73 ns
3 tw(CLKH) Pulse duration, VIN[x]A_CLK low (45% of tc) 2.73 ns
tsu(DE-CLK)
tsu(VSYNC-CLK)
Input setup time, control valid to VIN[x]A_CLK high/low 3
4 tsu(FLD-CLK) ns
tsu(HSYNC-CLK)
tsu(D-CLK) Input setup time, data valid to VIN[x]A_CLK high/low 3
th(CLK-DE)
th(CLK-VSYNC)
Input hold time, control valid from VIN[x]A_CLK high/low 0.1
5 th(CLK-FLD) ns
th(CLK-HSYNC)
th(CLK-D) Input hold time, data valid from VIN[x]A_CLK high/low 0.1
VIN[x]B_CLK
1 tc(CLK) Cycle time, VIN[x]B_CLK 6.06 (1) ns
2 tw(CLKH) Pulse duration, VIN[x]B_CLK high (45% of tc) 2.73 ns
3 tw(CLKH) Pulse duration, VIN[x]B_CLK low (45% of tc) 2.73 ns
tsu(DE-CLK)
tsu(VSYNC-CLK)
Input setup time, control valid to VIN[x]B_CLK high/low 3
4 tsu(FLD-CLK) ns
tsu(HSYNC-CLK)
tsu(D-CLK) Input setup time, data valid to VIN[x]B_CLK high/low 3
th(CLK-DE)
th(CLK-VSYNC)
Input hold time, control valid from VIN[x]B_CLK high/low 0.1
5 th(CLK-FLD) ns
th(CLK-HSYNC)
th(CLK-D) Input hold time, data valid from VIN[x]B_CLK high/low 0.1
(1) For maximum frequency of 165 MHz.

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Table 8-43. Switching Characteristics Over Recommended Operating Conditions for HDVPSS Output
(see Figure 8-38 and Figure 8-40)
OPP100/120/166
NO. PARAMETER UNIT
MIN MAX
1 tc(CLK) Cycle time, VOUT[x]_CLK 6.06 (1) ns
2 tw(CLKH) Pulse duration, VOUT[x]_CLK high (45% of tc) 2.73 ns
3 tw(CLKL) Pulse duration, VOUT[x]_CLK low (45% of tc) 2.73 ns
7 tt(CLK) Transition time, VOUT[x]_CLK (10%-90%) 2.64 ns
td(CLK-AVID)
td(CLK-FLD)
Delay time, VOUT[x]_CLK low (falling) to control valid -1.2 2 ns
td(CLK-VSYNC)
td(CLK-HSYNC)
6 td(CLK-RCR)
td(CLK-GYYC) Delay time, VOUT[0]_CLK low (falling) to data valid
td(CLK-BCBC) -1.2 2 ns
td(CLK-YYC)
Delay time, VOUT[1]_CLK low (falling) to data valid
td(CLK-C)
(1) For maximum frequency of 165 MHz.

2 3
1
VIN[x]A_CLK/
VIN[x]B_CLK/
VOUT[x]_CLK
1 7
7

Figure 8-38. HDVPSS Clock Timing

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VIN[x]A_CLK/
VIN[x]B_CLK
(positive-edge clocking)

VIN[x]A_CLK/
VIN[x]B_CLK
(negative-edge clocking)

5
4
VIN[x]A/
VIN[x]B

Figure 8-39. HDVPSS Input Timing

VOUT[x]_CLK

VOUT[x]

Figure 8-40. HDVPSS Output Timing

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8.10.2 Video DAC Guidelines and Electrical Data/Timing

The analog video DAC outputs of the device can be operated in one of two modes: Normal mode and
TVOUT Bypass mode. In Normal mode, the device’s internal video amplifier is used. In TVOUT Bypass
mode, the internal video amplifier is bypassed and an external amplifier is required.
Figure 8-41 shows a typical circuit that permits connecting the analog video output from the device to
standard 75-Ω impedance video systems in Normal mode. Figure 8-42 shows a typical circuit that permits
connecting the analog video output from the device to standard 75-Ω impedance video systems in TVOUT
Bypass mode.

Reconstruction
TV_OUTx (A)
Filter
~9.5 MHz (B)
CAC
ROUT

TV_VFBx
A. Reconstruction Filter (optional)
B. AC coupling capacitor (optional)

Figure 8-41. TV Output (Normal Mode)

Reconstruction 75 Ω
(A) Amplifier
TV_VFBx Filter 3.7 V/V
~9.5 MHz (B)
CAC
RLOAD

A. Reconstruction Filter (optional). Note: An amplifier with an integrated reconstruction filter can alternatively be used
instead of a discrete reconstruction filter.
B. AC coupling capacitor (optional)

Figure 8-42. TV Output (TVOUT Bypass Mode)

During board design, the onboard traces and parasitics must be matched for the channel. The video DAC
output pins (TV_OUTx/TV_VFBx) are very high-frequency analog signals and must be routed with
extreme care. As a result, the paths of these signals must be as short as possible, and as isolated as
possible from other interfering signals. In TVOUT Bypass mode, the load resistor and amplifier/buffer
should be placed as close as possible to the TV_VFBx pins. Other layout guidelines include:
• Take special care to bypass the VDDA_VDAC_1P8 power supply pin with a capacitor. For more
information, see Section 7.2.9, Power-Supply Decoupling.
• In TVOUT Bypass mode, place the RLOAD resistor as close as possible to the Reconstruction Filter
and Amplifier. In addition, place the 75-Ω resistor as close as possible (< 0.5 ") to the Amplifier/buffer
output pin. To maintain a high-quality video signal, the onboard traces after the 75-Ω resistor should
have a characteristic impedance of 75 Ω (± 20%).
• In Normal mode, TV_VFBx is the most sensitive pin in the TV out system. The ROUT resistor should
be placed as close as possible to the device pins. To maintain a high-quality video signal, the onboard
traces leading to the TV_OUTx pin should have a characteristic impedance of 75 Ω (± 20%) starting
from the closest possible place to the device pin output.
• Minimize input trace lengths to the device to reduce parasitic capacitance.
• Include solid ground return paths.
• Match trace lengths as close as possible within a video format group (that is, Y and C for S-Video
output should match each other).

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For additional Video DAC Design guidelines, see the High Definition Video Processing Subsystem chapter
of the TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual (Literature
Number: SPRUGZ8).

Table 8-44. Static and Dynamic DAC Specifications

VDAC STATIC SPECIFICATIONS
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Reference Current Setting Resistor Normal Mode 4653 4700 4747 Ω
(RSET)
TVOUT Bypass Mode 9900 10000 10100 Ω
Output resistor between TV_OUTx Normal Mode 2673 2700 2727 Ω
and TV_VFBx pins (ROUT)
TVOUT Bypass Mode N/A
Load Resistor (RLOAD) Normal Mode 75-Ω Inside the Display
TVOUT Bypass Mode 1485 1500 1515 Ω
AC-Coupling Capacitor (Optional) Normal Mode 220 uF
[CAC]
TVOUT Bypass Mode See External Amplifier Specification
Total Capacitance from TV_OUTx Normal Mode 300 pF
to VSSA_VDAC_1P8
TVOUT Bypass Mode N/A
Resolution 10 Bits
Integral Non-Linearity (INL), Best Normal Mode -4 4 LSB
Fit
TVOUT Bypass Mode -1 1 LSB
Differential Non-Linearity (DNL) Normal Mode -2.5 2.5 LSB
TVOUT Bypass Mode -1 1 LSB
Full-Scale Output Voltage Normal Mode (RLOAD = 75 Ω) 1.3 V
TVOUT Bypass Mode (RLOAD =
0.7 V
1.5 kΩ)
Full-Scale Output Current Normal Mode N/A
TVOUT Bypass Mode 470 uA
Gain Error Normal Mode (Composite) and
-10 10 %FS
TVOUT Bypass Mode
Normal Mode (S-Video) -20 20 %FS
Gain Mismatch (Luma-to-Chroma) Normal Mode (Composite) N/A
Normal Mode (S-Video) -10 10 %
Output Impedance Looking into TV_OUTx nodes 75 Ω
VDAC DYNAMIC SPECIFICATIONS
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Output Update Rate (FCLK) 54 60 MHz
Signal Bandwidth 3 dB 6 MHz
Spurious-Free Dynamic Range
FCLK = 54 MHz, FOUT = 1 MHz 50 dBc
(SFDR) within bandwidth
Signal-to-Noise Ration (SNR) FCLK = 54 MHz, FOUT = 1 MHz 54 dB
Normal Mode, 100 mVpp @ 6
6
MHz on VDDA_VDAC_1P8
Power Supply Rejection (PSR) TVOUT Bypass Mode, 100 dB
mVpp @ 6 MHz on 20
VDDA_VDAC_1P8

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8.11 Inter-Integrated Circuit (I2C)

The device includes four inter-integrated circuit (I2C) modules which provide an interface to other devices
compliant with Philips Semiconductors Inter-IC bus (I2C-bus™) specification version 2.1. External
components attached to this 2-wire serial bus can transmit/receive 8-bit data to/from the device through
the I2C module. The I2C port does not support CBUS compatible devices.
The I2C port supports the following features:
• Compatible with Philips I2C Specification Revision 2.1 (January 2000)
• Standard and fast modes from 10 - 400 Kbps (no fail-safe I/O buffers)
• Noise filter to remove noise 50 ns or less
• Seven- and ten-bit device addressing modes
• Multimaster transmitter/slave receiver mode
• Multimaster receiver/slave transmitter mode
• Combined master transmit/receive and receive/transmit modes
• Two DMA channels, one interrupt line
• Built-in FIFO (32 byte) for buffered read or write.
For more detailed information on the I2C peripheral, see the Inter-Integrated Circuit (I2C) Controller
Module chapter of the TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual
(Literature Number: SPRUGZ8).

8.11.1 I2C Peripheral Register Descriptions

Table 8-45. I2C Registers

HEX ADDRESS
I2C0 I2C1 I2C2 I2C3 ACRONYM REGISTER NAME
0x4802 8000 0x4802 A000 0x4819 C000 0x4819 E000 I2C_REVNB_LO Module Revision (LOW BYTES)
0x4802 8004 0x4802 A004 0x4819 C004 0x4819 E004 I2C_REVNB_HI Module Revision (HIGH BYTES)
0x4802 8010 0x4802 A010 0x4819 C010 0x4819 E010 I2C_SYSC System configuration
0x4802 8020 0x4802 A020 0x4819 C020 0x4819 E020 I2C_EOI I2C End of Interrupt
0x4802 8024 0x4802 A024 0x4819 C024 0x4819 E024 I2C_IRQSTATUS_RA I2C Status Raw
W
0x4802 8028 0x4802 A028 0x4819 C028 0x4819 E028 I2C_IRQSTATUS I2C Status
0x4802 802C 0x4802 A02C 0x4819 C02C 0x4819 E02C I2C_IRQENABLE_SET I2C Interrupt Enable Set
0x4802 8030 0x4802 A030 0x4819 C030 0x4819 E030 I2C_IRQENABLE_CLR I2C Interrupt Enable Clear
0x4802 8034 0x4802 A034 0x4819 C034 0x4819 E034 I2C_WE I2C Wakeup Enable
0x4802 8038 0x4802 A038 0x4819 C038 0x4819 E038 I2C_DMARXENABLE_ Receive DMA Enable Set
SET
0x4802 803C 0x4802 A03C 0x4819 C03C 0x4819 E03C I2C_DMATXENABLE_ Transmit DMA Enable Set
SET
0x4802 8040 0x4802 A040 0x4819 C040 0x4819 E040 I2C_DMARXENABLE_ Receive DMA Enable Clear
CLR
0x4802 8044 0x4802 A044 0x4819 C044 0x4819 E044 I2C_DMATXENABLE_ Transmit DMA Enable Clear
CLR
0x4802 8048 0x4802 A048 0x4819 C048 0x4819 E048 I2C_DMARXWAKE_EN Receive DMA Wakeup
0x4802 804C 0x4802 A04C 0x4819 C04C 0x4819 E04C I2C_DMATXWAKE_EN Transmit DMA Wakeup
0x4802 8090 0x4802 A090 0x4819 C090 0x4819 E090 I2C_SYSS System Status
0x4802 8094 0x4802 A094 0x4819 C094 0x4819 E094 I2C_BUF Buffer Configuration
0x4802 8098 0x4802 A098 0x4819 C098 0x4819 E098 I2C_CNT Data Counter
0x4802 809C 0x4802 A09C 0x4819 C09C 0x4819 E09C I2C_DATA Data Access
0x4802 80A4 0x4802 A0A4 0x4819 C0A4 0x4819 E0A4 I2C_CON I2C Configuration
0x4802 80A8 0x4802 A0A8 0x4819 C0A8 0x4819 E0A8 I2C_OA I2C Own Address

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Table 8-45. I2C Registers (continued)

HEX ADDRESS
I2C0 I2C1 I2C2 I2C3 ACRONYM REGISTER NAME
0x4802 80AC 0x4802 A0AC 0x4819 C0AC 0x4819 E0AC I2C_SA I2C Slave Address
0x4802 80B0 0x4802 A0B0 0x4819 C0B0 0x4819 E0B0 I2C_PSC I2C Clock Prescaler
0x4802 80B4 0x4802 A0B4 0x4819 C0B4 0x4819 E0B4 I2C_SCLL I2C SCL Low Time
0x4802 80B8 0x4802 A0B8 0x4819 C0B8 0x4819 E0B8 I2C_SCLH I2C SCL High Time
0x4802 80BC 0x4802 A0BC 0x4819 C0BC 0x4819 E0BC I2C_SYSTEST System Test
0x4802 80C0 0x4802 A0C0 0x4819 C0C0 0x4819 E0C0 I2C_BUFSTAT I2C Buffer Status
0x4802 80C4 0x4802 A0C4 0x4819 C0C4 0x4819 E0C4 I2C_OA1 I2C Own Address 1
0x4802 80C8 0x4802 A0C8 0x4819 C0C8 0x4819 E0C8 I2C_OA2 I2C Own Address 2
0x4802 80CC 0x4802 A0CC 0x4819 C0CC 0x4819 E0CC I2C_OA3 I2C Own Address 3
0x4802 80D0 0x4802 A0D0 0x4819 C0D0 0x4819 E0D0 I2C_ACTOA Active Own Address
0x4802 80D4 0x4802 A0D4 0x4819 C0D4 0x4819 E0D4 I2C_SBLOCK I2C Clock Blocking Enable

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8.11.2 I2C Electrical Data/Timing

Table 8-46. Timing Requirements for I2C Input Timings (1)

(see Figure 8-43)
OPP100/120/166
STANDARD
NO. FAST MODE UNIT
MODE
MIN MAX MIN MAX
1 tc(SCL) Cycle time, SCL 10 2.5 µs
Setup time, SCL high before SDA low (for a repeated START
2 tsu(SCLH-SDAL) 4.7 0.6 µs
condition)
Hold time, SCL low after SDA low (for a START and a
3 th(SDAL-SCLL) 4 0.6 µs
repeated START condition)
4 tw(SCLL) Pulse duration, SCL low 4.7 1.3 µs
5 tw(SCLH) Pulse duration, SCL high 4 0.6 µs
(2)
6 tsu(SDAV-SCLH) Setup time, SDA valid before SCL high 250 100 ns
7 th(SCLL-SDAV) Hold time, SDA valid after SCL low 0 (3) 3.45 (4) 0 (3) 0.9 (4) µs
Pulse duration, SDA high between STOP and START
8 tw(SDAH) 4.7 1.3 µs
conditions
(5)
9 tr(SDA) Rise time, SDA 1000 20 + 0.1Cb 300 ns
(5)
10 tr(SCL) Rise time, SCL 1000 20 + 0.1Cb 300 ns
(5)
11 tf(SDA) Fall time, SDA 300 20 + 0.1Cb 300 ns
(5)
12 tf(SCL) Fall time, SCL 300 20 + 0.1Cb 300 ns
13 tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition) 4 0.6 µs
14 tw(SP) Pulse duration, spike (must be suppressed) 0 50 ns
(5)
15 Cb Capacitive load for each bus line 400 400 pF
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(2) A Fast-mode I2C-bus™ device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH)≥ 250 ns must then be
met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH)= 1000 + 250 = 1250 ns
(according to the Standard-mode I2C-Bus Specification) before the SCL line is released.
(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(4) The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.
(5) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.

11 9

I2C[x]_SDA

8 6 14
4
13
10 5

I2C[x]_SCL

1 12
3
7 2
3

Stop Start Repeated Stop

Start

Figure 8-43. I2C Receive Timing

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Table 8-47. Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
(see Figure 8-44)
OPP100/120/166
STANDARD
NO. PARAMETER FAST MODE UNIT
MODE
MIN MAX MIN MAX
16 tc(SCL) Cycle time, SCL 10 2.5 µs
Setup time, SCL high before SDA low (for a repeated START
17 tsu(SCLH-SDAL) 4.7 0.6 µs
condition)
Hold time, SCL low after SDA low (for a START and a repeated
18 th(SDAL-SCLL) 4 0.6 µs
START condition)
19 tw(SCLL) Pulse duration, SCL low 4.7 1.3 µs
20 tw(SCLH) Pulse duration, SCL high 4 0.6 µs
21 tsu(SDAV-SCLH) Setup time, SDA valid before SCL high 250 100 ns
22 th(SCLL-SDAV) Hold time, SDA valid after SCL low (for I2C bus devices) 0 3.45 0 0.9 µs
Pulse duration, SDA high between STOP and START
23 tw(SDAH) 4.7 1.3 µs
conditions
20 + 0.1Cb
24 tr(SDA) Rise time, SDA 1000 (1) 300 ns

20 + 0.1Cb
25 tr(SCL) Rise time, SCL 1000 (1) 300 ns

20 + 0.1Cb
26 tf(SDA) Fall time, SDA 300 (1) 300 ns

20 + 0.1Cb
27 tf(SCL) Fall time, SCL 300 (1) 300 ns

28 tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition) 4 0.6 µs
29 Cp Capacitance for each I2C pin 10 10 pF
(1) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.

26 24

I2C[x]_SDA

23 21
19
28
25 20

I2C[x]_SCL

16 27
18
22
17
18

Stop Start Repeated Stop

Start

Figure 8-44. I2C Transmit Timing

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8.12 Imaging Subsystem (ISS)

The device Imaging Subsystem captures and processes pixel data from external image and video inputs.
The inputs can be connected to the Image Processing block through the Parallel Camera Interface
(CAM). . In addition, a Timing control module provides flash strobe and mechanical shutter interfaces. The
features of each component of the ISS are described below.
• Parallel Camera (CAM) interface features:
– Input format
• Bayer pattern Raw (up to 16bit) or YCbCr 422 (8bit or 16bit) data.
• ITU-R BT.656/1120 standard format
– Generates HD/VD timing signals and field ID to an external timing generator, or can synchronize to
the external timing generator.
– Support for progressive and interlaced sensors (hardware support for up to 2 fields and firmware
supports for higher number of fields, typically 3-, 4-, and 5-field sensors.
• Image Sensor Interface (ISIF) features:
– Support for up to 32K pixels (image size) in both the horizontal and vertical direction
– Color space conversion for non-Bayer pattern Raw data
– Digital black clamping with Horizontal/Vertical offset drift compensation
– Vertical Line defect correction based on a lookup table
– Color-dependent gain control and black level offset control
– Ability to control output to the DDR2/DDR3 via an external write enable signal
– Down sampling via programmable culling patterns
– A-law/DPCM compression
– Generating 16-, 12- or 8-bit output to memory
• Two independent Resizers
– Providing two different sizes of outputs simultaneously on one input
– Maximum line width is 5376 and 2336, respectively
– YUV422 to YUV420 conversion
– Data output format: RGB565, ARGB888, YUV422 co sited and YUV4:2:0 planar
– Resizer Ratio: x1/4096 approximately x20
– Input from memory
• Timing control module features:
– STROBE signal for flash pre-strobe and flash strobe
– SHUTTER signal for mechanical shutter control
– Global reset control
For more detailed information on the ISS, see the ISS Overview section, the ISS Interfaces section, and
the ISS ISP section of the Watchdog Timer chapter of the TMS320DM814x DaVinci Digital Media
Processors Technical Reference Manual (Literature Number: SPRUGZ8).

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8.12.1 ISSCAM Electrical Data/Timing

Table 8-48. Timing Requirements for ISSCAM (see Figure 8-45)

OPP100/120/166
NO. UNIT
MIN NOM MAX
1 tc(PCLK) Cycle time, PCLK 6.06 ns
2 tw(PCLKH) Pulse duration, PCLK high 2.73 ns
3 tw(PCLKL) Pulse duration, PCLK low 2.73 ns
4 tt(PCLK) Transition time, PCLK 2.64 ns
tsu(DATA-PCLK) 3.11 ns
tsu(DE-PCLK) 3.11 ns
5 tsu(VS-PCLK) Input setup time, Data/Control valid before PCLK high/low 3.11 ns
tsu(HS-PCLK) 3.11 ns
tsu(FLD-PCLK) 3.11 ns
th(PCLK-DATA) -0.15 ns
th(PCLK-DE) -0.15 ns
6 th(PCLK-VS) Input hold time, Data/Control valid after PCLK high/low -0.15 ns
th(PCLK-HS) -0.15 ns
th(PCLK-FLD) -0.15 ns

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Table 8-49. Switching Characteristics Over Recommended Operating Conditions for ISSCAM (see
Figure 8-45)
OPP100/120/166
NO. PARAMETER UNIT
MIN MAX
15 td(PCLK-FLD) Delay time, PCLK rising/falling clock edge to Control valid 3 11.5 ns
16 td(PCLK-VS) Delay time, PCLK rising/falling clock edge to Control valid 3 11.5 ns
17 td(PCLK-HS) Delay time, PCLK rising/falling clock edge to Control valid 3 11.5 ns
18 td(PCLK-STROBE) Delay time, PCLK rising/falling clock edge to Control valid 3 11.5 ns
19 td(PCLK-SHUTTER) Delay time, PCLK rising/falling clock edge to Control valid 3 11.5 ns

PCLK
(negative edge clocking)

1 4

3
PCLK
(positive edge clocking)
2
4

Data/Control input

5
6

Data/Control output
7

Figure 8-45. ISSCAM Timings

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8.13 DDR2/DDR3 Memory Controller

The device has a dedicated interface to DDR3 and DDR2 SDRAM. The device dedicated interface also
supports JEDEC standard compliant DDR2 and DDR3 SDRAM devices with the following features:
• 16-bit or 32-bit data path to external SDRAM memory
• Memory device capacity: 64Mb, 128Mb, 256Mb, 512Mb, 1Gb, 2Gb, and 4Gb devices
• Support for two independent chip selects, with their corresponding register sets, and independent page
tracking
• Two interfaces with associated DDR2/DDR3 PHYs
• Dynamic memory manager allows for interleaving of data between the two DDR interfaces.
For details on the DDR2/DDR3 Memory Controller, see the DDR2/DDR3 Memory Controller chapter of the
TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual (Literature Number:
SPRUGZ8).

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8.13.1 DDR2/3 Memory Controller Register Descriptions

Table 8-50. DDR2/3 Memory Controller Registers

DDR0 HEX ADDRESS DDR1 HEX ADDRESS ACRONYM REGISTER NAME
0x4C00 0004 0x4D00 0004 SDRSTAT SDRAM Status Register
0x4C00 0008 0x4D00 0008 SDRCR SDRAM Configuration Register
0x4C00 000C 0x4D00 000C SDRCR2 SDRAM Configuration Register 2
0x4C00 0010 0x4D00 0010 SDRRCR SDRAM Refresh Control Register
0x4C00 0014 0x4D00 0014 SDRRCSR SDRAM Refresh Control Shadow Register
0x4C00 0018 0x4D00 0018 SDRTIM1 SDRAM Timing 1 Register
0x4C00 001C 0x4D00 001C SDRTIM1SR SDRAM Timing 1 Shadow Register
0x4C00 0020 0x4D00 0020 SDRTIM2 SDRAM Timing 2 Register
0x4C00 0024 0x4D00 0024 SDRTIM2SR SDRAM Timing 2 Shadow Register
0x4C00 0028 0x4D00 0028 SDRTIM3 SDRAM Timing 3 Register
0x4C00 002C 0x4D00 002C SDRTIM3SR SDRAM Timing 3 Shadow Register
0x4C00 0038 0x4D00 0038 PMCR Power Management Control Register
0x4C00 003C 0x4D00 003C PMCSR Power Management Control Shadow Register
0x4C00 0054 0x4D00 0054 PBBPR Peripheral Bus Burst Priority Register
0x4C00 00A0 0x4D00 00A0 EOI End of Interrupt Register
0x4C00 00A4 0x4D00 00A4 SOIRSR System OCP Interrupt Raw Status Register
0x4C00 00AC 0x4D00 00AC SOISR System OCP Interrupt Status Register
0x4C00 00B4 0x4D00 00B4 SOIESR System OCP Interrupt Enable Set Register
0x4C00 00BC 0x4D00 00BC SOIECR System OCP Interrupt Enable Clear Register
0x4C00 00C8 0x4D00 00C8 ZQCR SDRAM Output Impedance Calibration Configuration
Register
0x4C00 00D4 0x4D00 00D4 RDWR_LVL_RMP_WIN Read-Write Leveling Ramp Window Register
0x4C00 00D8 0x4D00 00D8 RDWR_LVL_RMP_CTRL Read-Write Leveling Ramp Control Register
0x4C00 00DC 0x4D00 00DC RWLCR Read-Write Leveling Control Register
0x4C00 00E4 0x4D00 00E4 DDRPHYCR DDR PHY Control Register
0x4C00 00E8 0x4D00 00E8 DDRPHYCSR DDR PHY Control Shadow Register
0x4C00 0100 0x4D00 0100 PRI_COS_MAP Priority to Class of Service Mapping Register
0x4C00 0104 0x4D00 0104 CONNID_COS_1_MAP Connection ID to Class of Service 1 Mapping Register
0x4C00 0108 0x4D00 0108 CONNID_COS_2_MAP Connection ID to Class of Service 2 Mapping Register
0x4C00 0120 0x4D00 0120 RD_WR_EXEC_THRSH Read Write Execution Threshold Register

8.13.2 DDR2/DDR3 PHY Register Descriptions

Table 8-51. DDR2/DDR3 PHY Registers

DDR0 HEX DDR1 HEX
ACRONYM REGISTER NAME
ADDRESS ADDRESS
0x47C0_C41C 0x47C0_C81C CMD0_REG_PHY_CTRL_SLAVE_RATIO_0 DDR PHY Command 0
Address/Command Slave Ratio Register
0x47C0_C428 0x47C0_C828 CMD0_REG_PHY_DLL_LOCK_DIFF_0 DDR PHY Command 0
Address/Command DLL Lock Difference
Register
0x47C0_C42C 0x47C0_C82C CMD0_REG_PHY_INVERT_CLKOUT_0 DDR PHY Command 0 Invert Clockout
Selection Register
0x47C0_C450 0x47C0_C850 CMD1_REG_PHY_CTRL_SLAVE_RATIO_0 DDR PHY Command 1
Address/Command Slave Ratio Register
0x47C0_C45C 0x47C0_C85C CMD1_REG_PHY_DLL_LOCK_DIFF_0 DDR PHY Command 1
Address/Command DLL Lock Difference
Register

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Table 8-51. DDR2/DDR3 PHY Registers (continued)

DDR0 HEX DDR1 HEX
ACRONYM REGISTER NAME
ADDRESS ADDRESS
0x47C0_C460 0x47C0_C860 CMD1_REG_PHY_INVERT_CLKOUT_0 DDR PHY Command 1 Invert Clockout
Selection Register
0x47C0_C484 0x47C0_C884 CMD2_REG_PHY_CTRL_SLAVE_RATIO_0 DDR PHY Command 2
Address/Command Slave Ratio Register
0x47C0_C490 0x47C0_C890 CMD2_REG_PHY_DLL_LOCK_DIFF_0 DDR PHY Command 2
Address/Command DLL Lock Difference
Register
0x47C0_C494 0x47C0_C894 CMD2_REG_PHY_INVERT_CLKOUT_0 DDR PHY Command 2 Invert Clockout
Selection Register
0x47C0_C4C8 0x47C0_C8C8 DATA0_REG_PHY_RD_DQS_SLAVE_RATIO _0 DDR PHY Data Macro 0 Read DQS
Slave Ratio Register
0x47C0_C4DC 0x47C0_C8DC DATA0_REG_PHY_WR_DQS_SLAVE_RATI O_0 DDR PHY Data Macro 0 Write DQS
Slave Ratio Register
0x47C0_C4F0 0x47C0_C8F0 DATA0_REG_PHY_WRLVL_INIT_RATIO_0 DDR PHY Data Macro 0 Write Leveling
Init Ratio Register
0x47C0_C4F8 0x47C0_C8F8 DATA0_REG_PHY_WRLVL_INIT_MODE_0 DDR PHY Data Macro 0 Write Leveling
Init Mode Ratio Selection Register
0x47C0_C4FC 0x47C0_C8FC DATA0_REG_PHY_GATELVL_INIT_RATIO_0 DDR PHY Data Macro 0 DQS Gate
Training Init Ratio Register
0x47C0_C504 0x47C0_C904 DATA0_REG_PHY_GATELVL_INIT_MODE_0 DDR PHY Data Macro 0 DQS Gate
Training Init Mode Ratio Selection
Register
0x47C0_C508 0x47C0_C908 DATA0_REG_PHY_FIFO_WE_SLAVE_RATI O_0 DDR PHY Data Macro 0 DQS Gate
Slave Ratio Register
0x47C0_C51C 0x47C0_C91C DATA0_REG_PHY_DQ_OFFSET_0 Offset Value From DQS to DQ for Data
Macro 0
0x47C0_C520 0x47C0_C920 DATA0_REG_PHY_WR_DATA_SLAVE_RATI O_0 DDR PHY Data Macro 0 Write Data
Slave Ratio Register
0x47C0_C534 0x47C0_C934 DATA0_REG_PHY_USE_RANK0_DELAYS DDR PHY Data Macro 0 Delay Selection
Register
0x47C0_C538 0x47C0_C938 DATA0_REG_PHY_DLL_LOCK_DIFF_0 DDR PHY Data Macro 0 DLL Lock
Difference Register
0x47C0_C56C 0x47C0_C96C DATA1_REG_PHY_RD_DQS_SLAVE_RATIO _0 DDR PHY Data Macro 1 Read DQS
Slave Ratio Register
0x47C0_C580 0x47C0_C980 DATA1_REG_PHY_WR_DQS_SLAVE_RATI O_0 DDR PHY Data Macro 1 Write DQS
Slave Ratio Register
0x47C0_C594 0x47C0_C994 DATA1_REG_PHY_WRLVL_INIT_RATIO_0 DDR PHY Data Macro 1 Write Leveling
Init Ratio Register
0x47C0_C59C 0x47C0_C99C DATA1_REG_PHY_WRLVL_INIT_MODE_0 DDR PHY Data Macro 1 Write Leveling
Init Mode Ratio Selection Register
0x47C0_C5A0 0x47C0_C9A0 DATA1_REG_PHY_GATELVL_INIT_RATIO_0 DDR PHY Data Macro 1 DQS Gate
Training Init Ratio Register
0x47C0_C5A8 0x47C0_C9A8 DATA1_REG_PHY_GATELVL_INIT_MODE_0 DDR PHY Data Macro 1 DQS Gate
Training Init Mode Ratio Selection
Register
0x47C0_C5AC 0x47C0_C9AC DATA1_REG_PHY_FIFO_WE_SLAVE_RATI O_0 DDR PHY Data Macro 1 DQS Gate
Slave Ratio Register
0x47C0_C5C0 0x47C0_C9C0 DATA1_REG_PHY_DQ_OFFSET_1 Offset Value From DQS to DQ for Data
Macro 1
0x47C0_C5C4 0x47C0_C9C4 DATA1_REG_PHY_WR_DATA_SLAVE_RATI O_0 DDR PHY Data Macro 1 Write Data
Slave Ratio Register
0x47C0_C5D8 0x47C0_C9D8 DATA1_REG_PHY_USE_RANK0_DELAYS DDR PHY Data Macro 1 Delay Selection
Register
0x47C0_C5DC 0x47C0_C9DC DATA1_REG_PHY_DLL_LOCK_DIFF_0 DDR PHY Data Macro 1 DLL Lock
Difference Register

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Table 8-51. DDR2/DDR3 PHY Registers (continued)

DDR0 HEX DDR1 HEX
ACRONYM REGISTER NAME
ADDRESS ADDRESS
0x47C0_C610 0x47C0_CA10 DATA2_REG_PHY_RD_DQS_SLAVE_RATIO _0 DDR PHY Data Macro 2 Read DQS
Slave Ratio Register
0x47C0_C624 0x47C0_CA24 DATA2_REG_PHY_WR_DQS_SLAVE_RATI O_0 DDR PHY Data Macro 2 Write DQS
Slave Ratio Register
0x47C0_C638 0x47C0_CA38 DATA2_REG_PHY_WRLVL_INIT_RATIO_0 DDR PHY Data Macro 2 Write Leveling
Init Ratio Register
0x47C0_C640 0x47C0_CA40 DATA2_REG_PHY_WRLVL_INIT_MODE_0 DDR PHY Data Macro 2 Write Leveling
Init Mode Ratio Selection Register
0x47C0_C644 0x47C0_CA44 DATA2_REG_PHY_GATELVL_INIT_RATIO_0 DDR PHY Data Macro 2 DQS Gate
Training Init Ratio Register
0x47C0_C64C 0x47C0_CA4C DATA2_REG_PHY_GATELVL_INIT_MODE_0 DDR PHY Data Macro 2 DQS Gate
Training Init Mode Ratio Selection
Register
0x47C0_C650 0x47C0_CA50 DATA2_REG_PHY_FIFO_WE_SLAVE_RATI O_0 DDR PHY Data Macro 2 DQS Gate
Slave Ratio Register
0x47C0_C664 0x47C0_CA64 DATA2_REG_PHY_DQ_OFFSET_2 Offset value from DQS to DQ for Data
Macro 2
0x47C0_C668 0x47C0_CA68 DATA2_REG_PHY_WR_DATA_SLAVE_RATI O_0 DDR PHY Data Macro 2 Write Data
Slave Ratio Register
0x47C0_C67C 0x47C0_CA7C DATA2_REG_PHY_USE_RANK0_DELAYS DDR PHY Data Macro 2 Delay Selection
Register
0x47C0_C680 0x47C0_CA80 DATA2_REG_PHY_DLL_LOCK_DIFF_0 DDR PHY Data Macro 2 DLL Lock
Difference Register
0x47C0_C6B4 0x47C0_CAB4 DATA3_REG_PHY_RD_DQS_SLAVE_RATIO _0 DDR PHY Data Macro 3 Read DQS
Slave Ratio Register
0x47C0_C6C8 0x47C0_CAC8 DATA3_REG_PHY_WR_DQS_SLAVE_RATI O_0 DDR PHY Data Macro 3 Write DQS
Slave Ratio Register
0x47C0_C6DC 0x47C0_CADC DATA3_REG_PHY_WRLVL_INIT_RATIO_0 DDR PHY Data Macro 3 Write Leveling
Init Ratio Register
0x47C0_C6E4 0x47C0_CAE4 DATA3_REG_PHY_WRLVL_INIT_MODE_0 DDR PHY Data Macro 3 Write Leveling
Init Mode Ratio Selection Register
0x47C0_C6E8 0x47C0_CAE8 DATA3_REG_PHY_GATELVL_INIT_RATIO_0 DDR PHY Data Macro 3 DQS Gate
Training Init Ratio Register
0x47C0_C6F0 0x47C0_CAF0 DATA3_REG_PHY_GATELVL_INIT_MODE_0 DDR PHY Data Macro 3 DQS Gate
Training Init Mode Ratio Selection
Register
0x47C0_C6F4 0x47C0_CAF4 DATA3_REG_PHY_FIFO_WE_SLAVE_RATI O_0 DDR PHY Data Macro 3 DQS Gate
Slave Ratio Register
0x47C0_C708 0x47C0_CB08 DATA3_REG_PHY_DQ_OFFSET_3 Offset Value From DQS to DQ for Data
Macro 3
0x47C0_C70C 0x47C0_CB0C DATA3_REG_PHY_WR_DATA_SLAVE_RATI O_0 DDR PHY Data Macro 3 Write Data
Slave Ratio Register
0x47C0_C720 0x47C0_CB20 DATA3_REG_PHY_USE_RANK0_DELAYS DDR PHY Data Macro 3 Delay Selection
Register
0x47C0_C724 0x47C0_CB24 DATA3_REG_PHY_DLL_LOCK_DIFF_0 DDR PHY Data Macro 3 DLL Lock
Difference Register

8.13.3 DDR-Related Control Module Registers Description

Table 8-52. DDR-Related Control Module Registers

HEX ADDRESS RANGE ACRONYM REGISTER NAME
0x4814 0694 EMIF_CLK_GATE EMIF0/1 PHY Clock Gate Control Register
0x4814 0E04 DDR0_IO_CTRL DDR Memory Controller_0 IO Control Register
0x4814 0E08 DDR1_IO_CTRL DDR Memory Controller_1 IO Control Register

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Table 8-52. DDR-Related Control Module Registers (continued)

HEX ADDRESS RANGE ACRONYM REGISTER NAME
0x4814 0E0C DDR_VTP_CTRL_0 DDR0 VTP Control Register
0x4814 0E10 DDR_VTP_CTRL_1 DDR1 VTP Control Register

8.13.4 DDR2/DDR3 Memory Controller Electrical Data/Timing

TI only supports board designs that follow the DDR2 and DDR3 Routing Specifications outlined in this
document. The switching characteristics and the timing diagram for the DDR2 memory controller are
shown in Table 8-53 and Figure 8-46.

Table 8-53. Switching Characteristics Over Recommended Operating Conditions for DDR2/DDR3 Memory
Controller (1)
OPP100/120/166
NO. UNIT
MIN MAX
DDR2 mode 2.5
1 tc(DDR_CLK) Cycle time, DDR[x]_CLK ns
DDR3 mode 1.876
(1) The PLL_DDR Controller must be programmed such that the resulting DDR[x]_CLK clock frequency is within the specified range.

DDR[x]_CLK

Figure 8-46. DDR2/DDR3 Memory Controller Clock Timing

8.13.4.1 DDR2 Routing Specifications

8.13.4.1.1 DDR2 Interface

This section provides the timing specification for the DDR2 interface as a PCB design and manufacturing
specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,
and signal timing. These rules, when followed, result in a reliable DDR2 memory system without the need
for a complex timing closure process. For more information regarding the guidelines for using this DDR2
specification, see the Understanding TI’s PCB Routing Rule-Based DDR Timing Specification Application
Report (Literature Number: SPRAAV0).

8.13.4.1.1.1 DDR2 Interface Schematic

Figure 8-47 shows the DDR2 interface schematic for a x32 DDR2 memory system. In Figure 8-48 the x16
DDR2 system schematic is identical except that the high-word DDR2 device is deleted.
When not using all or part of a DDR2 interface, the proper method of handling the unused pins is to tie off
the DDR[x]_DQS[n] pins to the corresponding DVDD_DDR[x] supply via a 1k-Ω resistor and pulling the
DDR[x]_DQS[n] pins to ground via a 1k-Ω resistor. This needs to be done for each byte not used. Also,
include the 50-Ω pulldown for DDR[x]_VTP. The DVDD_DDR[x] and VREFSSTL_DDR[x] power supply
pins need to be connected to their respective power supplies even if DDR[x] is not being used. All other
DDR interface pins can be left unconnected. Note that the supported modes for use of the DDR EMIF are
32-bits wide, 16-bits wide, or not used.

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DDR2

DDR[x]_D[0] DQ0

DDR[x]_D[7] DQ7
DDR[x]_DQM[0] LDM
DDR[x]_DQS[0] LDQS
DDR[x]_DQS[0] LDQS
DDR[x]_D[8] DQ8

DDR[x]_D[15] DQ15
DDR[x]_DQM[1] UDM
DDR[x]_DQS[1] UDQS
DDR[x]_DQS[1] UDQS
DDR[x]_ODT[0] T0 ODT

DDR2

DDR_ODT1 NC ODT
DDR_D16 DQ0

DDR[x]_D[23 DQ7
DDR[x]_DQM[2] LDM
DDR[x]_DQS[2] LDQS
DDR[x]_DQS[2] LDQS
DDR[x]_D[24] DQ8

DDR[x]_D[31] DQ15
DDR[x]_DQM[3] UDM
DDR[x]_DQS[3] UDQS
DDR[x]_DQS[3] UDQS
DDR[x]_BA[0] T0 BA0 BA0

DDR[x]_BA[2] T0 BA2 BA2

DDR[x]_A[0] T0 A0 A0

DDR[x]_A[14] T0 A14 A14

DDR[x]_CS[0] T0 CS CS
DDR[x]_CS[1] NC
(A)
DDR[x]_CAS T0 CAS CAS Vio 1.8
DDR[x]_RAS T0 RAS RAS
DDR[x]_WE T0 WE WE
DDR[x]_CKE T0 CKE CKE
DDR[x]_CLK 0.1 µF 1 K Ω 1%
T0 CK CK
DDR[x]_CLK T0 CK CK
VREFSSTL_DDR[x] VREF VREF VREF VREF VREF
(B) (B) (B)
0.1 µF 0.1 µF 0.1 µF 0.1 µF 1 K Ω 1%

DDR[x]_RST NC

DDR[x]_VTP
50 Ω (±2%)

T0 Termination is required. See terminator comments.

A. Vio1.8 is the power supply for the DDR2 memories and the DM814x DDR2 interface.
B. One of these capacitors can be eliminated if the divider and its capacitors are placed near a VREF pin.

Figure 8-47. 32-Bit DDR2 High-Level Schematic

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DDR2

DDR[x]_D[0] DQ0

DDR[x]_D[7] DQ7
DDR[x]_DQM[0] LDM
DDR[x]_DQS[0] LDQS
DDR[x]_DQS[0] LDQS
DDR[x]_D[8] DQ8

DDR[x]_D[15] DQ15
DDR[x]_DQM[1] UDM
DDR[x]_DQS[1] UDQS
DDR[x]_DQS[1] UDQS

DDR[x]_ODT[0] T0 ODT
DDR[x]_ODT[1] NC
DDR[x]_D[16] NC

(A)
Vio 1.8
DDR[x]_D[23] NC
DDR[x]_DQM[2] NC 1 KΩ
DDR[x]_DQS[2]
DDR[x]_DQS[2]
DDR[x]_D[24] NC 1 KΩ

(A)
Vio 1.8
DDR[x]_D[31] NC
DDR[x]_DQM[3] NC 1 KΩ
DDR[x]_DQS[3]
DDR[x]_DQS[3]
1 KΩ
DDR[x]_BA[0] T0 BA0

DDR[x]_BA[2] T0 BA2
DDR[x]_A[0] T0 A0

DDR[x]_A[14] T0 A14
DDR[x]_CS[0] T0 CS
DDR[x]_CS[1] NC
DDR[x]_CAS T0 CAS
(A)
DDR[x]_RAS T0 RAS Vio 1.8
DDR[x]_WE T0 WE
DDR[x]_CKE T0 CKE
DDR[x]_CLK T0 CK
T0 CK 0.1 µF 1 K Ω 1%
DDR[x]_CLK

VREFSSTL_DDR[x] VREF VREF VREF

(B) (B)
0.1 µF 0.1 µF
0.1 µF 1 K Ω 1%
DDR[x]_RST NC
DDR[x]_VTP
50 Ω (±2%)

T0 Termination is required. See terminator comments.

A. Vio1.8 is the power supply for the DDR2 memories and the DM814x DDR2 interface.
B. One of these capacitors can be eliminated if the divider and its capacitors are placed near a VREF pin.

Figure 8-48. 16-Bit DDR2 High-Level Schematic

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8.13.4.1.1.2 Compatible JEDEC DDR2 Devices

Table 8-54 shows the parameters of the JEDEC DDR2 devices that are compatible with this interface.
Generally, the DDR2 interface is compatible with x16 DDR2-800 speed grade DDR2 devices.

Table 8-54. Compatible JEDEC DDR2 Devices (Per Interface)

NO. PARAMETER MIN MAX UNIT
1 JEDEC DDR2 device speed grade (1) DDR2-800
2 JEDEC DDR2 device bit width x16 x16 Bits
3 JEDEC DDR2 device count (2) 1 2 Devices
4 JEDEC DDR2 device ball count (3) 84 92 Balls
(1) Higher DDR2 speed grades are supported due to inherent JEDEC DDR2 backwards compatibility.
(2) One DDR2 device is used for a 16-bit DDR2 memory system. Two DDR2 devices are used for a 32-bit DDR2 memory system.
(3) The 92-ball devices are retained for legacy support. New designs will migrate to 84-ball DDR2 devices. Electrically, the 92- and 84-ball
DDR2 devices are the same.

8.13.4.1.1.3 PCB Stackup

The minimum stackup required for routing the DM814x device is a six-layer stackup as shown in Table 8-
55. Additional layers may be added to the PCB stackup to accommodate other circuitry or to reduce the
size of the PCB footprint.

Table 8-55. Minimum PCB Stackup

LAYER TYPE DESCRIPTION
1 Signal Top routing mostly horizontal
2 Plane Ground
3 Plane Power
4 Signal Internal routing
5 Plane Ground
6 Signal Bottom routing mostly vertical

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Complete stackup specifications are provided in Table 8-56.

Table 8-56. PCB Stackup Specifications

NO. PARAMETER MIN TYP MAX UNIT
1 PCB routing/plane layers 6
2 Signal routing layers 3
3 Full ground layers under DDR2 routing region 2
4 Number of ground plane cuts allowed within DDR routing region 0
5 Number of ground reference planes required for each DDR2 routing layer 1
6 Number of layers between DDR2 routing layer and reference ground plane 0
7 PCB routing feature size 4 Mils
8 PCB trace width, w 4 Mils
9 PCB BGA escape via pad size (1) 18 20 Mils
(1)
10 PCB BGA escape via hole size 10 Mils
11 Processor BGA pad size 0.4 mm
13 Single-ended impedance, Zo 50 75 Ω
14 Impedance control (2) Z-5 Z Z+5 Ω
(1) A 20/10 via may be used if enough power routing resources are available. An 18/10 via allows for more flexible power routing to the
processor.
(2) Z is the nominal singled-ended impedance selected for the PCB specified by item 13.

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8.13.4.1.1.4 Placement
Figure 8-49 shows the required placement for the processor as well as the DDR2 devices. The
dimensions for this figure are defined in Table 8-57. The placement does not restrict the side of the PCB
on which the devices are mounted. The ultimate purpose of the placement is to limit the maximum trace
lengths and allow for proper routing space. For a 16-bit DDR memory system, the high-word DDR2 device
is omitted from the placement.

Recommended DDR2 Device X

Orientation
X1

A1 A1

X1 X1
Y OFFSET OFFSET

Controller
DDR2
Figure 8-49. DM814x Device and DDR2 Device Placement

Table 8-57. Placement Specifications

NO. PARAMETER MIN MAX UNIT
(1) (2)
1 X+Y 1660 Mils
2 X' (1) (2) 1280 Mils
3 X' Offset (1) (2) (3)
650 Mils
4 DDR2 keepout region (4)
5 Clearance from non-DDR2 signal to DDR2 keepout region (5) 4 w
(1) For dimension definitions, see Figure 8-47.
(2) Measurements from center of processor to center of DDR2 device.
(3) For 16-bit memory systems, it is recommended that X' offset be as small as possible.
(4) DDR2 keepout region to encompass entire DDR2 routing area.
(5) Non-DDR2 signals allowed within DDR2 keepout region provided they are separated from DDR2 routing layers by a ground plane.

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8.13.4.1.1.5 DDR2 Keepout Region

The region of the PCB used for the DDR2 circuitry must be isolated from other signals. The DDR2
keepout region is defined for this purpose and is shown in Figure 8-50. The size of this region varies with
the placement and DDR routing. Additional clearances required for the keepout region are shown in
Table 8-57.

A1 A1

DDR2 Controller
DDR2 Device

A1 A1

Figure 8-50. DDR2 Keepout Region

NOTE
The region shown in should encompass all the DDR2 circuitry and varies depending on
placement. Non-DDR2 signals should not be routed on the DDR signal layers within the
DDR2 keepout region. Non-DDR2 signals may be routed in the region, provided t hey are
routed on layers separated from DDR2 signal layers by a ground layer. No breaks should be
allowed in the reference ground layers in this region. In addition, the 1.8-V power plane
should cover the entire keepout region. Routes for the two DDR interfaces must be
separated by at least 4x; the more separation, the better.

8.13.4.1.1.6 Bulk Bypass Capacitors

Bulk bypass capacitors are required for moderate speed bypassing of the DDR2 and other circuitry.
Table 8-58 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note
that this table only covers the bypass needs of the DDR2 interfaces and DDR2 device. Additional bulk
bypass capacitance may be needed for other circuitry.

Table 8-58. Bulk Bypass Capacitors

No. Parameter Min Max Unit
1 DVDD18 bulk bypass capacitor count (1) 6 Devices
2 DVDD18 bulk bypass total capacitance 60 μF
(1)
3 DDR#1 bulk bypass capacitor count 1 Devices
4 DDR#1 bulk bypass total capacitance (1) 10 μF
5 DDR#2 bulk bypass capacitor count (2) 1 Devices
6 DDR#2 bulk bypass total capacitance (1) (2) 10 μF
(1) These devices should be placed near the device they are bypassing, but preference should be given to the placement of the high-speed
(HS) bypass capacitors. Use half of these capacitors for DDR[0] and half for DDR[1].
(2) Only used on 32-bit wide DDR2 memory systems.

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8.13.4.1.1.7 High-Speed Bypass Capacitors

High-speed (HS) bypass capacitors are critical for proper DDR2 interface operation. It is particularly
important to minimize the parasitic series inductance of the HS bypass capacitors, processor/DDR power,
and processor/DDR ground connections. Table 8-59 contains the specification for the HS bypass
capacitors as well as for the power connections on the PCB.

Table 8-59. High-Speed Bypass Capacitors

NO. PARAMETER MIN MAX UNIT
1 HS bypass capacitor package size (1) 0402 10 Mils
2 Distance from HS bypass capacitor to device being bypassed 250 Mils
3 Number of connection vias for each HS bypass capacitor (2) 2 Vias
4 Trace length from bypass capacitor contact to connection via 1 30 Mils
5 Number of connection vias for each processor power/ground ball 1 Vias
6 Trace length from processor power/ground ball to connection via 35 Mils
7 Number of connection vias for each DDR2 device power/ground ball 1 Vias
8 Trace length from DDR2 device power/ground ball to connection via 35 Mils
9 DVDD18 HS bypass capacitor count (3) (4) 40 Devices
10 DVDD18 HS bypass capacitor total capacitance (5) 2.4 μF
11 DDR device HS bypass capacitor count (6) (7) 8 Devices
12 DDR device HS bypass capacitor total capacitance (7) 0.4 μF
(1) LxW, 10-mil units, that is, a 0402 is a 40x20-mil surface-mount capacitor.
(2) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board.
(3) These devices should be placed as close as possible to the device being bypassed.
(4) Use half of these capacitors for DDR[0] and half for DDR[1].
(5) Use half of these capacitors for DDR[0] and half for DDR[1].
(6) These devices should be placed as close as possible to the device being bypassed.
(7) Per DDR device.

8.13.4.1.1.8 Net Classes

Table 8-60 lists the clock net classes for the DDR2 interface. Table 8-61 lists the signal net classes, and
associated clock net classes, for the signals in the DDR2 interface. These net classes are used for the
termination and routing rules that follow.

Table 8-60. Clock Net Class Definitions

CLOCK NET CLASS PROCESSOR PIN NAMES
CK DDR[x]_CLK/DDR[x]_CLK
DQS0 DDR[x]_DQS[0]/DDR[x]_DQS[0]
DQS1 DDR[x]_DQS[1]/DDR[x]_DQS[1]
DQS2 (1) DDR[x]_DQS[2]/DDR[x]_DQS[2]
(1)
DQS3 DDR[x]_DQS[3]/DDR[x]_DQS[3]
(1) Only used on 32-bit wide DDR2 memory systems.

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Table 8-61. Signal Net Class Definitions

ASSOCIATED CLOCK
CLOCK NET CLASS PROCESSOR PIN NAMES
NET CLASS
ADDR_CTRL CK DDR[x]_BA[2:0], DDR[x]_A[14:0], DDR[x]_CS[x], DDR[x]_CAS, DDR[x]_RAS,
DDR[x]_WE, DDR[x]_CKE, DDR[x]_ODT[x]
DQ0 DQS0 DDR[x]_D[7:0], DDR[x]_DQM[0]
DQ1 DQS1 DDR[x]_D[15:8], DDR[x]_DQM[1]
DQ2 (1) DQS2 DDR[x]_D[23:16], DDR[x]_DQM[2]
(1)
DQ3 DQS3 DDR[x]_D[31:24], DDR[x]_DQM[3]
(1) Only used on 32-bit wide DDR2 memory systems.

8.13.4.1.1.9 DDR2 Signal Termination

Signal terminators are required in CK and ADDR_CTRL net classes. Serial terminators may be used on
data lines to reduce EMI risk; however, serial terminations are the only type permitted. ODTs are
integrated on the data byte net classes. They should be enabled to ensure signal integrity.Table 8-62
shows the specifications for the series terminators.

Table 8-62. DDR2 Signal Terminations

NO. PARAMETER MIN TYP MAX UNIT
1 CK net class (1) (2) 0 10 Ω
(1) (2) (3) (4)
2 ADDR_CTRL net class 0 22 Zo Ω
3 Data byte net classes (DQS0-DQS3, DQ0-DQ3) (5) 0 Zo Ω
(1) Only series termination is permitted, parallel or SST specifically disallowed on board.
(2) Only required for EMI reduction.
(3) Terminator values larger than typical only recommended to address EMI issues.
(4) Termination value should be uniform across net class.
(5) No external terminations allowed for data byte net classes. ODT is to be used.

8.13.4.1.1.10 VREFSSTL_DDR Routing

VREFSSTL_DDR is used as a reference by the input buffers of the DDR2 memories as well as the
processor. VREF is intended to be half the DDR2 power supply voltage and should be created using a
resistive divider as shown in Figure 8-48. Other methods of creating VREF are not recommended.
Figure 8-51 shows the layout guidelines for VREF.

VREF Nominal Max Trace

width is 20 mils DDR2 Device
VREF Bypass Capacitor
A1 A1
+ +

DDR2 Controller

Neck down to minimum in BGA escape

regions is acceptable. Narrowing to
accomodate via congestion for short
distances is also acceptable. Best
performance is obtained if the width
of VREF is maximized.

Figure 8-51. VREF Routing and Topology

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8.13.4.1.2 DDR2 CK and ADDR_CTRL Routing

Figure 8-52 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a
balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A
(A'+A'') should be maximized.

A1 A1

B C

A´´

Controller
T

DDR2
A´

A = A´ + A´´

Figure 8-52. CK and ADDR_CTRL Routing and Topology

(1)
Table 8-63. CK and ADDR_CTRL Routing Specification
NO. PARAMETER MIN TYP MAX UNIT
1 Center-to-center CK-CK spacing 2w
2 CK/CK skew (1) 25 Mils
3 CK A-to-B/A-to-C skew length mismatch (2) 25 Mils
4 CK B-to-C skew length mismatch 25 Mils
5 Center-to-center CK to other DDR2 trace spacing (3) 4w
6 CK/ADDR_CTRL nominal trace length (4) CACLM-50 CACLM CACLM+50 Mils
7 ADDR_CTRL-to-CK skew length mismatch 100 Mils
8 ADDR_CTRL-to-ADDR_CTRL skew length mismatch 100 Mils
9 Center-to-center ADDR_CTRL to other DDR2 trace spacing (3) 4w
10 Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing (3) 3w
11 ADDR_CTRL A-to-B/A-to-C skew length mismatch (2) 100 Mils
12 ADDR_CTRL B-to-C skew length mismatch 100 Mils

(1) The length of segment A = A' + A′′ as shown in Figure 8-52.

(2) Series terminator, if used, should be located closest to the processor.
(3) Center-to-center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(4) CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes.

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Figure 8-53 shows the topology and routing for the DQS and DQ net classes; the routes are point to point.
Skew matching across bytes is not needed nor recommended.

A1 T A1 T
E2 E0
T T
E3 E1

Controller
DDR2
Figure 8-53. DQS and DQ Routing and Topology

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Table 8-64. DQS and DQ Routing Specification

NO. PARAMETER MIN TYP MAX UNIT
1 Center-to-center DQS-DQSn spacing in E0|E1|E2|E3 2w
2 DQS-DQSn skew in E0|E1|E2|E3 25 Mils
3 Center-to-center DQS to other DDR2 trace spacing (1) 4w
(2) (3) (4)
4 DQS/DQ nominal trace length DQLM-50 DQLM DQLM+50 Mils
5 DQ-to-DQS skew length mismatch (2) (3) (4) 100 Mils
6 DQ-to-DQ skew length mismatch (2) (3) (4) 100 Mils
(2) (3) (4)
7 DQ-to-DQ/DQS via count mismatch 1 Vias
8 Center-to-center DQ to other DDR2 trace spacing (1) (5) 4w
9 Center-to-center DQ to other DQ trace spacing (1) (6) (7) 3w
(2) (3) (4)
10 DQ/DQS E skew length mismatch 100 Mils
(1) Center-to-center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(2) A 16-bit DDR memory system has two sets of data net classes; one for data byte 0, and one for data byte 1, each with an associated
DQS (2 DQSs) per DDR EMIF used.
(3) A 32-bit DDR memory system has four sets of data net classes; one each for data bytes 0 through 3, and each associated with a DQS
(4 DQSs) per DDR EMIF used.
(4) There is no need, and it is not recommended, to skew match across data bytes; that is, from DQS0 and data byte 0 to DQS1 and data
byte 1.
(5) DQs from other DQS domains are considered other DDR2 trace.
(6) DQs from other data bytes are considered other DDR2 trace.
(7) DQLM is the longest Manhattan distance of each of the DQS and DQ net classes.

8.13.4.2 DDR3 Routing Specifications

8.13.4.2.1 DDR3 versus DDR2

This specification only covers PCB designs that utilize DDR3 memory. PCB designs using other types of
DDR memory should follow the specification appropriate for that type of memory. It is currently not
possible to design a single PCB that supports multiple types of DDR memory.

8.13.4.2.2 DDR3 EMIFs

A processor may contain more than one EMIF. This specification covers only one EMIF and needs to be
implemented for each additional EMIF. Requirements are identical between the EMIFs, however, the PCB
layouts will most likely be different.

8.13.4.2.3 DDR3 Device Combinations

Since there are several possible combinations of device counts and single- or dual-side mounting,
Table 8-65 summarizes the supported device configurations.

Table 8-65. Supported DDR3 Device Combinations (1)

NUMBER OF DDR3 DEVICES DDR3 DEVICE WIDTH (BITS) MIRRORED? DDR3 EMIF WIDTH (BITS)
1 16 N 16
(2)
2 8 Y 16
2 16 N 32
2 16 Y (2) 32
4 8 N 32
4 8 Y (3) 32
(1) This table is per EMIF.
(2) Two DDR3 devices are mirrored when one device is placed on the top of the board and the second device is placed on the bottom of
the board.
(3) This is two mirrored pairs of DDR3 devices.

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8.13.4.2.4 DDR3 Interface Schematic

The DDR3 interface schematic varies, depending upon the width of the DDR3 devices used and the width
of the bus used (16 or 32 bits). General connectivity is straightforward and very similar. 16-bit DDR
devices look like two 8-bit devices. Figure 8-54 and Figure 8-55 show the schematic connections for 32-bit
interfaces using x16 and x8 devices.
Note that a 16-bit wide interface schematic is practically identical to the 32-bit interface; only the high-word
DDR memories are removed.
When not using all or part of a DDR3 interface, the proper method of handling the unused pins is to tie off
the DDR[x]_DQS[n] pins to the corresponding DVDD_DDR[x] supply via a 1-kΩ resistor and pulling the
DDR[x]_DQS[n] pins to ground via a 1k-Ω resistor. This needs to be done for each byte not used.
Although these signals have internal pullups and pulldowns, external pullups and pulldowns provide
additional protection against external electrical noise causing activity on the signals.Also, include the 50-Ω
pulldown for DDR[x]_VTP. The DVDD_DDR[x] and VREFSSTL_DDR[x] power supply pins need to be
connected to their respective power supplies even if DDR[x] is not being used. All other DDR interface
pins can be left unconnected. Note that the supported modes for use of the DDR EMIF are 32 bits wide,
16 bits wide, or not used.

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32-bit DDR3 EMIF

DDR[x]_ODT[1] 16-Bit DDR3

NC
Devices
DDR[x]_CS[1] NC
DDR[x]_D[31] DQ15
8

DDR[x]_D[24] DQ8
DDR[x]_DQM[3] UDM
DDR[x]_DQS[3] UDQS
DDR[x]_DQS[3] UDQS
DDR[x]_D[23] DQ7
8

DDR[x]_D[16] D08
DDR[x]_DQM[2] LDM
DDR[x]_DQS[2] LDQS
DDR[x]_DQS[2] LDQS
DDR[x]_D[15] DQ15
8

DDR[x]_D[8] DQ8
DDR[x]_DQM[1] UDM
DDR[x]_DQS[1] UDQS
DDR[x]_DQS[1] UDQS
DDR[x]_D[7] DQ7
8

DDR[x]_D[0] DQ0
DDR[x]_DQM[0] LDM
DDR[x]_DQS[0] LDQS
DDR[x]_DQS[0] LDQS
Zo 0.1 µF
DDR[x]_CLK CK CK
DDR_1V5
DDR[x]_CLK CK CK
Zo
DDR[x]_ODT[0] ODT ODT
DDR[x]_CS[0] CS CS
DDR[x]_BA[0] BA0 BA0
DDR[x]_BA[1] BA1 BA1 DDR_VTT
DDR[x]_BA[2] BA2 BA2
DDR[x]_A[0] A0 A0 Zo
15

DDR[x]_A[14] A14 A14 Zo

DDR[x]_CAS CAS CAS

DDR[x]_RAS RAS RAS
DDR[x]_WE WE WE
DDR[x]_CKE CKE CKE
DDR[x]_RST RST RST DDR_VREF
ZQ ZQ
ZQ VREFDQ VREFDQ ZQ
VREFSSTL_DDR[x] VREFCA VREFCA

0.1 µF 0.1 µF 0.1 µF

DDR[x]_VTP
50 Ω (±2%)

Zo
Termination is required. See terminator comments.
ZQ
Value determined according to the DDR memory device data sheet.

Figure 8-54. 32-Bit, One-Bank DDR3 Interface Schematic Using Two 16-Bit DDR3 Devices

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32-bit DDR3 EMIF

DDR[x]_ODT[1] 8-Bit DDR3 8-Bit DDR3

NC
Devices Devices
DDR[x]_CS[1] NC
DDR[x]_D[31] DQ7
8

DDR[x]_D[24] DQ0
DDR[x]_DQM[3] DM/TQS
NC TDQS
DDR[x]_DQS[3] DQS
DDR[x]_DQS[3] DQS
DDR[x]_D[23] DQ7
8

DDR[x]_D[16] DQ0
DDR[x]_DQM[2] DM/TQS
NC TDQS
DDR[x]_DQS[2] DQS
DDR[x]_DQS[2] DQS
DDR[x]_D[15] DQ7
8

DDR[x]_D[8] DQ0
DDR[x]_DQM[1] DM/TQS
NC TDQS
DDR[x]_DQS[1] DQS
DDR[x]_DQS[1] DQS
DDR[x]_D[7] DQ7
8

DDR[x]_D[0] DQ0
DDR[x]_DQM[0] DM/TQS
NC TDQS
DDR[x]_DQS[0] DQS
DDR[x]_DQS[0] DQS 0.1 µF
Zo
DDR[x]_CLK CK CK CK CK
DDR_1V5
DDR[x]_CLK CK CK CK CK
Zo
DDR[x]_ODT[0] ODT ODT ODT ODT
DDR[x]_CS[0] CS CS CS CS
DDR[x]_BA[0] BA0 BA0 BA0 BA0
DDR[x]_BA[1] BA1 BA1 BA1 BA1 DDR_VTT
DDR[x]_BA[2] BA2 BA2 BA2 BA2
DDR[x]_A[0] A0 A0 A0 A0 Zo
15

DDR[x]_A[14] A14 A14 A14 A14 Zo

DDR[x]_CAS CAS CAS CAS CAS
DDR[x]_RAS RAS RAS RAS RAS
DDR[x]_WE WE WE WE WE
DDR[x]_CKE CKE CKE CKE CKE
DDR[x]_RST RST RST RST RST DDR_VREF
ZQ ZQ ZQ ZQ
ZQ VREFDQ VREFDQ ZQ ZQ VREFDQ VREFDQ ZQ
VREFSSTL_DDR[x] VREFCA VREFCA VREFCA VREFCA

0.1 µF 0.1 µF 0.1 µF 0.1 µF 0.1 µF

DDR[x]_VTP
50 Ω (±2%)

Zo
Termination is required. See terminator comments.
ZQ
Value determined according to the DDR memory device data sheet.

Figure 8-55. 32-Bit, One-Bank DDR3 Interface Schematic Using Four 8-Bit DDR3 Devices

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8.13.4.2.4.1 Compatible JEDEC DDR3 Devices

Table 8-66 shows the parameters of the JEDEC DDR3 devices that are compatible with this interface.
Generally, the DDR3 interface is compatible with DDR3-1600 devices in the x8 or x16 widths.

Table 8-66. Compatible JEDEC DDR3 Devices (Per Interface)

NO. PARAMETER MIN MAX UNIT
1 JEDEC DDR3 device speed grade (1) DDR3-800 DDR3-
1600 (2)
2 JEDEC DDR3 device bit width x8 x16 Bits
(3)
3 JEDEC DDR3 device count 2 8 Devices
(1) DDR3 speed grade depends on desired clock rate. Data rate is 2x the clock rate. For DDR3-800, the clock rate is 400 MHz.
(2) DDR3 devices with speed grades up to DDR3-1600 are supported; however, max clock rate will still be limited to 533 MHz as stated in
Switching Characteristics Over Recommended Operating Conditions for DDR3 Memory Controller.
(3) For valid DDR3 device configurations and device counts, see Section 8.13.4.2.4, Figure 8-54, and Figure 8-55.

8.13.4.2.4.2 PCB Stackup

The minimum stackup for routing the DDR3 interface is a four-layer stack up as shown in Table 8-67.
Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance SI/EMI
performance, or to reduce the size of the PCB footprint. A six-layer stackup is shown in Table 8-68.
Complete stackup specifications are provided in Table 8-69.

Table 8-67. Minimum PCB Stackup

LAYER TYPE DESCRIPTION
1 Signal Top routing mostly vertical
2 Plane Split power plane
3 Plane Full ground plane
4 Signal Bottom routing mostly horizontal

Table 8-68. Six-Layer PCB Stackup Suggestion

LAYER TYPE DESCRIPTION
1 Signal Top routing mostly vertical
2 Plane Ground
3 Plane Split power plane
4 Plane Split power plane or Internal routing
5 Plane Ground
6 Signal Bottom routing mostly horizontal

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Table 8-69. PCB Stackup Specifications

NO. PARAMETER MIN TYP MAX UNIT
1 PCB routing/plane layers 4 6
2 Signal routing layers 2
3 Full ground reference layers under DDR3 routing region (1) 1
(1)
4 Full 1.5-V power reference layers under the DDR3 routing region 1
5 Number of reference plane cuts allowed within DDR routing region (2) 0
6 Number of layers between DDR3 routing layer and reference plane (3) 0
7 PCB routing feature size 4 Mils
8 PCB trace width, w 4 Mils
13 Single-ended impedance, Zo 50 75 Ω
(4)
14 Impedance control Z-5 Z Z+5 Ω
(1) Ground reference layers are preferred over power reference layers. Be sure to include bypass caps to accommodate reference layer
return current as the trace routes switch routing layers.
(2) No traces should cross reference plane cuts within the DDR routing region. High-speed signal traces crossing reference plane cuts
create large return current paths which can lead to excessive crosstalk and EMI radiation.
(3) Reference planes are to be directly adjacent to the signal plane to minimize the size of the return current loop.
(4) Z is the nominal singled-ended impedance selected for the PCB specified by item 13.

8.13.4.2.4.3 Placement
Figure 8-56 shows the required placement for the processor as well as the DDR3 devices. The
dimensions for this figure are defined in Table 8-70. The placement does not restrict the side of the PCB
on which the devices are mounted. The ultimate purpose of the placement is to limit the maximum trace
lengths and allow for proper routing space. For a 16-bit DDR memory system, the high-word DDR3
device(s) are omitted from the placement.

X1
X2 X2 X2

DDR3
Controller

Figure 8-56. Placement Specifications

It is strongly recommended that high-speed bypass capacitors be placed and accommodated for during
the placement and route planning phase. It is very difficult to add bypass capacitors once the board has
been routed and significant rework may be required to meet the high-speed bypass capacitor
requirements in Section 8.13.4.2.4.6, High-Speed Bypass Capacitors if the proper planning is not done. A
particular challenge to placing bypass capacitors in congested areas is fitting the required vias. It is
suggested that each pair of vias support two bypass capacitors by mounting one capacitor on the top of
the board and other on the bottom. Do not share vias between capacitors mounted on the same side of
the PCB. Another suggestion is to line up the vias for the bypass capacitors for the processor in rows
forming channels to allow the signals to escape.

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Table 8-70. Placement Specifications

NO. PARAMETER MIN MAX UNIT
1 X1 (1) (2) (3) 1000 Mils
2 X2 (1) (2) 600 Mils
3 Y Offset (1) (2) (3) 1500 Mils
4 DDR3 keepout region
5 Clearance from non-DDR3 signal to DDR3 keepout region (4) (5) (6) 4 w
(1) For dimension definitions, see Figure 8-56.
(2) Measurements from center of processor to center of DDR3 device.
(3) Minimizing X1 and Y improves timing margins.
(4) w is defined as the signal trace width.
(5) Non-DDR3 signals allowed within DDR3 keepout region provided they are separated from DDR3 routing layers by a ground plane.
(6) If a device has more than one DDR controller, the signals from the other controller(s) are considered non-DDR3 and should be
separated by this specification.

8.13.4.2.4.4 DDR3 Keepout Region

The region of the PCB used for DDR3 circuitry must be isolated from other signals. The DDR3 keepout
region is defined for this purpose and is shown in Figure 8-57. The size of this region varies with the
placement and DDR routing. Additional clearances required for the keepout region are shown in Table 8-
70. Non-DDR3 signals should not be routed on the DDR signal layers within the DDR3 keepout region.
Non-DDR3 signals may be routed in the region, provided they are routed on layers separated from the
DDR signal layers by a ground layer. No breaks should be allowed in the reference ground layers in this
region. In addition, the 1.5-V DDR3 power plane should cover the entire keepout region. Also note that if
there is more than one DDR controller, the signals from each controller need to be separated from each
other by the specification in Table 8-70, item 5. Each DDR controller should have its own DDR keepout
region.

DDR3 Controllers

DDR[1] Keep Out Region DDR[0] Keep Out Region

Encompasses Entire DDR[1] Routing Area Encompasses Entire DDR[0] Routing Area

Figure 8-57. DDR3 Keepout Region

Figure 8-57 is an example of a processor with two DDR controllers. Processors with a single DDR
controler will have only one DDR keepout region. Each DDR controller should have its own keepout
region.

8.13.4.2.4.5 Bulk Bypass Capacitors

Bulk bypass capacitors are required for moderate speed bypassing of the DDR3 and other circuitry.
Table 8-71 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note
that this table only covers the bypass needs of the DDR3 controllers and DDR3 device(s). Additional bulk
bypass capacitance may be needed for other circuitry.

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Table 8-71. Bulk Bypass Capacitors Per DDR3 EMIF

NO. PARAMETER MIN MAX UNIT
1 DDR_1V5 bulk bypass capacitor count (1) 3 Devices
2 DDR_1V5 bulk bypass total capacitance 70 μF
(1) These devices should be placed near the devices they are bypassing, but preference should be given to the placement of the high-
speed (HS) bypass capacitors and DDR3 signal routing.

8.13.4.2.4.6 High-Speed Bypass Capacitors

High-speed (HS) bypass capacitors are critical for proper DDR3 interface operation. It is particularly
important to minimize the parasitic series inductance of the HS bypass capacitors, processor/DDR power,
and processor/DDR ground connections. Table 8-72 contains the specification for the HS bypass
capacitors as well as for the power connections on the PCB. Generally speaking, it is good to:
1. Fit as many HS bypass capacitors as possible.
2. Minimize the distance from the bypass cap to the pins/balls being bypassed.
3. Use the smallest physical sized capacitors possible with the highest capacitance readily available.
4. Connect the bypass capacitor pads to their vias using the widest traces possible and using the largest
hole size via possible.
5. Minimize via sharing. Note the limits on via sharing shown in Table 8-72.

Table 8-72. High-Speed Bypass Capacitors

NO. PARAMETER MIN TYP MAX UNIT
1 HS bypass capacitor package size (1) 201 402 10 Mils
2 Distance, HS bypass capacitor to processor being bypassed (2) (3) (4) 400 Mils
(5)
3 Processor DDR_1V5 HS bypass capacitor count 35 Per
DDR3
EMIF
4 Processor DDR_1V5 HS bypass capacitor total capacitance 5 μF
(6)
5 Number of connection vias for each device power/ground ball Vias
6 Trace length from device power/ground ball to connection via (2) 35 70 Mils
7 Distance, HS bypass capacitor to DDR device being bypassed (7) 150 Mils
(8)
8 DDR3 device HS bypass capacitor count 12 Devices
9 DDR3 device HS bypass capacitor total capacitance (8) 0.85 μF
10 Number of connection vias for each HS capacitor (9) (10) 2 Vias
11 Trace length from bypass capacitor connect to connection via (2) (10) 35 100 Mils
12 Number of connection vias for each DDR3 device power/ground ball (11) 1 Vias
13 Trace length from DDR3 device power/ground ball to connection via (2) (9) 35 60 Mils
(1) LxW, 10-mil units, i.e., a 0402 is a 40x20-mil surface-mount capacitor.
(2) Closer/shorter is better.
(3) Measured from the nearest processor power/ground ball to the center of the capacitor package.
(4) Three of these capacitors should be located underneath the processor, between the cluster of DDR_1V5 balls and ground balls,
between the DDR interfaces on the package.
(5) Per DDR3 EMIF. For example, a processor with two DDR3 EMIFs would require 70 capacitors. The capacitors should be evenly
distributed near the Processor's DDR_1V5 pins.
(6) See the Via Channel™ escape for the processor package.
(7) Measured from the DDR3 device power/ground ball to the center of the capacitor package.
(8) Per DDR3 EMIF.
(9) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board. No sharing of
vias is permitted on the same side of the board.
(10) An HS bypass capacitor may share a via with a DDR device mounted on the same side of the PCB. A wide trace should be used for the
connection and the length from the capacitor pad to the DDR device pad should be less than 150 mils.
(11) Up to a total of two pairs of DDR power/ground balls may share a via.

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8.13.4.2.4.6.1 Return Current Bypass Capacitors and Vias

If a power plane is used as a reference plane then additional bypass capacitors may be required to
accommodate the signal return currents. Care should be taken to minimize the layer transitions during
routing. If a layer transition is necessary, it is better to transition to a layer using the same reference plane.
If this cannot be accommodated, ensure there is a nearby path to allow the return currents to transition
between reference planes. Transitions from power reference planes to ground reference planes must go
through a bypass capacitor. Transition between different ground references or DVDD_DDR planes can go
through a connecting via. As many of these return current bypass capacitors or vias should be used as
possible. The goal is to minimize the size of the return current loops. Generally, this type of situation
happens where signals must transition from horizontal to vertical routing and vice-versa.

8.13.4.2.4.7 Net Classes

Table 8-73 lists the clock net classes for the DDR3 interface. Table 8-74 lists the signal net classes, and
associated clock net classes, for signals in the DDR3 interface. These net classes are used for the
termination and routing rules that follow.

Table 8-73. Clock Net Class Definitions

CLOCK NET CLASS PROCESSOR PIN NAMES
CK DDR[x]_CLK/DDR[x]_CLK
DQS0 DDR[x]_DQS[0]/DDR[x]_DQS[0]
DQS1 DDR[x]_DQS[1]/DDR[x]_DQS[1]
(1)
DQS2 DDR[x]_DQS[2]/DDR[x]_DQS[2]
DQS3 (1) DDR[x]_DQS[3]/DDR[x]_DQS[3]
(1) Only used on 32-bit wide DDR3 memory systems.

Table 8-74. Signal Net Class Definitions

ASSOCIATED CLOCK
CLOCK NET CLASS PROCESSOR PIN NAMES
NET CLASS
ADDR_CTRL CK DDR[x]_BA[2:0], DDR[x]_A[14:0], DDR[x]_CS[x], DDR[x]_CAS, DDR[x]_RAS,
DDR[x]_WE, DDR[x]_CKE, DDR[x]_ODT[x]
DQ0 DQS0 DDR[x]_D[7:0], DDR[x]_DQM[0]
DQ1 DQS1 DDR[x]_D[15:8], DDR[x]_DQM[1]
DQ2 (1) DQS2 DDR[x]_D[23:16], DDR[x]_DQM[2]
(1)
DQ3 DQS3 DDR[x]_D[31:24], DDR[x]_DQM[3]
(1) Only used on 32-bit wide DDR3 memory systems.

8.13.4.2.4.8 DDR3 Signal Termination

Signal terminators are required for the CK and ADDR_CTRL net classes. The data lines are terminated by
ODT and, thus, the PCB traces should be unterminated. Detailed termination specifications are covered in
the routing rules in the following sections.

8.13.4.2.4.9 VREFSSTL_DDR Routing

VREFSSTL_DDR (VREF) is used as a reference by the input buffers of the DDR3 memories as well as
the processor. VREF is intended to be half the DDR3 power supply voltage and is typically generated with
the DDR3 1.5-V and VTT power supply. It should be routed as a nominal 20-mil wide trace with 0.1 µF
bypass capacitors near each device connection. Narrowing of VREF is allowed to accommodate routing
congestion.

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8.13.4.2.4.10 VTT
Like VREF, the nominal value of the VTT supply is half the DDR3 supply voltage. Unlike VREF, VTT is
expected to source and sink current, specifically the termination current for the ADDR_CTRL net class
Thevinen terminators. VTT is needed at the end of the address bus and it should be routed as a power
sub-plane. VTT should be bypassed near the terminator resistors.

8.13.4.2.4.11 CK and ADDR_CTRL Topologies and Routing Definition

The CK and ADDR_CTRL net classes are routed similarly and are length matched to minimize skew
between them. CK is a bit more complicated because it runs at a higher transition rate and is differential.
The following subsections show the topology and routing for various DDR3 configurations for CK and
ADDR_CTRL. Only the components shown in the topologies are allowed. Items such as test points and
additional terminations are specifically disallowed. The figures in the following subsections define the
terms for the routing specification detailed in Table 8-75.
Care should be taken to minimize layer transitions during routing. If a layer transition is necessary, it is
better to transition to a layer using the same reference plane. If this cannot be accommodated, ensure
there are nearby ground vias to allow the return currents to transition between reference planes if both
reference planes are ground or DVDD_DDR. Ensure there are nearby bypass capacitors to allow the
return currents to transition between reference planes if one of the reference planes is ground. The goal is
to minimize the size of the return current loops.

8.13.4.2.4.11.1 Four DDR3 Devices

Four DDR3 devices are supported on the DDR EMIF consisting of four x8 DDR3 devices arranged as one
bank (CS). These four devices may be mounted on a single side of the PCB, or may be mirrored in two
pairs to save board space at a cost of increased routing complexity and parts on the backside of the PCB.

8.13.4.2.4.11.2 CK and ADDR_CTRL Topologies, Four DDR3 Devices

Figure 8-58 shows the topology of the CK net classes and Figure 8-59 shows the topology for the
corresponding ADDR_CTRL net classes.

DDR Differential CK Input Buffers

+ – + – + – + –
AS+

AS+

AS+
AS+

AS-

AS-

AS-
AS-

Clock Parallel
Terminator
DDR_1V5
Rcp
A1 A2 A3 A4 A3 AT
Cac
Processor +
Differential Clock
Output Buffer –
Rcp 0.1 µF
A1 A2 A3 A4 A3 AT

Routed as Differential Pair

Figure 8-58. CK Topology for Four x8 DDR3 Devices

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DDR Address and Control Input Buffers

AS

AS

AS

AS
Address and Control
Terminator
Processor Rtt
Address and Control A1 A2 A3 A4 A3 AT Vtt
Output Buffer

Figure 8-59. ADDR_CTRL Topology for Four x8 DDR3 Devices

8.13.4.2.4.11.3 CK and ADDR_CTRL Routing, Four DDR3 Devices

Figure 8-60 shows the CK routing for four DDR3 devices placed on the same side of the PCB. Figure 8-61
shows the corresponding ADDR_CTRL routing.
A1
A1

DDR_1V5

Rcp Cac
A2 A3 A4 A3 AT
A2 A3 A4 A3 AT
Rcp 0.1 µF
AS+
AS-

Figure 8-60. CK Routing for Four Single-Side DDR3 Devices

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A1

Rtt
A2 A3 A4 A3 AT Vtt

AS

Figure 8-61. ADDR_CTRL Routing for Four Single-Side DDR3 Devices

To save PCB space, the four DDR3 memories may be mounted as two mirrored pairs at a cost of
increased routing and assembly complexity. Figure 8-62 and Figure 8-63 show the routing for CK and
ADDR_CTRL, respectively, for four DDR3 devices mirrored in a two-pair configuration.
A1
A1

DDR_1V5

Rcp Cac
A2 A3 A4 A3 AT
A2 A3 A4 A3 AT
Rcp 0.1 µF
AS+
AS-

Figure 8-62. CK Routing for Four Mirrored DDR3 Devices

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A1
Rtt
A2 A3 A4 A3 AT Vtt

AS
=

Figure 8-63. ADDR_CTRL Routing for Four Mirrored DDR3 Devices

8.13.4.2.4.11.4 Two DDR3 Devices

Two DDR3 devices are supported on the DDR EMIF consisting of two x8 DDR3 devices arranged as one
bank (CS), 16-bits wide, or two x16 DDR3 devices arranged as one bank (CS), 32-bits wide. These two
devices may be mounted on a single side of the PCB, or may be mirrored in a pair to save board space at
a cost of increased routing complexity and parts on the backside of the PCB.

8.13.4.2.4.11.5 CK and ADDR_CTRL Topologies, Two DDR3 Devices

Figure 8-64 shows the topology of the CK net classes and Figure 8-65 shows the topology for the
corresponding ADDR_CTRL net classes.

DDR Differential CK Input Buffers

+ – + –
AS+
AS+

AS-
AS-

Clock Parallel
Terminator
DDR_1V5
Rcp
A1 A2 A3 AT
Cac
Processor +
Differential Clock
Output Buffer –
Rcp 0.1 µF
A1 A2 A3 AT

Routed as Differential Pair

Figure 8-64. CK Topology for Two DDR3 Devices

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DDR Address and Control Input Buffers

AS

AS
Address and Control
Terminator
Processor Rtt
Address and Control A1 A2 A3 AT Vtt
Output Buffer

Figure 8-65. ADDR_CTRL Topology for Two DDR3 Devices

8.13.4.2.4.11.6 CK and ADDR_CTRL Routing, Two DDR3 Devices

Figure 8-66 shows the CK routing for two DDR3 devices placed on the same side of the PCB. Figure 8-67
shows the corresponding ADDR_CTRL routing.
A1
A1

DDR_1V5

Rcp Cac
A2 A3 AT
A2 A3 AT
Rcp 0.1 µF
AS+
AS-

Figure 8-66. CK Routing for Two Single-Side DDR3 Devices

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A1
Rtt
A2 A3 AT Vtt

AS
=

Figure 8-67. ADDR_CTRL Routing for Two Single-Side DDR3 Devices

To save PCB space, the two DDR3 memories may be mounted as a mirrored pair at a cost of increased
routing and assembly complexity. Figure 8-68 and Figure 8-69 show the routing for CK and ADDR_CTRL,
respectively, for two DDR3 devices mirrored in a single-pair configuration.
A1
A1

DDR_1V5

Rcp Cac
A2 A3 AT
A2 A3 AT
Rcp 0.1 µF
AS+
AS-

Figure 8-68. CK Routing for Two Mirrored DDR3 Devices

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A1
Rtt
A2 A3 AT Vtt

AS
=

Figure 8-69. ADDR_CTRL Routing for Two Mirrored DDR3 Devices

8.13.4.2.4.11.7 One DDR3 Device

A single DDR3 device is supported on the DDR EMIF consisting of one x16 DDR3 device arranged as
one bank (CS), 16-bits wide.

8.13.4.2.4.11.8 CK and ADDR_CTRL Topologies, One DDR3 Device

Figure 8-70 shows the topology of the CK net classes and Figure 8-71 shows the topology for the
corresponding ADDR_CTRL net classes.

DDR Differential CK Input Buffer

+ –
AS+
AS-

Clock Parallel
Terminator
DDR_1V5
Rcp
A1 A2 AT
Cac
Processor +
Differential Clock
Output Buffer –
Rcp 0.1 µF
A1 A2 AT

Routed as Differential Pair

Figure 8-70. CK Topology for One DDR3 Device

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DDR Address and Control Input Buffers

AS
Address and Control
Terminator
Processor Rtt
Address and Control A1 A2 AT Vtt
Output Buffer

Figure 8-71. ADDR_CTRL Topology for One DDR3 Device

8.13.4.2.4.11.9 CK and ADDR/CTRL Routing, One DDR3 Device

Figure 8-72 shows the CK routing for one DDR3 device placed on the same side of the PCB. Figure 8-73
shows the corresponding ADDR_CTRL routing.
A1
A1

DDR_1V5

Rcp Cac
A2 AT
A2 AT
Rcp 0.1 µF
AS+
AS-

Figure 8-72. CK Routing for One DDR3 Device

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A1
Rtt
A2 AT Vtt

AS
=

Figure 8-73. ADDR_CTRL Routing for One DDR3 Device

8.13.4.2.4.12 Data Topologies and Routing Definition

No matter the number of DDR3 devices used, the data line topology is always point-to-point, so its
definition is simple.
Care should be taken to minimize layer transitions during routing. If a layer transition is necessary, it is
better to transition to a layer using the same reference plane. If this cannot be accommodated, ensure
there are nearby ground vias to allow the return currents to transition between reference planes if both
reference planes are ground or DVDD_DDR. Ensure there are nearby bypass capacitors to allow the
return currents to transition between reference planes if one of the reference planes is ground. The goal is
to minimize the size of the return current loops.

8.13.4.2.4.12.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
DQS lines are point-to-point differential, and DQ/DM lines are point-to-point singled ended. Figure 8-74
and Figure 8-75 show these topologies.

Processor DQSn+ DDR

DQS DQS
IO Buffer DQSn- IO Buffer

Routed Differentially

n = 0, 1, 2, 3

Figure 8-74. DQS Topology

Processor DDR
DQ and DM Dn DQ and DM
IO Buffer IO Buffer

n = 0, 1, 2, 3

Figure 8-75. DQ/DM Topology

8.13.4.2.4.12.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
Figure 8-76 and Figure 8-77 show the DQS and DQ/DM routing.

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DQS
DQSn+
DQSn-

Routed Differentially

n = 0, 1, 2, 3

Figure 8-76. DQS Routing With Any Number of Allowed DDR3 Devices

DQ and DM
Dn

n = 0, 1, 2, 3

Figure 8-77. DQ/DM Routing With Any Number of Allowed DDR3 Devices

8.13.4.2.4.13 Routing Specification

8.13.4.2.4.13.1 CK and ADDR_CTRL Routing Specification

Skew within the CK and ADDR_CTRL net classes directly reduces setup and hold margin and, thus, this
skew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter
traces up to the length of the longest net in the net class and its associated clock. A metric to establish
this maximum length is Manhattan distance. The Manhattan distance between two points on a PCB is the
length between the points when connecting them only with horizontal or vertical segments. A reasonable
trace route length is to within a percentage of its Manhattan distance. CACLM is defined as Clock Address
Control Longest Manhattan distance.
Given the clock and address pin locations on the processor and the DDR3 memories, the maximum
possible Manhattan distance can be determined given the placement. Figure 8-78 and Figure 8-79 show
this distance for four loads and two loads, respectively. It is from this distance that the specifications on
the lengths of the transmission lines for the address bus are determined. CACLM is determined similarly
for other address bus configurations; i.e., it is based on the longest net of the CK/ADDR_CTRL net class.
For CK and ADDR_CTRL routing, these specifications are contained in Table 8-75.

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(A)
A8

A1 CACLMY

CACLMX

(A) (A) (A) (A)

A8 A8 A8 A8
Rtt
A2 A3 A4 A3 AT Vtt
AS

A. It is very likely that the longest CK/ADDR_CTRL Manhattan distance will be for Address Input 8 (A8) on the DDR3
memories. CACLM is based on the longest Manhattan distance due to the device placement. Verify the net class that
satisfies this criteria and use as the baseline for CK/ADDR_CTRL skew matching and length control.

The length of shorter CK/ADDR_CTRL stubs as well as the length of the terminator stub are not included in this
length calculation. Non-included lengths are grayed out in the figure.

Assuming A8 is the longest, CALM = CACLMY + CACLMX + 300 mils.

The extra 300 mils allows for routing down lower than the DDR3 memories and returning up to reach A8.

Figure 8-78. CACLM for Four Address Loads on One Side of PCB

(A)
A8
A1

CACLMY

CACLMX

(A) (A)
A8 A8
Rtt
A2 A3 AT Vtt
AS

A. It is very likely that the longest CK/ADDR_CTRL Manhattan distance will be for Address Input 8 (A8) on the DDR3
memories. CACLM is based on the longest Manhattan distance due to the device placement. Verify the net class that
satisfies this criteria and use as the baseline for CK/ADDR_CTRL skew matching and length control.

The length of shorter CK/ADDR_CTRL stubs as well as the length of the terminator stub are not included in this
length calculation. Non-included lengths are grayed out in the figure.

Assuming A8 is the longest, CALM = CACLMY + CACLMX + 300 mils.

The extra 300 mils allows for routing down lower than the DDR3 memories and returning up to reach A8.

Figure 8-79. CACLM for Two Address Loads on One Side of PCB

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Table 8-75. CK and ADDR_CTRL Routing Specification (1) (2)

NO. PARAMETER MIN TYP MAX UNIT
1 A1+A2 length 2500 mils
2 A1+A2 skew 25 mils
3 A3 length 660 mils
(3)
4 A3 skew 25 mils
5 A3 skew (4) 125 mils
6 A4 length 660 mils
7 A4 skew 25 mils
8 AS length 100 mils
9 AS skew 100 mils
10 AS+/AS- length 70 mils
11 AS+/AS- skew 5 mils
12 AT length (5) 500 mils
13 AT skew (6) 100 mils
(7)
14 AT skew 5 mils
15 CK/ADDR_CTRL nominal trace length (8) CACLM-50 CACLM CACLM+50 mils
16 Center-to-center CK to other DDR3 trace spacing (9) 4w
17 Center-to-center ADDR_CTRL to other DDR3 trace spacing (9) (10) 4w
18 Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing (9) 3w
19 CK center-to-center spacing (11) (12)

20 CK spacing to other net (9) 4w

21 Rcp (13) Zo-1 Zo Zo+ Ω
22 Rtt (13) (14) Zo-5 Zo Zo+5 Ω
(1) The use of vias should be minimized.
(2) Additional bypass capacitors are required when using the DDR_1V5 plane as the reference plane to allow the return current to jump
between the DDR_1V5 plane and the ground plane when the net class switches layers at a via.
(3) Non-mirrored configuration (all DDR3 memories on same side of PCB).
(4) Mirrored configuration (one DDR3 device on top of the board and one DDR3 device on the bottom).
(5) While this length can be increased for convenience, its length should be minimized.
(6) ADDR_CTRL net class only (not CK net class). Minimizing this skew is recommended, but not required.
(7) CK net class only.
(8) CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes + 300 mils. For definition, see
Section 8.13.4.2.4.13.1, Figure 8-78, and Figure 8-79.
(9) Center-to-center spacing is allowed to fall to minimum (w) for up to 1250 mils of routed length.
(10) The ADDR_CTRL net class of the other DDR EMIF is considered other DDR3 trace spacing.
(11) CK spacing set to ensure proper differential impedance.
(12) The most important thing to do is control the impedance so inadvertent impedance mismatches are not created. Generally speaking,
center-to-center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the single-
ended impedance, Zo.
(13) Source termination (series resistor at driver) is specifically not allowed.
(14) Termination values should be uniform across the net class.

8.13.4.2.4.13.2 DQS and DQ Routing Specification

Skew within the DQS and DQ/DM net classes directly reduces setup and hold margin and thus this skew
must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter traces
up to the length of the longest net in the net class and its associated clock. As with CK and ADDR_CTRL,
a reasonable trace route length is to within a percentage of its Manhattan distance. DQLMn is defined as
DQ Longest Manhattan distance n, where n is the byte number. For a 32-bit interface, there are four
DQLMs, DQLM0–DQLM3. Likewise, for a 16-bit interface, there are two DQLMs, DQLM0–DQLM1.

NOTE
It is not required, nor is it recommended, to match the lengths across all bytes. Length
matching is only required within each byte.

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Given the DQS and DQ/DM pin locations on the processor and the DDR3 memories, the maximum
possible Manhattan distance can be determined given the placement. Figure 8-80 shows this distance for
four loads. It is from this distance that the specifications on the lengths of the transmission lines for the
data bus are determined. For DQS and DQ/DM routing, these specifications are contained in Table 8-76.

DQLMX0
DQ[0:7]/DM0/DQS0
DB0
DQ[8:15]/DM1/DQS1
DB1

DQLMX1
DQ[16:23]/DM2/DQS2
DB2
DQLMX2 DQLMY0
DQLMY1
DQLMY3 DQLMY2 DQ[23:31]/DM3/DQS3
DB3
DQLMX3

3 2 1 0

DB0 - DB3 represent data bytes 0 - 3.

There are four DQLMs, one for each byte (32-bit interface). Each DQLM is the longest Manhattan distance of the
byte; therefore:
DQLM0 = DQLMX0 + DQLMY0
DQLM1 = DQLMX1 + DQLMY1
DQLM2 = DQLMX2 + DQLMY2
DQLM3 = DQLMX3 + DQLMY3

Figure 8-80. DQLM for Any Number of Allowed DDR3 Devices

Table 8-76. Data Routing Specification (1)

NO. PARAMETER MIN TYP MAX UNIT
1 DB0 nominal length (2) (3) DQLM0 mils
2 DB1 nominal length (2) (4) DQLM1 mils
(2) (5)
3 DB2 nominal length DQLM2 mils
4 DB3 nominal length (2) (6) DQLM3 mils
5 DBn skew (7) 25 mils
6 DQSn+ to DQSn- skew 5 mils
7 DQSn to DBn skew (7) (8) 25 mils
8 Center-to-center DBn to other DDR3 trace spacing (9) (10) 4w
9 Center-to-center DBn to other DBn trace spacing (9) (11) 3w
(12) (13)
10 DQSn center-to-center spacing
(9)
11 DQSn center-to-center spacing to other net 4w
(1) External termination disallowed. Data termination should use built-in ODT functionality.
(2) DQLMn is the longest Manhattan distance of a byte. For definition, see Section 8.13.4.2.4.13.2 and Figure 8-80.
(3) DQLM0 is the longest Manhattan length for the net classes of Byte 0.
(4) DQLM1 is the longest Manhattan length for the net classes of Byte 1.
(5) DQLM2 is the longest Manhattan length for the net classes of Byte 2.
(6) DQLM3 is the longest Manhattan length for the net classes of Byte 3.
(7) Length matching is only done within a byte. Length matching across bytes is neither required nor recommended.
(8) Each DQS pair is length matched to its associated byte.
(9) Center-to-center spacing is allowed to fall to minimum (w) for up to 1250 mils of routed length.
(10) Other DDR3 trace spacing means other DDR3 net classes not within the byte.
(11) This applies to spacing within the net classes of a byte.
(12) DQS pair spacing is set to ensure proper differential impedance.
(13) The most important thing to do is control the impedance so inadvertent impedance mismatches are not created. Generally speaking,
center-to-center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the single-
ended impedance, Zo.

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8.14 Multichannel Audio Serial Port (McASP)

The multichannel audio serial port (McASP) functions as a general-purpose audio serial port optimized for
the needs of multichannel audio applications. The McASP is useful for time-division multiplexed (TDM)
stream, Inter-Integrated Sound (I2S) protocols, and inter-component digital audio interface transmission
(DIT).

8.14.1 McASP Device-Specific Information

The device includes six multichannel audio serial port (McASP) interface peripherals (McASP0, McASP1,
McASP2, McASP3, McASP4, and McASP5). The McASP module consists of a transmit and receive
section. On McASP0/1, these sections can operate completely independently with different data formats,
separate master clocks, bit clocks, and frame syncs or, alternatively, the transmit and receive sections
may be synchronized. On McASP2, McASP3, McASP4, and McASP5, the transmit and receive sections
must always be synchronized. The McASP module also includes shift registers that may be configured to
operate as either transmit data or receive data.
The transmit section of the McASP can transmit data in either a time-division-multiplexed (TDM)
synchronous serial format or in a digital audio interface (DIT) format where the bit stream is encoded for
S/PDIF, AES-3, IEC-60958, CP-430 transmission. The receive section of the McASP peripheral supports
the TDM synchronous serial format.
The McASP module can support one transmit data format (either a TDM format or DIT format) and one
receive format at a time. All transmit shift registers use the same format and all receive shift registers use
the same format; however, the transmit and receive formats need not be the same. Both the transmit and
receive sections of the McASP also support burst mode, which is useful for non-audio data (for example,
passing control information between two devices).
The McASP peripheral has additional capability for flexible clock generation and error detection/handling,
as well as error management.
The device McASP0 and McASP1 modules have up to 10 serial data pins, while McASP2, McASP3,
McASP4, and McASP5 are limited to up to four serial data pins each. The McASP FIFO size is 256 bytes
and two DMA and two interrupt requests are supported. Buffers are used transparently to better manage
DMA, which can be leveraged to manage data flow more efficiently.
For more detailed information on and the functionality of the McASP peripheral, see the Multichannel
Audio Serial Port (McASP) chapter of the TMS320DM814x DaVinci Digital Media Processors Technical
Reference Manual (Literature Number: SPRUGZ8).

8.14.2 McASP0, McASP1, McASP2, McASP3, McASP4, and McASP5 Peripheral Registers
Descriptions

Table 8-77. McASP0/1/2/3/4/5 Registers

HEX ADDRESS RANGE
ACRONYM REGISTER NAME
MCASP0 MCASP1 MCASP2 MCASP3 MCASP4 MCASP5
0x4803 8000 0x4803 C000 0x4805 0000 0x4A1A 2000 0x4A1A 8000 0x4A1A E000 PID Peripheral ID
0x4803 8010 0x4803 C010 0x4805 0010 0x4A1A 2010 0x4A1A 8010 0x4A1A E010 PFUNC Pin Function
0x4803 8014 0x4803 C014 0x4805 0014 0x4A1A 2014 0x4A1A 8014 0x4A1A E014 PDIR Pin Direction
0x4803 8018 0x4803 C018 0x4805 0018 0x4A1A 2018 0x4A1A 8018 0x4A1A E018 PDOUT Pin Data Out
0x4803 801C 0x4803 C01C 0x4805 001C 0x4A1A 201C 0x4A1A 801C 0x4A1A PDIN Pin Data Input (Read)
E01C Read returns pin data input
PDSET Pin Data Set (Write)
Writes effect pin data set
(Alternate Write Address
PDOUT)

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Table 8-77. McASP0/1/2/3/4/5 Registers (continued)

HEX ADDRESS RANGE
ACRONYM REGISTER NAME
MCASP0 MCASP1 MCASP2 MCASP3 MCASP4 MCASP5
0x4803 8020 0x4803 C020 0x4805 0020 0x4A1A 2020 0x4A1A 8020 0x4A1A E020 PDCLR Pin Data Clear
(Alternate Write Address
PDOUT)
0x4803 8044 0x4803 C044 0x4805 0044 0x4A1A 2044 0x4A1A 8044 0x4A1A E044 GBLCTL Global Control
0x4803 8048 0x4803 C048 0x4805 0048 0x4A1A 2048 0x4A1A 8048 0x4A1A E048 AMUTE Mute Control
0x4803 804C 0x4803 C04C 0x4805 004C 0x4A1A 204C 0x4A1A 804C 0x4A1A LBCTL Loop-Back Test Control
E04C
0x4803 8050 0x4803 C050 0x4805 0050 0x4A1A 2050 0x4A1A 8050 0x4A1A E050 TXDITCTL Transmit DIT Mode Control
0x4803 8060 0x4803 C060 0x4805 0060 0x4A1A 2060 0x4A1A 8060 0x4A1A E060 GBLCTLR Alias of GBLCTL containing
only receiver reset bits;
allows transmit to be reset
independently from receive
0x4803 8064 0x4803 C064 0x4805 0064 0x4A1A 2064 0x4A1A 8064 0x4A1A E064 RXMASK Receiver Bit Mask
0x4803 8068 0x4803 C068 0x4805 0068 0x4A1A 2068 0x4A1A 8068 0x4A1A E068 RXFMT Receive Bitstream Format
0x4803 806C 0x4803 C06C 0x4805 006C 0x4A1A 206C 0x4A1A 806C 0x4A1A RXFMCTL Receive Frame Sync Control
E06C
0x4803 8070 0x4803 C070 0x4805 0070 0x4A1A 2070 0x4A1A 8070 0x4A1A E070 ACLKRCTL Receive Clock Control
0x4803 8074 0x4803 C074 0x4805 0074 0x4A1A 2074 0x4A1A 8074 0x4A1A E074 AHCLKRCTL High Frequency Receive
Clock Control
0x4803 8078 0x4803 C078 0x4805 0078 0x4A1A 2078 0x4A1A 8078 0x4A1A E078 RXTDM Receive TDM Slot 0-31
0x4803 807C 0x4803 C07C 0x4805 007C 0x4A1A 207C 0x4A1A 807C 0x4A1A EVTCTLR Receiver Interrupt Control
E07C
0x4803 8080 0x4803 C080 0x4805 0080 0x4A1A 2080 0x4A1A 8080 0x4A1A E080 RXSTAT Status Receiver
0x4803 8084 0x4803 C084 0x4805 0084 0x4A1A 2084 0x4A1A 8084 0x4A1A E084 RXTDMSLOT Current Receive TDM Slot
0x4803 8088 0x4803 C088 0x4805 0088 0x4A1A 2088 0x4A1A 8088 0x4A1A E088 RXCLKCHK Receiver Clock Check
Control
0x4803 808C 0x4803 C08C 0x4805 008C 0x4A1A 208C 0x4A1A 808C 0x4A1A REVTCTL Receiver DMA Event Control
E08C
0x4803 80A0 0x4803 C0A0 0x4805 00A0 0x4A1A 20A0 0x4A1A 80A0 0x4A1A E0A0 GBLCTLX Alias of GBLCTL containing
only transmit reset bits;
allows transmit to be reset
independently from receive
0x4803 80A4 0x4803 C0A4 0x4805 00A4 0x4A1A 20A4 0x4A1A 80A4 0x4A1A E0A4 TXMASK Transmit Format Unit Bit
Mask
0x4803 80A8 0x4803 C0A8 0x4805 00A8 0x4A1A 20A8 0x4A1A 80A8 0x4A1A E0A8 TXFMT Transmit Bitstream Format
0x4803 80AC 0x4803 C0AC 0x4805 00AC 0x4A1A 0x4A1A 0x4A1A TXFMCTL Transmit Frame Sync Control
20AC 80AC E0AC
0x4803 80B0 0x4803 C0B0 0x4805 00B0 0x4A1A 20B0 0x4A1A 80B0 0x4A1A E0B0 ACLKXCTL Transmit Clock Control
0x4803 80B4 0x4803 C0B4 0x4805 00B4 0x4A1A 20B4 0x4A1A 80B4 0x4A1A E0B4 AHCLKXCTL High Frequency Transmit
Clock Control
0x4803 80B8 0x4803 C0B8 0x4805 00B8 0x4A1A 20B8 0x4A1A 80B8 0x4A1A E0B8 TXTDM Transmit TDM Slot 0-31
0x4803 80BC 0x4803 C0BC 0x4805 00BC 0x4A1A 0x4A1A 0x4A1A EVTCTLX Transmitter Interrupt Control
20BC 80BC E0BC
0x4803 80C0 0x4803 C0C0 0x4805 00C0 0x4A1A 20C0 0x4A1A 80C0 0x4A1A TXSTAT Status Transmitter
E0C0
0x4803 80C4 0x4803 C0C4 0x4805 00C4 0x4A1A 20C4 0x4A1A 80C4 0x4A1A TXTDMSLOT Current Transmit TDM Slot
E0C4
0x4803 80C8 0x4803 C0C8 0x4805 00C8 0x4A1A 20C8 0x4A1A 80C8 0x4A1A TXCLKCHK Transmit Clock Check
E0C8 Control
0x4803 80CC 0x4803 0x4805 00CC 0x4A1A 0x4A1A 0x4A1A XEVTCTL Transmitter DMA Control
C0CC 20CC 80CC E0CC
0x4803 80D0 0x4803 C0D0 0x4805 00D0 0x4A1A 20D0 0x4A1A 80D0 0x4A1A CLKADJEN One-shot Clock Adjust
E0D0 Enable

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Table 8-77. McASP0/1/2/3/4/5 Registers (continued)

HEX ADDRESS RANGE
ACRONYM REGISTER NAME
MCASP0 MCASP1 MCASP2 MCASP3 MCASP4 MCASP5
0x4803 8100 0x4803 C100 0x4805 0100 0x4A1A 2100 0x4A1A 8100 Left (Even TDM Slot)
0x4A1A E100 DITCSRA0
Channel Status Register File
0x4803 8104 0x4803 C104 0x4805 0104 0x4A1A 2104 0x4A1A 8104 Left (Even TDM Slot)
0x4A1A E104 DITCSRA1
Channel Status Register File
0x4803 8108 0x4803 C108 0x4805 0108 0x4A1A 2108 0x4A1A 8108 Left (Even TDM Slot)
0x4A1A E108 DITCSRA2
Channel Status Register File
0x4803 810C 0x4803 C10C 0x4805 010C 0x4A1A 210C 0x4A1A 810C 0x4A1A Left (Even TDM Slot)
DITCSRA3
E10C Channel Status Register File
0x4803 8110 0x4803 C110 0x4805 0110 0x4A1A 2110 0x4A1A 8110 Left (Even TDM Slot)
0x4A1A E110 DITCSRA4
Channel Status Register File
0x4803 8114 0x4803 C114 0x4805 0114 0x4A1A 2114 0x4A1A 8114 Left (Even TDM Slot)
0x4A1A E114 DITCSRA5
Channel Status Register File
0x4803 8118 0x4803 C118 0x4805 0118 0x4A1A 2118 0x4A1A 8118 Right (Odd TDM Slot)
0x4A1A E118 DITCSRB0
Channel Status Register File
0x4803 811C 0x4803 C11C 0x4805 011C 0x4A1A 211C 0x4A1A 811C 0x4A1A Right (Odd TDM Slot)
DITCSRB1
E11C Channel Status Register File
0x4803 8120 0x4803 C120 0x4805 0120 0x4A1A 2120 0x4A1A 8120 Right (Odd TDM Slot)
0x4A1A E120 DITCSRB2
Channel Status Register File
0x4803 8124 0x4803 C124 0x4805 0124 0x4A1A 2124 0x4A1A 8124 Right (Odd TDM Slot)
0x4A1A E124 DITCSRB3
Channel Status Register File
0x4803 8128 0x4803 C128 0x4805 0128 0x4A1A 2128 0x4A1A 8128 Right (Odd TDM Slot)
0x4A1A E128 DITCSRB4
Channel Status Register File
0x4803 812C 0x4803 C12C 0x4805 012C 0x4A1A 212C 0x4A1A 812C 0x4A1A Right (Odd TDM Slot)
DITCSRB5
E12C Channel Status Register File
0x4803 8130 0x4803 C130 0x4805 0130 0x4A1A 2130 0x4A1A 8130 Left (Even TDM Slot) User
0x4A1A E130 DITUDRA0
Data Register File
0x4803 8134 0x4803 C134 0x4805 0134 0x4A1A 2134 0x4A1A 8134 Left (Even TDM Slot) User
0x4A1A E134 DITUDRA1
Data Register File
0x4803 8138 0x4803 C138 0x4805 0138 0x4A1A 2138 0x4A1A 8138 Left (Even TDM Slot) User
0x4A1A E138 DITUDRA2
Data Register File
0x4803 813C 0x4803 C13C 0x4805 013C 0x4A1A 213C 0x4A1A 813C 0x4A1A Left (Even TDM Slot) User
DITUDRA3
E13C Data Register File
0x4803 8140 0x4803 C140 0x4805 0140 0x4A1A 2140 0x4A1A 8140 Left (Even TDM Slot) User
0x4A1A E140 DITUDRA4
Data Register File
0x4803 8144 0x4803 C144 0x4805 0144 0x4A1A 2144 0x4A1A 8144 Left (Even TDM Slot) User
0x4A1A E144 DITUDRA5
Data Register File
0x4803 8148 0x4803 C148 0x4805 0148 0x4A1A 2148 0x4A1A 8148 Right (Odd TDM Slot) User
0x4A1A E148 DITUDRB0
Data Register File
0x4803 814C 0x4803 C14C 0x4805 014C 0x4A1A 214C 0x4A1A 814C 0x4A1A Right (Odd TDM Slot) User
DITUDRB1
E14C Data Register File
0x4803 8150 0x4803 C150 0x4805 0150 0x4A1A 2150 0x4A1A 8150 Right (Odd TDM Slot) User
0x4A1A E150 DITUDRB2
Data Register File
0x4803 8154 0x4803 C154 0x4805 0154 0x4A1A 2154 0x4A1A 8154 Right (Odd TDM Slot) User
0x4A1A E154 DITUDRB3
Data Register File
0x4803 8158 0x4803 C158 0x4805 0158 0x4A1A 2158 0x4A1A 8158 Right (Odd TDM Slot) User
0x4A1A E158 DITUDRB4
Data Register File
0x4803 815C 0x4803 C15C 0x4805 015C 0x4A1A 215C 0x4A1A 815C 0x4A1A Right (Odd TDM Slot) User
DITUDRB5
E15C Data Register File
0x4803 8180 0x4803 C180 0x4805 0180 0x4A1A 2180 0x4A1A 8180 0x4A1A E180 XRSRCTL0 - Serializer 0 Control -
- - - - - - XRSRCTL15 Serializer 15 Control
0x4803 81BC 0x4803 C1BC 0x4805 01BC 0x4A1A 0x4A1A 0x4A1A
21BC 81BC E1BC
0x4803 8200 0x4803 C200 0x4805 0200 0x4A1A 2200 0x4A1A 8200 0x4A1A E200 TXBUF0 - Transmit Buffer for Serializer
- - - - - - TXBUF15 0 - Transmit Buffer for
0x4803 8 0x4803 C23C 0x4805 023C 0x4A1A 223C 0x4A1A 823C 0x4A1A Serializer 15
23C E23C

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Table 8-77. McASP0/1/2/3/4/5 Registers (continued)

HEX ADDRESS RANGE
ACRONYM REGISTER NAME
MCASP0 MCASP1 MCASP2 MCASP3 MCASP4 MCASP5
0x4803 8280 0x4803 C280 0x4805 0280 0x4A1A 2280 0x4A1A 8280 0x4A1A E280 RXBUF0 - Receive Buffer for Serializer
- - - - - - RXBUF15 0 - Receive Buffer for
0x4803 82BC 0x4803 C2BC 0x4805 02BC 0x4A1A 0x4A1A 0x4A1A Serializer 15
22BC 82BC E2BC
0x4803 9000 0x4803 D000 0x4805 1000 0x4A1A 3000 0x4A1A 9000 0x4A1A F000 BUFFER_CF Write FIFO Control
GRD_WFIFO
CTL
0x4803 9004 0x4803 D004 0x4805 1004 0x4A1A 3004 0x4A1A 9004 0x4A1A F004 BUFFER_CF Write FIFO Status
GRD_WFIFO
STS
0x4803 9008 0x4803 D008 0x4805 1008 0x4A1A 3008 0x4A1A 9008 0x4A1A F008 BUFFER_CF Read FIFO Control
GRD_RFIFO
CTL
0x4803 900C 0x4803 D00C 0x4805 100C 0x0A1A 300C 0x0A1A 900C 0x0A1A F00C BUFFER_CF Read FIFO Status
GRD_RFIFO
STS
0x4803 9010 0x4803 D010 0x4805 1010 0x4A1A 3010 0x4A1A 9010 0x4A1A F010 – Reserved
- - - - - -
0x4803 9FFF 0x4803 DFFF 0x4805 1FFF 0x4A1A 3FFF 0x4A1A 9FFF 0x4A1A FFFF

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8.14.3 McASP (McASP[5:0]) Electrical Data/Timing

Table 8-78. Timing Requirements for McASP (1)

(see Figure 8-81)
OPP100/120/166
NO. McASP[5:2,0] Only McASP1 Only UNIT
MIN MAX MIN MAX
1 tc(AHCLKRX) Cycle time, MCA[x]_AHCLKR/X 20 20 ns
2 tw(AHCLKRX) Pulse duration, MCA[x]_AHCLKR/X high or low 0.5P - 3 (2) 0.5P - 3 (2) ns
Any Other
20 20 ns
Conditions
3 tc(ACLKRX) Cycle time, MCA[x]_ACLKR/X ACLKx, AFSX
and AXR are all – 12.5 ns
inputs
Any Other
0.5R - 3 (3) 0.5R - 3 (3) ns
Conditions
Pulse duration, MCA[x]_ACLKR/X high
4 tw(ACLKRX) ACLKx, AFSX
or low 0.5R -
and AXR are all – ns
1.5 (3)
inputs
ACLKR/X int 10.5 10.5
tsu(AFSRX- Setup time, MCA[x]_AFSR/X input
5 ACLKR/X ext in 4 2 ns
ACLKRX) valid before MCA[X]_ACLKR/X
ACLKR/X ext out 4 2
ACLKR/X int -1 -1
th(ACLKRX- Hold time, MCA[x]_AFSR/X input valid
6 ACLKR/X ext in 1 2 ns
AFSRX) after MCA[X]_ACLKR/X
ACLKR/X ext out 1 2
ACLKR/X int 10.5 10.5
Setup time, MCA[x]_AXR input valid
7 tsu(AXR-ACLKRX) ACLKR/X ext in 4 2 ns
before MCA[X]_ACLKR/X
ACLKR/X ext out 4 2
ACLKR/X int -1 -1
Hold time, MCA[x]_AXR input valid
8 th(ACLKRX-AXR) ACLKR/X ext in 1 2 ns
after MCA[X]_ACLKR/X
ACLKR/X ext out 1 2
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = MCA[x]_AHCLKR/X period in nano seconds (ns).
(3) R = MCA[x]_ACLKR/X period in ns.

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2
1
2
MCA[x]_ACLKR/X (Falling Edge Polarity)

MCA[x]_AHCLKR/X (Rising Edge Polarity)

4
3 4
(A)
MCA[x]_ACLKR/X (CLKRP = CLKXP = 0)

(B)
MCA[x]_ACLKR/X (CLKRP = CLKXP = 1)

6
5
MCA[x]_AFSR/X (Bit Width, 0 Bit Delay)

MCA[x]_AFSR/X (Bit Width, 1 Bit Delay)

MCA[x]_AFSR/X (Bit Width, 2 Bit Delay)

MCA[x]_AFSR/X (Slot Width, 0 Bit Delay)

MCA[x]_AFSR/X (Slot Width, 1 Bit Delay)

MCA[x]_AFSR/X (Slot Width, 2 Bit Delay)

8
7
MCA[x]_AXR[x] (Data In/Receive)

A0 A1 A30 A31 B0 B1 B30 B31 C0 C1 C2 C3 C31

A. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
B. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).

Figure 8-81. McASP Input Timing

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Table 8-79. Switching Characteristics Over Recommended Operating Conditions for McASP (1)
(see Figure 8-82)
OPP100/120/166
NO. PARAMETER UNIT
MIN MAX
9 tc(AHCLKRX) Cycle time, MCA[X]_AHCLKR/X 20 (2) ns
0.5P -
10 tw(AHCLKRX) Pulse duration, MCA[X]_AHCLKR/X high or low ns
2.5 (3)
11 tc(ACLKRX) Cycle time, MCA[X]_ACLKR/X 20 ns
0.5P -
12 tw(ACLKRX) Pulse duration, MCA[X]_ACLKR/X high or low ns
2.5 (3)
Delay time, MCA[X]_ACLKR/X transmit edge to ACLKR/X int -2 5
MCA[X]_AFSR/X output valid ACLKR/X ext in 1 11.5
13 td(ACLKRX-AFSRX) ns
Delay time, MCA[X]_ACLKR/X transmit edge to
ACLKR/X ext out 1 11.5
MCA[X]_AFSR/X output valid with Pad Loopback
Delay time, MCA[X]_ACLKX transmit edge to ACLKX int -2 5
MCA[X]_AXR output valid ACLKX ext in 1 11.5
14 td(ACLKX-AXR) ns
Delay time, MCA[X]_ACLKX transmit edge to
ACLKX ext out 1 11.5
MCA[X]_AXR output valid with Pad Loopback
Disable time, MCA[X]_ACLKX transmit edge to ACLKX int -2 5
MCA[X]_AXR output high impedance ACLKX ext in 1 11.5
15 tdis(ACLKX-AXR) ns
Disable time, MCA[X]_ACLKX transmit edge to
MCA[X]_AXR output high impedance with Pad ACLKX ext out 1 11.5
Loopback
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) 50 MHz
(3) P = AHCLKR/X period.

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10
9 10

MCA[x]_ACLKR/X (Falling Edge Polarity)

MCA[x]_AHCLKR/X (Rising Edge Polarity)

12
11
12
(A)
MCA[x]_ACLKR/X (CLKRP = CLKXP = 1)

(B)
MCA[x]_ACLKR/X (CLKRP = CLKXP = 0)

13 13
13 13

MCA[x]_AFSR/X (Bit Width, 0 Bit Delay)

MCA[x]_AFSR/X (Bit Width, 1 Bit Delay)

MCA[x]_AFSR/X (Bit Width, 2 Bit Delay)

MCA[x]_AFSR/X (Slot Width, 0 Bit Delay)

13 13 13
MCA[x]_AFSR/X (Slot Width, 1 Bit Delay)

MCA[x]_AFSR/X (Slot Width, 2 Bit Delay)

MCA[x]_AXR[x] (Data Out/Transmit)

14
15

A0 A1 A30 A31 B0 B1 B30 B31 C0 C1 C2 C3 C31

A. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
B. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).

Figure 8-82. McASP Output Timing

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8.15 Multichannel Buffered Serial Port (McBSP)

The McBSP provides these functions:
• Full-duplex communication
• Double-buffered data registers, which allow a continuous data stream
• Independent framing and clocking for receive and transmit
• Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially
connected analog-to-digital (A/D) and digital-to-analog (D/A) devices
• Supports TDM, I2S, and similar formats
• External shift clock or an internal, programmable frequency shift clock for data transfer
• 5KB Tx and Rx buffer
• Supports three interrupt and two DMA requests.
The McBSP module may support two types of data transfer at the system level:
• The full-cycle mode, for which one clock period is used to transfer the data, generated on one edge
and captured on the same edge (one clock period later).
• The half-cycle mode, for which one half clock period is used to transfer the data, generated on one
edge and captured on the opposite edge (one half clock period later). Note that a new data is
generated only every clock period, which secures the required hold time. The interface clock
(CLKX/CLKR) activation edge (data/frame sync capture and generation) has to be configured
accordingly with the external peripheral (activation edge capability) and the type of data transfer
required at the system level.
For more detailed information on the McBSP peripheral, see the Multichannel Buffered Serial Port
(McBSP) chapter of the TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual
(Literature Number: SPRUGZ8).
The following sections describe the timing characteristics for applications in normal mode (that is, the
McBSP connected to one peripheral) and TDM applications in multipoint mode.

8.15.1 McBSP Peripheral Register Descriptions

Table 8-80. McBSP Registers (1)

HEX ADDRESS ACRONYM REGISTER NAME
0x4700 0000 REVNB Revision Number Register
0x4700 0010 SYSCONFIG_REG System Configuration Register
0x4700 0020 EOI End of Interrupt Register
0x4700 0024 IRQSTATUS_RAW Interrupt Status Raw Register
0x4700 0028 IRQSTATUS Interrupt Status Register
0x4700 002C IRQENABLE_SET Interrupt Enable Set Register
0x4700 0030 IRQENABLE_CLR Interrupt Enable Clear Register
0x4700 0034 DMARXENABLE_SET DMA Rx Enable Set Register
0x4700 0038 DMATXENABLE_SET DMA Tx Enable Set Register
0x4700 003C DMARXENABLE_CLR DMA Rx Enable Clear Register
0x4700 0040 DMATXENABLE_CLR DMA Tx Enable Clear Register
0x4700 0048 DMARXWAKE_EN DMA Rx Wake Enable Register
0x4700 004C DMATXWAKE_EN DMA Tx Wake Enable Register
0x4700 0100 DRR_REG McBSP data receive
0x4700 0108 DXR_REG McBSP data transmit
0x4700 0110 SPCR2_REG McBSP serial port control 2
0x4700 0114 SPCR1_REG McBSP serial port control 1

(1) Note that the McBSP registers are 32-bit aligned.

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Table 8-80. McBSP Registers(1) (continued)

HEX ADDRESS ACRONYM REGISTER NAME
0x4700 0118 RCR2_REG McBSP receive control 2
0x4700 011C RCR1_REG McBSP receive control 1
0x4700 0120 XCR2_REG McBSP transmit control 2
0x4700 0124 XCR1_REG McBSP transmit control 1
0x4700 0128 SRGR2_REG McBSP sample rate generator 2
0x4700 012C SRGR1_REG McBSP sample rate generator 1
0x4700 0130 MCR2_REG McBSP multichannel 2
0x4700 0134 MCR1_REG McBSP multichannel 1
0x4700 0138 RCERA_REG McBSP receive channel enable partition A
0x4700 013C RCERB_REG McBSP receive channel enable partition B
0x4700 0140 XCERA_REG McBSP transmit channel enable partition A
0x4700 0144 XCERB_REG McBSP transmit channel enable partition B
0x4700 0148 PCR_REG McBSP pin control
0x4700 014C RCERC_REG McBSP receive channel enable partition C
0x4700 0150 RCERD_REG McBSP receive channel enable partition D
0x4700 0154 XCERC_REG McBSP transmit channel enable partition C
0x4700 0158 XCERD_REG McBSP transmit channel enable partition D
0x4700 015C RCERE_REG McBSP receive channel enable partition E
0x4700 0160 RCERF_REG McBSP receive channel enable partition F
0x4700 0164 XCERE_REG McBSP transmit channel enable partition E
0x4700 0168 XCERF_REG McBSP transmit channel enable partition F
0x4700 016C RCERG_REG McBSP receive channel enable partition G
0x4700 0170 RCERH_REG McBSP receive channel enable partition H
0x4700 0174 XCERG_REG McBSP transmit channel enable partition G
0x4700 0178 XCERH_REG McBSP transmit channel enable partition H
0x4700 017C REV_REG McBSP revision number
0x4700 0180 RINTCLR_REG McBSP receive interrupt clear
0x4700 0184 XINTCLR_REG McBSP transmit interrupt clear
0x4700 0188 ROVFLCLR_REG McBSP receive overflow interrupt clear
0x4700 018C SYSCONFIG_REG McBSP system configuration
0x4700 0190 THRSH2_REG McBSP transmit buffer threshold (DMA or IRQ trigger)
0x4700 0194 THRSH1_REG McBSP receive buffer threshold (DMA or IRQ trigger)
0x4700 01A0 IRQSTATATUS McBSP interrupt status (OCP compliant IRQ line)
0x4700 01A4 IRQENABLE McBSP interrupt enable (OCP compliant IRQ line)
0x4700 01A8 WAKEUPEN McBSP wakeup enable
0x4700 01AC XCCR_REG McBSP transmit configuration control
0x4700 01B0 RCCR_REG McBSP receive configuration control
0x4700 01B4 XBUFFSTAT_REG McBSP transmit buffer status
0x4700 01B8 RBUFFSTAT_REG McBSP receive buffer status
0x4700 01C0 STATUS_REG McBSP status

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8.15.2 McBSP Electrical Data/Timing

Table 8-81. Timing Requirements for McBSP - Master Mode (1)

(see Figure 8-83)
OPP100/120/166
NO. UNIT
MIN MAX
6 tsu(DRV-CLKAE) Setup time, MCB_DR valid before MCB_CLK active edge (2) 3.5 ns
(2)
7 th(CLKAE-DRV) Hold time, MCB_DR valid after MCB_CLK active edge 3.5 ns
(1) The timings apply to all configurations regardless of MCB_CLK polarity and which clock edges are used to drive output data and capture
input data.
(2) MCB_CLK corresponds to either MCB_CLKX or MCB_CLKR.

Table 8-82. Switching Characteristics Over Recommended Operating Conditions for McBSP - Master
Mode (1)
(see Figure 8-83)
OPP100/120/166
NO. PARAMETER UNIT
MIN MAX
1 tc(CLK) Cycle time, output MCB_CLK period (2) 20.83 ns
(2) (3)
2 tw(CLKL) Pulse duration, output MCB_CLK low 0.5*P - 1 ns
3 tw(CLKH) Pulse duration, output MCB_CLK high (2) 0.5*P - 1 (3) ns
Delay time, output MCB_CLK active edge to output MCB_FS
4 td(CLKAE-FSV) 0.3 9.4 ns
valid (2) (4)
Delay time, output MCB_CLKX active edge to output MCB_DX
5 td(CLKXAE-DXV) 0.3 9.4 ns
valid
(1) The timings apply to all configurations regardless of MCB_CLK polarity and which clock edges are used to drive output data and capture
input data.
(2) MCB_CLK corresponds to either MCB_CLKX or MCB_CLKR.
(3) P = MCB_CLKX/MCB_CLKR output CLK period, in ns; use whichever value is greater. This parameter applies to the maximum McBSP
frequency. Operate serial clocks (CLKX/R) in the reasonable range of 40/60 duty cycle.
(4) MCB_FS corresponds to either MCB_FSX or MCB_FSR.

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1 2
3
MCB_CLK

4 4
MCB_FS

5 5 5
MCB_DX MCB_DX7 MCB_DX6 MCB_DX0

7
6
MCB_DR MCB_DR7 MCB_DR6 MCB_DR0

A. The timings apply to all configurations regardless of MCB_CLK polarity and which clock edges are used to drive
output data and capture input data.
B. MCBSP_CLK corresponds to either MCBSP_CLKX or MCBSP_CLKR; MCBSP_FS corresponds to either
MCBSP_FSX or MCBSP_FSR.
McBSP in 6-pin mode: DX and DR as data pins; CLKX, CLKR, FSX and FSR as control pins.
McBSP in 4-pin mode: DX and DR as data pins; CLKX and FSX pins as control pins. The CLKX and FSX pins are
internally looped back via software configuration, respectively to the CLKR and FSR internal signals for data receive.
C. The polarity of McBSP frame synchronization is software configurable.
D. The active clock edge selection of MCBSP_CLK (rising or falling) on which MCBSP_DX data is latched and
MCBSP_DR data is sampled is software configurable.
E. Timing diagrams are for data delay set to 1.
F. For further details about the registers used to configure McBSP, see the Multichannel Buffered Serial Port (McBSP)
chapter of the TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual (Literature Number:
SPRUGZ8).

Figure 8-83. McBSP Master Mode Timing

Table 8-83. Timing Requirements for McBSP - Slave Mode (1)

(see Figure 8-84)
OPP100/120/166
NO. UNIT
MIN MAX
1 tc(CLK) Cycle time, MCB_CLK period (2) 20.83 ns
2 tw(CLKL) Pulse duration, MCB_CLK low (2) 0.5*P - 1 (3) ns
3 tw(CLKH) Pulse duration, MCB_CLK high (2) 0.5*P - 1 (3) ns
(2) (4)
4 tsu(FSV-CLKAE) Setup time, MCB_FS valid before MCB_CLK active edge 3.8 ns
5 th(CLKAE-FSV) Hold time, MCB_FS valid after MCB_CLK active edge (2) (4) 0.5 ns
7 tsu(DRV-CLKAE) Setup time, MCB_DR valid before MCB_CLK active edge (2) 3.8 ns
8 th(CLKAE-DRV) Hold time, MCB_DR valid after MCB_CLK active edge (2) 0.5 ns
(1) The timings apply to all configurations regardless of MCB_CLK polarity and which clock edges are used to drive output data and capture
input data.
(2) MCB_CLK corresponds to either MCB_CLKX or MCB_CLKR.
(3) P = MCB_CLKX/MCB_CLKR output CLK period, in ns; use whichever value is greater. This parameter applies to the maximum McBSP
frequency. Operate serial clocks (CLKX/R) in the reasonable range of 40/60 duty cycle.
(4) MCB_FS corresponds to either MCB_FSX or MCB_FSR.

Table 8-84. Switching Characteristics Over Recommended Operating Conditions for McBSP - Slave
Mode (1)
(see Figure 8-84)
OPP100/120/166
NO. PARAMETER UNIT
MIN MAX
6 td(CLKXAE-DXV) Delay time, input MCB_CLKx active edge to output MCB_DX valid 0.5 12.5 ns
(1) The timings apply to all configurations regardless of MCB_CLK polarity and which clock edges are used to drive output data and capture
input data.

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1 2
3
MCB_CLK
4
5
MCB_FS

6 6 6
MCB_DX MCB_DX7 MCB_DX6 MCB_DX0

8
7
MCB_DR MCB_DR7 MCB_DR6 MCB_DR0

A. The timings apply to all configurations regardless of MCB_CLK polarity and which clock edges are used to drive
output data and capture input data.
B. MCBSP_CLK corresponds to either MCBSP_CLKX or MCBSP_CLKR; MCBSP_FS corresponds to either
MCBSP_FSX or MCBSP_FSR.
McBSP in 6-pin mode: DX and DR as data pins; CLKX, CLKR, FSX and FSR as control pins.
McBSP in 4-pin mode: DX and DR as data pins; CLKX and FSX pins as control pins. The CLKX and FSX pins are
internally looped back via software configuration, respectively to the CLKR and FSR internal signals for data receive.
C. The polarity of McBSP frame synchronization is software configurable.
D. The active clock edge selection of MCBSP_CLK (rising or falling) on which MCBSP_DX data is latched and
MCBSP_DR data is sampled is software configurable.
E. Timing diagrams are for data delay set to 1.
F. For further details about the registers used to configure McBSP, see the Multichannel Buffered Serial Port (McBSP)
chapter of the TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual (Literature Number:
SPRUGZ8).

Figure 8-84. McBSP Slave Mode Timing

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8.16 MultiMedia Card/Secure Digital/Secure Digital Input Output (MMC/SD/SDIO)

The device includes 3 MMC/SD/SDIO Controllers which are compliant with MMC V4.3, Secure Digital Part
1 Physical Layer Specification V2.00 and Secure Digital Input Output (SDIO) V2.00 specifications.
The device MMC/SD/SDIO Controller has the following features:
• MultiMedia card (MMC)
• Secure Digital (SD) memory card
• MMC/SD protocol support
• SDIO protocol support
• Programmable clock frequency
• 1024 byte read/write FIFO to lower system overhead
• Slave EDMA transfer capability
• SD High capacity support

8.16.1 MMC/SD/SDIO Peripheral Register Descriptions

Table 8-85. MMC/SD/SDIO Registers (1)
MMC/SD/SDIO0 MMC/SD/SDIO1 MMC/SD/SDIO2 ACRONYM REGISTER NAME
HEX ADDRESS HEX ADDRESS HEX ADDRESS
0x4806 0000 0x481D 8000 0x4781 0000 MMCHS_HL_REV IP Revision Identifier
0x4806 0004 0x481D 8004 0x4781 0004 MMCHS_HL_HWINF Hardware Configuration
O
0x4806 0010 0x481D 8010 0x4781 0010 MMCHS_HL_SYSCO Clock Management Configuration
NFIG
0x4806 0110 0x481D 8110 0x4781 0110 MMCHS_SYSCONFI System Configuration
G
0x4806 0114 0x481D 8114 0x4781 0114 MMCHS_SYSSTATU System Status
S
0x4806 0124 0x481D 8124 0x4781 0124 MMCHS_CSRE Card status response error
0x4806 0128 0x481D 8128 0x4781 0128 MMCHS_SYSTEST System Test
0x4806 012C 0x481D 812C 0x4781 012C MMCHS_CON Configuration
0x4806 0130 0x481D 8130 0x4781 0130 MMCHS_PWCNT Power counter
0x4806 0200 0x481D 8200 0x4781 0200 MMCHS_SDMASA SDMA System address:
0x4806 0204 0x481D 8204 0x4781 0204 MMCHS_BLK Transfer Length Configuration
0x4806 0208 0x481D 8208 0x4781 0208 MMCHS_ARG Command argument
0x4806 020C 0x481D 820C 0x4781 020C MMCHS_CMD Command and transfer mode
0x4806 0210 0x481D 8210 0x4781 0210 MMCHS_RSP10 Command Response 0 and 1
0x4806 0214 0x481D 8214 0x4781 0214 MMCHS_RSP32 Command Response 2 and 3
0x4806 0218 0x481D 8218 0x4781 0218 MMCHS_RSP54 Command Response 4 and 5
0x4806 021C 0x481D 821C 0x4781 021C MMCHS_RSP76 Command Response 6 and 7
0x4806 0220 0x481D 8220 0x4781 0220 MMCHS_DATA Data
0x4806 0224 0x481D 8224 0x4781 0224 MMCHS_PSTATE Present state
0x4806 0228 0x481D 8228 0x4781 0228 MMCHS_HCTL Host Control
0x4806 022C 0x481D 822C 0x4781 022C MMCHS_SYSCTL SD system control
0x4806 0230 0x481D 8230 0x4781 0230 MMCHS_STAT Interrupt status
0x4806 0234 0x481D 8234 0x4781 0234 MMCHS_IE Interrupt SD enable
0x4806 0238 0x481D 8238 0x4781 0238 MMCHS_ISE Interrupt Signal Enable
0x4806 023C 0x481D 823C 0x4781 023C MMCHS_AC12 Auto CMD12 Error Status
0x4806 0240 0x481D 8240 0x4781 0240 MMCHS_CAPA Capabilities
0x4806 0248 0x481D 8248 0x4781 0248 MMCHS_CUR_CAPA Maximum current capabilities

(1) SD/SDIO registers are limited to 32-bit data accesses; 16-bit and 8-bit accesses are not allowed and can corrupt register content.
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Table 8-85. MMC/SD/SDIO Registers(1) (continued)

MMC/SD/SDIO0 MMC/SD/SDIO1 MMC/SD/SDIO2 ACRONYM REGISTER NAME
HEX ADDRESS HEX ADDRESS HEX ADDRESS
0x4806 0250 0x481D 8250 0x4781 0250 MMCHS_FE Force Event
0x4806 0254 0x481D 8254 0x4781 0254 MMCHS_ADMAES ADMA Error Status
0x4806 0258 0x481D 8258 0x4781 0258 MMCHS_ADMASAL ADMA System address Low bits
0x4806 025C 0x481D 825C 0x4781 025C MMCHS_ADMASAH ADMA System address High bits
0x4806 02FC 0x481D 82FC 0x4781 02FC MMCHS_REV Versions

8.16.2 MMC/SD/SDIO Electrical Data/Timing

Table 8-86. Timing Requirements for MMC/SD/SDIO

(see Figure 8-86, Figure 8-88)
OPP100/120/166
NO
ALL MODES UNIT
.
MIN MAX
1 tsu(CMDV-CLKH) Setup time, SD_CMD valid before SD_CLK rising clock edge 4.1 ns
SD1 1.9
2 th(CLKH-CMDV) Hold time, SD_CMD valid after SD_CLK rising clock edge ns
SD0, SD2 2.9
3 tsu(DATV-CLKH) Setup time, SD_DATx valid before SD_CLK rising clock edge 4.1 ns
SD1 1.9
4 th(CLKH-DATV) Hold time, SD_DATx valid after SD_CLK rising clock edge ns
SD0, SD2 2.9

Table 8-87. Switching Characteristics Over Recommended Operating Conditions for MMC/SD/SDIO
(see Figure 8-85 through Figure 8-88)
OPP100/120/166
MODES
NO. PARAMETER 3.3 V STD 3.3 V HS UNIT
1.8 V SDR12 1.8 V SDR25
MIN MAX MIN MAX
fop(CLK) Operating frequency, SD_CLK 24 48 MHz
7
tc(CLK) Operating period: SD_CLK 41.7 20.8 ns
fop(CLKID) Identification mode frequency, SD_CLK 400 400 kHz
8
tc(CLKID) Identification mode period: SD_CLK 2500.0 2500.0 ns
9 tw(CLKL) Pulse duration, SD_CLK low 0.5*P (1) 0.5*P (1) ns
(1) (1)
10 tw(CLKH) Pulse duration, SD_CLK high 0.5*P 0.5*P ns
11 tr(CLK) Rise time, All Signals (10% to 90%) 2.2 2.2 ns
12 tf(CLK) Fall time, All Signals (10% to 90%) 2.2 2.2 ns
Delay time, SD_CLK rising clock edge to SD_CMD
13 td(CLKL-CMD) 1.5 10 1.5 10 ns
transition
Delay time, SD_CLK rising clock edge to SD_DATx
14 td(CLKL-DAT) 1.5 10 1.5 10 ns
transition
(1) P = SD_CLK period.

10
7 9
SDx_CLK
13 13 13 13
START XMIT Valid Valid Valid END
SDx_CMD

Figure 8-85. MMC/SD/SDIO Host Command Timing

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9
7 10

SDx_CLK
1
2

SDx_CMD START XMIT Valid Valid Valid END

Figure 8-86. MMC/SD/SDIO Card Response Timing

10
7 9
SDx_CLK

14 14 14 14
START D0 D1 Dx END
SDx_DAT[x]

Figure 8-87. MMC/SD/SDIO Host Write Timing

9
7 10

SDx_CLK
4 4
3 3
SDx_DAT[x] Start D0 D1 Dx End

Figure 8-88. MMC/SD/SDIO Host Read and Card CRC Status Timing

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8.17 Peripheral Component Interconnect Express (PCIe)

The device supports connections to PCIe-compliant devices via the integrated PCIe master/slave bus
interface. The PCIe module is comprised of a dual-mode PCIe core and a SerDes PHY. The device
implements a single one-lane PCIe 2.0 (5.0 GT/s) Endpoint/Root Complex port.
The device PCIe supports the following features:
• Supports Gen1/Gen2 in x1 or x2 mode
• One port with one 5 GT/s lane
• Single virtual channel (VC), single traffic class (TC)
• Single function in end-point mode
• Automatic width and speed negotiation and lane reversal
• Max payload: 128 byte outbound, 256 byte inbound
• Automatic credit management
• ECRC generation and checking
• Configurable BAR filtering
• Supports PCIe messages
• Legacy interrupt reception (RC) and generation (EP)
• MSI generation and reception
• PCI device power management, except D3 cold with vaux
• Active state power management state L0 and L1.
For more detailed information on the PCIe port peripheral module, see the PCI Express (PCIe) Module
chapter of the TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual (Literature
Number: SPRUGZ8).
The PCIe peripheral on the device conforms to the PCI Express Base 2.0 Specification.

8.17.1 PCIe Peripheral Register Descriptions

Table 8-88. PCIe Registers

HEX ADDRESS ACRONYM REGISTER NAME
0x5100 0000 PID Peripheral Version and ID
0x5100 0004 CMD_STATUS Command Status
0x5100 0008 CFG_SETUP Config Transaction Setup
0x5100 000C IOBASE IO TLP Base
0x5100 0010 TLPCFG TLP Attribute Configuration
0x5100 0014 RSTCMD Reset Command and Status
0x5100 0020 PMCMD Power Management Command
0x5100 0024 PMCFG Power Management Configuration
0x5100 0028 ACT_STATUS Activity Status
0x5100 0030 OB_SIZE Outbound Size
0x5100 0034 DIAG_CTRL Diagnostic Control
0x5100 0038 ENDIAN Endian Mode
0x5100 003C PRIORITY CBA Transaction Priority
0x5100 0050 IRQ_EOI End of Interrupt
0x5100 0054 MSI_IRQ MSI Interrupt IRQ
0x5100 0064 EP_IRQ_SET Endpoint Interrupt Request Set
0x5100 0068 EP_IRQ_CLR Endpoint Interrupt Request Clear
0x5100 006C EP_IRQ_STATUS Endpoint Interrupt Status
0x5100 0070 GPRO General Purpose 0

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Table 8-88. PCIe Registers (continued)

HEX ADDRESS ACRONYM REGISTER NAME
0x5100 0074 GPR1 General Purpose 1
0x5100 0078 GPR2 General Purpose 2
0x5100 007C GPR3 General Purpose 3
0x5100 0100 MSI0_IRQ_STATUS_RAW MSI 0 Interrupt Raw Status
0x5100 0104 MSI0_IRQ_STATUS MSI 0 Interrupt Enabled Status
0x5100 0108 MSI0_IRQ_ENABLE_SET MSI 0 Interrupt Enable Set
0x5100 010C MSI0_IRQ_ENABLE_CLR MSI 0 Interrupt Enable Clear
0x5100 0180 IRQ_STATUS_RAW Raw Interrupt Status
0x5100 0184 IRQ_STATUS Interrupt Enabled Status
0x5100 0188 IRQ_ENABLE_SET Interrupt Enable Set
0x5100 018C IRQ_ENABLE_CLR Interrupt Enable Clear
0x5100 01C0 ERR_IRQ_STATUS_RAW Raw ERR Interrupt Status
0x5100 01C4 ERR_IRQ_STATUS ERR Interrupt Enabled Status
0x5100 01C8 ERR_IRQ_ENABLE_SET ERR Interrupt Enable Set
0x5100 01CC ERR_IRQ_ENABLE_CLR ERR Interrupt Enable Clear
0x5100 01D0 PMRST_IRQ_STATUS_RAW Power Management and Reset Interrupt Status
0x5100 01D4 PMRST_IRQ_STATUS Power Management and Reset Interrupt Enabled Status
0x5100 01D8 PMRST_ENABLE_SET Power Management and Reset Interrupt Enable Set
0x5100 01DC PMRST_ENABLE_CLR Power Management and Reset Interrupt Enable Clear
0x5100 0200 OB_OFFSET_INDEXn Outbound Translation Region N Offset Low and Index
0x5100 0204 OB_OFFSETn_HI Outbound Translation Region N Offset High
0x5100 0300 IB_BAR0 Inbound Translation Bar Match 0
0x5100 0304 IB_START0_LO Inbound Translation 0 Start Address Low
0x5100 0308 IB_START0_HI Inbound Translation 0 Start Address High
0x5100 030C IB_OFFSET0 Inbound Translation 0 Address Offset
0x5100 0310 IB_BAR1 Inbound Translation Bar Match 1
0x5100 0314 IB_START1_LO Inbound Translation 1 Start Address Low
0x5100 0318 IB_START1_HI Inbound Translation 1 Start Address High
0x5100 031C IB_OFFSET1 Inbound Translation 1 Address Offset
0x5100 0320 IB_BAR2 Inbound Translation Bar Match 2
0x5100 0324 IB_START2_LO Inbound Translation 2 Start Address Low
0x5100 0328 IB_START2_HI Inbound Translation 2 Start Address High
0x5100 032C IB_OFFSET2 Inbound Translation 2 Address Offset
0x5100 0330 IB_BAR3 Inbound Translation Bar Match 3
0x5100 0334 IB_START3_LO Inbound Translation 3 Start Address Low
0x5100 0338 IB_START3_HI Inbound Translation 3 Start Address High
0x5100 033C IB_OFFSET3 Inbound Translation 3 Address Offset
0x5100 0380 PCS_CFG0 PCS Configuration 0
0x5100 0384 PCS_CFG1 PCS Configuration 1
0x5100 0388 PCS_STATUS PCS Status
0x5100 038C SERDES_STATUS SerDes Status
0x5100 0390 SERDES_RXCFG0 SerDes Receive Configuration 0 Register
0x5100 0394 SERDES_RXCFG1 SerDes Receive Configuration 1 Register
0x5100 0398 SERDES_RXCFG2 SerDes Receive Configuration 2 Register
0x5100 039C SERDES_RXCFG3 SerDes Receive Configuration 3 Register
0x5100 03A0 SERDES_RXCFG4 SerDes Receive Configuration 4 Register
0x5100 03A4 SERDES_TXCFG0 SerDes Transmit Configuration 0 Register

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Table 8-88. PCIe Registers (continued)

HEX ADDRESS ACRONYM REGISTER NAME
0x5100 03A8 SERDES_TXCFG1 SerDes Transmit Configuration 1 Register
0x5100 03AC SERDES_TXCFG2 SerDes Transmit Configuration 2 Register
0x5100 03B0 SERDES_TXCFG3 SerDes Transmit Configuration 3 Register
0x5100 03B4 SERDES_TXCFG4 SerDes Transmit Configuration 4 Register

Table 8-89. Configuration Registers Type 0 Summary

HEX ADDRESS ACRONYM NAME
5100_1000 VENDOR_DEVICE Vendor Device ID Register
_ID
5100_1004 STATUS_COMMA Status and Command
ND Register
5100_1008 CLASSCODE_RE Class Code and Revision
VID Register
5100_100C BIST_HEADER BIST, Header Type, Latency
Time, and Cache Line Size
register
5100_1010 BAR0 (64/-32-Bit Base Address Register 0
Mode)
5100_1014 BAR1 (32-Bit Base Address Register 1
Mode)
BAR1 (64-Bit Base Address Register 1 (64-
Mode) bit BAR0)
5100_1018 BAR2 (64/-32-Bit Base Address Register 2
Mode)
5100_101C BAR3 (32-Bit Base Address Register 3
Mode)
BAR3 (64-Bit Base Address Register 3 (64-
Mode) bit BAR2)
5100_1020 BAR4 (64/-32-Bit Base Address Register 4
Mode)
5100_1024 BAR5 (32-Bit Base Address Register 5
Mode)
BAR5 (64-Bit Base Address Register 5 (64-
Mode) bit BAR4)
5100_1028 CARDBUS CardBus CIS Pointer
Register
5100_102C SUBSYS_VNDR_I Subsystem and Subsystem
D Vendor ID Register
5100_1030 EXPNSN_ROM Expansion ROM Base
Address Register
5100_1034 CAP_PTR Capabilities Pointer Register
5100_103C INT_PIN Interrupt Pin Register

Table 8-90. Configuration Registers Type 1 Summary

HEX ADDRESS ACRONYM NAME
5100_1000 VENDOR_DEVICE_ID Vendor Device ID Register
5100_1004 STATUS_COMMAND Status and Command Register
5100_1008 CLASSCODE_REVID Class Code and Revision Register
5100_100C BIST_HEADER BIST, Header Type, Latency Time, and Cache Line Size
register
5100_1010 BAR0 (64/-32-Bit Mode) Base Address Register 0 (64/32-bit mode)

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Table 8-90. Configuration Registers Type 1 Summary (continued)

HEX ADDRESS ACRONYM NAME
5100_1014 BAR1 (32-Bit Mode) Base Address Register 1 (32-bit mode)
BAR1 (64-Bit Mode) Base Address Register 1 (64-bit BAR0)
5100_1018 BUSNUM Latency Timer and Bus Number Register
5100_101C SECSTAT Secondary Status and I/O Base/Limit Register
5100_1020 MEMSPACE Memory Limit and Base Register
5100_1024 PREFETCH_MEM Prefetchable Memory Limit and Base Register
5100_1028 PREFETCH_BASE Prefetchable Memory Base Upper 32-bits Register
5100_102C PREFETCH_LIMIT Prefetchable Limit Upper 32-bits Register
5100_1030 IOSPACE I/O Base and Limit Upper 16-bits Register
5100_1034 CAP_PTR Capabilities Pointer Register
5100_1038 EXPNSN_ROM Expansion ROM Base Address Register
5100_103C BRIDGE_INT Bridge Control Register

Table 8-91. Power Management Capability Register Summary

HEX ADDRESS ACRONYM NAME
5100_1040 PMCAP Power Management Capability Register
5100_1044 PM_CTL_STAT Power Management Control and Status Register

Table 8-92. Message Signaled Interrupts (MSI) Register Summary

HEX ADDRESS ACRONYM NAME
5100_1050 MSI_CAP MSI Capabilities Register
5100_1054 MSI_LOW32 MSI Lower 32 bits Register
5100_1058 MSI_UP32 MSI Upper 32 bits Register
5100_105C MSI_DATA MSI Data Register

Table 8-93. PCI Express Capabilities Register Summary

HEX ADDRESS ACRONYM NAME
5100_1070 PCIES_CAP PCI Express Capabilities Register
5100_1074 DEVICE_CAP Device Capabilities Register
5100_1078 DEV_STAT_CTRL Device Status and Control Register
5100_107C LINK_CAP Link Capabilities Register
5100_1080 LINK_STAT_CTRL Link Status and Control Register
5100_1084 SLOT_CAP Slot Capabilities Register (RC Mode Only)
5100_1088 SLOT_STAT_CTRL Slot Status and Control Register (RC Mode Only)
5100_108C ROOT_CTRL_CAP Root Control and Capabilities Register (RC Mode Only)
5100_1090 ROOT_STATUS Root Status and Control Register (RC Mode Only)
5100_1094 DEV_CAP2 Device Capabilities 2 Register
5100_1098 DEV_STAT_CTRL2 Device Status and Control 2 Register
5100_10A0 LINK_CTRL2 Link Control 2 Register

Table 8-94. PCI Express Extended Capabilities Register Summary

HEX ADDRESS ACRONYM NAME
5100_1100 PCIE_EXTCAP PCI Express Extended Capabilities Header Register
5100_1104 PCIE_UNCERR PCI Express Uncorrectable Error Status Register
5100_1108 PCIE_UNCERR_MASK PCI Express Uncorrectable Error Mask Register
5100_110C PCIE_UNCERR_SVRTY PCI Express Uncorrectable Error Severity Register

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Table 8-94. PCI Express Extended Capabilities Register Summary (continued)

HEX ADDRESS ACRONYM NAME
5100_1110 PCIE_CERR PCI Express Correctable Error Status Register
5100_1114 PCIE_CERR_MASK PCI Express Correctable Error Mask Register
5100_1118 PCIE_ACCR PCI Express Advanced Capabilities and Control Register
5100_111C HDR_LOG0 Header Log 0 Register
5100_1120 HDR_LOG1 Header Log 1 Register
5100_1124 HDR_LOG2 Header Log 2 Register
5100_1128 HDR_LOG3 Header Log 3 Register
5100_112C RC_ERR_CMD Root Error Command Register
5100_1130 RC_ERR_ST Root Error Status Register
5100_1134 ERR_SRC_ID Error Source Identification Register

Table 8-95. Port Logic Register Summary

HEX ADDRESS ACRONYM NAME
5100_1700 PL_ACKTIMER Ack Latency Time and Replay Timer Register
5100_1704 PL_OMSG Other Message Register
5100_1708 PL_FORCE_LINK Port Force Link Register
5100_170C ACK_FREQ Ack Frequency Register
5100_1710 PL_LINK_CTRL Port Link Control Register
5100_1714 LANE_SKEW Lane Skew Register
5100_1718 SYM_NUM Symbol Number Register
5100_171C SYMTIMER_FLTMASK Symbol Timer and Filter Mask Register
5100_1720 FLT_MASK2 Filter Mask 2 Register
5100_1728 DEBUG0 Debug 0 Register
5100_172C DEBUG1 Debug 1 Register
5100_180C PL_GEN2 Gen2 Register

8.17.2 PCIe Electrical Data/Timing

Texas Instruments (TI) has performed the simulation and system characterization to ensure that the PCIe
peripheral meets all AC timing specifications as required by the PCI Express Base 2.0 Specification.
Therefore, the AC timing specifications are not reproduced here. For more information on the AC timing
specifications, see Sections 4.3.3.5 and 4.3.4.4 of the PCI Express Base 2.0 Specification.

8.17.3 PCIe Design and Layout Guidelines

8.17.3.1 Clock Source

A standard 100-MHz PCIe differential clock source must be used for PCIe operation (for more details, see
Section 7.4.2, SERDES CLKN/P Input Clock).

8.17.3.2 PCIe Connections and Interface Compliance

The PCIe interface on the device is compliant with the PCI Express Base 2.0 Specification. Refer to the
PCIe specifications for all connections that are described in it. For coupling capacitor selection, see
Section 8.17.3.2.1, Coupling Capacitors.
The use of PCIe-compatible bridges and switches is allowed for interfacing with more than one other
processor or PCIe device.

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8.17.3.2.1 Coupling Capacitors

AC coupling capacitors are required on the transmit data pair. Table 8-96 shows the requirements for
these capacitors.

Table 8-96. AC Coupling Capacitors Requirements

PARAMETER MIN TYP MAX UNIT
PCIe AC coupling capacitor value 75 200 nF
PCIe AC coupling capacitor package size (1) 0402 0603 EIA (2)
(1) The physical size of the capacitor should be as small as practical. Use the same size on both lines in each pair, placed side by side.
(2) EIA LxW units; that is, a 0402 is a 40x20 mil (thousandths of an inch) surface-mount capacitor.

8.17.3.2.2 Polarity Inversion

The PCIe specification requires polarity inversion support. This means, for layout purposes, polarity is
unimportant since each signal can change its polarity on-die inside the chip. This means polarity within a
lane is unimportant for layout.

8.17.3.3 Non-Standard PCIe Connections

The following sections contain suggestions for any PCIe connection that is not described in the official
PCIe specification, such as an on-board device-to-device connection, or device-to-other PCIe-compliant
processor connection.

8.17.3.3.1 PCB Stackup Specifications

Table 8-97 shows the stackup and feature sizes required for these types of PCIe connections.

Table 8-97. PCIe PCB Stackup Specifications

PARAMETER MIN TYP MAX UNIT
PCB Routing/Plane Layers 4 6 - Layers
Signal Routing Layers 2 3 - Layers
Number of ground plane cuts allowed within PCIe routing region - - 0 Cuts
Number of layers between PCIe routing area and reference plane (1) - - 0 Layers
PCB Routing clearance - 4 - Mils
PCB Trace width (2) - 4 - Mils
PCB BGA escape via pad size - 20 - Mils
PCB BGA escape via hole size - 10 Mils
(3) (4)
Processor BGA pad size 0.4 mm
(1) A reference plane may be a ground plane or the power plane referencing the PCIe signals.
(2) In breakout area.
(3) Non-solder mask defined pad.
(4) Per IPC-7351A BGA pad size guideline.

8.17.3.3.2 Routing Specifications

The PCIe data signal traces must be routed to achieve 100 Ω (±20%) differential impedance and 60 Ω
(±15%) single-ended impedance. The single-ended impedance is required because differential signals are
extremely difficult to closely couple on PCBs and, therefore, single-ended impedance becomes important.
These requirements are the same as those recommended in the PCIe Motherboard Checklist 1.0
document, available from PCI-SIG.
These impedances are impacted by trace width, trace spacing, distance between signals and referencing
planes, and dielectric material. Verify with a PCB design tool that the trace geometry for both data signal
pairs result in as close to 100 Ω differential impedance and 60 Ω single-ended impedance as possible. For
best accuracy, work with your PCB fabricator to ensure this impedance is met.

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In general, closely coupled differential signal traces are not an advantage on PCBs. When differential
signals are closely coupled, tight spacing and width control is necessary. Very small width and spacing
variations affect impedance dramatically, so tight impedance control can be more problematic to maintain
in production.
Loosely coupled PCB differential signals make impedance control much easier. Wider traces and spacing
make obstacle avoidance easier, and trace width variations do not affect impedance as much; therefore, it
is easier to maintain an accurate impedance over the length of the signal. The wider traces also show
reduced skin effect and, therefore, often result in better signal integrity.
Table 8-98 shows the routing specifications for the PCIe data signals.

Table 8-98. PCIe Routing Specifications

PARAMETER MIN TYP MAX UNIT
PCIe signal trace length 10 (1) Inches
Differential pair trace matching 10 (2) Mils
Number of stubs allowed on PCIe traces (3) 0 Stubs
TX/RX pair differential impedance 80 100 120 Ω
TX/RX single ended impedance 51 60 69 Ω
Pad size of vias on PCIe trace 25 (4) Mils
Hole size of vias on PCIe trace 14 Mils
Number of vias on each PCIe trace 3 Vias (5)
PCIe differential pair to any other trace spacing 2*DS (6)
(1) Beyond this, signal integrity may suffer.
(2) For example, RXP0 within 10 Mils of RXN0.
(3) In-line pads may be used for probing.
(4) 35-Mil antipad max recommended.
(5) Vias must be used in pairs with their distance minimized.
(6) DS = differential spacing of the PCIe traces.

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8.18 Serial ATA Controller (SATA)

The Serial ATA (SATA) peripheral provides a direct interface to one hard disk drive (SATA 300) or up to
15 hard disk drives using a Port Multiplier and supports the following features:
• Serial ATA 1.5 Gbps and 3 Gbps speeds
• Integrated PHY
• Integrated Rx and Tx data buffers
• Supports all SATA power management features
• Hardware-assisted native command queuing (NCQ) for up to 32 entries
• Supports port multiplier with command-based switching
• Activity LED support.

8.18.1 SATA Peripheral Register Descriptions

Table 8-99. SATA Registers

HEX ADDRESS ACRONYM REGISTER NAME
0x4A14 0000 CAP HBA Capabilities
0x4A14 0004 GHC Global HBA Control
0x4A14 0008 IS Interrupt Status
0x4A14 000C PI Ports Implemented
0x4A14 0010 VS AHCI Version
0x4A14 0014 CCC_CTL Command Completion Coalescing Control
0x4A14 0018 CCC_PORTS Command Completion Coalescing Ports
0x4A14 001C - 0x4A14 009C - Reserved
0x4A14 00A0 BISTAFR BIST Active FIS
0x4A14 00A4 BISTCR BIST Control
0x4A14 00A8 BISTFCTR BIST FIS Count
0x4A14 00AC BISTSR BIST Status
0x4A14 00B0 BISTDECR BIST DWORD Error Count
0x4A14 00B4 - 0x4A14 00DF - Reserved
0x4A14 00E0 TIMER1MS BIST DWORD Error Count
0x4A14 00E4 - Reserved
0x4A14 00E8 GPARAM1R Global Parameter 1
0x4A14 00EC GPARAM2R Global Parameter 2
0x4A14 00F0 PPARAMR Port Parameter
0x4A14 00F4 TESTR Test
0x4A14 00F8 VERSIONR Version
0x4A14 00FC IDR (PID) ID
0x4A14 0100 P0CLB Port 0 Command List Base Address
0x4A14 0104 - Reserved
0x4A14 0108 P0FB Port 0 FIS Base Address
0x4A14 010C - Reserved
0x4A14 0110 P0IS Port 0 Interrupt Status
0x4A14 0114 P0IE Port 0 Interrupt Enable
0x4A14 0118 P0CMD Port 0 Command
0x4A14 011C - Reserved
0x4A14 0120 P0TFD Port 0 Task File Data
0x4A14 0124 P0SIG Port 0 Signature
0x4A14 0128 P0SSTS Port 0 Serial ATA Status (SStatus)

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Table 8-99. SATA Registers (continued)

HEX ADDRESS ACRONYM REGISTER NAME
0x4A14 012C P0SCTL Port 0 Serial ATA Control (SControl)
0x4A14 0130 P0SERR Port 0 Serial ATA Error (SError)
0x4A14 0134 P0SACT Port 0 Serial ATA Active (SActive)
0x4A14 0138 P0CI Port 0 Command Issue
0x4A14 013C P0SNTF Port 0 Serial ATA Notification
0x4A14 0140 - 0x4A14 016C - Reserved
0x4A14 0170 P0DMACR Port 0 DMA Control
0x4A14 0174 - 0x4A14 017C - Reserved
0x4A14 0180 - 0x4A14 01FC - Reserved
0x4A14 1100 IDLE Idle and Standby Modes
0x4A14 1104 CFGRX0 PHY Configuration Receive 0 Register
0x4A14 1108 CFGRX1 PHY Configuration Receive 1 Register
0x4A14 110C CFGRX2 PHY Configuration Receive 2 Register
0x4A14 1110 CFGRX3 PHY Configuration Receive 3 Register
0x4A14 1114 CFGRX4 PHY Configuration Receive 4 Register
0x4A14 1118 STSRX Receive Bus PHY-to-Controller Status Register (Used for
Debug Purposes)
0x4A14 111C CFGTX0 PHY Configuration Transmit 0 Register
0x4A14 1120 CFGTX1 PHY Configuration Transmit 1 Register
0x4A14 1124 CFGTX2 PHY Configuration Transmit 2 Register
0x4A14 1128 CFGTX3 PHY Configuration Transmit 3 Register
0x4A14 112C CFGTX4 PHY Configuration Transmit 4 Register
0x4A14 1130 STSTX Transmit Bus Controller-to-PHY Status Register (Used for
Debug Purposes)

8.18.2 SATA Interface Design Guidelines

This section provides PCB design and layout guidelines for the SATA interface. The design rules constrain
PCB trace length, PCB trace skew, signal integrity, cross-talk, and signal timing. Simulation and system
design work has been done to ensure the SATA interface requirements are met.
A standard 100-MHz differential clock source must be used for SATA operation (for details, see
Section 7.4.2, SERDES_CLKN/P Input Clock).

8.18.2.1 SATA Interface Schematic

Figure 8-89 shows the data portion of the SATA interface schematic. The specific pin numbers can be
obtained from Table 3-26, Serial ATA Terminal Functions.

SATA Interface (Processor) SATA Connector

10 nF
SATA_TXN0 TX-
SATA_TXP0 TX+
10 nF
10 nF
SATA_RXN0 RX-
SATA_RXP0 RX+
10 nF

Figure 8-89. SATA Interface High-Level Schematic

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8.18.2.2 Compatible SATA Components and Modes

Table 8-100 shows the compatible SATA components and supported modes. Note that the only supported
configuration is an internal cable from the processor host to the SATA device.

Table 8-100. SATA Supported Modes

PARAMETER MIN MAX UNIT SUPPORTED
Transfer Rates 1.5 3.0 Gbps
xSATA - - - No
Backplane - - - No
Internal Cable (iSATA) - - - Yes

8.18.2.3 PCB Stackup Specifications

Table 8-101 shows the PCB stackup and feature sizes required for SATA.

Table 8-101. SATA PCB Stackup Specifications

PARAMETER MIN TYP MAX UNIT
PCB routing/plane layers 4 6 - Layers
Signal routing layers 2 3 - Layers
Number of ground plane cuts allowed within SATA routing region - - 0 Cuts
Number of layers between SATA routing region and reference ground plane - - 0 Layers
PCB trace width, w - 4 - Mils
PCB BGA escape via pad size - 20 - Mils
PCB BGA escape via hole size - 10 Mils
Processor BGA pad size (1) 0.4 mm
(1) NSMD pad, per IPC-7351A BGA pad size guideline.

8.18.2.4 Routing Specifications

The SATA data signal traces must be routed to achieve 100 Ω (±20%) differential impedance and 60 Ω
(±15%) single-ended impedance. The single-ended impedance is required because differential signals are
extremely difficult to closely couple on PCBs and, therefore, single-ended impedance becomes important.
60 Ω is chosen for the single-ended impedance to minimize problems caused by too low an impedance.
These impedances are impacted by trace width, trace spacing, distance to reference planes, and dielectric
material. Verify with a PCB design tool that the trace geometry for both data signal pairs results in as
close to 100 Ω differential impedance and 60 Ω single-ended impedance traces as possible. For best
accuracy, work with your PCB fabricator to ensure this impedance is met.
Table 8-102 shows the routing specifications for the SATA data signals.

Table 8-102. SATA Routing Specifications

PARAMETER MIN TYP MAX UNIT
Processor-to-SATA header trace length 10 (1) Inches
Number of stubs allowed on SATA traces (2) 0 Stubs
TX/RX pair differential impedance 80 100 120 Ω
TX/RX single ended impedance 51 60 69 Ω
Number of vias on each SATA trace 3 Vias (3)
SATA differential pair to any other trace spacing 2*DS (4)
(1) Beyond this, signal integrity may suffer.
(2) In-line pads may be used for probing.
(3) Vias must be used in pairs with their distance minimized.
(4) DS = differential spacing of the SATA traces.

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8.18.2.5 Coupling Capacitors

AC coupling capacitors are required on the receive data pair. Table 8-103 shows the requirements for
these capacitors.

Table 8-103. SATA AC Coupling Capacitors Requirements

PARAMETER MIN TYP MAX UNIT
SATA AC coupling capacitor value 1 10 12 nF
SATA AC coupling capacitor package size (1) 0402 0603 EIA (2)
(1) The physical size of the capacitor should be as small as practical. Use the same size on both lines in each pair, placed side by side.
(2) EIA LxW units; that is, a 0402 is a 40 x 20 mil surface-mount capacitor.

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8.19 Serial Peripheral Interface (SPI)

The SPI is a high-speed synchronous serial input/output port that allows a serial bit stream of programmed
length (4 to 32 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The SPI is
normally used for communication between the device and external peripherals. Typical applications
include an interface-to-external I/O or peripheral expansion via devices such as shift registers, display
drivers, SPI EEPROMs, and Analog-to-Digital Converters (ADCs).
The SPI supports the following features:
• Master/Slave operation
• Four chip selects for interfacing/control to up to four SPI Slave devices and connection to a single
external Master
• 32-bit shift register
• Buffered receive/transmit data register per channel (1 word deep), FIFO size is 64 bytes
• Programmable SPI configuration per channel (clock definition, enable polarity and word width)
• Supports one interrupt request and two DMA requests per channel.
For more detailed information on the SPI, see the Multichannel Serial Port Interface (McSPI) chapter of
the TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual (Literature Number:
SPRUGZ8).

8.19.1 SPI Peripheral Register Descriptions

Table 8-104. SPI Registers

HEX ADDRESS RANGE ACRONYM REGISTER NAME
SPI0 SPI1 SPI2 SPI3
0x4803 0000 0x481A 0000 0x481A 2000 0x481A 4000 MCSPI_HL_REV SPI REVISION
0x4803 0004 0x481A 0004 0x481A 2004 0x481A 4004 MCSPI_HL_HWIN SPI HARDWARE
FO INFORMATION
0x4803 0008 - 0x481A 0008 - 0x481A 2008 - 0x481A 4008 - - RESERVED
0x4803 000C 0x481A 000C 0x481A 200C 0x481A 400C
0x4803 0010 0x481A 0010 0x481A 2010 0x481A 4010 MCSPI_HL_SYSC SPI SYSTEM
ONFIG CONFIGURATION
0x4803 0014 - 0x481A 0014 - 0x481A 2014 - 0x481A 4014 - - RESERVED
0x4803 00FF 0x481A 00FF 0x481A 20FF 0x481A 40FF
0x4803 0100 0x481A 0100 0x481A 2100 0x481A 4100 MCSPI_REVISION REVISION
0x4803 0104 - 0x481A 0104 - 0x481A 2104 - 0x481A 4104 - - RESERVED
0x4803 010C 0x481A 010C 0x481A 210C 0x481A 410C
0x4803 0110 0x481A 0110 0x481A 2110 0x481A 4110 MCSPI_SYSCONF SYSTEM CONFIGURATION
IG
0x4803 0114 0x481A 0114 0x481A 2114 0x481A 4114 MCSPI_SYSSTAT SYSTEM STATUS
US
0x4803 0118 0x481A 0118 0x481A 2118 0x481A 4118 MCSPI_IRQSTATU INTERRUPT STATUS
S
0x4803 011C 0x481A 011C 0x481A 211C 0x481A 411C MCSPI_IRQENABL INTERRUPT ENABLE
E
0x4803 0120 0x481A 0120 0x481A 2120 0x481A 4120 MCSPI_WAKEUPE WAKEUP ENABLE
NABLE
0x4803 0124 0x481A 0124 0x481A 2124 0x481A 4124 MCSPI_SYST SYSTEM TEST
0x4803 0128 0x481A 0128 0x481A 2128 0x481A 4128 MCSPI_MODULCT MODULE CONTROL
RL
0x4803 012C 0x481A 012C 0x481A 212C 0x481A 412C MCSPI_CH0CONF CHANNEL 0 CONFIGURATION
0x4803 0130 0x481A 0130 0x481A 2130 0x481A 4130 MCSPI_CH0STAT CHANNEL 0 STATUS
0x4803 0134 0x481A 0134 0x481A 2134 0x481A 4134 MCSPI_CH0CTRL CHANNEL 0 CONTROL
0x4803 0138 0x481A 0138 0x481A 2138 0x481A 4138 MCSPI_TX0 CHANNEL 0 TRANSMITTER

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Table 8-104. SPI Registers (continued)

HEX ADDRESS RANGE ACRONYM REGISTER NAME
SPI0 SPI1 SPI2 SPI3
0x4803 013C 0x481A 013C 0x481A 213C 0x481A 413C MCSPI_RX0 CHANNEL 0 RECEIVER
0x4803 0140 0x481A 0140 0x481A 2140 0x481A 4140 MCSPI_CH1CONF CHANNEL 1 CONFIGURATION
0x4803 0144 0x481A 0144 0x481A 2144 0x481A 4144 MCSPI_CH1STAT CHANNEL 1 STATUS
0x4803 0148 0x481A 0148 0x481A 2148 0x481A 4148 MCSPI_CH1CTRL CHANNEL 1 CONTROL
0x4803 014C 0x481A 014C 0x481A 214C 0x481A 414C MCSPI_TX1 CHANNEL 1 TRANSMITTER
0x4803 0150 0x481A 0150 0x481A 2150 0x481A 4150 MCSPI_RX1 CHANNEL 1 RECEIVER
0x4803 0154 0x481A 0154 0x481A 2154 0x481A 4154 MCSPI_CH2CONF CHANNEL 2 CONFIGURATION
0x4803 0158 0x481A 0158 0x481A 2158 0x481A 4158 MCSPI_CH2STAT CHANNEL 2 STATUS
0x4803 015C 0x481A 015C 0x481A 215C 0x481A 415C MCSPI_CH2CTRL CHANNEL 2 CONTROL
0x4803 0160 0x481A 0160 0x481A 2160 0x481A 4160 MCSPI_TX2 CHANNEL 2 TRANSMITTER
0x4803 0164 0x481A 0164 0x481A 2164 0x481A 4164 MCSPI_RX2 CHANNEL 2 RECEIVER
0x4803 0168 0x481A 0168 0x481A 2168 0x481A 4168 MCSPI_CH3CONF CHANNEL 3 CONFIGURATION
0x4803 016C 0x481A 016C 0x481A 216C 0x481A 416C MCSPI_CH3STAT CHANNEL 3 STATUS
0x4803 0170 0x481A 0170 0x481A 2170 0x481A 4170 MCSPI_CH3CTRL CHANNEL 3 CONTROL
0x4803 0174 0x481A 0174 0x481A 2174 0x481A 4174 MCSPI_TX3 CHANNEL 3 TRANSMITTER
0x4803 0178 0x481A 0178 0x481A 2178 0x481A 4178 MCSPI_RX3 CHANNEL 3 RECEIVER
0x4803 017C 0x481A 017C 0x481A 217C 0x481A 417C MCSPI_XFERLEV TRANSFER LEVELS
EL
0x4803 0180 0x481A 0180 0x481A 2180 0x481A 4180 MCSPI_DAFTX DMA ADDRESS ALIGNED
FIFO TRANSMITTER
0x4803 0184 - 0x481A 0184 - 0x481A 2184 - 0x481A 4184 - - RESERVED
0x4803 019C 0x481A 019C 0x481A 219C 0x481A 419C
0x4803 01A0 0x481A 01A0 0x481A 21A0 0x481A 41A0 MCSPI_DAFRX DMA ADDRESS ALIGNED
FIFO RECEIVER
0x4803 01A4 - 0x481A 01A4 - 0x481A 21A4 - 0x481A 41A4 - - RESERVED
0x4803 01FF 0x481A 01FF 0x481A 21FF 0x481A 41FF

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8.19.2 SPI Electrical Data/Timing

Table 8-105. Timing Requirements for SPI - Master Mode

(see Figure 8-90 and Figure 8-91)
OPP100/120/166
NO. UNIT
MIN MAX
MASTER: SPI0, SPI1, SPI2 (M0) and SPI3 (M0)1 LOAD AT A MAXIMUM OF 5 pF
1 tc(SPICLK) Cycle time, SPI_CLK (1) (2) 20.8 (3) ns
(1)
2 tw(SPICLKL) Pulse duration, SPI_CLK low 0.5*P - 1 (4) ns
3 tw(SPICLKH) Pulse duration, SPI_CLK high (1) 0.5*P - 1 (4) ns
Setup time, SPI_D[x] valid before SPI_CLK active SPI0, SPI1 2.29
4 tsu(MISO-SPICLK) ns
edge (1) SPI2, SPI3 4
5 th(SPICLK-MISO) Hold time, SPI_D[x] valid after SPI_CLK active edge (1) 2.67 ns
6 td(SPICLK-MOSI) Delay time, SPI_CLK active edge to SPI_D[x] transition (1) -3.57 3.57 ns
7 td(SCS-MOSI) Delay time, SPI_SCS[x] active edge to SPI_D[x] transition 3.57 ns
MASTER_PH (6)
B-4.2 ns
Delay time, SPI_SCS[x] active to SPI_CLK first A0 (5)
8 td(SCS-SPICLK)
edge (1) MASTER_PH
A-4.2 (7) ns
A1 (5)
MASTER_PH
A-4.2 (7) ns
Delay time, SPI_CLK last edge to SPI_SCS[x] A0 (5)
9 td(SPICLK-SCS)
inactive (1) MASTER_PH
B-4.2 (6) ns
A1 (5)
MASTER: SPI0, SPI1, SPI2 (M0) and SPI3 (M0) LOAD AT MAX 25pF
MASTER: SPI2 (M1, M2, M3) and SPI3 (M1, M2, M3) 1 to 4 LOAD AT 5 to 25pF
1 tc(SPICLK) Cycle time, SPI_CLK (1) (2) 41.7 (8) ns
(1)
2 tw(SPICLKL) Pulse duration, SPI_CLK low 0.5*P - 2 (4) ns
3 tw(SPICLKH) Pulse duration, SPI_CLK high (1) 0.5*P - 2 (4) ns
Setup time, SPI_D[x] valid before SPI_CLK active SPI0, SPI1 4
4 tsu(MISO-SPICLK) ns
edge (1) SPI2, SPI3 6
5 th(SPICLK-MISO) Hold time, SPI_D[x] valid after SPI_CLK active edge (1) 3.8 ns
6 td(SPICLK-MOSI) Delay time, SPI_CLK active edge to SPI_D[x] transition (1) -5.5 5.5 ns
7 td(SCS-MOSI) Delay time, SPI_SCS[x] active edge to SPI_D[x] transition 5.5 ns
MASTER_PH (6)
B-3.5 ns
Delay time, SPI_SCS[x] active to SPI_CLK first A0 (5)
8 td(SCS-SPICLK)
edge (1) MASTER_PH
A-3.5 (7) ns
A1 (5)
MASTER_PH
A-3.5 (7) ns
Delay time, SPI_CLK last edge to SPI_SCS[x] A0 (5)
9 td(SPICLK-SCS)
inactive (1) MASTER_PH
B-3.5 (6) ns
A1 (5)
(1) This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture
input data.
(2) Related to the SPI_CLK maximum frequency.
(3) Maximum frequency = 48 MHz
(4) P = SPICLK period.
(5) SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.
(6) B = (TCS + 0.5) * TSPICLKREF * Fratio, where TCS is a bit field of the SPI_CH(i)CONF register and Fratio = Even ≥2.
(7) When P = 20.8 ns, A = (TCS + 1) * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register. When P > 20.8 ns, A = (TCS
+ 0.5) * Fratio * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register.
(8) Maximum frequency = 24 MHz

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PHA=0
EPOL=1
SPI_SCS[x] (Out)
1
3
8 2 9
SPI_SCLK (Out) POL=0
1
2

POL=1 3
SPI_SCLK (Out)

6
7 6
SPI_D[x] (Out) Bit n-1 Bit n-2 Bit n-3 Bit n-4 Bit 0

PHA=1
EPOL=1
SPI_SCS[x] (Out)
1
3
8 2 9
SPI_SCLK (Out) POL=0
1
2

POL=1 3
SPI_SCLK (Out)

6 6
6 6
SPI_D[x] (Out) Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit 0

Figure 8-90. SPI Master Mode Transmit Timing

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PHA=0
EPOL=1
SPI_SCS[x] (Out)
1
3
8 2 9
SPI_SCLK (Out) POL=0
1
2

POL=1 3
SPI_SCLK (Out)
4 4
5 5
SPI_D[x] (In) Bit n-1 Bit n-2 Bit n-3 Bit n-4 Bit 0

PHA=1
EPOL=1
SPI_SCS[x] (Out)
1
3
8 2 9
SPI_SCLK (Out) POL=0
1
2

POL=1 3
SPI_SCLK (Out)
4 4
5 5
SPI_D[x] (In) Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit 0

Figure 8-91. SPI Master Mode Receive Timing

Table 8-106. Timing Requirements for SPI - Slave Mode

(see Figure 8-92 and Figure 8-93)
OPP100/120/166
NO. UNIT
MIN MAX
1 tc(SPICLK) Cycle time, SPI_CLK (1) (2) 62.5 (3) ns
(1) (4)
2 tw(SPICLKL) Pulse duration, SPI_CLK low 0.5*P - 3 ns
3 tw(SPICLKH) Pulse duration, SPI_CLK high (1) 0.5*P - 3 (4) ns
4 tsu(MOSI-SPICLK) Setup time, SPI_D[x] valid before SPI_CLK active edge (1) 12.92 ns
(1)
5 th(SPICLK-MOSI) Hold time, SPI_D[x] valid after SPI_CLK active edge 12.92 ns
6 td(SPICLK-MISO) Delay time, SPI_CLK active edge to SPI_D[x] transition (1) -4.00 17.1 ns
Delay time, SPI_SCS[x] active edge to SPI_D[x]
7 td(SCS-MISO) 17.1 ns
transition (5)
8 tsu(SCS-SPICLK) Setup time, SPI_SCS[x] valid before SPI_CLK first edge (1) 12.92 ns

(1) This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture
input data.
(2) Related to the input maximum frequency supported by the SPI module.
(3) Maximum frequency = 16 MHz
(4) P = SPICLK period.
(5) PHA = 0; SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.
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Table 8-106. Timing Requirements for SPI - Slave Mode (continued)

(see Figure 8-92 and Figure 8-93)
OPP100/120/166
NO. UNIT
MIN MAX
9 th(SPICLK-SCS) Hold time, SPI_SCS[x] valid after SPI_CLK last edge (1) 12.92 ns

PHA=0
EPOL=1
SPI_SCS[x] (In)
1
3
8 2 9
SPI_SCLK (In) POL=0
1
3
2
POL=1
SPI_SCLK (In)

6
7 6
SPI_D[x] (Out) Bit n-1 Bit n-2 Bit n-3 Bit n-4 Bit 0

PHA=1
EPOL=1
SPI_SCS[x] (In)
1
3
8 2 9
SPI_SCLK (In) POL=0
1
2

POL=1 3
SPI_SCLK (In)

6 6
6 6
SPI_D[x] (Out) Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit 0

Figure 8-92. SPI Slave Mode Transmit Timing

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PHA=0
EPOL=1
SPI_SCS[x] (In)
1
3
8 2 9
SPI_SCLK (In) POL=0
1
3

POL=1 2
SPI_SCLK (In)
4 4
5 5
SPI_D[x] (In) Bit n-1 Bit n-2 Bit n-3 Bit n-4 Bit 0

PHA=1
EPOL=1
SPI_SCS[x] (In)
1
3
8 2 9
SPI_SCLK (In) POL=0
1
2

POL=1 3
SPI_SCLK (In)
4 4
5 5
SPI_D[x] (In) Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit 0

Figure 8-93. SPI Slave Mode Receive Timing

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8.20 Timers
The device has eight 32-bit general-purpose (GP) timers (TIMER8 - TIMER1) that have the following
features:
• TIMER8, TIMER1 are for software use and do not have an external connection
• Dedicated input trigger for capture mode and dedicated output trigger/pulse width modulation (PWM)
signal
• Interrupts generated on overflow, compare, and capture
• Free-running 32-bit upward counter
• Supported modes:
– Compare and capture modes
– Auto-reload mode
– Start-stop mode
• TIMER[8:1] functional clock is sourced from either the DEVOSC, AUXOSC, AUD_CLK2/1/0, TCLKIN,
or SYSCLK18 27 MHz as selected by the timer clock multiplexers.
• On-the-fly read/write register (while counting)
• Generates interrupts to the ARM, DSP, and Media Controller.
The device has one system watchdog timer that have the following features:
• Free-running 32-bit upward counter
• On-the-fly read/write register (while counting)
• Reset upon occurrence of a timer overflow condition
• The system watchdog timer has two possible clock sources:
– RCOSC32K oscillator
– RTCDIVIDER
• The watchdog timer is used to provide a recovery mechanism for the device in the event of a fault
condition, such as a non-exiting code loop.
For more detailed information on the GP and Watchdog Timers, see the Timers and Watchdog Timer
chapters of the TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual
(Literature Number: SPRUGZ8).

8.20.1 Timer Peripheral Register Descriptions

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8.20.2 Timer Electrical/Data Timing

Table 8-107. Timing Requirements for Timer

(see Figure 8-94)
OPP100/120/166
NO. UNIT
MIN MAX
1 tw(EVTIH) Pulse duration, high 4P (1) ns
(1)
2 tw(EVTIL) Pulse duration, low 4P ns
(1) P = module clock.

Table 8-108. Switching Characteristics Over Recommended Operating Conditions for Timer
(see Figure 8-94)
OPP100/120/166
NO. PARAMETER UNIT
MIN MAX
3 tw(EVTOH) Pulse duration, high 4P-3 (1) ns
(1)
4 tw(EVTOL) Pulse duration, low 4P-3 ns
(1) P = module clock.

1
2
TCLKIN

3
4
TIMx_IO

Figure 8-94. Timer Timing

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8.21 Universal Asynchronous Receiver/Transmitter (UART)

The UART performs serial-to-parallel conversions on data received from a peripheral device and parallel-
to-serial conversion on data received from the CPU. The device provides up to six UART peripheral
interfaces, depending on the selected pin multiplexing.
Each UART has the following features:
• Selectable UART/IrDA (SIR/MIR)/CIR modes
• Dual 64-entry FIFOs for received and transmitted data payload
• Programmable and selectable transmit and receive FIFO trigger levels for DMA and interrupt
generation
• Baud-rate generation based upon programmable divisors N (N=1…16384)
• Two DMA requests and one interrupt request to the system
• Can connect to any RS-232 compliant device.
UART functions include:
• Baud-rate up to 3.6 Mbit/s on UART0, UART1, and UART2
• Baud-rate up to 12 Mbit/s on UART3, UART4, and UART5
• Programmable serial interfaces characteristics
– 5, 6, 7, or 8-bit characters
– Even, odd, or no parity-bit generation and detection
– 1, 1.5, or 2 stop-bit generation
– Flow control: hardware (RTS/CTS) or software (XON/XOFF)
• Additional modem control functions (UART0_DTR, UART0_DSR, UART0_DCD, and UART0_RIN) for
UART0 only; UART1, UART2, UART3, UART4, and UART5 do not support full-flow control signaling.
IR-IrDA functions include:
• Support of IrDA 1.4 slow infrared (SIR, baud-rate up to 115.2 Kbits/s), medium infrared (MIR, baud-
rate up to 1.152 Mbits/s) and fast infrared (FIR baud-rate up to 4.0 Mbits/s) communications
• Supports framing error, cyclic redundancy check (CRC) error, illegal symbol (FIR), and abort pattern
(SIR, MIR) detection
• 8-entry status FIFO (with selectable trigger levels) available to monitor frame length and frame errors.
IR-CIR functions include:
• Consumer infrared (CIR) remote control mode with programmable data encoding
• Free data format (supports any remote control private standards)
• Selectable bit rate and configurable carrier frequency.
For more detailed information on the UART peripheral, see the UART/IrDA/CIR Module chapter of the
TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual (Literature Number:
SPRUGZ8).

8.21.1 UART Peripheral Register Descriptions

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8.21.2 UART Electrical/Data Timing

Table 8-109. Timing Requirements for UART

(see Figure 8-95)
OPP100/120/166
NO. UNIT
MIN MAX
4 tw(RX) Pulse width, receive data bit, 15/30/100pF high or low 0.96U (1) 1.05U (1) ns
(1) (1)
5 tw(CTS) Pulse width, receive start bit, 15/30/100pF high or low 0.96U 1.05U ns
td(RTS-TX) Delay time, transmit start bit to transmit data P (2) ns
td(CTS-TX) Delay time, receive start bit to transmit data P (2) ns
(1) U = UART baud time = 1/programmed baud rate
(2) P = Clock period of the reference clock (FCLK, usually 48 MHz).

Table 8-110. Switching Characteristics Over Recommended Operating Conditions for UART
(see Figure 8-95)
OPP100/120/166
NO. PARAMETER UNIT
MIN MAX
15 pF
5
(UART0/1/2)
15 pF
f(baud) Maximum programmable baud rate 12 MHz
(UART3/4/5)
30 pF 0.23
100 pF 0.115
2 tw(TX) Pulse width, transmit data bit, 15/30/100 pF high or low U - 2 (1) U + 2 (1) ns
(1)
3 tw(RTS) Pulse width, transmit start bit, 15/30/100 pF high or low U-2 U + 2 (1) ns
(1) U = UART baud time = 1/programmed baud rate

3
2
Start
UARTx_TXD Bit

Data Bits

5
4

Start
UARTx_RXD Bit

Data Bits

Figure 8-95. UART Timing

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8.22 Universal Serial Bus (USB2.0)

The device includes two USB2.0 modules which support the Universal Serial Bus Specification Revision
2.0. The following are some of the major USB features that are supported:
• USB 2.0 peripheral at high speed (HS: 480 Mbps) and full speed (FS: 12 Mbps)
• USB 2.0 host at HS, FS, and low speed (LS: 1.5 Mbps)
• Each endpoint (other than endpoint 0, control only) can support all transfer modes (control, bulk,
interrupt, and isochronous)
• Supports high-bandwidth ISO mode
• Supports 16 Transmit (TX) and 16 Receive (RX) endpoints including endpoint 0
• FIFO RAM
– 32K endpoint
– Programmable size
• Includes two integrated PHYs
• RNDIS-like mode for terminating RNDIS-type protocols without using short-packet termination for
support of MSC applications.
• USB OTG extensions — session request protocol (SRP) and host negotiation protocol (HNP)
The USB2.0 peripherals do not support the following features:
• On-chip charge pump (VBUS Power must be generated external to the device.)
• RNDIS mode acceleration for USB sizes that are not multiples of 64 bytes
• Endpoint max USB packet sizes that do not conform to the USB 2.0 spec (for FS/LS: 8, 16, 32, 64, –
and 1023 are defined; for HS: 64, 128, 512, and 1024 are defined
For more detailed information on the USB2.0 peripheral, see the Universal Serial Bus (USB) chapter of
the TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual (Literature Number:
SPRUGZ8).

8.22.1 USB2.0 Peripheral Register Descriptions

Table 8-111. USB2.0 Submodules

SUBMODULE
SUBMODULE NAME
ADDRESS OFFSET
0x0000 USBSS registers
0x1000 USB0 controller registers
0x1800 USB1 controller registers
0x2000 CPPI DMA controller registers
0x3000 CPPI DMA scheduler registers
0x4000 CPPI DMA Queue Manager registers

Table 8-112. USB Subsystem (USBSS) Registers (1)

HEX ADDRESS ACRONYM REGISTER NAME
0x4740 0000 REVREG USBSS REVISION
0x4740 0004 - 0x4740 000C - Reserved
0x4740 0010 SYSCONFIG USBSS SYSCONFIG
0x4740 0014 - 0x4740 001C - Reserved
0x4740 0020 EOI USBSS IRQ_EOI
0x4740 0024 IRQSTATRAW USBSS IRQ_STATUS_RAW
0x4740 0028 IRQSTAT USBSS IRQ_STATUS

(1) USBSS registers contain the registers that are used to control at the global level and apply to all sub-modules.
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Table 8-112. USB Subsystem (USBSS) Registers(1) (continued)

HEX ADDRESS ACRONYM REGISTER NAME
0x4740 002C IRQENABLER USBSS IRQ_ENABLE_SET
0x4740 0030 IRQCLEARR USBSS IRQ_ENABLE_CLR
0x4740 0034 - 0x4740 00FC - Reserved
0x4740 0100 IRQDMATHOLDTX00 USBSS IRQ_DMA_THRESHOLD_TX0_0
0x4740 0104 IRQDMATHOLDTX01 USBSS IRQ_DMA_THRESHOLD_TX0_1
0x4740 0108 IRQDMATHOLDTX02 USBSS IRQ_DMA_THRESHOLD_TX0_2
0x4740 010C IRQDMATHOLDTX03 USBSS IRQ_DMA_THRESHOLD_TX0_3
0x4740 0110 IRQDMATHOLDRX00 USBSS IRQ_DMA_THRESHOLD_RX0_0
0x4740 0114 IRQDMATHOLDRX01 USBSS IRQ_DMA_THRESHOLD_RX0_1
0x4740 0118 IRQDMATHOLDRX02 USBSS IRQ_DMA_THRESHOLD_RX0_2
0x4740 011C IRQDMATHOLDRX03 USBSS IRQ_DMA_THRESHOLD_RX0_3
0x4740 0120 IRQDMATHOLDTX10 USBSS IRQ_DMA_THRESHOLD_TX1_0
0x4740 0124 IRQDMATHOLDTX11 USBSS IRQ_DMA_THRESHOLD_TX1_1
0x4740 0128 IRQDMATHOLDTX12 USBSS IRQ_DMA_THRESHOLD_TX1_2
0x4740 012C IRQDMATHOLDTX13 USBSS IRQ_DMA_THRESHOLD_TX1_3
0x4740 0130 IRQDMATHOLDRX10 USBSS IRQ_DMA_THRESHOLD_RX1_0
0x4740 0134 IRQDMATHOLDRX11 USBSS IRQ_DMA_THRESHOLD_RX1_1
0x4740 0138 IRQDMATHOLDRX12 USBSS IRQ_DMA_THRESHOLD_RX1_2
0x4740 013C IRQDMATHOLDRX13 USBSS IRQ_DMA_THRESHOLD_RX1_3
0x4740 0140 IRQDMAENABLE0 USBSS IRQ_DMA_ENABLE_0
0x4740 0144 IRQDMAENABLE1 USBSS IRQ_DMA_ENABLE_1
0x4740 0148 - 0x4740 01FC - Reserved
0x4740 0200 IRQFRAMETHOLDTX00 USBSS IRQ_FRAME_THRESHOLD_TX0_0
0x4740 0204 IRQFRAMETHOLDTX01 USBSS IRQ_FRAME_THRESHOLD_TX0_1
0x4740 0208 IRQFRAMETHOLDTX02 USBSS IRQ_FRAME_THRESHOLD_TX0_2
0x4740 020C IRQFRAMETHOLDTX03 USBSS IRQ_FRAME_THRESHOLD_TX0_3
0x4740 0210 IRQFRAMETHOLDRX00 USBSS IRQ_FRAME_THRESHOLD_RX0_0
0x4740 0214 IRQFRAMETHOLDRX01 USBSS IRQ_FRAME_THRESHOLD_RX0_1
0x4740 0218 IRQFRAMETHOLDRX02 USBSS IRQ_FRAME_THRESHOLD_RX0_2
0x4740 021C IRQFRAMETHOLDRX03 USBSS IRQ_FRAME_THRESHOLD_RX0_3
0x4740 0220 IRQFRAMETHOLDTX10 USBSS IRQ_FRAME_THRESHOLD_TX1_0
0x4740 0224 IRQFRAMETHOLDTX11 USBSS IRQ_FRAME_THRESHOLD_TX1_1
0x4740 0228 IRQFRAMETHOLDTX12 USBSS IRQ_FRAME_THRESHOLD_TX1_2
0x4740 022C IRQFRAMETHOLDTX13 USBSS IRQ_FRAME_THRESHOLD_TX1_3
0x4740 0230 IRQFRAMETHOLDRX10 USBSS IRQ_FRAME_THRESHOLD_RX1_0
0x4740 0234 IRQFRAMETHOLDRX11 USBSS IRQ_FRAME_THRESHOLD_RX1_1
0x4740 0238 IRQFRAMETHOLDRX12 USBSS IRQ_FRAME_THRESHOLD_RX1_2
0x4740 023C IRQFRAMETHOLDRX13 USBSS IRQ_FRAME_THRESHOLD_RX1_3
0x4740 0240 IRQFRAMEENABLE0 USBSS IRQ_FRAME_ENABLE_0
0x4740 0244 IRQFRAMEENABLE1 USBSS IRQ_FRAME_ENABLE_1
0x4740 0248 - 0x4740 0FFC - Reserved

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Table 8-113. USB0 Controller Registers

HEX ADDRESS ACRONYM REGISTER NAME
0x4740 1000 USB0REV USB0 REVISION
0x4740 1004 - 0x4740 1010 - Reserved
0x4740 1014 USB0CTRL USB0 Control
0x4740 1018 USB0STAT USB0 Status
0x4740 101C - Reserved
0x4740 1020 USB0IRQMSTAT USB0 IRQ_MERGED_STATUS
0x4740 1024 USB0IRQEOI USB0 IRQ_EOI
0x4740 1028 USB0IRQSTATRAW0 USB0 IRQ_STATUS_RAW_0
0x4740 102C USB0IRQSTATRAW1 USB0 IRQ_STATUS_RAW_1
0x4740 1030 USB0IRQSTAT0 USB0 IRQ_STATUS_0
0x4740 1034 USB0IRQSTAT1 USB0 IRQ_STATUS_1
0x4740 1038 USB0IRQENABLESET0 USB0 IRQ_ENABLE_SET_0
0x4740 103C USB0IRQENABLESET1 USB0 IRQ_ENABLE_SET_1
0x4740 1040 USB0IRQENABLECLR0 USB0 IRQ_ENABLE_CLR_0
0x4740 1044 USB0IRQENABLECLR1 USB0 IRQ_ENABLE_CLR_1
0x4740 1048 - 0x4740 106C - Reserved
0x4740 1070 USB0TXMODE USB0 Tx Mode
0x4740 1074 USB0RXMODE USB0 Rx Mode
0x4740 1078 - 0x4740 107C - Reserved
0x4740 1080 USB0GENRNDISEP1 USB0 Generic RNDIS Size EP1
0x4740 1084 USB0GENRNDISEP2 USB0 Generic RNDIS Size EP2
0x4740 1088 USB0GENRNDISEP3 USB0 Generic RNDIS Size EP3
0x4740 108C USB0GENRNDISEP4 USB0 Generic RNDIS Size EP4
0x4740 1090 USB0GENRNDISEP5 USB0 Generic RNDIS Size EP5
0x4740 1094 USB0GENRNDISEP6 USB0 Generic RNDIS Size EP6
0x4740 1098 USB0GENRNDISEP7 USB0 Generic RNDIS Size EP7
0x4740 109C USB0GENRNDISEP8 USB0 Generic RNDIS Size EP8
0x4740 10A0 USB0GENRNDISEP9 USB0 Generic RNDIS Size EP9
0x4740 10A4 USB0GENRNDISEP10 USB0 Generic RNDIS Size EP10
0x4740 10A8 USB0GENRNDISEP11 USB0 Generic RNDIS Size EP11
0x4740 10AC USB0GENRNDISEP12 USB0 Generic RNDIS Size EP12
0x4740 10B0 USB0GENRNDISEP13 USB0 Generic RNDIS Size EP13
0x4740 10B4 USB0GENRNDISEP14 USB0 Generic RNDIS Size EP14
0x4740 10B8 USB0GENRNDISEP15 USB0 Generic RNDIS Size EP15
0x4740 10BC - 0x4740 10CC - Reserved
0x4740 10D0 USB0AUTOREQ USB0 Auto Req
0x4740 10D4 USB0SRPFIXTIME USB0 SRP Fix Time
0x4740 10D8 USB0TDOWN USB0 Teardown
0x4740 10DC - Reserved
0x4740 10E0 USB0UTMI USB0 PHY UTMI
0x4740 10E4 USB0UTMILB USB0 MGC UTMI Loopback
0x4740 10E8 USB0MODE USB0 Mode
0x4740 10E8 - 0x4740 13FF - Reserved
0x4740 1400 - 0x4740 1468 - USB0 Mentor Core Registers/FIFOs
0x4740 146C USB0_HWVERS USB0 Mentor Core Hardware Version Register
0x4740 1470 - 0x4740 159C - USB0 Mentor Core Registers/FIFOs
0x4740 15A0 - 0x4740 17FC - Reserved

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Table 8-114. USB1 Controller Registers

HEX ADDRESS ACRONYM REGISTER NAME
0x4740 1800 USB1REV USB1 Revision
0x4740 1804 - 0x4740 1810 - Reserved
0x4740 1814 USB1CTRL USB1 Control
0x4740 1818 USB1STAT USB1 Status
0x4740 181C - Reserved
0x4740 1820 USB1IRQMSTAT USB1 IRQ_MERGED_STATUS
0x4740 1824 USB1IRQEOI USB1 IRQ_EOI
0x4740 1828 USB1IRQSTATRAW0 USB1 IRQ_STATUS_RAW_0
0x4740 182C USB1IRQSTATRAW1 USB1 IRQ_STATUS_RAW_1
0x4740 1830 USB1IRQSTAT0 USB1 IRQ_STATUS_0
0x4740 1834 USB1IRQSTAT1 USB1 IRQ_STATUS_1
0x4740 1838 USB1IRQENABLESET0 USB1 IRQ_ENABLE_SET_0
0x4740 183C USB1IRQENABLESET1 USB1 IRQ_ENABLE_SET_1
0x4740 1840 USB1IRQENABLECLR0 USB1 IRQ_ENABLE_CLR_0
0x4740 1844 USB1IRQENABLECLR1 USB1 IRQ_ENABLE_CLR_1
0x4740 1848 - 0x4740 186C - Reserved
0x4740 1870 USB1TXMODE USB1 Tx Mode
0x4740 1874 USB1RXMODE USB1 Rx Mode
0x4740 1878 - 0x4740 187C - Reserved
0x4740 1880 USB1GENRNDISEP1 USB1 Generic RNDIS Size EP1
0x4740 1884 USB1GENRNDISEP2 USB1 Generic RNDIS Size EP2
0x4740 1888 USB1GENRNDISEP3 USB1 Generic RNDIS Size EP3
0x4740 188C USB1GENRNDISEP4 USB1 Generic RNDIS Size EP4
0x4740 1890 USB1GENRNDISEP5 USB1 Generic RNDIS Size EP5
0x4740 1894 USB1GENRNDISEP6 USB1 Generic RNDIS Size EP6
0x4740 1898 USB1GENRNDISEP7 USB1 Generic RNDIS Size EP7
0x4740 189C USB1GENRNDISEP8 USB1 Generic RNDIS Size EP8
0x4740 18A0 USB1GENRNDISEP9 USB1 Generic RNDIS Size EP9
0x4740 18A4 USB1GENRNDISEP10 USB1 Generic RNDIS Size EP10
0x4740 18A8 USB1GENRNDISEP11 USB1 Generic RNDIS Size EP11
0x4740 18AC USB1GENRNDISEP12 USB1 Generic RNDIS Size EP12
0x4740 18B0 USB1GENRNDISEP13 USB1 Generic RNDIS Size EP13
0x4740 18B4 USB1GENRNDISEP14 USB1 Generic RNDIS Size EP14
0x4740 18B8 USB1GENRNDISEP15 USB1 Generic RNDIS Size EP15
0x4740 18BC - 0x4740 18CC - Reserved
0x4740 18D0 USB1AUTOREQ USB1 Auto Req
0x4740 18D4 USB1SRPFIXTIME USB1 SRP Fix Time
0x4740 18D8 USB1TDOWN USB1 Teardown
0x4740 18DC - Reserved
0x4740 18E0 USB1UTMI USB1 PHY UTMI
0x4740 18E4 USB1UTMILB USB1 MGC UTMI Loopback
0x4740 18E8 USB1MODE USB1 Mode
0x4740 18E8 - 0x4740 1BFF - Reserved
0x4740 1C00 - 0x4740 1C68 - USB1 Mentor Core Registers
0x4740 1C6C USB1HWVERS USB1 Mentor Core Hardware Version Register
0x4740 1C70 - 0x4740 1D9C - USB1 Mentor Core Registers
0x4740 1DA0 - 0x4740 1FFC - Reserved

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Table 8-115. CPPI DMA Controller Registers

HEX ADDRESS ACRONYM REGISTER NAME
0x4740 2000 DMAREVID Revision Register
0x4740 2004 TDFDQ Teardown Free Descriptor Queue Control
0x4740 2008 DMAEMU Emulation Control Register
0x4740 200C - Reserved
0x4740 2010 DMAMEM1BA CPPI Mem1 Base Address Register
0x4740 2014 DMAMEM1MASK CPPI Mem1 Mask Address Register
0x4740 200C - 0x4740 27FF - Reserved
0x4740 2800 TXGCR0 Tx Channel 0 Global Configuration Register
0x4740 2804 - Reserved
0x4740 2808 RXGCR0 Rx Channel 0 Global Configuration Register
0x4740 280C RXHPCRA0 Rx Channel 0 Host Packet Configuration Register A
0x4740 2810 RXHPCRB0 Rx Channel 0 Host Packet Configuration Register B
0x4740 2814 - 0x4740 281C - Reserved
0x4740 2820 TXGCR1 Tx Channel 1 Global Configuration Register
0x4740 2824 - Reserved
0x4740 2828 RXGCR1 Rx Channel 1 Global Configuration Register
0x4740 282C RXHPCRA1 Rx Channel 1 Host Packet Configuration Register A
0x4740 2830 RXHPCRB1 Rx Channel 1 Host Packet Configuration Register B
0x4740 2834 - 0x4740 283C - Reserved
0x4740 2840 TXGCR2 Tx Channel 2 Global Configuration Register
0x4740 2844 - Reserved
0x4740 2848 RXGCR2 Rx Channel 2 Global Configuration Register
0x4740 284C RXHPCRA2 Rx Channel 2 Host Packet Configuration Register A
0x4740 2850 RXHPCRB2 Rx Channel 2 Host Packet Configuration Register B
0x4740 2854 - 0x4740 285F - Reserved
0x4740 2860 TXGCR3 Tx Channel 3 Global Configuration Register
0x4740 2864 - Reserved
0x4740 2868 RXGCR3 Rx Channel 3 Global Configuration Register
0x4740 286C RXHPCRA3 Rx Channel 3 Host Packet Configuration Register A
0x4740 2870 RXHPCRB3 Rx Channel 3 Host Packet Configuration Register B
0x4740 2880 - 0x4740 2B9F - ...
0x4740 2BA0 TXGCR29 Tx Channel 29 Global Configuration Register
0x4740 2BA4 - Reserved
0x4740 2BA8 RXGCR29 Rx Channel 29 Global Configuration Register
0x4740 2BAC RXHPCRA29 Rx Channel 29 Host Packet Configuration Register A
0x4740 2BB0 RXHPCRB29 Rx Channel 29 Host Packet Configuration Register B
0x4740 2BB4 - 0x4740 2FFF - Reserved

Table 8-116. CPPI DMA Scheduler Registers

HEX ADDRESS ACRONYM REGISTER NAME
0x4740 3000 DMA_SCHED_CTRL CPPI DMA Scheduler Control Register
0x4740 3804 - 0x4740 38FF - Reserved
0x4740 3800 WORD0 CPPI DMA Scheduler Table Word 0
0x4740 3804 WORD1 CPPI DMA Scheduler Table Word 1
… … …
0x4740 38F8 WORD62 CPPI DMA Scheduler Table Word 62
0x4740 38FC WORD63 CPPI DMA Scheduler Table Word 63

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Table 8-116. CPPI DMA Scheduler Registers (continued)

HEX ADDRESS ACRONYM REGISTER NAME
0x4740 38FF - 0x4740 3FFF - Reserved

Table 8-117. CPPI DMA Queue Manager Registers

HEX ADDRESS ACRONYM REGISTER NAME
0x4740 4000 QMGRREVID Queue Manager Revision
0x4740 4004 - Reserved
0x4740 4008 DIVERSION Queue Manager Queue Diversion
0x4740 400C - 0x4740 401F - Reserved
0x4740 4020 FDBSC0 Queue Manager Free Descriptor/Buffer Starvation Count 0
0x4740 4024 FDBSC1 Queue Manager Free Descriptor/Buffer Starvation Count 1
0x4740 4028 FDBSC2 Queue Manager Free Descriptor/Buffer Starvation Count 2
0x4740 402C FDBSC3 Queue Manager Free Descriptor/Buffer Starvation Count 3
0x4740 4030 FDBSC4 Queue Manager Free Descriptor/Buffer Starvation Count 4
0x4740 4034 FDBSC5 Queue Manager Free Descriptor/Buffer Starvation Count 5
0x4740 4038 FDBSC6 Queue Manager Free Descriptor/Buffer Starvation Count 6
0x4740 403C FDBSC7 Queue Manager Free Descriptor/Buffer Starvation Count 7
0x4740 4030 - 0x4740 407C - Reserved
0x4740 4080 LRAM0BASE Queue Manager Linking RAM Region 0 Base Address
0x4740 4084 LRAM0SIZE Queue Manager Linking RAM Region 0 Size
0x4740 4088 LRAM1BASE Queue Manager Linking RAM Region 1 Base Address
0x4740 408C - Reserved
0x4740 4090 PEND0 Queue Manager Queue Pending 0
0x4740 4094 PEND1 Queue Manager Queue Pending 1
0x4740 4098 PEND2 Queue Manager Queue Pending 2
0x4740 409C PEND3 Queue Manager Queue Pending 3
0x4740 40A0 PEND4 Queue Manager Queue Pending 4
0x4740 40A4 - 0x4740 4FFF - Reserved
0x4740 5000 + 16xR QMEMRBASE0 Memory Region 0 Base Address (R ranges from 0 to 15)
0x4740 5000 + 16xR + 4 QMEMRCTRL0 Memory Region 0 Control 0 (R ranges from 0 to 15)
0x4740 5000 + 16xR + 8 - Reserved
0x4740 5000 + 16xR + C - Reserved
0x4740 5010 – 0x4740 50EF - ...
0x4740 5000 + 16xR QMEMRBASE15 Memory Region 15 Base Address (R ranges from 0 to 15)
0x4740 5000 + 16xR + 4 QMEMRCTRL15 Memory Region 15 Control (R ranges from 0 to 15)
0x4740 5000 + 16xR + 8 - Reserved
0x4740 5000 + 16xR + C - Reserved
0x4740 5080 - 0x4740 5FFF - Reserved
0x4740 6000 + 16xN - Reserved
0x4740 6000 + 16xN + 4 - Reserved
0x4740 6000 + 16xN + 8 - Reserved
0x4740 6000 + 16xN + C CTRLD0 Queue N Register D (N ranges from 0 to 155)
0x4740 6010 – 0x4740 69AF - ...
0x4740 6000 + 16xN - Reserved
0x4740 6000 + 16xN + 4 - Reserved
0x4740 6000 + 16xN + 8 - Reserved
0x4740 6000 + 16xN + C CTRLD155 Queue N Register D (N ranges from 0 to 155)
0x4740 69B0 - 0x4740 6FFF - Reserved

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Table 8-117. CPPI DMA Queue Manager Registers (continued)

HEX ADDRESS ACRONYM REGISTER NAME
0x4740 7000 + 16xN QSTATA0 Queue N Status A (N ranges from 0 to 155)
0x4740 7000 + 16xN + 4 QSTATB0 Queue N Status B (N ranges from 0 to 155)
0x4740 7000 + 16xN + 8 QSTATC0 Queue N Status C (N ranges from 0 to 155)
0x4740 7000 + 16xN + C - Reserved
0x4740 7010 – 0x4740 79AF - ...
0x4740 7000 + 16xN QSTATA155 Queue N Status A (N ranges from 0 to 155)
0x4740 7000 + 16xN + 4 QSTATB155 Queue N Status B (N ranges from 0 to 155)
0x4740 7000 + 16xN + 8 QSTATC155 Queue N Status C (N ranges from 0 to 155)
0x4740 7000 + 16xN + C - Reserved
0x4740 79B0 - 0x4740 7FFF - Reserved

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8.22.2 USB2.0 Electrical Data/Timing

Table 8-118. Switching Characteristics Over Recommended Operating Conditions for USB2.0
(see Figure 8-96)
OPP100/120/166
LOW SPEED FULL SPEED HIGH SPEED
NO. PARAMETER UNIT
1.5 Mbps 12 Mbps 480 Mbps
MIN MAX MIN MAX MIN MAX
1 tr(D) Rise time, USBx_DP and USBx_DM signals (1) 75 300 4 20 0.5 ns
(1)
2 tf(D) Fall time, USBx_DP and USBx_DM signals 75 300 4 20 0.5 ns
3 trfM Rise/Fall time, matching (2) 80 125 90 111 – – %
4 VCRS Output signal cross-over voltage (1) 1.3 2 1.3 2 – – V
(3)
5 tjr(source)NT Source (Host) Driver jitter, next transition 2 2 ns
(3)
tjr(FUNC)NT Function Driver jitter, next transition 25 2 ns
6 tjr(source)PT Source (Host) Driver jitter, paired transition (4) 1 1 (3)
ns
(3)
tjr(FUNC)PT Function Driver jitter, paired transition 10 1 ns
7 tw(EOPT) Pulse duration, EOP transmitter 1250 1500 160 175 – – ns
8 tw(EOPR) Pulse duration, EOP receiver (5) 670 82 – ns
Mbp
9 t(DRATE) Data Rate 1.5 12 480
s
10 ZDRV Driver Output Resistance – – 28 49.5 40.5 49.5 Ω
11 ZINP Receiver Input Impedance (6) 300 300 – – – kΩ
(1) Low Speed: CL = 200 pF, Full Speed: CL = 50 pF, High Speed: CL = 50 pF
(2) tRFM = (tr/tf) x 100. [Excluding the first transaction from the Idle state.]
(3) For more detailed information, see the Universal Serial Bus Specification Revision 2.0, Chapter 7, Electrical.
(4) tjr = tpx(1) - tpx(0)
(5) Must accept as valid EOP.
(6) These values do not include the external resistors required per USB 2.0 specification.

t per − t jr
USBx_DM
90% VOH
VCRS
10% VOL
USBx_DP
tf
tr

Figure 8-96. USB2.0 Integrated Transceiver Interface Timing

For more detailed information on USB2.0 board design, routing, and layout guidelines, see the USB 2.0
Board Design and Layout Guidelines Application Report (Literature Number: SPRAAR7).

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9 Device and Documentation Support

9.1 Device Support

9.1.1 Development Support

TI offers an extensive line of development tools, including tools to evaluate the performance of the
processors, generate code, develop algorithm implementations, and fully integrate and debug software
and hardware modules. The support documentation for the tools is electronically available within the Code
Composer Studio™ Integrated Development Environment (IDE).
The following products support development of TMS320DM814x processor applications:
Software Development Tools: Code Composer Studio™ Integrated Development Environment (IDE):
including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target
software needed to support any DaVinci Digital Media Processor application.
Hardware Development Tools: Extended Development System (XDS™) Emulator
For a complete listing of development-support tools for the DM814x DaVinci™ Digital Media Processor
platform, visit the Texas Instruments website at www.ti.com. For information on pricing and availability,
contact the nearest TI field sales office or authorized distributor.

9.1.2 Device and Development-Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
DSP + ARM devices and support tools. Each DSP + ARM commercial family member has one of three
prefixes: TMX, TMP, or TMS (for example, TMX320DM8148BCYE0). Texas Instruments recommends two
of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent
evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully
qualified production devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device's electrical
specifications.
TMP Final silicon die that conforms to the device's electrical specifications but has not completed
quality and reliability verification.
TMS Fully-qualified production device.

Support tool development evolutionary flow:

TMDX Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS Fully qualified development-support product.

TMX and TMP devices and TMDX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.

370 Device and Documentation Support Copyright © 2011–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320DM8148 TMS320DM8147
 TMS320DM8148, TMS320DM8147
www.ti.com SPRS647E – MARCH 2011 – REVISED DECEMBER 2013

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, CYE), the temperature range (for example, "Blank" is the commercial
temperature range), and the device speed range in megahertz (for example, "Blank" is the default [600-
MHz ARM, 500-MHz DSP]).
Figure 9-1 provides a legend for reading the complete device name for any TMS320DM814x platform
member.
For device part numbers and further ordering information of TMS320DM814x devices in the CYE package
type, see the TI website (www.ti.com) or contact your TI sales representative.
For additional description of the device nomenclature markings on the die, see the TMS320DM814x
DaVinci™ Digital Media Processors Silicon Errata (Silicon Revision 2.1) (Literature Number: SPRZ343).

TMS 320 DM8148 ( ) CYE ( ) ( )

PREFIX DEVICE SPEED RANGE

TMX = Experimental Device Blank = 600-MHz ARM, 500-MHz DSP
TMS = Qualified Device 0 = 720-MHz ARM, 600-MHz DSP
1 = 1000-MHz ARM, 700-MHZ DSP
DEVICE FAMILY 1 = 1000-MHz ARM, 750-MHZ DSP [SR3.0 only]
320 = TMS320™ DSP Family 2 = 1000-MHz ARM, 750-MHz DSP
TEMPERATURE RANGE
DEVICE
Blank = 0°C to 90°C, Commercial Temperature
DM814x DaVinci™ Digital Media Processors D = -40°C to 90°C, Industrial Temperature
DM8148 A = -40°C to 105°C, Extended Temperature
DM8147
(A)
PACKAGE TYPE
SILICON REVISION CYE = 684-Pin Plastic BGA, with Pb-Free Die Bump
B = Revision 2.1 and Solder Ball
C = Revision 3.0 (Other)
S = Revision 3.0 (Video Security)
A. BGA = Ball Grid Array
B. For actual device part numbers (P/Ns) and ordering information, see the TI website (http://www.ti.com).
C. The TEMPERATURE RANGE values are specified over operating junction temperature.

Figure 9-1. Device Nomenclature(B)(C)

9.2 Documentation Support

The following document describes the DM814x DaVinci™ Digital Media Processors.
SPRUGZ8 TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual.

9.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and
help solve problems with fellow engineers.
TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help
developers get started with Embedded Processors from Texas Instruments and to foster
innovation and growth of general knowledge about the hardware and software surrounding
these devices.

Copyright © 2011–2013, Texas Instruments Incorporated Device and Documentation Support 371
Submit Documentation Feedback
Product Folder Links: TMS320DM8148 TMS320DM8147
TMS320DM8148, TMS320DM8147
SPRS647E – MARCH 2011 – REVISED DECEMBER 2013 www.ti.com

10 Mechanical
The device package has been specially engineered with a new technology called Via Channel™. The Via
Channel technology allows larger than normal PCB via sizes and reduced PCB signal layers to be used in
a PCB design with this 0.8-mm pitch package, and will substantially reduce PCB costs. Via Channel also
allows PCB routing in only two signal layers (four layers total) due to the increased layer efficiency of the
Via Channel™ BGA technology.

10.1 Thermal Data for CYE-04 (Top Hat)

Table 10-1. Thermal Resistance Characteristics (PBGA Package) [CYE-04] (Thinner Top Hat)
NO. °C/W (1) AIR FLOW (m/s) (2)
1 RΘJC Junction-to-case 0.39 N/A
2 RΘJB Junction-to-board 3.87 N/A
3 RΘJA Junction-to-free air 11.67 0.00
5 8.59 1.00
6 RΘJMA Junction-to-moving air 7.80 2.00
7 7.33 3.00
8 0.19 0.00
10 0.20 1.00
PsiJT Junction-to-package top
11 0.20 2.00
12 0.21 3.00
13 3.44 0.00
15 3.37 1.00
PsiJB Junction-to-board
16 3.26 2.00
17 3.17 3.00
(1) These measurements were conducted in a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] measurement,
which was conducted in a JEDEC defined 1S0P system) and will change based on environment as well as application. For more
information, see these EIA/JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Packages

Power dissipation of 2 W and an ambient temperature of 70ºC is assumed.

(2) m/s = meters per second

10.2 Packaging Information

The following packaging information and addendum reflect the most current data available for the
designated device(s). This data is subject to change without notice and without revision of this document.

372 Mechanical Copyright © 2011–2013, Texas Instruments Incorporated

Submit Documentation Feedback
Product Folder Links: TMS320DM8148 TMS320DM8147
 PACKAGE OPTION ADDENDUM

www.ti.com 30-Aug-2023

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

DM8147SCIS0 ACTIVE FCBGA CYE 684 60 RoHS & Green Call TI Level-4-250C-72 HR 0 to 90 TMS320DM8147SCYE0 Samples
662
MTDM8148CCYE2 ACTIVE FCBGA CYE 684 60 RoHS & Green Call TI Level-4-250C-72 HR 0 to 90 TMS320DM8148CCYE2 Samples
662
TMS320DM8147SCYE0 ACTIVE FCBGA CYE 684 60 RoHS & Green Call TI Level-4-250C-72 HR 0 to 90 TMS320DM8147SCYE0 Samples
662
TMS320DM8147SCYE1 ACTIVE FCBGA CYE 684 60 RoHS & Green Call TI Level-4-250C-72 HR 0 to 90 TMS320DM8147SCYE1 Samples
662
TMS320DM8147SCYE2 ACTIVE FCBGA CYE 684 60 RoHS & Green Call TI Level-4-250C-72 HR 0 to 90 TMS320DM8147SCYE2 Samples
662
TMS320DM8148CCYE0 ACTIVE FCBGA CYE 684 60 RoHS & Green Call TI Level-4-250C-72 HR 0 to 90 TMS320DM8148CCYE0 Samples
662
TMS320DM8148CCYE1 ACTIVE FCBGA CYE 684 60 RoHS & Green Call TI Level-4-250C-72 HR 0 to 90 TMS320DM8148CCYE1 Samples
662
TMS320DM8148CCYE2 ACTIVE FCBGA CYE 684 60 RoHS & Green Call TI Level-4-250C-72 HR 0 to 90 TMS320DM8148CCYE2 Samples
662
TMS320DM8148CCYEA0 ACTIVE FCBGA CYE 684 60 RoHS & Green Call TI | SNAGCU Level-4-250C-72 HR TMS320DM8148CCYEA0 Samples
662
TMS320DM8148SCYE0 ACTIVE FCBGA CYE 684 60 RoHS & Green Call TI Level-4-250C-72 HR TMS320DM8148SCYE0 Samples

TMS320DM8148SCYE1 ACTIVE FCBGA CYE 684 60 RoHS & Green Call TI Level-4-250C-72 HR TMS320DM8148SCYE1 Samples
662
TMS320DM8148SCYE2 ACTIVE FCBGA CYE 684 60 RoHS & Green Call TI Level-4-250C-72 HR TMS320DM8148SCYE2 Samples
662
TMS320DM8148SCYEA0 ACTIVE FCBGA CYE 684 60 RoHS & Green Call TI Level-4-250C-72 HR TMS320DM8148SCYEA0 Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 30-Aug-2023

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2022

TRAY

L - Outer tray length without tabs KO -

Outer
tray
height

W-
Outer
tray
width
Text

P1 - Tray unit pocket pitch

CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center

Chamfer on Tray corner indicates Pin 1 orientation of packed units.

*All dimensions are nominal

Device Package Package Pins SPQ Unit array Max L (mm) W K0 P1 CL CW
Name Type matrix temperature (mm) (µm) (mm) (mm) (mm)
(°C)
DM8147SCIS0 CYE FCBGA 684 60 5 X 12 150 315 135.9 12190 25.5 17.25 16.95
MTDM8148CCYE2 CYE FCBGA 684 60 5 X 12 150 315 135.9 12190 25.5 17.25 16.95
TMS320DM8147SCYE0 CYE FCBGA 684 60 5 X 12 150 315 135.9 12190 25.5 17.25 16.95
TMS320DM8147SCYE1 CYE FCBGA 684 60 5 X 12 150 315 135.9 12190 25.5 17.25 16.95
TMS320DM8147SCYE2 CYE FCBGA 684 60 5 X 12 150 315 135.9 12190 25.5 17.25 16.95
TMS320DM8148CCYE0 CYE FCBGA 684 60 5 X 12 150 315 135.9 12190 25.5 17.25 16.95
TMS320DM8148CCYE1 CYE FCBGA 684 60 5 X 12 150 315 135.9 12190 25.5 17.25 16.95
TMS320DM8148CCYE2 CYE FCBGA 684 60 5 X 12 150 315 135.9 12190 25.5 17.25 16.95
TMS320DM8148CCYEA0 CYE FCBGA 684 60 5 X 12 150 315 135.9 12190 25.5 17.25 16.95
TMS320DM8148SCYE0 CYE FCBGA 684 60 5 X 12 150 315 135.9 12190 25.5 17.25 16.95
TMS320DM8148SCYE1 CYE FCBGA 684 60 5 X 12 150 315 135.9 12190 25.5 17.25 16.95
TMS320DM8148SCYE2 CYE FCBGA 684 60 5 X 12 150 315 135.9 12190 25.5 17.25 16.95
TMS320DM8148SCYEA0 CYE FCBGA 684 60 5 X 12 150 315 135.9 12190 25.5 17.25 16.95

Pack Materials-Page 1
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