20100025590
20100025590
20100025590
Kenneth A. LaBel
ken.label@nasa.gov
301-286-9936
Co- Manager,
Manager NEPP Program
http://nepp.nasa.gov
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SoC Overview - NEPP ETW presented by Kenneth A. LaBel June 23, 2010 1
What is a SOC?
• Wikipedia definition
– System-on-a-chip or system on chip (SoC or SOC) refers to
integrating all components of a computer or other electronic
system into a single integrated circuit (chip). It may contain
digital, analog, mixed-signal, and often radio-frequency
functions – all on a single chip substrate
substrate.
• A typical SoC may consist of:
– One microcontroller, microprocessor or DSP core(s).
• Some SoCs – called multiprocessor System
System-on-Chip
on Chip (MPSoC) – include more than one
processor core.
– Memory blocks including a selection of ROM, RAM, EEPROM and flash.
– Timing sources including oscillators and phase-locked loops.
– Peripherals including counter-timers, real-time timers and power-on reset generators.
– External interfaces including industry standards such as USB, FireWire, Ethernet,
USART, SPI.
– Analog interfaces including ADCs and DACs.
DACs
– Voltage regulators and power management circuits.
– These blocks are connected by either a proprietary or industry-standard bus such as
the AMBA bus from ARM. DMA controllers route data directly between external
i t f
interfaces and
d memory, by-passing
b i the
th processor core and d thereby
th b increasing
i i the
th
data throughput of the SoC.
SoC Overview - NEPP ETW presented by Kenneth A. LaBel June 23, 2010 2
Examples of SoCs
FPGA version
Microcontroller-based SOC
Standard IC version
Microcontroller based SOC
Microcontroller-based
SoC Overview - NEPP ETW presented by Kenneth A. LaBel June 23, 2010 3
What types of devices are tagged
SOCs?
• SoCs can be fabricated in several technologies, including:
– Full custom
– Standard cell
– FPGA
• Advantages
Ad t
– Lower power and cost than the multi-chip systems that they replace.
– Higher reliability (fewer components)
• However, like most VLSI designs, the total cost is higher for
one large chip than for the same functionality distributed over
several smaller chips,
p , because of lower yields
y and higher
g NRE
costs.
– In addition, packages tend to be much larger, have a very high IO pin
count,, and push
p the state-of-the-art for new p
package
g techniques
q to obtain
performance (non-space). Examples:
• Upwards of 1700 pins
• Flip-chip packages
• Non-hermetic
• BGA, CCGA, LGA…
SoC Overview - NEPP ETW presented by Kenneth A. LaBel June 23, 2010 4
Example SoC of Interest: MAESTRO
Multi-Core Processor (OGA)
• Highest Performance Rad Hard Processor
– 260 MHz, 38 GOPS, 19 GFLOPS
• Tiled Architecture
– 49 tile, 2-D Processor Array connected by low-latency
high bandwidth registermapped networks
• Tile Processor
– Main Processor: 3-way VLIW CPU
• 64-bit instruction bundle
• 32-bit integer operations
SoC Overview - NEPP ETW presented by Kenneth A. LaBel June 23, 2010 5
Example SoC of Interest: FPGAs
• FPGAs have been the poster child for
new technologies and have replaced
standard logic, ASICs, and processors
in many NASA missions.
• Newer devices have even more features
that make them true SoCs “RT ProASIC®3 FPGAs are the first to offer designers
– (Re)programmable logic/fabric of space-flight hardware a radiation-tolerant (RT),
reprogrammable, nonvolatile logic integration
– Embedded processors/DSP strings vehicle. Theyy are intended for low-power
p space
p
– High speed IO (to 10 Gbps) applications requiring up to 350 MHz operation and
up to 3 million system gates”
– ADC functions, and more
SoC Overview - NEPP ETW presented by Kenneth A. LaBel June 23, 2010 10