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System on a Chip (SoC) Overview

Kenneth A. LaBel
ken.label@nasa.gov
301-286-9936
Co- Manager,
Manager NEPP Program

http://nepp.nasa.gov
p pp g
SoC Overview - NEPP ETW presented by Kenneth A. LaBel June 23, 2010 1
What is a SOC?
• Wikipedia definition
– System-on-a-chip or system on chip (SoC or SOC) refers to
integrating all components of a computer or other electronic
system into a single integrated circuit (chip). It may contain
digital, analog, mixed-signal, and often radio-frequency
functions – all on a single chip substrate
substrate.
• A typical SoC may consist of:
– One microcontroller, microprocessor or DSP core(s).
• Some SoCs – called multiprocessor System
System-on-Chip
on Chip (MPSoC) – include more than one
processor core.
– Memory blocks including a selection of ROM, RAM, EEPROM and flash.
– Timing sources including oscillators and phase-locked loops.
– Peripherals including counter-timers, real-time timers and power-on reset generators.
– External interfaces including industry standards such as USB, FireWire, Ethernet,
USART, SPI.
– Analog interfaces including ADCs and DACs.
DACs
– Voltage regulators and power management circuits.
– These blocks are connected by either a proprietary or industry-standard bus such as
the AMBA bus from ARM. DMA controllers route data directly between external
i t f
interfaces and
d memory, by-passing
b i the
th processor core and d thereby
th b increasing
i i the
th
data throughput of the SoC.

SoC Overview - NEPP ETW presented by Kenneth A. LaBel June 23, 2010 2
Examples of SoCs

FPGA version
Microcontroller-based SOC
Standard IC version
Microcontroller based SOC
Microcontroller-based

SoC Overview - NEPP ETW presented by Kenneth A. LaBel June 23, 2010 3
What types of devices are tagged
SOCs?
• SoCs can be fabricated in several technologies, including:
– Full custom
– Standard cell
– FPGA
• Advantages
Ad t
– Lower power and cost than the multi-chip systems that they replace.
– Higher reliability (fewer components)
• However, like most VLSI designs, the total cost is higher for
one large chip than for the same functionality distributed over
several smaller chips,
p , because of lower yields
y and higher
g NRE
costs.
– In addition, packages tend to be much larger, have a very high IO pin
count,, and push
p the state-of-the-art for new p
package
g techniques
q to obtain
performance (non-space). Examples:
• Upwards of 1700 pins
• Flip-chip packages
• Non-hermetic
• BGA, CCGA, LGA…
SoC Overview - NEPP ETW presented by Kenneth A. LaBel June 23, 2010 4
Example SoC of Interest: MAESTRO
Multi-Core Processor (OGA)
• Highest Performance Rad Hard Processor
– 260 MHz, 38 GOPS, 19 GFLOPS

• Tiled Architecture
– 49 tile, 2-D Processor Array connected by low-latency
high bandwidth registermapped networks

• Tile Processor
– Main Processor: 3-way VLIW CPU
• 64-bit instruction bundle
• 32-bit integer operations

– Static Switch Processor


– Floating Point Co-Processor (IEEE 754 single and
double precision)
• Memory
y
– L1 cache: 2 cycle latency
– L2 cache: 7 cycle latency
750 million transistors
– Tiles can access each others L2 18 million gates
– Off-chip
Off chip Main Memory: 88 cycle latency
44 million
illi memory bits bit
• I/O Interfaces
– Four XAUI
3 million flip-flops
– Four DDR1/2 Largest
g die fabricated by y IBM in 9SF
– Two GBE
(30.6X25.6 mm)

SoC Overview - NEPP ETW presented by Kenneth A. LaBel June 23, 2010 5
Example SoC of Interest: FPGAs
• FPGAs have been the poster child for
new technologies and have replaced
standard logic, ASICs, and processors
in many NASA missions.
• Newer devices have even more features
that make them true SoCs “RT ProASIC®3 FPGAs are the first to offer designers
– (Re)programmable logic/fabric of space-flight hardware a radiation-tolerant (RT),
reprogrammable, nonvolatile logic integration
– Embedded processors/DSP strings vehicle. Theyy are intended for low-power
p space
p
– High speed IO (to 10 Gbps) applications requiring up to 350 MHz operation and
up to 3 million system gates”
– ADC functions, and more

• Examples of newer devices:


– Vilinx Virtex 4QV
• Rad hard Virtex 5QV
forthcoming “Xilinx Virtex-4QV devices offer up to 200,000 logic cells, 10Mbit of RAM/FIFO,
two built-in PowerPC® 405 processor blocks with an APU controller, 512 DSP™
– ACTEL RTAX4000S slices, and four built-in Ethernet blocks. Virtex-4QV FPGA s deliver outstanding
performance with 400Mhz clocking, DSP slices delivering 204 GMACs at
• New RTProASIC series 400MHz, and 350MHz PowerPC processors, all in a single device. Flexible 800
Mbps differential I/O and 500 Mbps single-ended I/O support industry-standard
and custom protocols. “
SoC Overview - NEPP ETW presented by Kenneth A. LaBel June 23, 2010 6
Why Does NEPP Care about SOCs?
• Potential savings of Size, Weight, and Power
(SW P) tto S
(SWaP) Spacecraft
ft as well
ll as increased
i d system
t
performance
• Multi-core
Multi core processor SoCs have sparked interest
by aerospace technology developers and at
multiple
u t p e agencies
age c es
– Example: autonomous docking operations
• Existing
g test guidance
g often doesn’t cover new
technology issues
SoCs are p
pushing
g the state-of-the-art for both fabrication
and packaging as well as design and verification/validation
Understandingg qualification
q issues are critical
to NASA mission insertion
SoC Overview - NEPP ETW presented by Kenneth A. LaBel June 23, 2010 7
So what’s the concern?
• Complexity
C l it drives
di it all
ll
– Radiation tolerance and testability are challenges for fault
isolation, propagation, and validation
– Bigger single silicon die than flown before and technology is
scaling below 90nm (new qual methods)
– Packages
g have changedg and are bigger
gg and more difficult to
inspect, test, and understand. Add in embedded passives…
– Material interfaces are more complex (underfills, processing)
– New rules for board layouts.
layouts Mechanical and thermal designs,
designs
etc…
• How to predict radiation performance (SEU rates, etc)
requires
i complex
l toolbox
t lb
– DoD and NEPP are funding the tools for the toolbox
– NASA OTC funding g toolbox infrastructure for users – this is at
risk with NASA’s recent change of technology direction
Lesson learned:
Manufacturers are here to make money
money.
Believing marketing briefs is risky at best.
SoC Overview - NEPP ETW presented by Kenneth A. LaBel June 23, 2010 8
NEPP and SOCs

• Efforts that follow are focused on understanding


b th the
both th failure
f il modes
d off this
thi class
l off devices
d i as
well as developing qualification guidelines
• Radiation Evaluation
– SoC Processors
– SoC FPGAs
– Predicting SEU Rates for Advanced CMOS Electronics
(6/24)
• Parts and Package Qualification
– Class Y non-hermetic qualification
– Th
Thermal l reliability
li bilit (hot
(h t spots!)
t !)
– Design impacts
– Scaled CMOS (6/24) will highlights the CMOS based
issues involved
SoC Overview - NEPP ETW presented by Kenneth A. LaBel June 23, 2010 9
QUESTIONS?

SoC Overview - NEPP ETW presented by Kenneth A. LaBel June 23, 2010 10

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