Infineon-MA12070P-DataSheet-v01_01-EN (2)

MA12070P
Filterless and High-Efficiency +4V to +26V

Audio Amplifier with I2S Digital Input
Description Features
The MA12070P is a super-efficient audio power • Proprietary Multi-level Switching Technology
amplifier based on proprietary multi-level switching ◦ 3-level and 5-level modulation
technology. It supports a 4-26V supply voltage range, ◦ Low EMI emission
allowing it to be used in many different applications.
◦ Filterless amplification
Multi-level switching enables very low power loss ◦ Digital Power Management Algorithm
during operation. In addition, it allows the amplifier to • High Power Efficiency (PMP4)
be used in filterless configurations at full rated power
◦ 400mW Idle power dissipation (26V PVDD, all
in a wide range of audio products.
channels switching)
The MA12070P features an embedded digital power ◦ >80% Efficiency at 2W power (1kHz sine, 8Ω)
management scheme. The power management ◦ >92% Efficiency at Full Power (1kHz sine, 8Ω)
algorithm dynamically adjusts switching frequency and
• Audio Performance (PMP2)
modulation to optimize power loss and EMI across the
output power range. ◦ >101dB DNR (A-w, rel. to 1% THD+N power
level)
An integrated digital-to-analog converter enables ◦ 140µV output integrated noise (A-w)
digital I2S audio stream input. It supports sample rates
◦ 0.007% THD+N at high output levels
from 44.1 kHz to 192 kHz.
• 4th Order Feedback Error Control
Highly flexible output stage configurations are offered, ◦ High suppression of supply disturbance
ranging from four single-ended outputs to a single
◦ HD audio quality
parallel-BTL output.
• Supply Voltages: +4V to +26V (PVDD) and +5V
The MA12070P features protection against DC, short- (A/DVDD)
circuits, over-temperature and under-voltage • Volume Control and Limiter
situations.
• 2x30W continuous output power (RL = 8Ω at 22V,
Flexible “Power Mode Profiles” allow the user to utilize PMP4, 10% THD+N level, without heatsink)
the multi-level switching technique for very low power • 2×80W peak output power (26V PVDD, RL = 4Ω,
loss or very high audio performance. 10% THD+N level)
Device communication and programming is controlled • 2.0, 2.1, 4.0, 1.0 Output Stage Configurations
through an I2C interface as well as dedicated control • Protection
pins. ◦ Under-voltage-lockout
◦ Over-temperature warning/error
◦ Short-circuit/overload protection
◦ Power stage pin-to-pin short-circuit
Applications ◦ Error-reporting through serial interface (I2C)
• Battery Operated Speakers ◦ DC protection
• Wireless and Docking Speakers • I2C control (four selectable addresses)
• Soundbars • Heatsink free operation with EPAD-down package
• Multiroom Systems
Package
• Home Theater Systems
• 64-pin QFN Package with exposed thermal pad
(EPAD) and Lead-free Soldering
Datasheet Please read the Important Notice and Warnings at the end of this document V 1.1
www.infineon.com page 1 of 88 2022-02-09
1 Ordering Information
Table 1-1
Part Number Package Moisture Description

Sensitivity Level
Quad Flat No-leads package, EPAD-down (exposed thermal pad on
MA12070P QFN-64 Level 3
bottom side)
2 Known Issues and Limitations

Please refer to the errata sheet document for descriptions of issues and limitations relating to device operation and performance.
3 Typical Application Block Diagram
100nF 1µF 1µF 1µF

CFGD CGD0 CGD1 CFDC
VDD VDD
CGDC 1µF
CFDCP
CFDCN
CFGDP
CFGDN
CGD1P
CGD0P
CGD0N
CGD1N
VGDC
AVDD DVDD
1µF
1µF
AVSS Analog DVSS
power CDC
1µF CREF CDC 1µF PVDD
and Charge pump power supplies
1µF CMSE reference PVDD
voltages
1µF 1µF
+
PVSS 470µF
Audio source
Data pair 0 SD0 PVDD
DAC
reciever 0
(0L,0R)
Power OUT0A
I2S
amp CF0AP
Volume control
2x10µF
and limiter
DAC CF0AN
PVSS CF0A
0L
SD1 PVDD
DAC
reciever 1
Power OUT0B
Channel configuration
I2S
amp CF0BP
DAC 2x10µF
CF0BN
PVSS CF0B
SCK PVDD
Power
Clock and WS
Clock management Power OUT1A
timing CLK
management amp CF1AP
CLKM/S 2x10µF
Temp sensor CF1AN
PVSS CF1A
0R
PVDD
Control and protection Power OUT1B
amp CF1BP
2x10µF
/ENABLE
CF1BN
/ERROR
/MUTE
MSEL1
MSEL0
PVSS CF1B EMC filter

/CLIP
AD1
AD0
SDA
depending on
SCL
EPAD
application
Host system 5V
Figure 3-1 Typical application block diagram
4 Pin Description
4.1 Pinout MA12070P
Top view
Pin 1
CGD0N
CGD1N
CFGDN
CFDCN
CGD0P
CGD1P
CFGDP
MSEL0
MSEL1
Indicator
CFDCP
DVDD
VGDC
DVSS
CDC
NC
NC
64
63
62
61
58
57
56
55
53
52
51
50
60
59
54
49
PVSS 1 48 PVSS
PVSS 2 47 PVSS
CF0AN 3 46 CF1AN
OUT0A 4 45 OUT1A
OUT0A 5 44 OUT1A
CF0AP 6 43 CF1AP
PVDD 7 42 PVDD
PVDD 8 exposed thermal 41 PVDD
CF0BP 9 pad on bottom side 40 CF1BP
OUT0B 10 39 OUT1B
OUT0B 11 38 OUT1B
CF0BN 12 37 CF1BN
PVSS 13 36 PVSS
PVSS 14 35 PVSS
/CLIP 15 34 /MUTE
/ERROR 16 33 /ENABLE
17
18
19
20
23
24
25
26
28
29
30
31
21
22
27
32
DVSS
SCK
SCL
CMSE
CREF
AVDD
SD0
SD1
AD0
AD1
CLKM/S
AVSS
AVSS
CLK
SDA
WS
Figure 4-1 Pinout MA12070P
4.2 Pin Function
Table 4-1
Pin No. Name Type1 Description
1 PVSS P Power ground for internal power amplifiers
3 CF0AN P Connect to external flying capacitor negative terminal for amplifier channel 0A
4 OUT0A O Audio power output 0A
6 CF0AP P Connect to external flying capacitor positive terminal for amplifier channel 0A
7 PVDD P Power supply for internal power amplifiers
8 PVDD P Power supply for internal power amplifiers
9 CF0BP P Connect to external flying capacitor positive terminal for amplifier channel 0B
10 OUT0B O Audio power output 0B
12 CF0BN P Connect to external flying capacitor negative terminal for amplifier channel 0B
15 /CLIP O Audio clipping indicator (open drain output), pulled low when clipping occurs
16 /ERROR O Error indicator (open drain output), pulled low when an error occurs
17 AVDD P Power supply for internal analog circuitry
18 CMSE O Decoupling pin for internally generated common-mode voltage in SE configuration.
Should be externally decoupled to AVSS. Can be left floating for 2 x BTL and PBTL
configurations.
19 AVSS P Ground for internal analog circuitry
20 CREF O Decoupling pin for internally generated analog reference voltage. Should be externally
decoupled to AVSS.
21 SCK I I2S, digital audio serial clock. Must be synchronized to CLK
22 WS I I2S, digital audio word select. Must be synchronized to CLK
23 SD0 I I2S, digital audio serial data pair 0
24 SD1 I I2S, digital audio serial data pair 1
25 AVSS P Ground for internal analog circuitry
26 DVSS P Ground for internal digital circuitry
27 SCL IO I2C bus serial clock
28 AD0 I I2C device address select 0 (see “MCU/Serial control interface” section)
29 AD1 I I2C device address select 1 (see “MCU/Serial control interface” section)
30 SDA IO I2C bus serial data
31 CLKM/S I Reserved - must be pulled low
32 CLK I Clock input. Must be present before enabling the amplifier.
33 /ENABLE I When pulled high, the device is reset and kept in an inactive state with minimum power
consumption.
34 /MUTE I Mute audio output when pulled low
37 CF1BN P Connect to external flying capacitor negative terminal for amplifier channel 1B
40 CF1BP P Connect to external flying capacitor positive terminal for amplifier channel 1B
Pin No. Name Type1 Description
41 PVDD P Power supply for power amplifiers
42 PVDD P Power supply for power amplifiers
43 CF1AP P Connect to external flying capacitor positive terminal for amplifier channel 1A
46 CF1AN P Connect to external flying capacitor negative terminal for amplifier channel 1A
49 NC P Internally connected to DVDD – should be not connected
50 MSEL1 I SE/BTL/PBTL configuration select 1
51 MSEL0 I SE/BTL/PBTL configuration select 0
52 CGD1N P Connect to external decoupling capacitor negative terminal for internal gate driver
power supply 1
53 CGD1P P Connect to external decoupling capacitor positive terminal for internal gate driver
power supply 1
54 VGDC P Internally generated virtual ground voltage for digital core. Should be decoupled to
DVDD.
55 DVDD P Power supply for internal digital circuitry and charge pumps
56 CDC P Connect to external decoupling capacitor for digital core internal power supply
57 CFDCP P Connect to external flying capacitor positive terminal for internal digital core power
supply
58 CFDCN P Connect to external flying capacitor negative terminal for internal digital core power
supply
59 DVSS P Power ground for internal digital circuitry
60 CGD0P P Connect to external decoupling capacitor positive terminal for internal gate driver
power supply 0
61 CGD0N P Connect to external decoupling capacitor negative terminal for internal gate driver
power supply 0
62 CFGDP P Connect to external flying capacitor positive terminal for internal gate driver power
supplies
63 CFGDN P Connect to external flying capacitor negative terminal for internal gate driver power
supplies
64 NC P Internally connected to DVDD - should be not connected
Type1: P = Power; I = Input; O = Output; IO = Input or Output
5 Absolute Maximum Ratings
Table 5-1
Parameter Value Unit
Power Supplies
Power stage supply voltage, PVDD -0.5 to +27.5 V
System supply voltage, DVDD, AVDD -0.5 to +6.0 V
Input / Output
Logic: /ENABLE, /MUTE, /ERROR, /CLIP, MSEL0, MSEL1,
CLKM/S, CLKIO, SCL, SDA, AD0, AD1 -0.5 to +6.0 V
Output current, Logic and Interface 25 mA
Thermal Conditions
Ambient temperature range, TA -40 to +85 °C
Junction temperature range, TJ -40 to +150 °C
Storage temperature range -65 to +150 °C
Thermal resistance, Junction-to-Ambient 23 °C/W
Thermal resistance, Junction-to-EPAD 2.3 °C/W
Lead soldering temperature, 10s +300 °C
Electrostatic Discharge (ESD)
Human body model (HBM) ± 2000 V
Charged device model (CDM) ± 1000 V
PLEASE NOTE:
Device usage beyond the above stated ratings may cause permanent damage to the device. Permanent usage at the above stated ratings may limit
device lifetime and result in reduced reliability. This is a stress rating only; functional operation of the device at these or any other conditions above
those indicated in the operational section of this specification is not implied.
See “Recommended Operation Conditions” for continuous functional ratings.
6 Recommended Operating Conditions
Table 6-1
Symbol Parameter Min Typ Max Unit
PVDD Power Stage Power Supply 5 26 V
DVDD Digital Power Supply 4.75 5 5.25 V
AVDD Analog Power Supply 4.75 5 5.25 V
VIH_3V3 High Level for:
/ENABLE, /MUTE, /ERROR, /CLIP, CLKIO, SCL, SDA, AD0, AD1 2 V
VIL_3V3 Low Level for:
/ENABLE, /MUTE, /ERROR, /CLIP, CLKIO, SCL, SDA, AD0, AD1 0.8 V
VIH_5V0 High Level for MSEL0, MSEL1, CLKM/S 3.5 V
VIL_5V0 Low Level for MSEL0, MSEL1, CLKM/S 0.8 V
VIN_dc DC Offset Level for Analog Inputs 1.2 2.5 3.8 V
VIN_ac Audio Signal Level for Analog Inputs 1.8 Vpp
RL (BTL) Minimum Load in Bridge-Tied Load Mode 3.2 4 Ω
RL (PBTL) Minimum Load in Parallel Bridge-Tied Load Mode 1.6 2 Ω
RL (SE) Minimum Load in Single Ended Mode 2.4 3 Ω
Minimum required equivalent load inductance per output pin

LLeq 0.5 µH
for short circuit protection
TA Ambient temperature range 0 +25 +85 °C
Note: Minimum Load resistance was measured in Filterless output condition.
7 Electrical and Audio Characteristics
Table 7-1
Power Mode Profile = 0; VDD (Analog & Digital) = +5V; PVDD = +26V; TA = 0°C to +85°C. Typical values are at TA = +25°C
Symbol Parameter Conditions Min Typ Max Unit
Output Power per channel (peak),
POUT (BTL) THD+N = 10%, RL = 8Ω, f = 1kHz 45 W
Without Heatsink, see Note 1
THD+N = 10%, RL = 4Ω, f = 1kHz 80 W
THD+N = 1%, RL = 8Ω, f = 1kHz 35 W
THD+N = 1%, RL = 4Ω, f = 1kHz 60 W

Output Power per channel
(continuous) Without Heatsink, RL = 8Ω, f = 1kHz, PVDD = +22V 30 W
see Note 2
POUT (PBTL) Output Power (peak), see Note 1 THD+N = 10%, RL = 2Ω, f = 1kHz 160 W
THD+N = 1%, RL = 2Ω, f= 1kHz 120 W

Output Power per channel (peak), THD+N = 10%, RL = 4Ω, f = 1kHz 20 W
POUT (SE) see Note 1
THD+N = 10%, RL = 3Ω, f = 1kHz 25 W
THD+N = 1%, RL = 4Ω, f = 1kHz 15 W
THD+N = 1%, RL = 3Ω, f = 1kHz 20 W
TENABLE Shutdown/Full Operation Timing NENABLE = 1 → 0 1 ms
TMUTE Mute/Unmute Timing NMUTE = 1 → 0 and 0 → 1 0.3 ms
VOS,BTL/PBTL Output Offset Voltage, see Note 4 ±35 mV
VOS,SE Output Offset Voltage, see Note 4,5 50 mV
PSRR Power Supply Rejection Ratio ± 100mVpp ripple voltage 70 dB
Ron Resistance, switch on 0.10 0.15 0.20 Ω
Power Mode A 618 672 726 kHz

Power MOSFET Switching
fSW Power Mode B & C 316 336 356 kHz
Frequency, see Note 3
Power Mode D 158 168 178 kHz
fCLK_IO Clock Output Frequency 2.7151 2.8224 2.9296 MHz
IOUT/OCPTHR Maximum Output Current 8 A
XTalk Crosstalk BTL, POUT = 1W, f=1kHz, Ch1 & 2 -108 dB
Note 1: The thermal design of the target application will significantly impact the ability to achieve the peak output power levels for extended time.
See “Thermal Characteristics and Test Signals” section for thermal optimization recommendations.
Note 2: Continuous power measurements were performed on the MA12070 proprietary Amplifier EVK without heatsinking at 25⁰C ambient
temperature in Power Mode Profile 4.
Note 3: Power MOSFET switching frequency depends on which properties are assigned to the individual power modes of the device. Detailed
information on this can be found in “Power Mode Management” section.
Note 4: Offset is specified as the voltage difference between the “mute” and “unmute” state.
Note 5: The offset number is only guaranteed for the SE channels in 2.1 configuration.
Table 7-2
VDD (Analog & Digital) = +5V; PVDD = +26V; Typical values are at TA = +25°C; Output Configuration: BTL
η Efficiency POUT = 2×40W, 8Ω , PMP = 0 91 %
POUT = 2×40W, 8Ω , PMP = 1 91 %
POUT = 2×40W, 8Ω , PMP = 2 89 %
POUT = 2×40W, 8Ω , PMP = 4 92 %
POUT = 2×80W, 4Ω , PMP = 0 87 %
POUT = 2×80W, 4Ω , PMP = 1 87 %
POUT = 2×80W, 4Ω , PMP = 2 86 %
POUT = 2×80W, 4Ω , PMP = 4 88 %
Table 7-3
Power Mode Profile = 0; VDD (Analog & Digital) = +5V; PVDD = +26V; TA = 0°C to +85°C. Typical values are at TA = +25°C.
Ishutdown Current Consumption, PVDD Shutdown 10 35 180 µA
Iidle,mute Current Consumption, PVDD Idle, mute 4 6 12 mA
Iidle,unmute Current Consumption, PVDD Idle, unmute, inputs grounded 4 9 18 mA
IDVDD+AVDD Current Consumption, AVDD+DVDD Idle, unmute, inputs grounded 30 35 42 mA
1kHz, POUT = 1W, RL = 4Ω 0.013 %

THD+N Total Harmonic Distortion + Noise
1kHz, POUT = 20W, RL = 4Ω 0.014 %
DNR Dynamic Range1 20-20kHz, A-weighted 100 dB
Vnoise Output integrated noise level 20-20kHz, A-weighted 105 150 190 µVrms
Table 7-4
Power Mode Profile = 2; VDD (Analog & Digital) = +5V; PVDD = +26V; TA = 0°C to +85°C. Typical values are at TA = +25°C.
Ishutdown Current Consumption, PVDD Shutdown 10 35 180 µA
Iidle,mute Current Consumption, PVDD Idle, mute 4 6 12 mA
Iidle,unmute Current Consumption, PVDD Idle, unmute, inputs grounded 4 11 22 mA
IDVDD+AVDD Current Consumption, AVDD+DVDD Idle, unmute, inputs grounded 33 38 45 mA
1kHz, POUT = 1W, RL = 4Ω 0.012 %

THD+N Total Harmonic Distortion + Noise
1kHz, POUT = 20W, RL = 4Ω 0.016 %
DNR Dynamic Range1 20-20kHz, A-weighted 101 dB
Vnoise Output integrated noise level 20-20kHz, A-weighted 110 140 170 µVrms
1 Output power at THD+N < 1% reference to noise floor at -60dBFS signal.
NOTE: MA12070P gives users the freedom to choose Power Mode Profiles (PMP) independently. As noted in the specifications table, the choice in
power mode profiles gives a trade-off between power efficiency and audio performance as an individual set of performance characteristics. See
“Power Mode Profiles” section for more details.
8 Functional description
Multi-level modulation
The power stage of the MA12070P is a true multi-level switching topology. Each half-bridge is capable of delivering a
PWM output with three voltage levels, rather than the conventional two. The three-level half-bridges are each driven
with a two-phase PWM signal, so that the switching frequency seen at the PWM output is twice that of the individual
power MOSFET switching frequency.
For very low EMI in BTL configuration, the two half-bridges are operated in a complementary fashion (i.e. with 240⁰
phase shift), which removes common-mode PWM output content. This configuration is ideal for driving long speaker
cables without an output filter. Differentially, this modulation method drives the filter/load assembly with three PWM
levels.
For reduced power loss in the BTL configuration, the half-bridges can also be driven in a quadrature phase shifted
fashion (i.e. with 90⁰ phase shift). This provides a total of five PWM levels at the load, along with a quadrupling of
MOSFET switching frequency with respect to the differential PWM switching frequency. With this modulation scheme,
the MOSFET switching frequency can therefore be lowered, in order to decrease switching losses. The five-level
modulation scheme produces a common-mode voltage on the load wires, but with less high-frequency content
compared to conventional two-level BD modulation.
The multi-level switching topology of the MA12070P makes filterless operation viable, since the modulation schemes
ensure little or no idle losses in the speaker magnetic system.
For applications with stringent EMC requirements or long speaker cables, the MA12070P can operate with a very small
and inexpensive EMI/EMC output filter. This is enabled by the multiple PWM output levels and the frequency
multiplication seen on the PWM switching nodes. Notably, with the multi-level modulation of the MA12070P, there is
no tradeoff between idle power loss and inductor cost/size, which is due to the absence of inductor ripple current under
idle conditions in all configurations. Due to the high filter cutoff frequency, non-linearities of LC components have less
impact on audio performance than with a conventional amplifier. Therefore, the MA12070P can operate with
inexpensive iron-powder cored inductors and ceramic (X7R) filter capacitors with no significant audio performance
penalty.
Very low power consumption

The MA12070P achieves very low power loss under idle and near-idle operating conditions. This is due to the zero idle
ripple property of the multi-level PWM scheme, in combination with the programmable automatic reduction of
switching frequency at low modulation index levels; resulting in a state-of-the-art power efficiency at low and medium
output power levels.
For high output power levels, power efficiency is determined primarily by the on-resistance (Rdson) of the output power
MOSFETs. With music and music-like (e.g. pink noise) output signals with high crest factor, the reduced near-idle losses
of the MA12070P contribute to reducing power losses compared to a conventional amplifier with the same Rdson. In
most applications, this allows the MA12070P to run at high power levels without a heatsink.
Power Mode Management

The MA12070P is equipped with an intelligent power management algorithm which applies automatic power mode
selection during audio playback. In this state, the amplifier will seamlessly transition between three different power
modes depending on the audio level in order to achieve optimal performance in terms of power loss, audio performance
and EMI. Figure 8-1 shows an illustration of the basic power mode management. Alternatively, it is possible to manually
select the desired power mode for the MA12070P via the serial interface.
In both manual and automatic power mode selection, the power mode can be configured and set on-the-fly during
audio playback, with no audible artifacts. This makes it possible to optimize the target application to achieve the best
possible operating performance at all audio power levels.
During automatic power mode selection, the MA12070P can transition between power modes at programmable audio
level thresholds. The thresholds can be set via the serial control interface, by addressing the associated registers.
Power mode Power mode
change change
1 2 3 Power mode
Low to
Medium High Max Audio level
moderate
Figure 8-1 Illustration of automatic power mode selection ranges.

To allow easy use of the power mode management, “Power Mode Profiles” have been defined. The “Power Mode
Profiles” address the appropriate power modes for a variety of applications.
Power Modes Profiles

The MA12070P provides 5 different power mode profiles for operating the internal power amplifiers. The power mode
profiles give the user freedom to choose optimal settings of the amplifier for the intended application.
The available power modes profiles are referred to as 0, 1, 2, 3 and 4 and can be set by programming the according
register (see). The power mode profile selection affects various parameters such as switching frequency, modulation
scheme and loop-gain, thus providing flexibility in design tradeoffs such as audio performance, power loss and EMI.
Table 8-1 shows the characteristics of the power mode profiles.
Table 8-1 Power Mode Profile characteristics
Property Profile 0 Profile 1 Profile 2 Profile 3 Profile 4

PM switch seq. D↔D↔C B↔B↔B B↔B↔A D↔B↔A D↔D↔D
Idle loss Very low Low Low Very low Very low
Full scale
Good Good Good Normal Best
efficiency
THD+N Good Best Best Good/Best Good
Common-mode
Only DC Only DC Only DC Only DC Only DC
content, idle
DC + Sidebands DC + sidebands
Common-mode
around 600kHz, around 300kHz,
content, full-scale Only DC Only DC Only DC
1.8MHz, 3.0MHz, 900kHz, 1.5MHz,
audio
etc. etc.
Differential Audio + sidebands Audio + sidebands Audio + sidebands Audio + sidebands Audio + sidebands
content low-to- around multiples around multiples around multiples around multiples around multiples
mid-power of 1.2MHz of 1.2MHz of 1.2MHz of 600kHz of 600kHz
Differential Audio + sidebands Audio + sidebands Audio + sidebands Audio + sidebands Audio + sidebands
content mid-to- around multiples around multiples around multiples around multiples around multiples
high power of 600kHz of 1.2MHz of 1.2MHz of 1.2MHz of 600kHz
Filterfree: Filterfree: LC filter: high Filterfree:

Filterfree:
optimized audio optimized audio efficiency, high optimized
optimized
Application performance, performance, audio perform- efficiency, active
efficiency, default
active speaker default ance, good EMI, speaker
applications
applications applications low ripple loss applications
Note: There is a programmable “Profile 5” which allows the user to set up a custom profile.
The first row of Table 8-1 shows that each Power Mode Profile follows a certain Power Mode transition sequence. This
means that each Power Mode within every Power Mode Profile will have its specific set of properties (A, B, C or D).
The exact details of each assigned set of properties is reflected in Table 8-2.
Table 8-2 Set of properties assigned to Power Modes in the selectable Power Mode Profiles
Property A B C D
FET switching
600kHz 300kHz 300kHz 150kHz
frequency, fFET
Modulation scheme 3-level 5-level 3-level 5-level
Switching frequency
1.2MHz (2 x fFET) 1.2MHz (4 x fFET) 600kHz (2 x fFET) 600kHz (4 x fFET)
seen at load, fSW
Idle loss Reduced Low Low Very low
Full scale efficiency Normal Good Good Best
Open-loop gain High High Low Low
THD+N Best Best Good Good

Common-mode
Only DC Only DC Only DC Only DC
content, idle
Common-mode DC + sidebands around DC + sidebands around
content, full-scale Only DC 600kHz, 1.8MHz, Only DC 300kHz, 900kHz,
audio 3.0MHz, etc. 1.5MHz, etc.
Audio + sidebands Audio + sidebands Audio + sidebands Audio + sidebands
Differential content around multiples of around multiples of around multiples of around multiples of
1.2MHz 1.2MHz 600kHz 600kHz
Next to the pre-defined Power Mode Profiles it is also possible to define a custom profile which will be available under
Power Mode Profile 5. This profile can be configured using the “custom power mode profile” register (address 30). See
“Register Map” section for more details.
The MA12070P employs feedback of the output PWM signals in order to compensate for noise and other non-idealities
in the power processing path. A fourth-order analog feedback loop is used, which typically provides a loop gain of 60dB
to suppress errors in the audio band. For the typical high efficiency application this results in low THD (Total Harmonic
Distortion) at all audio frequencies, as well as excellent immunity (in excess of 75dB) to power supply borne
interferences.
Maximum achievable loop-gain is typically set by the PWM frequency stability criteria. Inherent frequency multiplication
of the multilevel topology therefore allows for a much more aggressive loop-filter (and therefore better THD and noise
properties) because of a higher effective PWM switching frequency seen at the output. See “Profile 0 and Profile 2” in
Table 8-1 for high-fidelity Power Mode Profiles.
For the lowest switching frequencies, the proprietary loop filter architecture seamlessly reduces feedback bandwidth
to ensure loop stability. In most applications (e.g. filterless applications), no further special attention is required to
ensure loop stability. In applications with very stringent EMI requirements, an LC filter can be used. In these cases
attention to loop stability is required since an un-damped LC filter effectively represents a short-circuit to ground at the
resonance frequency. In extreme cases, this can cause instability of the analog feedback loops. In order to avoid this, an
LC filter should use an inductor with more than 10mΩ DC resistance, and a series R-C circuit should be used to limit the
Q of the LC circuit to around 5.
Power supplies
The MA12070P generates internal supply voltages and uses external capacitors for this purpose and for decoupling.
Gate driver supplies
The MA12070P utilizes a floating supply voltage for the gate driver circuitry generated internally by a charge pump. The
gate driver power supply voltage is approximately 6V to 9V higher than PVDD. For PVDD voltages of 24V and higher it is
recommended to add decoupling capacitors (1uF & 100nF) from CGD0N & CGD1N to GND for improved power supply
robustness. Table 8-3 shows the required external charge pump and decoupling capacitors.
Table 8-3 Gate driver supply capacitors

Name Purpose Connection Type Value
CGD0 Decoupling of gate driver supply voltage 0 CGD0P, CGD0N 16V, high capacity, low precision 1uF
CGD1 Decoupling of gate driver supply voltage 1 CGD1P, CGD1N 16V, high capacity, low precision 1uF
CFGD Charge pump flying capacitor CFGDP, CFGDN 50V, high capacity, low precision 100nF
CGD0N Decoupling of gate driver supply voltage 0 CGD0N, GND 50V, high capacity, low precision 1uF, 100nF
CGD1N Decoupling of gate driver supply voltage 1 CGD1N, GND 50V, high capacity, low precision 1uF, 100nF
Digital core supply

The digital control unit in the MA12070P uses a supply voltage generated internally by a charge pump and a voltage
regulator for highest efficiency. Table 8-4 lists the external capacitors required and describes their function and
connection.
Table 8-4 Digital supply capacitors
CDC Charge pump output voltage decoupling to GND CDC, GND >=6.3V, high capacity, low precision 1uF
CFDC Charge pump flying capacitor CFDCP, CFDCN >=6.3V, high capacity, low precision 1uF
CGDC Decoupling of digital core virtual ground voltage VGDC, DVDD >=6.3V, high capacity, low precision 1uF
on the VGDC pin. The voltage on the VGDC pin is
approximately 1.8V below DVDD, i.e. about 3.2V
Flying capacitors
The MA12070P power stage uses flying capacitors to generate a ½PVDD supply voltage to enable multi-level operation.
Each output switch node OUTXX has a corresponding flying capacitor, with a positive and a negative terminal, CFXXP
and CFXXN.
The two flying capacitor terminals are to be considered high power switching nodes carrying voltages and currents
similar to that on the OUTXX nodes. Care must be taken in the PCB design to reduce both the inductance and the
resistance of these nodes. Table 8-5 lists the flying capacitors, incl. connection, type and value.
Table 8-5 Flying capacitors
CF0A Half-bridge 0A flying capacitor CF0AP, CF0AN >=25V, high capacity, low precision 10uF
CF0B Half-bridge 0B flying capacitor CF0BP, CF0BN >=25V, high capacity, low precision 10uF
CF1A Half-bridge 1A flying capacitor CF1AP, CF1AN >=25V, high capacity, low precision 10uF
CF1B Half-bridge 1B flying capacitor CF1BP, CF1BN >=25V, high capacity, low precision 10uF
Care must be taken when choosing flying capacitors in applications where maximum output power is needed. The
effective capacitance of poor ceramic capacitors can be greatly reduced when a DC bias voltage is applied. A
recommended part is the GRM21BZ71E106KE15L capacitor from Murata. Other parts may also be used as long as the
effective capacitance is minimum 4.0 µF at 0.5*PVDD voltage.
Protection
The MA12070P integrates a range of protection features to protect the device and attached speakers from damage.
Protection features include:
• Current protection on OUTXX nodes during operation.
• On-chip temperature sensor for protection against device over-heating.
• Undervoltage supply monitors on AVDD, DVDD, VGDC and PVDD.
• DC protection, preventing DC to be present on the amplifier outputs.
Over-current protection on OUTXX nodes

During switching operation the output stage monitors the forward current flow in all output switches that are turned
on. This is done to limit the maximum power dissipated in the switches and prevent damage to the device and the
speaker load. The current in the output stage can exceed unwanted levels if:
• The speaker load impedance drops to a low value while the device is powered from a high PVDD supply.
• A failure occurs on the speaker terminals causing a low impedance short.
• The speaker is damaged and thereby exhibiting a low impedance.
Over-current protection and short-circuit protection use a latching mechanism. If an over current or a short-circuit
condition occurs, it will shut down the power stage and report the error on the /ERROR pin. By default the power stage
will restart and remove the latch – after 1-2 sec. If the over current is still present it will cycle through the described
process again until the over current is removed. Current limiting will not occur for currents below the OCPTHR level, see
Table 7-1.
Current protection against speaker terminal shorts requires an equivalent load inductance L Leq on each of the output
OUTXX pins (see Table 6-1). Load inductance from loudspeaker cables and, if used, ferrite beads (EMC filter) will typically
be sufficient.
Temperature protection
An on-chip temperature sensor effectively safeguards the device against a thermally induced failure due to overloading
and/or insufficient cooling.
A high junction temperature initially causes a temperature warning, TW. This can be detected by reading the error
register (address 124, bit 4) via I2C. If the temperature continues to rise the device will reach the temperature error (TE)
level and set the TE bit in the error register (address 124, bit 5). This will cause the device to stop all switching activity.
The device will restart after sufficient cooling down of the system. Both TW and TE will report the error on the /ERROR
pin.
Table 8-6 High-Temperature Warning and Error Signaling Levels
Symbol Parameter Test Conditions Typical Value Unit
TETHR,SET High-Temperature Error (TE) Set Threshold Temperature rising 150 °C
TETHR,CLR High-Temperature Error (TE) Clear Threshold Temperature falling 135 °C
TWTHR,SET High-Temperature Warning (TW) Set Threshold Temperature rising 125 °C
TWTHR,CLR High-Temperature Warning (TW) Clear Threshold Temperature falling 105 °C
Power supply monitors
The MA12070P features integrated PVDD, DVDD and AVDD under-voltage lockout.
Table 8-7 shows typical limits for the supply monitors.
Table 8-7 Under-voltage lockout levels
Parameter Test Conditions Typical Value Unit
UVPDVDD DVDD under-voltage error threshold DVDD Rising 4.2 V
DVDD Falling 4.0 V
UVPAVDD AVDD under-voltage error threshold AVDD Rising 4.2 V
AVDD Falling 4.0 V
UVPPVDD PVDD under-voltage error threshold PVDD Rising 4.3 V
PVDD Falling 4.1 V
DC protection
The MA12070P incorporates a circuit, detecting whether a DC is present on the amplifier output terminals driving the
loudspeaker. In case of an unexpected DC being present on any of the amplifier outputs, the power stage will be shut
down to protect the loudspeaker from harmful DC content. Furthermore, a failure is reported on the /ERROR pin and in
the error register readable by the device serial interface. The power stage can be restarted by resetting the device by
cycling the /ENABLE pin or toggle the eh_clear bit (bit 2, address 45) to clear the error register. DC protection is default
on. It can be disabled by clearing bit 2 of Eh_dcShdn (address 0x26).
For the DC protection circuit to trigger, the DC value of an output pin must be staying above 0.63*PVDD or below
0.37*PVDD for more than 700ms.
Digital serial audio input

The MA12070P provides a digital serial audio interface for providing up to four input PCM audio signals to the amplifier.
The digital serial audio input port on the MA12070P consist of the pins SCK (serial clock), WS (word select), SD0 (serial
data 0 – input channels 0L and 0R), and SD1 (serial data 1 – input channels 1L and 1R). All pins are inputs, i.e. the serial
input port is slave. The format of the digital serial audio inputs can be configured using the serial control interface. The
timing diagram for left justified mode (default) are illustrated in Figure 8-2 and I2S mode in Figure 8-3. In the following
the various settings for the digital serial audio input interface are described.
Table 8-8 Parameters for the digital serial audio input interface
Address(bits) Register name Description
0x35(2-0) i2s_format PCM word format:
000: i2s
001: left justified (default)
100: right justified 16bits
0x36(0) i2s_sck_pol Clocking edge of the serial clock signal (SCK):
0: Serial data (SDX) and word select (WS) are changing at rising edge of the serial
clock signal (SCK). The MA12070P will capture data at the falling edge of the
serial clock signal SCK.
1: Serial data (SDX) and word select (WS) are changing at falling edge of the
serial clock signal (SCK). The MA12070P will capture data at the rising edge of
the serial clock signal SCK. (default)
0x36(4-3) i2s_framesize Number of data bits per frame:
00: 64 serial clock (SCK) cycles are present in each period of the word select
signal (WS). (default)
signal (WS).
signal (WS).
11: reserved
0x36(1) i2s_ws_pol Temporal pairing of the two PCM data words in the serial data signals:
0: First word of a simultaneously sampled PCM data pair is transmitted while
word select (WS) is low. (default)
1: First word of a simultaneously sampled PCM data pair is transmitted while
word select (WS) is high.
0x36(2) i2s_order Bit order for PCM data words:
0: Most significant bit of the PCM data word is transmitted first. (default)
1: Least significant bit of the PCM data word is transmitted first.
0x36(5) i2s_rightfirst Left/right order of the two temporally paired PCM words:
0: Left PCM data word (of a simultaneously sampled PCM data pair) is send first.
(default)
1: Right PCM data word (of a simultaneously sampled PCM data pair) is send
first.
1/FS
WS
SCK
Left Channel 32 bits Right Channel 32 bits
SD0/SD1 N N-1 1 0 N N-1 1 0 N
MSB LSB MSB LSB
Figure 8-2 Timing diagram of left justified mode (default).
1/FS
WS
SCK
1Bit
Left Channel 32 bits Right Channel 32 bits
SD0/SD1 N N-1 1 0 N N-1 1 0
MSB LSB MSB LSB
Figure 8-3 Timing diagram of I2S mode with 2x32 bit.
Volume and limiter processor (VLP)
The MA12070P incorporates a volume and limiter processor (VLP). The VLP is a dedicated digital signal processor
capable of processing up to four audio channels. Customized signal processing is used to ensure preservation of the
audio quality in all stages of the VLP.
Figure 8-4 shows a functional block diagram of the VLP. The VLP is capable of applying a high precision volume control
on the incoming audio signals. After volume scaling, the signals can be passed through high precision limiters to protect
the loudspeakers from overload or to avoid undesired clipping occurring due to bad signal or gain scaling (volume
overdrive). The VLP can also be programmed to reduce the signal level in case of a temperature warning event to
prevent a system shutdown caused by overheating.
Figure 8-4. Functional block diagram of the volume and limiter processor (VLP)
Volume control
The volume controls in the VLP are organized as a master volume, which applies gain on all channels and four channel
volumes, applying gain on each of the individual channels. The resulting gain for a channel will consequently be a
product of the master volume and the channel gain. To avoid undesired audible artifacts when changing the volume
settings, smoothing is performed on the resulting gain before applying it to the audio signal.
The master volume and the channel volume settings can be controlled via the serial control interface. Each volume
setting is represented by 10 bits. The 10 bits are organized as an 8-bit number giving the integer part of the gain in dB
(the digits before the decimal point) - and a 2-bit number giving the fractional part of the gain in dB (the digits after the
decimal point). The granularity of volume settings is 0.25dB. The mapping from the serial control interface register to
the gain is shown in Table 8-9.
Table 8-9 VLP Mapping from register values to gain and level
Integer dB Fractional dB
VLP Gain/Level dB
register setting register setting
dec Hex dec hex
0 (0x00) 0 (0x0) 24.00
0 (0x00) 1 (0x1) 23.75
… … … … …
22 (0x16) 3 (0x3) 1.25
23 (0x17) 0 (0x0) 1.00
23 (0x17) 1 (0x1) 0.75
23 (0x17) 2 (0x2) 0.50
23 (0x17) 3 (0x3) 0.25
24 (0x18) 0 (0x0) 0.00
24 (0x18) 1 (0x1) -0.25
24 (0x18) 2 (0x2) -0.50
24 (0x18) 3 (0x3) -0.75
25 (0x19) 0 (0x0) -1.00
… … … … …
167 (0xA7) 3 (0x3) -143.75
168 (0xA8) 0 (0x0) -144.00
… … … … …
255 (0xFF) 2 (0x2) -144.00
255 (0xFF) 3 (0x3) -144.00
Limiter
The limiter block in the VLP is capable of ensuring that the audio output level from the MA12070P is kept below a
programmable threshold level, regardless of the volume gain settings and signal level. This way, the limiter can protect
the loudspeakers against harmful signal levels and prevent severe degradation of audio quality, due to clipping caused
by volume over-drive of the audio system.
The input to output level characteristic for the limiter is illustrated on Figure 8-5. At input audio levels below the
threshold, the gain through the limiter is unity and consequently the limiter passes the signal unaffected. This is seen as
a 1:1 slope on the input to output level characteristic plot. If the input signal level increases above the threshold level,
the limiter reduces the gain correspondingly in order to reduce the output signal level to the threshold level. This way
the output signal level will generally not exceed the threshold.
The slew-rate of the limiter is finite and the output signal can therefore occasionally exceed the set threshold. When
the limiter reduces the gain (caused by the input signal level exceeding the threshold) the speed of gain reduction is
limited by an attack-time constant. Similarly, when the limiter restores the gain to unity after being active the speed of
gain increase is limited by a release-time constant. The attack-time constant and the release-time constant can be
controlled in three steps (“slow”, ”normal” and “fast”) via the serial control interface. An example of the attack and
release behavior for the limiter is shown in Figure 8-6.
Limiter bypassed
Output level (dBFS)

Threshold
Limiter active
Input level (dBFS)
Figure 8-5 Input to Output level characteristic for the Limiter

Level (dBFS)
Threshold
Input level
Output level
Time
Gain (dB)
Unity gain
Limiter gain
Time
Attack Phase Release Phase
Figure 8-6 Example of limiter attack - and release behavior
VLP parameter interface

The parameters for the volume controls and limiters are accessible via the serial control interface. In Table 8-10 is shown
a list of parameters in the VLP.
Table 8-10 Parameters and status signals for the VLP accessible via the serial control interface.
Address
Register name Description
(bits)
0x35 (5-4) audio_proc_release Controls the limiter release time. 00: slow, 01: normal, 10: fast
0x35 (7-6) audio_proc_attack Controls the limiter attack time. 00: slow, 01: normal, 10: fast
0x35 (3) audio_proc_enable Controls the processing bypass mux
When high use the VLP
When low: bypass the VLP
0x36 (6) audio_proc_ limiterEnable Controls the Limiter bypass mux
When high: use the limiter
When low: bypass the limiter
0x36 (7) audio_proc_mute Controls the mute mux
When high: mute the audio
When low: play as normal
0x40 vol_db_master Controls the integer dB gain for the master volume1
0x41 (1-0) vol_lsb_master Controls the fractional dB gain for the master volume (quarter dB’s) 1
0x42 vol_db_ch0 Controls the integer dB gain for channel 0L1
0x43 vol_db_ch1 Controls the integer dB gain for channel 0R1
0x44 vol_db_ch2 Controls the integer dB gain for channel 1L1
0x45 vol_db_ch3 Controls the integer dB gain for channel 1R1
0x46 (1-0) vol_lsb_ch0 Controls the fractional dB gain for channel 0R (quarter dBs) 1
0x46 (3-2) vol_lsb_ch1 Controls the fractional dB gain for channel 0L (quarter dBs) 1
0x46 (5-4) vol_lsb_ch2 Controls the fractional dB gain for channel 1R (quarter dBs) 1
0x46 (7-6) vol_lsb_ch3 Controls the fractional dB gain for channel 1L (quarter dBs) 1
0x47 thr_db_ch0 Controls the integer dBFS limiter threshold level for channel 0L1
0x48 thr_db_ch1 Controls the integer dBFS limiter threshold level for channel 0R1
0x49 thr_db_ch2 Controls the integer dBFS limiter threshold level for channel 1L1
0x4A thr_db_ch3 Controls the integer dBFS limiter threshold level for channel 1R1
0x4B (1-0) thr_lsb_ch0 Controls the fractional dBFS limiter threshold level for channel 0L(quarter dBFS)1
0x4B (3-2) thr_lsb_ch1 Controls the fractional dBFS limiter threshold level for channel 0R(quarter dBFS)1
0x4B (5-4) thr_lsb_ch2 Controls the fractional dBFS limiter threshold level for channel 1L(quarter dBFS)1
0x4B (7-6) thr_lsb_ch3 Controls the fractional dBFS limiter threshold level for channel 1R(quarter dBFS)1
0x7E (7-4) audio_proc_limiter_mon Indicates if limiters are active
Bit 4 high: limiter is active on channel 0L
Bit 5 high: limiter is active on channel 0R
0x7E (3-0) audio_proc_clip_mon Indicates if clipping occurs on the VLP output signals
Bit 0 high: clipping present on channel 0L
Bit 1 high: clipping present on channel 0R
Bit 2 high: clipping present on channel 1L
Bit 3 high: clipping present on channel 1R
1 See Table 8-9 for mapping.
Clock system
The MA12070P incorporates a clock system consisting of an input clock divider, a PLL, a low-jitter low-TC oscillator
(2.8224 MHz), and control logic. At the CLK input pin the MA12070P requires a clock signal that is in phase-lock with the
incoming digital serial audio samples. This CLK input signal provides the reference for the internal PLL through the input
clock divider circuit. The CLK frequency is auto-detected by the MA12070P, and when a valid frequency is detected, the
corresponding input divider ratio is selected to internally generate the correct reference clock to the PLL. The PLL divider
ratio is also selected as a function of the CLK base frequency (2.8224 or 3.072 MHz).
The clock for the internal DAC’s is sourced from the PLL, or at some CLK rates, a divided version of the CLK input. Valid
combinations of audio sample rate (fs) and CLK frequency are listed in Table 8-11 together with maximum number of
supported VLP channels.
Table 8-11 Valid combinations of audio sample rate and CLK frequency
Also maximum number of supported VLP channels are shown
Audio sample rate (fs) CLK frequency No. VLP channels
44.1kHz 64 x fs = 2822.4kHz 4
128 x fs = 5644.8kHz 4
256 x fs = 11289.6kHz 4
512 x fs = 22579.2kHz 4
48kHz 64 x fs = 3072kHz 4
128 x fs = 6144kHz 4
256 x fs = 12288kHz 4
512 x fs = 24576kHz 4
88.2kHz 32 x fs = 2822.4kHz 2
64 x fs = 5644.8kHz 2
128 x fs = 11289.6kHz 2
256 x fs = 22579.2kHz 2
96kHz 32 x fs = 3072kHz 2
64 x fs = 6144kHz 2
128 x fs = 12288kHz 2
256 x fs = 24576kHz 2
176.4kHz 16 x fs = 2822.4kHz None

32 x fs = 5644.8kHz None
64 x fs = 11289.6kHz None
128 x fs = 22579.2kHz None
192kHz 16 x fs = 3072kHz None
32 x fs = 6144kHz None
MCU/Serial control interface

The I2C serial control interface of the MA12070P allows an I2C master to read and/or modify a wide range of device
parameters.
The I2C interface consists of four physical pins, SDA, SCL, AD0 and AD1. I2C decoder logic handles transaction protocol
and read/write access to the device register bank. SDA and SCL are standard bidirectional I2C slave pins for data and
clock, respectively. Both SDA and SCL must be pulled-up to a digital I/O (3.3V - 5V) with a 5k resistor on each pin and
operated in standard I2C mode up to 100 kbps transmission rate. Pins AD0 and AD1 are used to configure the 7-bit I2C
address of the device. The I2C address is decoded according to Table 8-12.
Table 8-12 I2C address decoding
I2C device address AD1 pin AD0 pin 7-bit I2C address
0x20 0 0 0b0100000
0x21 0 1 0b0100001
0x22 1 0 0b0100010
0x23 1 1 0b0100011
The I2C interface enables read/write operations to the device register bank. The register bank is organized as a 128
entry, byte wide memory, holding device configuration and status registers. The address space from 0 to 80 holds
read/write registers and the address space from 96 to 127 are read only. The complete address map and description of
each register is presented in “Register Map” section.. Figure 8-7 shows the block schematic of the I2C interface between:
I2C bus and MA12070P (serial interface controller and the register bank).
Digital I/O
DVDD
I2C bus MA12040
SDA Read/Write
SCL
AD0 Read only
AD1
Serial interface
Register bank
controller
Figure 8-7. I2C bus interface and register bank
I2C write operation

Each I2C transaction is initiated from a master by sending an I2C start condition followed by the 7-bit I2C device address
and cleared read/write bit. The device address and read/write bit is signaled on the SDA bus by pulling the bus to ground
indicating a ‘0’ or releasing the bus to indicate a ‘1’. The I2C SDA input is sampled by the device on the rising edge of the
SCL bus.
If the transmitted I2C address matches the configured address of the device, the device will acknowledge the request
by pulling the SDA bus to ground. The master samples the acknowledged bit from the device on the next rising edge of
SCL. The I2C initialization as described is shown in the waveform in Figure 8-8.
Figure 8-8. I2C init addressing sequence.

To complete the device register write operation, the master must continue transmitting the address and at least one
data byte. The device continues to acknowledge each byte received on the 9 th SCL rising edge. Each additional data
written to the device is written to the next address in the register bank.
The write transaction is terminated when the master sends a stop signal to the device. The stop signal consists of a rising
edge on SDA during SCL kept high. Figure 8-9 shows a single write operation.
Figure 8-9 I2C write operation.
I2C read operation

To read data from the device register bank, the read transaction is started by sending a write command to the I2C
address with the R/W bit cleared, followed by the device address to read from. See Figure 8-10.
Figure 8-10 I2C read transaction, register bank to be read from is written to the device.
The device will acknowledge the two bytes. Then data can be fetched from the device by sending a repeated start,
followed by an I2C read command consisting of a byte with the device I2C address and the R/W bit set.
The device will acknowledge the read request and start to drive the SDA bus with the bits from the requested register
bank address. See Figure 8-11.
Figure 8-11 I2C read transaction last part.
The read transaction continues until the master does not acknowledge the 9 th bit of the data read byte transaction and
sends a stop signal. The stop condition is defined as a rising edge of SDA while SCL is high. Timing requirements are
reflected in Table 8-13.
Table 8-13 I2C timing requirements

Parameter Min Typ Max Unit
Clock frequency1 0 100 400 kHz
SDA and SCL rise time 1 µs
SDA and SCL fall time 1 µs
SCL clock high 1 µs
SCL clock low 1 µs
Data, setup 300 ns
Data, hold 10 ns
Min stop to start condition 1 µs
NOTE1: Pull up resistance is equal to 2.2kΩ for 400kHz.
/CLIP pin and soft-clipping

The /CLIP pin changes from a HIGH state to LOW state when audio output is close to clipping. A system microcontroller
can at this instance decrease volume level or, if possible, increase power stage voltage in order to avoid clipping. The
associated modulation index for both channel 0 and channel 1 can be read out by reading address 98 and address 102
respectively. Note that /CLIP pin is an open-drain output which means that it should be pulled-up through a pull-up
resistor to the digital I/O DVDD of the system.
To minimize possible audible artifacts from sticky clipping or ringing around the clipping region, it is possible to enable
a soft-clipping scheme. This clipping scheme prevents the amplifier to sticky clip and minimizes ringing which
subsequently minimizes possible audible artifacts apart from normal clipping audibility. The soft-clipping scheme can
be enabled by setting bit 7 of address 10.
/ERROR pin and error handling

The /ERROR pin changes from a HIGH state to a LOW state when one of the associated error sources is triggered. A
system microcontroller can at this instance read out the error registers (address 45 and 109). According to the type of
error or warning the right measures can be taken. The errors will be shown in the error register (address 124) which
shows the live status of the error sources. Another register error_acc (address 109) will contain all the errors
accumulated over time. The error_acc register can be cleared by toggling the eh_clear bit (bit 2, address 45).
Table 8-14 shows the content of the error vector which is mapped to both the error register and the accumulated error
register. A more detailed explanation can be found in “Register Map” section.
Table 8-14 Error vector
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
dc_prot pps ote otw uvp pll ocp fcov
Note that the /ERROR pin has an open-drain output and should be pulled up to the interface I/O rail.
9 Application Information
Input/Output Configurations
The MA12070P is highly flexible regarding configuration of the four power amplifier channels. MA12070P can be set to
four different output configurations. By setting the configuration pins MSEL0 and MSEL1 according to Table 9-1, the
device is configured to one of the four different configurations. Each configuration is individually described in the
following sections.
Table 9-1 Signal configuration
MSEL0 pin MSEL1 pin Configuration
0 0 1 channel parallel bridge tied load (PBTL)
0 1 2 channels single ended load (SE) and 1 channel bridge tied load (BTL)
1 0 2 channels bridge tied load (BTL)
1 1 4 channels single ended load (SE)
Bridge Tied Load (BTL) Configuration

In BTL configuration, two input- and output terminals are used per channel as shown in Figure 9-1. This way two
power stage half-bridges are used to form one differential output configuration. This configuration will enable the full
potential of multi-level technology where the speaker load will experience up to 5 levels. This enables low near-idle
power consumption and beneficial noise properties.
Audio source
Data pair 0 OUT0A

SD0
(0L,0R)
SD1
OUT0B
Serial clock SCK
(master) (slave)
Word select WS
OUT1A
Master clock CLK
OUT1B
MSEL0
MSEL1
EMC filter
depending on
5V
application
Figure 9-1 Bridge tied load (BTL) configuration, with symmetrical audio sources.
Single Ended (SE) Configuration
In single ended (SE) configuration, the MA12070P is able to drive one loudspeaker per output power stage, i.e. up to
four loudspeakers. The output is biased to half the power supply voltage, ½ PVDD. One of the solutions to drive a speaker
in this configuration is to use AC-coupling capacitors (Cout) in series with the load, as shown in Figure 9-2. The value of
the capacitors depends on the load resistance and the desired audio bandwidth.
Table 9-2 shows examples of AC-coupling capacitor values. The DC voltage across the capacitors at the output is
approximately ½PVDD. However, significant AC-voltage swing might occur at low frequencies, which must be accounted
for in the voltage rating of the capacitors.
Audio source
+ Cout
Data pair 0 OUT0A
SD0
(0L,0R)
Data pair 1
SD1
(1L,1R) Cout
OUT0B +
Serial clock SCK

(master) (slave)
Word select WS + Cout
OUT1A
Master clock CLK
+ Cout
OUT1B
MSEL0
MSEL1
5V 5V EMC filter
depending on
application
Figure 9-2 Four channel, single ended (SE) configuration.

Table 9-2 Typical values for the output AC-coupling capacitor, Cout
Load Resistance Output AC-coupling -3dB frequency
capacitor, Cout
8Ω 220µF 90Hz
8Ω 1000µF 20Hz
4Ω 2200µF 24Hz
Combined SE and BTL Configuration
A combination of SE and BTL configuration can be used as shown in Figure 9-3. In this configuration two half-bridges are
combined to run in BTL configuration and the two remaining half-bridges are configured to run in SE configuration.
Audio source
Data pair 0 OUT0A

SD0
(0L,dummy)
Data pair 1
SD1
(1L,1R)
OUT0B
Serial clock SCK
(master) (slave)
Word select WS + Cout
OUT1A
Master clock CLK
+ Cout
OUT1B
MSEL0
MSEL1
5V EMC filter
depending on
application
Figure 9-3 Combined Bridge tied load (BTL) and single ended (SE) configuration, with SE audio sources
Parallel Bridge Tied Load (PBTL)

For providing additional power the MA12070P can be configured for mono operation using a parallel BTL mode (PBTL),
as shown in Figure 9-4. In this fashion the two BTL output stages are combined to be able to deliver twice the current.
This makes high output power sub-woofer application possible.
Audio source
Data pair 0 OUT0A

SD0
(0L,dummy)
0L
SD1
OUT0B
Serial clock SCK
(master) (slave) EMC filter
Word select WS depending on
OUT1A application
Master clock CLK
OUT1B
MSEL1
MSEL0
Figure 9-4 Parallel Bridge Tied Load (PBTL) configuration
EMC output filter Considerations
The proprietary 5-level modulation significantly reduces EMC emissions, and the amplifiers can pass the Radiated
Emission test with speaker cables lengths up to 80 cm with just a small ferrite filter. For cables longer than 80 cm it is
recommended to use a LC-filter.
For more information regarding filter type, components and measurements, see the document “Applications note –
EMC Output Filter Recommendations” at the Infineon homepage.
Audio Performance Measurements

In a typical audio application the outputs of the MA12070P will be connected directly to the speaker loads. However,
for audio performance evaluation it can be beneficial to configure the circuit board with an LC filter. This is due to the
fact that many audio analyzers do not handle PWM signals at their inputs well.
When using an audio analyzer configured with an external and/or internal measurement filter the use of an LC filter is
not necessary. However, be sure to verify the audio analyzer’s input limits before connecting it to a filterless amplifier
output.
When using an LC filter, the design depends on the specific load. L and C values should therefore be optimized for this.
Thermal Characteristics and Test Signals

Performing audio measurements by use of an audio analyzer is typically very helpful during the evaluation of an
amplifier. However, using an audio analyzer can be misleading when evaluating thermal performance.
Audio analyzers typically generate full tone, continuous sine wave signals as the input signal for the amplifier. While this
is required to perform many audio measurements, it is also the worst-case thermal scenario for the device. Using full-
scale continuous sine waves for thermal evaluation or testing will lead to an overly conservative and more costly thermal
design which will be unnecessary in almost all real audio applications.
Actual audio content, such as music, has much lower RMS values compared to its maximum peak output power than a
full-scale continuous sine wave. This results in significantly less heat dissipation from the device when amplifying actual
audio. For thermal evaluation it is therefore recommended to use actual music signals during tests. Alternatively, a pink
noise signal can be used to emulate a music signal.
It is not uncommon for an amplifier solution to have limited thermal performance, potentially resulting in thermal
protection shutdown, when amplifying full-scale continuous sine wave signals.
Start-up procedure
It is recommended to follow the start-up procedure as described below:
1) Make sure the all hardware pins are configured correctly: e.g. BTL, Slave Clock mode.
2) Keep the device in disable and mute: /ENABLE = 1; /MUTE = 0.
3) Bring up 5V VDD supply and PVDD supply (it does not matter if VDD or PVDD comes up first, provided that
the device is held in disable).
4) Wait for VDD and PVDD to be stable.
5) CLK must be present before enabling the amplifier.
6) Enable device: /ENABLE = 0.
7) Program applicable initialization to registers.
8) Unmute device: /MUTE = 1.
9) The device is now in normal operation state.
Shut-down / power-down procedure
It is recommended to follow the start-up procedure as described below:
1) The device is in normal operation state.
2) Mute device: /MUTE = 0.
3) Disable device: /ENABLE = 1.
4) The device is now power-down state.
5) Bring down 5V VDD supply and PVDD supply.
6) The device is now in shut-down state.
Recommended PCB Design for MA12070P (EPAD-down package)

The QFN package with exposed thermal pad at the bottom side is thermally sufficient for most applications. However,
in order to remove heat from the package care should be taken in designing the PCB.
The PCB footprint for the device should include a thermal relief pad underneath the device with a size of 6 x 6 mm. This
thermal relief pad must be centered so the device can be soldered easily. It is recommended to use a PCB design with
two or more layers of copper for good thermal performance. Using multiple layers enables a design with a large area of
copper connected to the EPAD.
To achieve best thermal performance it is also important to design the surrounding connections in such a way that
avoids cutting up the copper area into many sections.
Figure 9-5 shows a PCB design using 26 via connections directly underneath the chip between the top and bottom layers.
These should be placed on a grid each with a 0.65 mm plated through hole. These connections ensure good thermal
transfer from the top side EPAD to a large section of ground connected copper area on the bottom side of the PCB.
Figure 9-5 Example of 2-layer PCB layout, top and bottom layers
It is recommended to use a PCB made from glass/epoxy laminate (e.g. FR-4) material. This type of material works well
with PCB designs that require thermal relief as it can endure high temperatures for a long duration of time.
PCB copper thickness is recommended to be a minimum of 35μ (1 oz) and the PCB must be made to the IPC 6012C, Class
2 standard.
10 Typical Characteristics (PVDD = +26V, Load = 4Ω + 22µH)
BTL configuration; Load = 4Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses
AES17 brick-wall filter (20kHz).
100 100
PVDD = +26V PVDD = +26V
Load = 4Ω + 22µH Load = 4Ω + 22µH
10 10
1 1
THD+N (%)
THD+N (%)
0,1 0,1
0,01 0,01
100Hz 100Hz
1kHz 1kHz
6kHz 6kHz
0,001 0,001
0,001 0,01 0,1 1 10 100 0,001 0,01 0,1 1 10 100
Output Power (W) Output Power (W)
Figure 10-1 THD+N vs Output Power for PMP0 Figure 10-2 THD+N vs Output Power for PMP1
100 100
10 10
1
THD+N (%)
1
THD+N (%)
0,1 0,1
0,01 0,01
100Hz 100Hz
1kHz 1kHz
6kHz 6kHz
0,001 0,001
0,001 0,01 0,1 1 10 100 0,001 0,01 0,1 1 10 100
100 100
1W PVDD = +26V 1W
PVDD = +26V
Load = 4Ω + 22µH 5W Load = 4Ω + 22µH 5W
10W 10W
10 10
THD+N (%)
1 1
THD+N (%)
0,1 0,1
0,01 0,01
0,001 0,001
20 200 2000 20000 20 200 2000 20000
Frequency (Hz) Frequency (Hz)
Figure 10-5 THD+N vs Frequency for PMP0 Figure 10-6 THD+N vs Frequency for PMP1
100 100
PVDD = +26V 1W PVDD = +26V 1W
10W 10W
10 10
1 1
THD+N (%)
THD+N (%)
0,1 0,1
0,01 0,01
0,001 0,001
20 200 2000 20000 20 200 2000 20000
100 100
90 90
80 80
70 70
Efficiency (%)
Efficiency (%)
60 60
50 50
40 40
30 30
20 20
10 PVDD = +26V Output Power 10 PVDD = +26V Output Power
Load = 4Ω + 22µH Per Channel Load = 4Ω + 22µH Per Channel
0 0
0 10 20 30 40 50 60 70 80 90 0 10 20 30 40 50 60 70 80 90
Figure 10-9 PMP0 Efficiency (VDD+PVDD) vs Output Power Figure 10-10 PMP1 Efficiency (VDD+PVDD) vs Output Power
100 100
90 90
80 80
70 70
Efficiency (%)
Efficiency (%)
60 60
50 50
40 40
30 30
20 20

0 0
0 10 20 30 40 50 60 70 80 90 0 10 20 30 40 50 60 70 80 90
100 100
10 10
Input Power (W)

Input Power (W)
1 1
Output Power Output Power

Per Channel Per Channel
0,1 0,1
0,0001 0,001 0,01 0,1 1 10 100 0,0001 0,001 0,01 0,1 1 10 100
Figure 10-13 Input Power vs Output Power for PMP0 Figure 10-14 Input Power vs Output Power for PMP1
100 100
10 10
Input Power (W)
Input Power (W)
1 1

0,1 0,1
0,0001 0,001 0,01 0,1 1 10 100 0,0001 0,001 0,01 0,1 1 10 100
10 10
1 1
PVDD Current (A)
PVDD Current (A)

0,1 0,1
0,01 0,01
PMP0 PMP2
PMP1 PMP4
0,001 0,001
0,0001 0,001 0,01 0,1 1 10 100 1000 0,0001 0,001 0,01 0,1 1 10 100 1000
Figure 10-17 PVDD Current vs Output Power for PMP0 & PMP1 Figure 10-18 PVDD Current vs Output Power for PMP2 & PMP4
10 10
9 9
8 8
PVDD Idle Current (mA)
7 7
6 6
5 5
4 4
3 3
2 2
1 PMP0 1 PMP2
PMP1 PMP4
0 0
4 6 8 10 12 14 16 18 20 22 24 26 4 6 8 10 12 14 16 18 20 22 24 26
PVDD (V) PVDD (V)
Figure 10-19 PVDD Idle Current vs PVDD for PMP0 & PMP1 Figure 10-20 PVDD Idle Current vs PVDD for PMP2 & PMP4
90 90
80 80
70 70
60
Output Power (W)
60
Output Power (W)

50 50
40 40
30 30
20 20
10 1% THD+N 10 1% THD+N
10% THD+N 10% THD+N
0 0
4 6 8 10 12 14 16 18 20 22 24 26 4 6 8 10 12 14 16 18 20 22 24 26
PVDD (V) PVDD (V)
Figure 10-21 Output Power vs PVDD for PMP0 Figure 10-22 Output Power vs PVDD for PMP1
90 90
80 80
70 70
60 60
Output Power (W)
Output Power (W)
50 50
40 40
30 30
20 20
10 1% THD+N 10 1% THD+N
10% THD+N 10% THD+N
0 0
4 6 8 10 12 14 16 18 20 22 24 26 4 6 8 10 12 14 16 18 20 22 24 26
PVDD (V) PVDD (V)
27 27
1W PVDD = +26V 1W
PVDD = +26V
26,8 Load = 4Ω + 22µH 5W 26,8 Load = 4Ω + 22µH 5W
10W 10W
26,6 26,6
26,4 26,4
26,2 26,2
Gain (dB)
Gain (dB)
26 26
25,8 25,8
25,6 25,6
25,4 25,4
25,2 25,2
25 25
20 200 2000 20000 20 200 2000 20000
Figure 10-25 Gain vs Frequency for PMP0 Figure 10-26 Gain vs Frequency for PMP1
27 27
1W PVDD = +26V 1W
PVDD = +26V
10W 10W
26,6 26,6
26,4 26,4
26,2 26,2
Gain (dB)
Gain (dB)
26 26
25,8 25,8
25,6 25,6
25,4 25,4
25,2 25,2
25 25
20 200 2000 20000 20 200 2000 20000
0 0
PVDD = +26V Ch0 to Ch1 PVDD = +26V Ch0 to Ch1
-10 -10
Load = 4Ω + 22µH Ch1 to Ch0 Load = 4Ω + 22µH Ch1 to Ch0
-20 -20
-30 -30
-40 -40
-50 -50
Crosstalk (dB)
Crosstalk (dB)
-60 -60
-70 -70
-80 -80
-90 -90
-100 -100
-110 -110
-120 -120
-130 -130
-140 -140
20 200 2.000 20.000 20 200 2.000 20.000
Figure 10-29 Crosstalk vs Frequency for PMP0 Figure 10-30 Crosstalk vs Frequency for PMP1
0 0
Ch0 to Ch1 PVDD = +26V Ch0 to Ch1
-10 PVDD = +26V -10
-20 -20
-30 -30
-40 -40
-50 -50
Crosstalk (dB)
Crosstalk (dB)
-60 -60
-70 -70
-80 -80
-90 -90
-100 -100
-110 -110
-120 -120
-130 -130
-140 -140
20 200 2.000 20.000 20 200 2.000 20.000
100 100
10 10
1 1
THD+N (%)
THD+N (%)
0,1 0,1
0,01 0,01
100Hz 100Hz
1kHz 1kHz
6kHz 6kHz
0,001 0,001
0,001 0,01 0,1 1 10 100 0,001 0,01 0,1 1 10 100
100 100
10 10
1 1
THD+N (%)
THD+N (%)
0,1 0,1
0,01 0,01
100Hz 100Hz
1kHz 1kHz
6kHz 6kHz
0,001 0,001
0,001 0,01 0,1 1 10 100 0,001 0,01 0,1 1 10 100
100 100
1W 1W
10W 10W
10 10
1 1
THD+N (%)
THD+N (%)
0,1 0,1
0,01 0,01
0,001 0,001
20 200 2000 20000 20 200 2000 20000
100 100
10W 10W
10 10
1 1
THD+N (%)
THD+N (%)
0,1 0,1
0,01 0,01
0,001 0,001
20 200 2000 20000 20 200 2000 20000
100 100
90 90
80 80
70 70
Efficiency (%)
Efficiency (%)
60 60
50 50
40 40
30 30
20 20

0 0
0 10 20 30 40 50 60 0 10 20 30 40 50 60
100 100
90 90
80 80
70 70
Efficiency (%)
Efficiency (%)
60 60
50 50
40 40
30 30
20 20

0 0
0 10 20 30 40 50 60 0 10 20 30 40 50 60
100 100
10 10
Input Power (W)
Input Power (W)

1 1

0,1 0,1
0,0001 0,001 0,01 0,1 1 10 100 0,0001 0,001 0,01 0,1 1 10 100
100 100
10 10
Input Power (W)
Input Power (W)
1 1

0,1 0,1
0,0001 0,001 0,01 0,1 1 10 100 0,0001 0,001 0,01 0,1 1 10 100
10 10
1 1
PVDD Current (A)
PVDD Current (A)

0,1 0,1
0,01 0,01
PMP0 PMP2
PMP1 PMP4
0,001 0,001
0,0001 0,001 0,01 0,1 1 10 100 1000 0,0001 0,001 0,01 0,1 1 10 100 1000
Figure 11-17 PVDD Current vs Output Power for PMP0 & PMP1 Figure 11-18 PVDD Current vs Output Power for PMP2 & PMP4
10 10
9 9
8 8
7 7
6 6
5 5
4 4
3 3
2 2
1 PMP0 1 PMP2
PMP1 PMP4
0 0
4 6 8 10 12 14 16 18 20 22 24 26 4 6 8 10 12 14 16 18 20 22 24 26
PVDD (V) PVDD (V)
Figure 11-19 PVDD Idle Current vs PVDD for PMP0 & PMP1 Figure 11-20 PVDD Idle Current vs PVDD for PMP2 & PMP4
50 50
45 45
40 40
35 35
Output Power (W)

Output Power (W)
30 30
25 25
20 20
15 15
10 10
5 1% THD+N 5 1% THD+N
10% THD+N 10% THD+N
0 0
4 6 8 10 12 14 16 18 20 22 24 26 4 6 8 10 12 14 16 18 20 22 24 26
PVDD (V) PVDD (V)
50 50
45 45
40 40
35 35
Output Power (W)
Output Power (W)
30 30
25 25
20 20
15 15
10 10
5 1% THD+N 5 1% THD+N
10% THD+N 10% THD+N
0 0
4 6 8 10 12 14 16 18 20 22 24 26 4 6 8 10 12 14 16 18 20 22 24 26
PVDD (V) PVDD (V)
27 27
10W 10W
26,6 26,6
26,4 26,4
26,2 26,2
Gain (dB)
Gain (dB)
26 26
25,8 25,8
25,6 25,6
25,4 25,4
25,2 25,2
25 25
20 200 2000 20000 20 200 2000 20000
27 27
1W PVDD = +26V 1W
PVDD = +26V
10W 10W
26,6 26,6
26,4 26,4
26,2 26,2
Gain (dB)
Gain (dB)
26 26
25,8 25,8
25,6 25,6
25,4 25,4
25,2 25,2
25 25
20 200 2000 20000 20 200 2000 20000
0 0
-10 -10
-20 -20
-30 -30
-40 -40
-50 -50
Crosstalk (dB)
Crosstalk (dB)
-60 -60
-70 -70
-80 -80
-90 -90
-100 -100
-110 -110
-120 -120
-130 -130
-140 -140
20 200 2.000 20.000 20 200 2.000 20.000
0 0
Ch0 to Ch1 Ch0 to Ch1
-10 PVDD = +26V -10 PVDD = +26V
-20 -20
-30 -30
-40 -40
-50 -50
Crosstalk (dB)
Crosstalk (dB)
-60 -60
-70 -70
-80 -80
-90 -90
-100 -100
-110 -110
-120 -120
-130 -130
-140 -140
20 200 2.000 20.000 20 200 2.000 20.000
100 100
10 10
1 1
THD+N (%)
THD+N (%)
0,1 0,1
0,01 0,01
100Hz 100Hz
1kHz 1kHz
6kHz 6kHz
0,001 0,001
0,001 0,01 0,1 1 10 100 0,001 0,01 0,1 1 10 100
100 100
10 10
1 1
THD+N (%)
THD+N (%)
0,1 0,1
0,01 0,01
100Hz 100Hz
1kHz 1kHz
6kHz 6kHz
0,001 0,001
0,001 0,01 0,1 1 10 100 0,001 0,01 0,1 1 10 100
100 100
1W PVDD = +24V 1W
PVDD = +24V
10W 10W
10 10
1 1
THD+N (%)
THD+N (%)
0,1 0,1
0,01 0,01
0,001 0,001
20 200 2000 20000 20 200 2000 20000
100 100
10W 10W
10 10
1 1
THD+N (%)
THD+N (%)
0,1 0,1
0,01 0,01
0,001 0,001
20 200 2000 20000 20 200 2000 20000
100 100
90 90
80 80
70 70
Efficiency (%)
60 60
Efficiency (%)
50 50
40 40
30 30
20 20
0 0
0 10 20 30 40 50 60 70 80 90 0 10 20 30 40 50 60 70 80 90
100 100
90 90
80 80
70 70
60 60
Efficiency (%)
Efficiency (%)
50 50
40 40
30 30
20 20

0 0
0 10 20 30 40 50 60 70 80 90 0 10 20 30 40 50 60 70 80 90
100 100
10 10
Input Power (W)

Input Power (W)
1 1

0,1 0,1
0,0001 0,001 0,01 0,1 1 10 100 0,0001 0,001 0,01 0,1 1 10 100
100 100
10 10
Input Power (W)
Input Power (W)
1 1

0,1 0,1
0,0001 0,001 0,01 0,1 1 10 100 0,0001 0,001 0,01 0,1 1 10 100
10 10
1 1
PVDD Current (A)
PVDD Current (A)

0,1 0,1
0,01 0,01
PMP0 PMP1
0,001 0,001
0,0001 0,001 0,01 0,1 1 10 100 1000 0,0001 0,001 0,01 0,1 1 10 100 1000
Figure 12-17 PVDD Current vs Output Power for PMP0 Figure 12-18 PVDD Current vs Output Power for PMP1
10 10
1 1
PVDD Current (A)
PVDD Current (A)
0,1 0,1
0,01 0,01
PMP2 PMP4
0,001 0,001
0,0001 0,001 0,01 0,1 1 10 100 1000 0,0001 0,001 0,01 0,1 1 10 100 1000
27 27
1W PVDD = +24V 1W
PVDD = +24V
10W 10W
26,6 26,6
26,4 26,4
26,2 26,2
Gain (dB)
Gain (dB)
26 26
25,8 25,8
25,6 25,6
25,4 25,4
25,2 25,2
25 25
20 200 2000 20000 20 200 2000 20000
27 27
PVDD = +24V 1W 1W
PVDD = +24V
10W 10W
26,6 26,6
26,4 26,4
26,2 26,2
Gain (dB)
Gain (dB)
26 26
25,8 25,8
25,6 25,6
25,4 25,4
25,2 25,2
25 25
20 200 2000 20000 20 200 2000 20000
0 0
-10 -10
-20 -20
-30 -30
-40 -40
-50 -50
Crosstalk (dB)
Crosstalk (dB)
-60 -60
-70 -70
-80 -80
-90 -90
-100 -100
-110 -110
-120 -120
-130 -130
-140 -140
20 200 2.000 20.000 20 200 2.000 20.000
0 0
-10 -10
-20 -20
-30 -30
-40 -40
-50 -50
Crosstalk (dB)
Crosstalk (dB)
-60 -60
-70 -70
-80 -80
-90 -90
-100 -100
-110 -110
-120 -120
-130 -130
-140 -140
20 200 2.000 20.000 20 200 2.000 20.000
100 100
10 10
THD+N (%)
1
THD+N (%)
0,1 0,1
0,01 0,01
100Hz 100Hz
1kHz 1kHz
6kHz 6kHz
0,001 0,001
0,001 0,01 0,1 1 10 100 0,001 0,01 0,1 1 10 100
100 100
10 10
1
THD+N (%)
1
THD+N (%)
0,1 0,1
0,01 0,01
100Hz 100Hz
1kHz 1kHz
6kHz 6kHz
0,001 0,001
0,001 0,01 0,1 1 10 100 0,001 0,01 0,1 1 10 100
100 100
1W PVDD = +24V 1W
PVDD = +24V
10W 10W
10 10
1 1
THD+N (%)
THD+N (%)
0,1 0,1
0,01 0,01
0,001 0,001
20 200 2000 20000 20 200 2000 20000
100 100
PVDD = +24V 1W 1W
PVDD = +24V
10W 10W
10 10
1 1
THD+N (%)
THD+N (%)
0,1 0,1
0,01 0,01
0,001 0,001
20 200 2000 20000 20 200 2000 20000
100 100
90 90
80 80
70 70
Efficiency (%)
60 60
Efficiency (%)
50 50
40 40
30 30
20 20

0 0
0 10 20 30 40 50 0 10 20 30 40 50
100 100
90 90
80 80
70 70
60 60
Efficiency (%)
Efficiency (%)
50 50
40 40
30 30
20 20

0 0
0 10 20 30 40 50 0 10 20 30 40 50
100 100
10 10
Input Power (W)
Input Power (W)

1 1

0,1 0,1
0,0001 0,001 0,01 0,1 1 10 100 0,0001 0,001 0,01 0,1 1 10 100
100 100
10 10
Input Power (W)
Input Power (W)
1 1

0,1 0,1
0,0001 0,001 0,01 0,1 1 10 100 0,0001 0,001 0,01 0,1 1 10 100
10 10
1 1
PVDD Current (A)
PVDD Current (A)

0,1 0,1
0,01 0,01
PMP0 PMP1
0,001 0,001
0,0001 0,001 0,01 0,1 1 10 100 0,0001 0,001 0,01 0,1 1 10 100
10 10
1 1
PVDD Current (A)
PVDD Current (A)
0,1 0,1
0,01 0,01
PMP2 PMP4
0,001 0,001
0,0001 0,001 0,01 0,1 1 10 100 0,0001 0,001 0,01 0,1 1 10 100
27 27
1W PVDD = +24V 1W
PVDD = +24V
10W 10W
26,6 26,6
26,4 26,4
26,2 26,2
Gain (dB)
Gain (dB)
26 26
25,8 25,8
25,6 25,6
25,4 25,4
25,2 25,2
25 25
20 200 2000 20000 20 200 2000 20000
27 27
10W 10W
26,6 26,6
26,4 26,4
26,2 26,2
Gain (dB)
Gain (dB)
26 26
25,8 25,8
25,6 25,6
25,4 25,4
25,2 25,2
25 25
20 200 2000 20000 20 200 2000 20000
0 0
-10 -10
-20 -20
-30 -30
-40 -40
-50 -50
Crosstalk (dB)
Crosstalk (dB)
-60 -60
-70 -70
-80 -80
-90 -90
-100 -100
-110 -110
-120 -120
-130 -130
-140 -140
20 200 2.000 20.000 20 200 2.000 20.000
0 0
PVDD = +24V Ch0 to Ch1 Ch0 to Ch1
-10 -10 PVDD = +24V
-20 -20
-30 -30
-40 -40
-50 -50
Crosstalk (dB)
Crosstalk (dB)
-60 -60
-70 -70
-80 -80
-90 -90
-100 -100
-110 -110
-120 -120
-130 -130
-140 -140
20 200 2.000 20.000 20 200 2.000 20.000
100 100
10 10
THD+N (%)
1 1
THD+N (%)
0,1 0,1
0,01 0,01
100Hz 100Hz
1kHz 1kHz
6kHz 6kHz
0,001 0,001
0,001 0,01 0,1 1 10 100 0,001 0,01 0,1 1 10 100
100 100
10 10
1 1
THD+N (%)
THD+N (%)
0,1 0,1
0,01 0,01
100Hz 100Hz
1kHz 1kHz
6kHz 6kHz
0,001 0,001
0,001 0,01 0,1 1 10 100 0,001 0,01 0,1 1 10 100
100 100
10W 10W
10 10
1 1
THD+N (%)
THD+N (%)
0,1 0,1
0,01 0,01
0,001 0,001
20 200 2000 20000 20 200 2000 20000
100 100
1W PVDD = +21V 1W
PVDD = +21V
10W 10W
10 10
1 1
THD+N (%)
THD+N (%)
0,1 0,1
0,01 0,01
0,001 0,001
20 200 2000 20000 20 200 2000 20000
100 100
90 90
80 80
70 70
Efficiency (%)
Efficiency (%)
60 60
50 50
40 40
30 30
20 20

0 0
0 10 20 30 40 50 60 70 0 10 20 30 40 50 60 70
100 100
90 90
80 80
70 70
Efficiency (%)
Efficiency (%)
60 60
50 50
40 40
30 30
20 20

0 0
0 10 20 30 40 50 60 70 0 10 20 30 40 50 60 70
100 100
10 10
Input Power (W)
Input Power (W)

1 1

0,1 0,1
0,0001 0,001 0,01 0,1 1 10 100 0,0001 0,001 0,01 0,1 1 10 100
100 100
10 10
Input Power (W)
Input Power (W)
1 1

0,1 0,1
0,0001 0,001 0,01 0,1 1 10 100 0,0001 0,001 0,01 0,1 1 10 100
10 10
1 1
PVDD Current (A)
PVDD Current (A)

0,1 0,1
0,01 0,01
PMP0 PMP1
0,001 0,001
0,0001 0,001 0,01 0,1 1 10 100 1000 0,0001 0,001 0,01 0,1 1 10 100 1000
10 10
1 1
PVDD Current (A)
PVDD Current (A)
0,1 0,1
0,01 0,01
PMP2 PMP4
0,001 0,001
0,0001 0,001 0,01 0,1 1 10 100 1000 0,0001 0,001 0,01 0,1 1 10 100 1000
27 27
10W 10W
26,6 26,6
26,4 26,4
26,2 26,2
Gain (dB)
Gain (dB)
26 26
25,8 25,8
25,6 25,6
25,4 25,4
25,2 25,2
25 25
20 200 2000 20000 20 200 2000 20000
27 27
PVDD = +21V 1W 1W
PVDD = +21V
10W 10W
26,6 26,6
26,4 26,4
26,2 26,2
Gain (dB)
Gain (dB)
26 26
25,8 25,8
25,6 25,6
25,4 25,4
25,2 25,2
25 25
20 200 2000 20000 20 200 2000 20000
0 0
PVDD = +21V Ch0 to Ch1 Ch0 to Ch1
-10 -10 PVDD = +21V
-20 -20
-30 -30
-40 -40
-50 -50
Crosstalk (dB)
Crosstalk (dB)
-60 -60
-70 -70
-80 -80
-90 -90
-100 -100
-110 -110
-120 -120
-130 -130
-140 -140
20 200 2.000 20.000 20 200 2.000 20.000
0 0
-10 -10
-20 -20
-30 -30
-40 -40
-50 -50
Crosstalk (dB)
Crosstalk (dB)
-60 -60
-70 -70
-80 -80
-90 -90
-100 -100
-110 -110
-120 -120
-130 -130
-140 -140
20 200 2.000 20.000 20 200 2.000 20.000
100 100
10 10
1 1
THD+N (%)
THD+N (%)
0,1 0,1
0,01 0,01
100Hz 100Hz
1kHz 1kHz
6kHz 6kHz
0,001 0,001
0,001 0,01 0,1 1 10 100 0,001 0,01 0,1 1 10 100
100 100
10 10
1 1
THD+N (%)
THD+N (%)
0,1 0,1
0,01 0,01
100Hz 100Hz
1kHz 1kHz
6kHz 6kHz
0,001 0,001
0,001 0,01 0,1 1 10 100 0,001 0,01 0,1 1 10 100
100 100
1W PVDD = +21V 1W
PVDD = +21V
10W 10W
10 10
1 1
THD+N (%)
THD+N (%)
0,1 0,1
0,01 0,01
0,001 0,001
20 200 2000 20000 20 200 2000 20000
100 100
1W PVDD = +21V 1W
PVDD = +21V
10W 10W
10 10
1 1
THD+N (%)
THD+N (%)
0,1 0,1
0,01 0,01
0,001 0,001
20 200 2000 20000 20 200 2000 20000
100 100
90 90
80 80
70 70
Efficiency (%)
Efficiency (%)
60 60
50 50
40 40
30 30
20 20

0 0
0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40
100 100
90 90
80 80
70 70
Efficiency (%)
Efficiency (%)
60 60
50 50
40 40
30 30
20 20

0 0
0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40
100 100
Input Power (W)
10 10
Input Power (W)

1 1

0,1 0,1
0,0001 0,001 0,01 0,1 1 10 100 0,0001 0,001 0,01 0,1 1 10 100
100 100
10 10
Input Power (W)
Input Power (W)
1 1

0,1 0,1
0,0001 0,001 0,01 0,1 1 10 100 0,0001 0,001 0,01 0,1 1 10 100
10 10
1 1
PVDD Current (A)
PVDD Current (A)

0,1 0,1
0,01 0,01
PMP0 PMP1
0,001 0,001
0,0001 0,001 0,01 0,1 1 10 100 0,0001 0,001 0,01 0,1 1 10 100
10 10
1 1
PVDD Current (A)
PVDD Current (A)
0,1 0,1
0,01 0,01
PMP2 PMP4
0,001 0,001
0,0001 0,001 0,01 0,1 1 10 100 0,0001 0,001 0,01 0,1 1 10 100
27 27
1W PVDD = +21V 1W
PVDD = +21V
10W 10W
26,6 26,6
26,4 26,4
26,2 26,2
Gain (dB)
Gain (dB)
26 26
25,8 25,8
25,6 25,6
25,4 25,4
25,2 25,2
25 25
20 200 2000 20000 20 200 2000 20000
27 27
10W 10W
26,6 26,6
26,4 26,4
26,2 26,2
Gain (dB)
Gain (dB)
26 26
25,8 25,8
25,6 25,6
25,4 25,4
25,2 25,2
25 25
20 200 2000 20000 20 200 2000 20000
0 0
-10 -10
-20 -20
-30 -30
-40 -40
-50 -50
Crosstalk (dB)
Crosstalk (dB)
-60 -60
-70 -70
-80 -80
-90 -90
-100 -100
-110 -110
-120 -120
-130 -130
-140 -140
20 200 2.000 20.000 20 200 2.000 20.000
0 0
-10 -10
-20 -20
-30 -30
-40 -40
-50 -50
Crosstalk (dB)
Crosstalk (dB)
-60 -60
-70 -70
-80 -80
-90 -90
-100 -100
-110 -110
-120 -120
-130 -130
-140 -140
20 200 2.000 20.000 20 200 2.000 20.000
16 Register map
For all register map:
“ f “ : Don’t Care condition
“ – “ : Reserved bits configured during factory settings.
Read / Write Access (Power Mode Settings):

Default
Address Address Description Name Bit(s) Value Function
Value
Select manual Power Mode control. Default
the device will operate in automatic Power
manualPM 6 -011----
Mode control. This bit can be set to 1 if manual
Power Mode control is required.
Manual selected power mode. These two bits
Power Mode can be used selecting the Power Mode of the
0x00 0x3D -011----
Control device when it is in manual Power Mode
control.
PM_man 5:4 --00---- Reserved
--01---- Power Mode 1
Threshold value for PM1=>PM2 change. This
Threshold for
value will set the threshold for when automatic
Power Mode
0x01 0x3C Mthr_1to2 7:0 00111100 Power Mode changes from PM1 to PM2. It can
change
be programmed from 0 - 255; this maps to 0
PM1=>PM2
output power – max output power.
Threshold for
Power Mode
0x02 0x32 Mthr_2to1 7:0 00110010 Power Mode changes from PM2 to PM1. It can
change
PM2=>PM1
Threshold for
Power Mode
0x03 0x5A Mthr_2to3 7:0 01011010 Power Mode changes from PM2 to PM3. It can
change
PM2=>PM3
Threshold for
Power Mode
0x04 0x50 Mthr_3to2 7:0 01010000 Power Mode changes from PM3 to PM2. It can
change
PM3=>PM2
0x07 0x00 Disable DCU1 dcu1_disable 7 1------- Disables CH0 of the amplifier
0x07 0x00 Disable DCU0 dcu0_disable 6 -1----- Disables CH1 of the amplifier
Soft-clipping Enables soft-clipping. High to enable. Low to

lf_clamp_en 7 0-----0-
and over- disable.
0x0A 0xC current
protection
latching ocp_latch_en 1 0-----0- High to use permanently latching OCP.
Read / Write Access (Power Mode Profile Settings):
Default
Value
Power Mode Profile select. With this register
fffff000 the user can selects the appropriate Power
Mode Profile.
Select Power -----000 Power Mode Profile 0
0x1D 0x00 Mode Profile PMprofile 2:0 -----001 Power Mode Profile 1
setting -----010 Power Mode Profile 2
-----011 Power Mode Profile 3
-----100 Power Mode Profile 4
-----101 Power Mode Profile 5 (custom profile)
ff10---- Custom profile PM3 content
--00---- Assign scheme A to PM3
PM3_man 5:4 --01---- Assign scheme B to PM3
--10---- Assign scheme C to PM3
--11---- Assign scheme D to PM3
ff--11-- Custom profile PM2 content
Power Mode ----00-- Assign scheme A to PM2
0x1E 0x2F Profile PM2_man 3:2 ----01-- Assign scheme B to PM2
configuration ----10-- Assign scheme C to PM2
----11-- Assign scheme D to PM2
ff----11 Custom profile PM1 content
------00 Assign scheme A to PM1
PM1_man 1:0 ------01 Assign scheme B to PM1
------10 Assign scheme C to PM1
------11 Assign scheme D to PM1
Over-current Clears over current protection latch. A low to
ocp_latch_cle
0x20 0x1F protection 7 0------- high toggle clears the current OCP latched
ar
latch clear condition.
Enables or disables DC protection. High to
0x26 0x05 DC protection Eh_dcShdn 2 ffff-1--
enable. Low to disable.
Error handler Clears error handler. A low-to-high-to-low
0x2D 0x10 eh_clear 2 -----0--
clear toggle clears the error handler.
Read / Write Access (I2S format configuration)
Default
Value
00000000 i2s standard
00000001 Left justified
PCM word 00000100 Right justified 16bits
0x35 0x01 i2s_format 2:0
format 00000110 Right justified 18bits
00000000 Right justified 20bits
00000111 Right justified 24bits
Left PCM data word (of a simultaneously
Left/right 00000001
sampled PCM data pair) is send first
order of PCM i2s_rightfirst 5
words Right PCM data word (of a simultaneously
00100001
sampled PCM data pair) is send first
64 serial clock (SCK) cycles are present in each
00000001
period of the word select signal (WS)
Number of
data bits per i2s_framesize 4:3 00001001
frame
00010001
Most significant bit of the PCM data word is
Bit order of 00000001
transmitted first
PCM data i2s_order 2
words Least significant bit of the PCM data word is
00000101
transmitted first
0x36 0x01
First word of a simultaneously sampled PCM
00000001 data pair is transmitted while word select (WS)
Pairing of is low
i2s_ws_pol 1
data words First word of a simultaneously sampled PCM
00000011 data pair is transmitted while word select (WS)
is high
Serial data (SDX) and word select (WS) are
changing at rising edge of the serial clock signal
00000000
Clocking edge (SCK). The MA12070P will capture data at the
of the serial falling edge of the serial clock signal SCK
i2s_sck_pol 0
clock signal Serial data (SDX) and word select (WS) are
(SCK) changing at falling edge of the serial clock
00000001
signal (SCK). The MA12070P will capture data
at the rising edge of the serial clock signal SCK
Read / Write Access (Volume control and limiter)
Default
Value
0 0 0 0 0 0 0 1 Slow attack time
Limiter attack audio_proc_rele
7:6 0 1 0 0 0 0 0 1 Normal attack time
time control ase
1 0 0 0 0 0 0 1 Fast attack time
audio_proc_atta 0 0 0 0 0 0 0 1 Slow release time
0x35 0x01 Limiter release ck 5:4 0 0 0 1 0 0 0 1 Normal release time
time
0 0 1 0 0 0 0 1 Fast release time
Processor bypass audio_proc_ena 0 0 0 0 0 0 01 Bypass the audio processor
3
mux ble 0 0 0 0 1 0 01 Use the audio processor
audio_proc_mut 1 0 0 0 0 0 0 1 Mute audio
Mute mux control 7
e 0 0 0 0 0 0 0 1 Play audio
0x36 0x01
Limiter bypass audio_proc_limi 0 0 0 0 0 0 0 1 Bypass the limiter
6
mux terEnable 0 1 0 0 0 0 0 1 Use the limiter
Master integer dB Control of integer value master dB volume
0x40 0x18 vol_db_master 7:0 00011000
volume (see Table 8-9 for mapping overview)
Master fract dB Control of fractional value dB volume (see
0x41 0x00 vol_lsb_master 1:0 ffffff00
volume Table 8-9 for mapping overview)
Ch0L integer dB Control of integer value ch0L dB volume (see
0x42 0x18 vol_db_ch0 7:0 00011000
Ch0R integer dB Control of integer value ch0R dB volume (see
0x43 0x18 vol_db_ch1 7:0 00011000
Ch1L integer dB Control of integer value ch0L dB volume (see
0x44 0x18 vol_db_ch2 7:0 00011000
Ch1R integer dB Control of integer value ch0R dB volume (see
0x45 0x18 vol_db_ch3 7:0 00011000
Ch0L fract dB Control of fractional value ch0L dB volume
vol_lsb_ch0 1:0 00000000
Ch0R fract dB Control of fractional value ch0R dB volume
vol_lsb_ch1 3:2 00000000
0x46 0x00
Ch1L fract dB Control of fractional value ch1L dB volume
vol_lsb_ch2 5:4 00000000
Ch0R fract dB Control of fractional value ch1R dB volume
vol_lsb_ch3 7:6 00000000
Ch0L integer dBFS Control of integer value ch0L dBFS limiter
0x47 0x18 thr_db_ch0 7:0 00011000
limiter threshold (see section “Limiter”)
Ch0R integer dBFS Control of integer value ch0R dBFS limiter
0x48 0x18 thr _db_ch1 7:0 00011000
Ch1L integer dBFS Control of integer value ch0L dBFS limiter
0x49 0x18 thr _db_ch2 7:0 00011000
limiter threshold (see section “Limiter)
Ch1R integer dBFS Control of integer value ch0R dBFS limiter
0x4A 0x18 thr _db_ch3 7:0 00011000
Ch0L fract dBFS Control of fractional value ch0L dBFS limiter
thr _lsb_ch0 1:0 00000000
Ch0R fract dBFS Control of fractional value ch0R dBFS limiter
thr _lsb_ch1 1:0 00000000
0x4B 0x00
Ch1L fract dBFS Control of fractional value ch1L dBFS limiter
thr _lsb_ch2 1:0 00000000
Ch0R fract dBFS Control of fractional value ch1R dBFS limiter
thr _lsb_ch3 1:0 00000000
Read Only Access (Volume control and limiter monitor)
Default
Value
Indicates if Bit 5 high: limiter is active on channel 0R
audio_proc_li
0x7E 0x00 limiters are 7:4 00000000
miter_mon Bit 6 high: limiter is active on channel 1L
active
Indicates if Bit 0 high: clipping is present on channel 0L
clipping Bit 1 high: clipping is present on channel 0R
audio_proc_c
0x7E 0x00 occurs on the 3:0 00000000
lip_mon Bit 2 high: clipping is present on channel 1L
VLP output
signals Bit 3 high: clipping is present on channel 0R
Read Only Access (Monitor Channel 0 and Channel 1)
Default
Value
Monitor Frequency mode monitor channel 0. Register
dcu_mon0.fr
register 6:4 -000ff00 to read out in which frequency mode channel 0
eqMode
channel 0 of the device is currently operating in.
0x60 0x00
(Frequency Power mode monitor channel 0. Monitor to
and Power dcu_mon0.P
1:0 ----ff00 read out in which Power Mode channel 0 of
Mode) M_mon
the device is currently operating in.
dcu_mon0.m Channel 0 mute monitor. Monitor to read out
5 ff000000
ute if channel 0 is in mute or in unmute.
dcu_mon0.vd Channel 0 VDD monitor. Monitor to read out if
4 ff000000
d_ok VDD for channel 0 is ok.
dcu_mon0.pv Channel 0 PVDD monitor. Monitor to read out
3 ff000000
Monitor dd_ok if PVDD for channel 0 is ok.
0x61 0x00 register dcu_mon0.Vc Channel 0 Cfly2 protection monitor. Monitor to
2 ff000000
channel 0 fly2_ok read out if Cfly2 for channel 0 is ok.
dcu_mon0.Vc Channel 0 Cfly1 protection monitor. Monitor to
1 ff000000
fly1_ok read out if Cfly1 for channel 0 is ok.
Channel 0 over current protection monitor.
OCP Monitor
0 ff000000 Monitor to read out if an over current
channel 0
protection event has occurred.
Monitor
Channel 0 modulation index monitor. Monitor
register
dcu_mon0.M to read out live modulation index. Modulation
0x62 0x00 channel 0 7:0 00000000
_mon index from 0 to 1 maps on the 8-bits register
(Modulation
from 0 to 255.
Index)
Monitor Frequency mode monitor channel 1. Register
dcu_mon1.fr
register 6:4 -000ff00 to read out in which frequency mode channel 1
eqMode
channel 1 of the device is currently operating in.
0x64 0x00
(Frequency Power mode monitor channel 1. Monitor to
and Power dcu_mon1.P
1:0 ----ff00 read out in which Power Mode channel 1 of
Mode) M_mon
the device is currently operating in.
dcu_mon1.m Channel 1 mute monitor. Monitor to read out
5 ff000000
ute if channel 1 is in mute or in unmute.
dcu_mon1.vd Channel 1 VDD monitor. Monitor to read out if
4 ff000000
d_ok VDD for channel 1 is ok.
dcu_mon1.pv Channel 1 PVDD monitor. Monitor to read out
3 ff000000
Monitor dd_ok if PVDD for channel 1 is ok.
0x65 0x00 register dcu_mon1.Vc Channel 1 Cfly2 protection monitor. Monitor to
2 ff000000
channel 1 fly2_ok read out if Cfly2 for channel 1 is ok.
dcu_mon1.Vc Channel 1 Cfly1 protection monitor. Monitor to
1 ff000000
fly1_ok read out if Cfly1 for channel 1 is ok.
Channel 1 over current protection monitor.
OCP Monitor
0 ff000000 Monitor to read out if an over current
channel 1
protection event has occurred.
Monitor
Channel 1 modulation index monitor. Monitor
register
dcu_mon1.M to read out live modulation index. Modulation
0x66 0x00 channel 1 7:0 00000000
_mon index from 0 to 1 maps on the 8-bits register
(Modulation
from 0 to 255.
Index)
Read Only Access (Error Register Monitoring):
Default
Address Address Description Name Bit(s) Value
Value
Error monitor register. Gives the accumulated
status of every potential error source. This
register should be cleared by using the error
handler clear register.
All bits will be 0 in default/normal operation
and 1 when triggered
Error Bit 0: flying capacitor over-voltage error
0x6D 0x00 accumulated error_acc 7:0 00000000 Bit 1: over-current protection
register
Bit 2: pll error
Bit 3: PVDD under-voltage protection
Bit 4: over-temperature warning
Bit 5: over-temperature error
Bit 6: pin-to-pin low impedance protection
Bit 7: DC protection
MSEL[2:0] monitor register. Monitor to read
Monitor
0x75 0x00 msel_mon 2:0 fffff000 out which output configuration the device is in:
MSEL register
BTL, SE, BTL/SE or PBTL
Error monitor register. Gives the live status of
every potential error source.
All bits will be 0 in default/normal operation
and 1 when triggered
Bit 0: flying capacitor over-voltage error
Bit 1: over-current protection
0x7C 0x00 Error register error 7:0 00000000
Bit 2: pll error
Bit 3: PVDD under-voltage protection
Bit 4: over-temperature warning
Bit 5: over-temperature error
Bit 6: pin-to-pin low impedance protection
Bit 7: DC protection
17 Package Information
QFN pad-down 64-pin mechanical data
18 Tape and Reel Information
19 Revision History
Doc. Rev. Date Comments

July
V 1.0 Initial release in Infineon format
2018
Silicon update. Improve of DC offset in BTL, PBTL and 2.1 configurations. Correction of
known issues and limitations in errata sheet v1.0 in sections 1.1, 1.2 and 1.4.
Feb Show power mode profile 5 value as “101” in 0X1D register address.
V 1.1
2022 Show channel disable register 0x07.
Running the DAC directly from the MCLK is not supported, delete functionality.
Amplifier gain modification is not supported, delete register.
20 Contents
Description 1
Applications 1
Features 1
Package 1
1 Ordering Information 2
2 Known Issues and Limitations 2
3 Typical Application Block Diagram 3
4 Pin Description 4
4.1 Pinout MA12070P 4
4.2 Pin Function 5
5 Absolute Maximum Ratings 7
6 Recommended Operating Conditions 8
7 Electrical and Audio Characteristics 9
8 Functional description 12
Multi-level modulation 12
Very low power consumption 12
Power Mode Management 12
Power Modes Profiles 13
Power supplies 14
Gate driver supplies 15
Digital core supply 15
Flying capacitors 15
Protection 16
Over-current protection on OUTXX nodes 16
Temperature protection 16
Power supply monitors 17
DC protection 17
Digital serial audio input 17
Volume and limiter processor (VLP) 19
Volume control 19
Limiter 20
VLP parameter interface 21
Clock system 22
MCU/Serial control interface 23
I2C write operation 24
I2C read operation 25
/CLIP pin and soft-clipping 26
/ERROR pin and error handling 26
9 Application Information 27
Input/Output Configurations 27
Bridge Tied Load (BTL) Configuration 27
Single Ended (SE) Configuration 28
Combined SE and BTL Configuration 29
Parallel Bridge Tied Load (PBTL) 29
EMC output filter Considerations 30
Audio Performance Measurements 30
Thermal Characteristics and Test Signals 30
Start-up procedure 30
Shut-down / power-down procedure 31
Recommended PCB Design for MA12070P (EPAD-down package) 31
10 Typical Characteristics (PVDD = +26V, Load = 4Ω + 22µH) 32
16 Register map 76
Read / Write Access (Power Mode Settings): 76
Read / Write Access (Power Mode Profile Settings): 77
Read / Write Access (I2S format configuration) 78
Read / Write Access (Volume control and limiter) 79
Read Only Access (Volume control and limiter monitor) 80
Read Only Access (Monitor Channel 0 and Channel 1) 81
Read Only Access (Error Register Monitoring): 82
17 Package Information 83
18 Tape and Reel Information 84
19 Revision History 85
20 Contents 86
Trademarks
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Infineon Technologies AG condition or quality of the product. Before
81726 Munich, Germany implementation of the product, the recipient of this
application note must verify any function and other WARNINGS
technical information given herein in the real Due to technical requirements products may contain
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MA12070P

Filterless and High-Efficiency +4V to +26V

Part Number Package Moisture Description

2 Known Issues and Limitations

100nF 1µF 1µF 1µF

PVSS CF1B EMC filter

Figure 3-1 Typical application block diagram

Figure 4-1 Pinout MA12070P

Type1: P = Power; I = Input; O = Output; IO = Input or Output

See “Recommended Operation Conditions” for continuous functional ratings.

Minimum required equivalent load inductance per output pin

TA Ambient temperature range 0 +25 +85 °C

Note: Minimum Load resistance was measured in Filterless output condition.

THD+N = 1%, RL = 8Ω, f = 1kHz 35 W

THD+N = 1%, RL = 4Ω, f = 1kHz 60 W

THD+N = 1%, RL = 2Ω, f= 1kHz 120 W

THD+N = 1%, RL = 4Ω, f = 1kHz 15 W

THD+N = 1%, RL = 3Ω, f = 1kHz 20 W

TENABLE Shutdown/Full Operation Timing NENABLE = 1 → 0 1 ms

TMUTE Mute/Unmute Timing NMUTE = 1 → 0 and 0 → 1 0.3 ms

VOS,BTL/PBTL Output Offset Voltage, see Note 4 ±35 mV

VOS,SE Output Offset Voltage, see Note 4,5 50 mV

PSRR Power Supply Rejection Ratio ± 100mVpp ripple voltage 70 dB

Ron Resistance, switch on 0.10 0.15 0.20 Ω

Power Mode A 618 672 726 kHz

fCLK_IO Clock Output Frequency 2.7151 2.8224 2.9296 MHz

IOUT/OCPTHR Maximum Output Current 8 A

XTalk Crosstalk BTL, POUT = 1W, f=1kHz, Ch1 & 2 -108 dB

POUT = 2×40W, 8Ω , PMP = 1 91 %

POUT = 2×40W, 8Ω , PMP = 2 89 %

POUT = 2×40W, 8Ω , PMP = 4 92 %

POUT = 2×80W, 4Ω , PMP = 0 87 %

POUT = 2×80W, 4Ω , PMP = 1 87 %

POUT = 2×80W, 4Ω , PMP = 2 86 %

POUT = 2×80W, 4Ω , PMP = 4 88 %

Iidle,mute Current Consumption, PVDD Idle, mute 4 6 12 mA

Iidle,unmute Current Consumption, PVDD Idle, unmute, inputs grounded 4 9 18 mA

IDVDD+AVDD Current Consumption, AVDD+DVDD Idle, unmute, inputs grounded 30 35 42 mA

1kHz, POUT = 1W, RL = 4Ω 0.013 %

DNR Dynamic Range1 20-20kHz, A-weighted 100 dB

Iidle,mute Current Consumption, PVDD Idle, mute 4 6 12 mA

Iidle,unmute Current Consumption, PVDD Idle, unmute, inputs grounded 4 11 22 mA

IDVDD+AVDD Current Consumption, AVDD+DVDD Idle, unmute, inputs grounded 33 38 45 mA

1kHz, POUT = 1W, RL = 4Ω 0.012 %

DNR Dynamic Range1 20-20kHz, A-weighted 101 dB

1 Output power at THD+N < 1% reference to noise floor at -60dBFS signal.

Very low power consumption

Power Mode Management

Figure 8-1 Illustration of automatic power mode selection ranges.

Power Modes Profiles

Property Profile 0 Profile 1 Profile 2 Profile 3 Profile 4

THD+N Good Best Best Good/Best Good

Filterfree: Filterfree: LC filter: high Filterfree:

Modulation scheme 3-level 5-level 3-level 5-level

Idle loss Reduced Low Low Very low

Full scale efficiency Normal Good Good Best

Open-loop gain High High Low Low

THD+N Best Best Good Good

Table 8-3 Gate driver supply capacitors

Digital core supply