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EEC 116 Lecture #3:
CMOS Inverters
MOS Scaling
Rajeevan Amirtharajah
University of California, Davis
Jeff Parkhurst
Intel Corporation
Outline
• Review: Inverter Transfer Characteristics
• Lecture 3: Noise Margins, Rise & Fall Times,
Inverter Delay
• CMOS Inverters: Rabaey 1.3.2, 5 (Kang &
Leblebici, 5.1-5.3 and 6.1-6.2)
Amirtharajah, EEC 116 Fall 2011 3

Review: Inverter Voltage Transfer Curve
Voltage transfer curve (VTC): plot of output voltage
Vout vs. input voltage Vin
Vin Inverter Vout
Ideal digital inverter:

Vdd ideal
–When Vin=0,
Vout=Vdd
Vout
actual –When Vin=Vdd,
Vout=0
–Sharp transition region
0V Vdd
Vin
Review: Actual Inverter Output Levels
• VOH and VOL represent the
“high” and “low” output
voltages of the inverter
• VOH = output voltage when
VOH Vin = ‘0’ (V Output High)
Vout • VOL = output voltage when

Vin = ‘1’ (V Output Low)
VOL • Ideally,
0V Vdd
Vin – VOH = Vdd
– VOL = 0 V

Review: VOL and VOH
• In transfer function terms:

– VOL = f(VOH)
VOH – VOH = f(VOL)

– f = inverter transfer
Vout function
• Difference (VOH-VOL) is the
VOL voltage swing of the gate
VOL Vin VOHVdd – Full-swing logic swings
from ground to Vdd
– Other families with
smaller swings

Review: Inverter Switching Threshold
Inverter switching
threshold:
– Point where voltage
transfer curve intersects
VOH Vout=Vin
line Vout=Vin
Vout – Represents the point at

VM
which the inverter
switches state
VOL
Vdd – Normally, VM ≈ Vdd/2
Vin
– Sometimes other
thresholds desirable

VTC Mathematical Definitions
• VOH is the output high level of an inverter
VOH = VTC(VOL)
• VOL is the output low level of an inverter
VOL = VTC(VOH)
• VM is the switching threshold
VM = VIN = VOUT
• VIH is the lowest input voltage for which the output
will be ≥ the input (worst case ‘1’)
dVTC(VIH)/dVIH = -1
• VIL is the highest input voltage for which the output
will be ≤ the input (worst case ‘0’)
dVTC(VIL)/dVIL = -1

Noise Margin and Delay Definitions
• NML is the difference between the highest
acceptable ‘0’ and the lowest possible ‘0’
NML = VIL – VOL
• NMH is the difference between the lowest acceptable
‘1’ and the highest possible ‘1’
NMH = VOH – VIH
• tPHL is the propagation delay from the 50% point of
the input to the output when the output goes from
high to low
• tPLH is the propagation delay from the 50% point of
low to high
• tP is the average propagation delay
• tR is the rise time (usually 10% to 90%)
• tF is the fall time (usually 90% to 10%)
CMOS Inverter
• Complementary NMOS and
PMOS devices Vdd
• In steady-state, only one device
is on (no static power
consumption) Vin Vout
• Vin=1: NMOS on, PMOS off
– Vout = VOL = 0
• Vin=0: PMOS on, NMOS off
– Vout = VOH = Vdd
• Ideal VOL and VOH!
• Ratioless logic: output is
independent of transistor sizes in
Gnd
steady-state
CMOS Inverter: VTC
PMOS NMOS
Vin=4V
Drain current IDS
Vin=3V Vdd
Vout
Vin=2V
Vin=1V
Vout = VDS Vdd 0 1 2 Vin 3 4
• Output goes completely to Vdd and Gnd

• Sharp transition region
CMOS Inverter Operation
VDD
• NMOS transistor:
– Cutoff if Vin < VTN Vin Vout
– Linear if Vout < Vin – VTN
– Saturated if Vout > Vin – VTN
• PMOS transistor
– Cutoff if (Vin-VDD) > VTP → Vin > VDD+VTP
– Linear if (Vout-VDD)>Vin-VDD-VTP → Vout>Vin - VTP
– Sat. if (Vout-VDD)<Vin-VDD-VTP → Vout < Vin-VTP

CMOS Inverter VTC: Device Operation
P linear P cutoff
N cutoff N linear
P linear
N sat P sat
N sat
P sat
N linear

CMOS Inverter VTC: Device Sizing
• Increase W of PMOS
VDD kp=kn kp increases
VTC moves to right
• Increase W of NMOS
Vout kp=5kn
kn increases
VTC moves to left
kp=0.2kn • For VM = VDD/2

kn = kp
VDD 2Wn ≈ Wp
Vin

Effects of VM adjustment
• Result from changing kp/kn ratio:
– Inverter threshold VM ≠ VDD/2
– Rise and fall delays unequal
– Noise margins not equal
• Reasons for changing inverter threshold
– Want a faster delay for one type of transition
(rise/fall)
– Remove noise from input signal: increase one
noise margin at expense of the other
– Interfacing other types of logic (with different
swings)

CMOS Inverter: VIL Calculation
• KCL (NMOS saturation, PMOS linear):
kn
2
2
2
[
(VGS ,n − VT 0,n ) = 2(VGS , p − VT 0, p )VDS , p − VDS , p 2
kp
]
kn
2
2
2
[
(Vin − VT 0,n ) = 2(Vin − VDD − VT 0, p )(Vout − VDD ) − (Vout − VDD )2
kp
]
• Differentiate and set dVout/dVin to –1
⎡ dVout ⎤
k n (Vin − VT 0,n ) = k p ⎢(Vin − VDD − VT 0, p ) + (Vout − VDD ) − (Vout − VDD )
dVout
⎥
⎣ dV in dV in ⎦
kn (VIL −VT 0,n ) = k p (2Vout −VIL +VT 0, p −VDD )
2Vout + VT 0, p − VDD + k RVT 0,n kn

VIL = kR =
1 + kR kp
• Solve simultaneously with KCL to find VIL
CMOS Inverter: VIH Calculation
• KCL: k n 2(V
2
GS , n[− VT 0,n )V DS , n − V DS , n
2
=
kp
2
(V ]
GS , p − V T 0, p )2
kn
2
[
2(Vin − VT 0,n )Vout − Vout =
2 kp
2
] (
Vin − VDD − VT 0, p
2
)
⎡ dVout ⎤
k n ⎢(Vin − VT 0,n ) ⎥ = k p (Vin − VDD − VT 0, p )
dVout
+ Vout − Vout
⎣ dVin dVin ⎦
( )
kn 2Vout −VIH +VT 0, p = k p VIH −VDD −VT 0, p ( )
VDD + VT 0, p + k R (2Vout + VT 0,n ) kn
VIH = kR =
1 + kR kp
• Solve simultaneously with KCL to find VIH
CMOS Inverter: VM Calculation
• KCL (NMOS & PMOS saturated):
(VGS ,n − VT 0,n ) = (VGS , p − VT 0, p )2

kn 2 kp
2 2
kn
(Vin − VT 0,n ) = (Vin − VDD − VT 0, p )
2 kp 2
2 2
• Solve for VM = Vin = Vout
VT 0,n +
1
(VDD + VT 0, p )
kR kn
VM = kR =
1 kp
1+
kR
CMOS Inverter: Achieving Ideal VM
VT 0,n +
1
kR
(VDD + VT 0, p )
kn
VTH = kR =
1 kp
1+
kR
2
⎛ VDD 2 + VT 0, p ⎞
• Ideally, VM = VDD/2 k R ,ideal = ⎜⎜ ⎟
⎟
⎝ V DD 2 + VT 0 , n ⎠
• Assuming VT0,n = VT0,p, k R ,ideal =1

⎛W ⎞
⎜ ⎟
⎝ L ⎠ p μn
= ≈ 2.5
⎛W ⎞ μp
⎜ ⎟
⎝ L ⎠n
CMOS Inverter: VIL and VIH for Ideal VM
• Assuming VT0,n=-VT0,p, and kR = 1,
VIL = (3VDD + 2 VT 0 )
1
8
VIH = (5VDD − 2 VT 0 )
1
8
VIL + VIH = VDD
NM L = VIL − VOL = VIL
NM H = VOH − VIH = VDD − VIH = VIL

MOSFET Scaling Effects
• Rabaey Section 3.5 (Kang & Leblebici Section 3.5)

• Scaling provides enormous advantages
– Scale linear dimension (channel length) by factor S > 1
– Better area density, yield, performance
• Two types of scaling
– Constant field scaling (full scaling)
• A’ = A/S2; L’ = L/S; W’ = W/S; ID’ = ID/S; P’ = P/S2 ;
Vdd’ = Vdd/S
• Power Density P’/A’ = stays the same Change these two
– Constant voltage scaling
• A’ = A/S2; L’ = L/S; W’ = W/S; ID’ = ID*S; P’ = P*S;
Vdd’ = Vdd
• Power Density P’/A’ = S3*P (Reliability issue)
Amirtharajah, EEC 116 Fall 2011
This changed as well 21
Short Channel Effects
• As geometries are scaled down
– VT (effective) goes lower
– Effective channel length decreases
– Sub-threshold Ids occurs
• Current goes from drain to source while Vgs < Vt
– Tox is scaled which can cause reliability problems
• Can’t handle large Vg without hot electron effects
– Changes the Vt when carriers imbed themselves
in the oxide
– Interconnects scale
• Electromigration and ESD become issues

MOSFET Capacitances
• Rabaey Section 3.3 (Kang & Leblebici Section 3.6)
• Oxide Capacitance
– Gate to Source overlap
– Gate to Drain overlap
– Gate to Channel
• Junction Capacitance
– Source to Bulk junction
– Drain to Bulk junction

Oxide Capacitances: Overlap
source Ldrawn drain
xd
• Overlap capacitances
– Gate electrode overlaps source and drain regions
– xd is overlap length on each side of channel

– Leff = Ldrawn – 2xd (effective channel length)
– Overlap capacitance:
CGSO = CGDO = CoxWxd Assume xd equal on both sides
Total Oxide Capacitance
• Total capacitance consists of 2 components
– Overlap capacitance
– Channel capacitance Cgs Cgd
source drain
Cgb
• Cutoff:
– No channel connecting to source or drain
– CGS = CGD = CoxWxd
– CGB = CoxWLeff
– Total Gate Capacitance = CG = CoxWL

Oxide Capacitances: Channel
• Linear mode
– Channel spans from source to drain
– Channel Capacitance split equally between S and D
1 1
CGS = C oxWLeff CGD = C oxWLeff CGB = 0
2 2
– Total Gate capacitance CG = CoxWL
• Saturation regime
– Channel is pinched off: Channel Capacitance --
2
CGD = Wxd Cox CGS = CoxWLeff + COX Wxd CGB = 0
3
– Total Gate capacitance:
CG = 2/3 CoxWLeff + 2xdWCOX
Oxide Capacitances: Channel
Cg,total
(no overlap,
xd = 0)

Junction Capacitance
Reverse-biased P-N junctions!

Capacitance depends on reverse-bias voltage.

A 2qε N d N a
For a P-N junction: Cj =
2 V0 − V N d + N a
qε Si N d N a
If V=0, cap/area = C j0 =
2V0 N d + N a
AC j 0
General form: Cj = m
⎛ V ⎞
⎜⎜1 − ⎟⎟
⎝ V0 ⎠
m = grading coefficient (0.5 for abrupt junctions)

(0.3 for graded junctions)
• Junction with substrate
– Bottom area = W * LS (length of drain/source)
– Total cap = Cj
• Junction with sidewalls
– “Channel-stop implant”
– Perimeter = 2LS + W
– Area = P * Xj
– Total cap = Cjsw
• Total junction cap C = Cj + Cjsw

• Voltage Equivalence Factor
– Creates an average capacitance value for a
voltage transition, defined as ΔQ/ΔV
⎛
− AC j 0V0 ⎜ ⎛ V2 ⎞
1− m
⎛ V1 ⎞ ⎞⎟
1− m
Ceq = ⎜⎜1 − ⎟⎟ − ⎜⎜1 − ⎟⎟ = AK eq C j 0

(V2 − V1 )(1 − m ) ⎜⎝ ⎝ V0 ⎠ ⎝ V0 ⎠ ⎟⎠
K eq =
− 2 V0
(V2 − V1 )
(
V0 − V2 − V0 − V1 ) (abrupt junction only)
Cdb = AK eq C j 0 + PX j K eqswC jsw0

Example: Junction Cap
• Consider the following NMOS device
– Substrate doping: NA = 1015 cm-3
– Source/drain doping: ND = 2 x 1020 cm-3
– Channel-stop doping: 10X substrate doping
– Drain length LD = 1um
– Transistor W = 10um
– Junction depth Xj = 0.5um, abrupt junction
• Find capacitance of drain-bulk junction when

drain voltage = 3V

Next Time: AC Characteristics
• CMOS Inverters
– AC Characteristics: Designing for speed

EEC 118 Lecture #4:
CMOS Inverters
Jeff Parkhurst
Intel Corporation
Announcements
• Lab 2 this week, report due next week
• Lab 1 reports due this week at lab section
• HW 2 due this Friday at 4 PM in box, Kemper
2131
Amirtharajah/Parkhurst, EEC 118 Spring 2011 2

Outline
• Review: Inverter Transfer Characteristics
• Lecture 3: Noise Margins, Rise & Fall Times,
Inverter Delay
• CMOS Inverters: Rabaey 1.3.2, 5 (Kang &
Leblebici, 5.1-5.3 and 6.1-6.2)

Review: Inverter Voltage Transfer Curve
Voltage transfer curve (VTC): plot of output voltage
Vout vs. input voltage Vin
Vin Inverter Vout
Ideal digital inverter:

Vdd ideal
–When Vin=0,
Vout=Vdd
Vout
actual –When Vin=Vdd,
Vout=0
–Sharp transition region
0V Vdd
Vin
Review: Actual Inverter Output Levels
• VOH and VOL represent the
“high” and “low” output
voltages of the inverter
• VOH = output voltage when
VOH Vin = ‘0’ (V Output High)
Vout • VOL = output voltage when

Vin = ‘1’ (V Output Low)
VOL • Ideally,
0V Vdd
Vin – VOH = Vdd
– VOL = 0 V

Review: VOL and VOH
• In transfer function terms:

– VOL = f(VOH)
VOH – VOH = f(VOL)

– f = inverter transfer
Vout function
• Difference (VOH-VOL) is the
VOL voltage swing of the gate
VOL Vin VOHVdd – Full-swing logic swings
from ground to Vdd
– Other families with
smaller swings

Review: Inverter Switching Threshold
Inverter switching
threshold:
– Point where voltage
transfer curve intersects
VOH Vout=Vin
line Vout=Vin
Vout – Represents the point at

VM
which the inverter
switches state
VOL
Vdd – Normally, VM ≈ Vdd/2
Vin
– Sometimes other
thresholds desirable

VTC Mathematical Definitions
• VOH is the output high level of an inverter
VOH = VTC(VOL)
• VOL is the output low level of an inverter
VOL = VTC(VOH)
• VM is the switching threshold
VM = VIN = VOUT
• VIH is the lowest input voltage for which the output
will be ≥ the input (worst case ‘1’)
dVTC(VIH)/dVIH = -1
• VIL is the highest input voltage for which the output
will be ≤ the input (worst case ‘0’)
dVTC(VIL)/dVIL = -1

Noise Margin and Delay Definitions
• NML is the difference between the highest
acceptable ‘0’ and the lowest possible ‘0’
NML = VIL – VOL
• NMH is the difference between the lowest acceptable
‘1’ and the highest possible ‘1’
NMH = VOH – VIH
• tPHL is the propagation delay from the 50% point of
high to low
• tPLH is the propagation delay from the 50% point of
low to high
• tP is the average propagation delay
• tR is the rise time (usually 10% to 90%)
• tF is the fall time (usually 90% to 10%)
CMOS Inverter
• Complementary NMOS and
PMOS devices Vdd
• In steady-state, only one device
is on (no static power
consumption) Vin Vout
• Vin=1: NMOS on, PMOS off
– Vout = VOL = 0
• Vin=0: PMOS on, NMOS off
– Vout = VOH = Vdd
• Ideal VOL and VOH!
• Ratioless logic: output is
independent of transistor sizes in
Gnd
steady-state
CMOS Inverter: VTC
PMOS NMOS
Vin=4V
Drain current IDS
Vin=3V Vdd
Vout
Vin=2V
Vin=1V
Vout = VDS Vdd 0 1 2 Vin 3 4
• Output goes completely to Vdd and Gnd

• Sharp transition region
CMOS Inverter Operation
VDD
• NMOS transistor:
– Cutoff if Vin < VTN Vin Vout
– Linear if Vout < Vin – VTN
– Saturated if Vout > Vin – VTN
• PMOS transistor
– Cutoff if (Vin-VDD) > VTP → Vin > VDD+VTP
– Linear if (Vout-VDD)>Vin-VDD-VTP → Vout>Vin - VTP
– Sat. if (Vout-VDD)<Vin-VDD-VTP → Vout < Vin-VTP

P linear P cutoff
N cutoff N linear
P linear
N sat P sat
N sat
P sat
N linear

CMOS Inverter VTC: Device Sizing
• Increase W of PMOS
VDD kp=kn kp increases
VTC moves to right
• Increase W of NMOS
Vout kp=5kn
kn increases
VTC moves to left
kp=0.2kn • For VM = VDD/2

kn = kp
VDD 2Wn ≈ Wp
Vin

Effects of VM adjustment
• Result from changing kp/kn ratio:
– Inverter threshold VM ≠ VDD/2
– Rise and fall delays unequal
– Noise margins not equal
• Reasons for changing inverter threshold
– Want a faster delay for one type of transition
(rise/fall)
– Remove noise from input signal: increase one
noise margin at expense of the other
– Interfacing other types of logic (with different
swings)

CMOS Inverter: VIL Calculation
• KCL (NMOS saturation, PMOS linear):
kn
2
2
2
[
(VGS ,n − VT 0,n ) = 2(VGS , p − VT 0, p )VDS , p − VDS , p 2
kp
]
kn
2
2
2
[
(Vin − VT 0,n ) = 2(Vin − VDD − VT 0, p )(Vout − VDD ) − (Vout − VDD )2
kp
]
⎡ dVout ⎤
k n (Vin − VT 0,n ) = k p ⎢(Vin − VDD − VT 0, p ) + (Vout − VDD ) − (Vout − VDD )
dVout
⎥
⎣ dV in dV in ⎦
kn (VIL −VT 0,n ) = k p (2Vout −VIL +VT 0, p −VDD )
2Vout + VT 0, p − VDD + k RVT 0,n kn

VIL = kR =
1 + kR kp
• Solve simultaneously with KCL to find VIL
CMOS Inverter: VIH Calculation
• KCL: k n 2(V
2
GS , n[− VT 0,n )V DS , n − V DS , n
2
=
kp
2
(V ]
GS , p − V T 0, p )2
kn
2
[
2(Vin − VT 0,n )Vout − Vout =
2 kp
2
] (
Vin − VDD − VT 0, p
2
)
⎡ dVout ⎤
k n ⎢(Vin − VT 0,n ) ⎥ = k p (Vin − VDD − VT 0, p )
dVout
+ Vout − Vout
⎣ dVin dVin ⎦
( )
kn 2Vout −VIH +VT 0, p = k p VIH −VDD −VT 0, p ( )
VDD + VT 0, p + k R (2Vout + VT 0,n ) kn
VIH = kR =
1 + kR kp
• Solve simultaneously with KCL to find VIH
CMOS Inverter: VM Calculation
• KCL (NMOS & PMOS saturated):
(VGS ,n − VT 0,n ) = (VGS , p − VT 0, p )2

kn 2 kp
2 2
kn
(Vin − VT 0,n ) = (Vin − VDD − VT 0, p )
2 kp 2
2 2
• Solve for VM = Vin = Vout
VT 0,n +
1
(VDD + VT 0, p )
kR kn
VM = kR =
1 kp
1+
kR
CMOS Inverter: Achieving Ideal VM
VT 0,n +
1
kR
(VDD + VT 0, p )
kn
VTH = kR =
1 kp
1+
kR
2
⎛ VDD 2 + VT 0, p ⎞
• Ideally, VM = VDD/2 k R ,ideal = ⎜⎜ ⎟
⎟
⎝ V DD 2 + VT 0 , n ⎠
• Assuming VT0,n = VT0,p, k R ,ideal =1

⎛W ⎞
⎜ ⎟
⎝ L ⎠ p μn
= ≈ 2.5
⎛W ⎞ μp
⎜ ⎟
⎝ L ⎠n
CMOS Inverter: VIL and VIH for Ideal VM
• Assuming VT0,n=-VT0,p, and kR = 1,
VIL = (3VDD + 2 VT 0 )
1
8
VIH = (5VDD − 2 VT 0 )
1
8
VIL + VIH = VDD
NM L = VIL − VOL = VIL
NM H = VOH − VIH = VDD − VIH = VIL

Next Time: AC Characteristics & Fabrication
• CMOS Inverters
– AC Characteristics: Designing for speed

EEC 118 Lecture #5:
CMOS Inverter AC
Characteristics
Jeff Parkhurst
Intel Corporation
Acknowledgments
• Slides due to Rajit Manohar from ECE 547
Advanced VLSI Design at Cornell University

Outline
• Review: CMOS Inverter Transfer Characteristics
• CMOS Inverters: Rabaey 5.4-5.5 (Kang &
Leblebici, 6.1-6.4, 6.7)

P linear P cutoff
N cutoff N linear
P linear
N sat P sat
N sat
P sat
N linear

Logic Circuit Delay
• For CMOS (or almost all logic circuit families), only
one fundamental equation necessary to determine
delay:
dV
I =C
dt
ΔV
• Consider the discretized version: I =C
Δt
ΔV
• Rewrite to solve for delay: Δt = C
I
• Only three ways to make faster logic: C, ΔV, I

CMOS Inverter Capacitances
Vdd • Assume input
Cgs,p Csb,p transition is fixed,
then delay
determined by
output
Cgd,p Cdb,p
Capacitance on
Vin f node f (output):
Cgd,n Cdb,n Cint
Cg
• Junction cap
Cdb,p and Cdb,n
• Gate capacitance
Cgd,p and Cgd,n
Cgs,n Csb,n • Interconnect cap
Gnd • Receiver gate cap
CMOS Inverter Junction Capacitances
• Junction capacitances Cdb,p and Cdb,n:
– Equation for junction cap:
m
AC j 0 ⎛ εq N a N d 1 ⎞
C j (V ) = , C j0 = ⎜⎜ ⎟⎟
⎝ 2 N a + N d φ0 ⎠
m
⎛ V⎞
⎜⎜ 1 − ⎟⎟
⎝ φ0 ⎠
– Non-linear, depends on voltage across junction
– Use Keq factor to get equivalent capacitance for a
voltage transition
Cdb = AK eq C j + PK eqswC jsw

CMOS Inverter Gate Capacitances
• Gate capacitances CGD,p and CGD,n:
– Just after the input switches(t = 0+), what regions
are transistors in?
– One is in cutoff: CGD = Overlap Cap
– One is in Saturation: CGD = Overlap Cap
– Therefore, gate-to-drain capacitance is due to
overlap capacitance :
C gd , p = C gd ,n = CoxWLD
However, also need to consider Miller effect ...
CMOS Inverter Capacitances: Miller Effect
Cgd1
Vout
Vout
Vin Vin 2Cgd1
• When input rises by ΔV, output falls by ΔV

– Change in stored charge: ΔQ = Cgd1ΔV – (-Cgd1ΔV)
– Effective voltage change across Cgd1 is 2ΔV
– Effective capacitance to ground is twice Cgd1
• Including Miller effect:
C gd , p = C gd ,n = 2CoxWLD (For transistor in Cutoff)

CMOS Inverter Capacitances: Receiver
• Receiver gate capacitance

– Includes all capacitances of gate(s) connected to
output node
– Unknown region of operation for receiver
transistor: total gate cap varies from (2/3)WLCox to
WLCox
– Ignore Miller effect (taken into account on output)
– Assume worst-case value, include overlap
C g = WLeff Cox + 2WLD Cox
Cg = WL Cox
Inverter Capacitances: Analysis
• Simplify the circuit: combine all capacitances at
output into one lumped linear capacitance:
Cload = 2*Cgd,n + 2*Cgd,p + Cdb,n + Cdb,p + Cint

+ Cg
Miller effect
• Csb,n = Csb,p = 0
• Cgs,n and Cgs,p are not connected to the load.

These are part of the gate capacitance Cg

First-Order Inverter Delay
• Suppose ideal voltage step at input
• Assume: Current charging or
discharging capacitance Cload is
nearly constant Iavg Vout
Vin
• tPHL = Cload (Vdd - Vdd/2) / Iavg Cload
• tPLH = Cload (Vdd/2 - Vss) / Iavg

Inverter Delay: Falling
ID.n Cload
Vin
• Assume PMOS fully off (ideal step input, ID,p = 0)
dV
I =C
dt
dVout
I D ,n = Cload Need to determine ID,n
dt

Inverter Delay: Falling
NMOS in saturation
Vdd
Vdd - Vtn NMOS in linear region
Vdd/2
t0 t1 t2
• From t0 to t1: NMOS in saturation

• From t1 to t2: NMOS in linear region
• Find ID in each region

Inverter Delay: Falling t1-t0
• Assumption: Input fast enough to go through
transition before output voltage changes
• Vout drops from VOH to VDD-VTN (NMOS saturated)
I DS = kn (Vin − VT 0,n ) / 2 = kn (VOH − VT 0,n ) / 2

2 2
VOH −VT 0 , n
− 2CL
t1
∫t dt = kn (VOH − VT 0,n )2 ∫ dV
VOH
out
0
2CLVT 0,n
t1 − t0 =
kn (VOH − VT 0,n )2

Inverter Delay: Falling t2-t1
• Vout drops from (VOH-VT0,n) to VDD/2
• NMOS in linear region
[
I DS = kn (VOH − VT 0,n )Vout − 12 Vout
2
]
(VOH +VOL ) / 2
dVout
t2 − t1 = −CL ∫
VOH −VT 0 ,n
[
kn (VOH − VT 0,n )Vout − 12 Vout
2
]
CL ⎡ 2(VOH − VT 0,n ) − (VOH + VOL ) / 2 ⎤
t2 − t1 = ln⎢ ⎥
kn (VOH − VT 0,n ) ⎣ (VOH + VOL ) / 2 ⎦

Inverter Delay: Falling, Total
• Total fall delay = (t1-t0) + (t2-t1)
CL ⎡ 2VT 0,n ⎛ 4(VOH − VT 0,n ) ⎞⎤

t PHL = ⎢ + ln⎜⎜ − 1⎟⎟⎥
k n (VOH − VT 0,n ) ⎣VOH − VT 0,n ⎝ VOH + VOL ⎠⎦

Inverter Delay: Rising
• Similar calculation as for falling delay
• Separate into regions where PMOS is in linear,
saturation
CL ⎡ 2 VT 0, p ⎛ 4(VOH − VOL − VT 0, p ) ⎞⎤
t PLH = ⎢ + ln⎜ − 1⎟⎥
k p (VOH − VOL − VT 0, p ) ⎣⎢VOH − VOL − VT 0, p ⎜ V + V ⎟⎥
⎝ OH OL ⎠⎦
• Note: to balance rise and fall delays (assuming VOH =

VDD, VOL = 0V, and VT0,n=VT0,p) requires
⎛W ⎞
kp ⎜ ⎟
⎝ L ⎠ p μn
=1 ⎛W ⎞
=
μp
≈ 2.5
kn ⎜ ⎟
⎝ L ⎠n
Inverter Rise, Fall Times
• Summary -- Exact method: separate into two regions
– t1
• Vout drops from 0.9VDD to VDD-VT,n (NMOS in
saturation)
• Vout rises from 0.1VDD to |VT,p| (PMOS in saturation)
– t2
• Vout drops from VDD-VT,n to 0.1VDD (NMOS in linear
region)
• Vout rises from |VT,p| to 0.9 VDD (PMOS in linear
region)
– tf,r = t1 + t2

CMOS Inverter Delay
• Review of approximate
method
– Assume a constant average I1
V1=Vdd
current for the transition
– Iavg = average of drain V2=½Vdd I2
current at beginning and end
of transition
t1 t2
t PHL =
Cload
(VDD − 12 VDD )
I avg Iavg = ½(I1+I2)
t PLH =
Cload
( 12 VDD − VSS )
I avg
CMOS Inverter Delay: 2nd Approximation
• Another approximate
method:
– Again assume constant Iavg
– Iavg = current I1 at start of I1
V1=Vdd
transition
CloadVDD
t PHL = V2=½Vdd
k n (VDD − VTn )
2
CloadVDD
t PLH =
k p (VDD − VTP )
2 t1 t2
– Why is this a good Iavg = I1

approximation (esp. for deep
submicron)?
CMOS Inverter Delay: Finite Input Transitions
• What if input has finite rise/fall time?
– Both transistors are on for some amount of time
– Capacitor charge/discharge current is reduced
Empirical equations:
2
⎛ tr ⎞
tpHL(ns)
t phl (actual ) = t phl ( step ) + ⎜ ⎟

2
⎝2⎠
2
⎛tf ⎞
t plh (actual ) = t ( step ) + ⎜⎜ ⎟⎟
2
plh
⎝2⎠
trise(ns)
How to Improve Delay?
• Minimize load capacitances
– Small interconnect capacitance
– Small Cg of next stage
• Raise supply voltage
– Increases current faster than increased swing ΔV
• Increase transistor gain factor
– Increase transistor drive current for
charging/discharging output capacitance
• Use low threshold voltage devices
– More subthreshold leakage power dissipation
Inverter Power Consumption
• Static power consumption (ideal) = 0
– Actually DIBL (Drain-Induced Barrier Lowering),
gate leakage, junction leakage are still present
• Dynamic power consumption
T
1
Pavg = ∫ v(t )i(t )dt
T0
1⎡ ⎛ dVout ⎞ ⎛ dVout ⎞ ⎤
T /2 T
Pavg = ⎢ ∫ Vout ⎜ − Cload ⎟dt + ∫ (VDD − Vout )⎜ Cload ⎟dt ⎥
T⎣0 ⎝ dt ⎠ T /2 ⎝ dt ⎠ ⎦
⎡ T /2 T ⎤
1 ⎢⎛ Vout ⎞
⎟ + ⎛⎜VDDVout Cload − CloadVout 2 ⎞⎟ ⎥
2
1
Pavg = ⎜ − Cload
T ⎢⎜⎝ 2 ⎟⎠ ⎝ 2 ⎠ T /2 ⎥
⎣ 0 ⎦
1
Pavg = CloadVDD = CloadVDD f
2 2
T
Next Time: Combinational Logic
• Combinational MOS Logic
– DC Characteristics, Equivalent Inverter method
– AC Characteristics, Switch Model

EEC 118 Lecture #6:
CMOS Logic
Jeff Parkhurst
Intel Corporation
Announcements
• Quiz 1 today!
• Lab 2 reports due this week
• Lab 3 this week
2131

Outline
• Review: CMOS Inverter Transient Characteristics
• Review: Inverter Power Consumption
• Combinational MOS Logic Circuits: Rabaey 6.1-
6.2 (Kang & Leblebici, 7.1-7.4)
• Combinational MOS Logic Transient Response
– AC Characteristics, Switch Model

Review: Logic Circuit Delay
• For CMOS (or almost all logic circuit families), only
one fundamental equation necessary to determine
delay:
dV
I =C
dt
ΔV
• Consider the discretized version: I =C
Δt
ΔV
• Rewrite to solve for delay: Δt = C
I
• Only three ways to make faster logic: C, ΔV, I

Review: Inverter Delays
• High-to-low and low-to-high transitions (exact):
CL ⎡ 2VT 0,n ⎛ 4(VOH − VT 0,n ) ⎞⎤
t PHL = ⎢ + ln⎜⎜ − 1⎟⎟⎥
k n (VOH − VT 0,n ) ⎣VOH − VT 0,n ⎝ VOH + VOL ⎠⎦
CL ⎡ 2 VT 0, p ⎛ 4(VOH − VOL − VT 0, p ) ⎞⎤
t PLH = ⎢ + ln⎜ − 1⎟⎥
k p (VOH − VOL − VT 0, p ) ⎣⎢VOH − VOL − VT 0, p ⎜ V + V ⎟⎥
⎝ OH OL ⎠⎦
• Similar exact method to find rise and fall times
• Note: to balance rise and fall delays (assuming VOH =
VDD, VOL = 0V, and VT0,n=VT0,p) requires
kp ⎛W ⎞ ⎛W ⎞ μn
=1 ⎜ ⎟ ⎜ ⎟ = ≈ 2.5
kn ⎝ L ⎠p ⎝ L ⎠n μ p
Review: Inverter Power Consumption
• Static power consumption (ideal) = 0
– Actually DIBL (Drain-Induced Barrier Lowering),
gate leakage, junction leakage are still present
• Dynamic power consumption
T
1
Pavg = ∫ v(t )i(t )dt
T0
1⎡ dVout ⎞ ⎤
T /2
⎛ dVout ⎞ ⎛
T
Pavg = ⎢ ∫ Vout ⎜ − Cload ⎟dt + ∫ (VDD − Vout )⎜ Cload ⎟dt ⎥
T⎣0 ⎝ dt ⎠ T /2 ⎝ dt ⎠ ⎦
⎡ T /2 T ⎤
1 ⎢⎛ Vout ⎞
2
⎟ + ⎛⎜VDDVout Cload − CloadVout 2 ⎞⎟ ⎥
1
Pavg = ⎜ − Cload
T ⎢⎜⎝ 2 ⎟⎠ ⎝ 2 ⎠ T /2 ⎥
⎣ 0 ⎦
1
Pavg = CloadVDD = CloadVDD f
2 2
T
Static CMOS
• Complementary pullup
network (PUN) and pulldown
network (PDN)
• Only one network is on at a A
time B PUN
C
• PUN: PMOS devices
F
– Why? A
• PDN: NMOS devices B PDN
C
– Why?
• PUN and PDN are dual
networks

Dual Networks
• Dual networks: parallel Example: NAND gate
connection in PDN = series
connection in PUN, vice- parallel
versa
A F
• If CMOS gate implements
B
logic function F:
series
– PUN implements function F
– PDN implements function G
=F

NAND Gate
• NAND function: F = A•B
• PUN function: F = A•B = A + B

– “Or” function (+) → parallel connection
– Inverted inputs A, B → PMOS transistors
• PDN function: G = F = A•B

– “And” function (•) → series connection
– Non-inverted inputs → NMOS transistors

NOR Gate
• NOR gate operation: F = A+B
A
• PUN: F = A+B = A•B
B
• PDN: G = F = A+B A B

Analysis of CMOS Gates
• Represent “on” transistors as resistors
1 1 W R
W R
1 W R
• Transistors in series → resistances in series

• Effective resistance = 2R
• Effective length = 2L

Analysis of CMOS Gates (cont.)
W W R R
W R
0 0
0
• Transistors in parallel → resistances in parallel

• Effective resistance = ½ R
• Effective width = 2W

CMOS Gates: Equivalent Inverter
• Represent complex gate as inverter for delay
estimation
• Typically use worst-case delays
• Example: NAND gate
– Worst-case (slowest) pull-up: only 1 PMOS “on”
– Pull-down: both NMOS “on”
WP WP WP
WN ½ WN
WN

Example: Complex Gate
Design CMOS gate for this truth table:
A B C F
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 0
F = A•(B+C)
Design CMOS gate for this logic function:
F = A•(B+C) = A + B•C
1. Find NMOS pulldown network diagram:

G = F = A•(B+C)
B C
Not a unique solution: can exchange order of

series connection
2. Find PMOS pullup network diagram: F = A+(B•C)
B
A
C
F
Not a unique solution: can exchange order of

series connection (B and C inputs)
Completed gate: • What is worse-case pullup delay?
B WP
A WP • What is worse-case pulldown delay?
C WP
F • Effective inverter for delay calculation:
A WN
B C WN ½ WP
WN
½ WN

CMOS Gate Design
• Designing a CMOS gate:
– Find pulldown NMOS network from logic function
or by inspection
– Find pullup PMOS network
• By inspection
• Using logic function
• Using dual network approach
– Size transistors using equivalent inverter
• Find worst-case pullup and pulldown paths
• Size to meet rise/fall or threshold requirements

Analysis of CMOS gates
1 1 W R
W R
1 W R
• Transistors in series → resistances in series

• Effective resistance = 2R
• Effective width = ½ W (equivalent to 2L)
• Typically use minimum length devices (L = Lmin)

Analysis of CMOS Gates (cont.)
W W R R
W R
0 0
0
• Transistors in parallel → resistances in parallel

• Effective resistance = ½ R
• Effective width = 2W
• Typically use minimum length devices (L = Lmin)

Equivalent Inverter
• CMOS gates: many paths to Vdd and Gnd
– Multiple values for VM, VIL, VIH, etc
– Different delays for each input combination
• Equivalent inverter
– Represent each gate as an inverter with
appropriate device width
– Include only transistors which are on or switching
– Calculate VM, delays, etc using inverter equations

Static CMOS Logic Characteristics
• For VM, the VM of the equivalent inverter is used
(assumes all inputs are tied together)
– For specific input patterns, VM will be different
• For VIL and VIH, only the worst case is interesting
since circuits must be designed for worst-case
noise margin
• For delays, both the maximum and minimum
must be accounted for in race analysis

Equivalent Inverter: VM
• Example: NAND gate threshold VM
Three possibilities:
– A & B switch together
– A switches alone
– B switches alone
• What is equivalent inverter for each case?

Equivalent Inverter: Delay
estimation
• Use worse-case delays
– Worse-case (slowest) pull-up: only 1 PMOS “on”
WP WP WP
WN ½ WN
WN

Example: NOR gate
• Find threshold voltage VTH when
both inputs switch
simultaneously
• Two methods:
A WP
– Transistor equations (complex)
B WP
F – Equivalent inverter
A WN – Should get same answer

B
WN

Completed gate: • What is worse-case pullup delay?
B WP
A WP • What is worse-case pulldown delay?
C WP
F • Effective inverter for delay calculation:
A WN
B WNC WN ½ WP
½ WN

Transistor Sizing
• Sizing for switching threshold
– All inputs switch together
• Sizing for delay

– Find worst-case input combination
• Find equivalent inverter, use inverter analysis to

set device sizes

Common CMOS Gate Topologies
• And-Or-Invert (AOI)
– Sum of products boolean function
– Parallel branches of series connected NMOS
• Or-And-Invert (OAI)
– Product of sums boolean function
– Series connection of sets of parallel NMOS

Graph-Based Dual Network
• Use graph theory to help design gates
– Mostly implemented in CAD tools
• Draw network for PUN or PDN
– Circuit nodes are vertices
– Transistors are edges
F
F
A B
A B
gnd

Graph-Based Dual Network (2)
• To derive dual network:

– Create new node in each enclosed region of graph
– Draw new edge intersecting each original edge
– Edge is controlled by inverted input
F
A n1 B A
vdd F n1
A B B
F
gnd
– Convert to layout using consistent Euler paths
Propagation Delay Analysis - The Switch Model
RON
=
VDD VDD
VDD
Rp Rp Rp
Rp
A B B
A F
Rn Rp
F CL
B A
Rn
CL F
Rn Rn Rn
A CL
A B
A
(a) Inverter (b) 2-input NAND (c) 2-input NOR
tp = 0.69 Ron CL
(assuming that CL dominates!)

Switch Level Model
• Model transistors as switches with
series resistance
• Resistance Ron = average resistance
for a transition RP
A
• Capacitance CL = average load
capacitance for a transition (same as
we analyzed for transient inverter RN CL
delays) A

What is the Value of Ron?

Switch Level Model Delays
Delay estimation using switch-level
model (for general RC circuit):
dV C
I =C → dt = dV
RN CL dt I
V RC
I= → dt = dV
R V
V1
RC
t1 − t0 = t p = ∫ dV
V0
V
⎛ V1 ⎞
t p = RC [ln(V1 ) − ln(V0 )] = RC ln⎜⎜ ⎟⎟
⎝ V0 ⎠
Switch Level Model RC Delays
• For fall delay tphl, V0=VDD, V1=VDD/2
⎛ V1 ⎞ ⎛ 12 VDD ⎞
t p = RC ln⎜⎜ ⎟⎟ = RC ln⎜⎜ ⎟⎟
⎝ V0 ⎠ ⎝ VDD ⎠
t p = RC ln(0.5)
t phl = 0.69 RnC L Standard RC-delay
equations from literature
t plh = 0.69 R p C L

Numerical Examples
• Example resistances for 1.2 μm CMOS

Analysis of Propagation Delay
VDD 1. Assume Rn =Rp = resistance of minimum
Rp Rp sized NMOS inverter
A B 2. Determine “Worst Case Input” transition

F (Delay depends on input values)
Rn
CL 3. Example: tpLH for 2input NAND
B - Worst case when only ONE PMOS Pulls
up the output node
Rn
- For 2 PMOS devices in parallel, the
A
resistance is lower
tpLH = 0.69Rp CL
2-input NAND 4. Example: tpHL for 2input NAND
- Worst case : TWO NMOS in series
tpHL = 0.69(2Rn)CL
Design for Worst Case
V DD
VDD
1 1 B 4
A A 2
B
F C 4
2 CL
B D 2
F
2 A 2
D 1
A
B 2C 2
NAND Gate Complex Gate
Here it is assumed that Rp = Rn

Fan-In and Fan-Out
V
DD Fan-Out
Number of logic gates
A B C D connected to output
(2 FET gate capacitances
per fan-out)
A
Fan-In
B Number of logical inputs
Quadratic delay term due to:
C 1. Resistance increasing
2. Capacitance increasing
D
for tpHL (series NMOS)
tp proportional to a1FI + a2FI2 + a3FO

Fast Complex Gates - Design Techniques
• Increase Transistor Sizing:
Works as long as Fan-out capacitance
dominates self capacitance (S/D cap increases
with increased width)
• Progressive Sizing:
Out
InN MN CL
M 1 > M 2 > M 3 > MN
In3 C3
M3
Distributed RC-line
In2 M2 C2
Can Reduce Delay by more

In1 M1 C1 than 30%!
Fast Complex Gates - Design Techniques (2)
• Transistor Ordering
Place last arriving input closest to output node
critical path critical path
CL CL
In3 M3 In1 M1
In2 M2 C2 C2
In2 M2
In1 M1 C1 C3
In3 M3
(a) (b)
• Improved Logic Design
Note Fan-Out capacitance is the same, but Fan-In

resistance lower for input gates (fewer series FETs)

• Buffering: Isolate Fan-in from Fan-out
CL CL
Keeps high fan-in resistance isolated from large

capacitive load CL
4 Input NAND Gate
VDD VDD
In1 In2 In3 In4

Out
In1
In2
Out
In3
In4
GND
In1 In2 In3 In4

Capacitances in a 4 input NAND Gate
VDD
Cgs5 Cgs6 Csb6 Cgs7

Csb5 Csb7 Cgs8 Csb8
In1 In2 In3 In4
Cgd5 Cgd6 Cdb6 Cgd7
Cdb5 Cdb Cgd8
7 Cdb8
Vout
Cgd Cdb1
In1 1 Note that the value of Cload for calculating
Cgs1 Csb1 propagation delay depends on which capacitances
2
Cgd Cdb2 need to be discharged or charged when the critical
In2 2 signal arrives.
Cgs2 Csb2
3 Example: In1 = In3 = In4 = 1. In2 = 0. In2 switches from low
Cgd Cdb3 to high. Hence, Nodes 3 and 4 are already discharged to
In3 3
ground. In order for Vout to go from high to low… Vout
Cgs3 Csb3
4 node and node 2 must be discharged.
Cgd Cdb4 CL =
In4 4 Cgd5+Cgd7+Cgd8+2Cgd6(Miller)+Cdb5+Cdb6+Cdb7+Cd
Cgs4 Csb4 b8 +Cgd1+ Cdb1+ Cgs1+ Csb1+ 2Cgd2+ Cdb2+ Cw

Next Topic: Sequential Logic
• Basic sequential circuits in CMOS
– RS latches, transparent latches, flip-flops
– Alternative sequential element topologies
– Pipelining

EEC 118 Lecture #7:
Designing with Logical Effort
Jeff Parkhurst
Intel Corporation
Announcements
• Lab 3 this week at lab section
2131
• Quizzes will be handed back in lab section

Outline
• Review: CMOS Combinational Gate Design
• Finish Lecture 6 slides
• Logical Effort
6.2 (Kang & Leblebici, 7.1-7.4)

Acknowledgments
• Slides due to David Money Harris from E158:
Introduction to CMOS VLSI Design at Harvey Mudd
College

Review: Static CMOS
network (PDN)
time B PUN
C
F
– Why? Pulls up to VDD. A
C
– Why? Pulls down to ground.
networks

Review: Dual Networks
versa
A F
B
logic function F:
series
=F

Lecture 6:
Logical
Effort
Outline
Logical Effort
Delay in a Logic Gate
Multistage Logic Networks
Choosing the Best Number of Stages
Example
Summary
Amirtharajah/Parkhurst, EEC 118 Spring 2011 CMOS VLSI Design 4th Ed. 8
Introduction
Chip designers face a bewildering array of choices
– What is the best circuit topology for a function?
– How many stages of logic give least delay?
???
– How wide should the transistors be?
Logical effort is a method to make these decisions

– Uses a simple model of delay
– Allows back-of-the-envelope calculations
– Helps make rapid comparisons between alternatives
– Emphasizes remarkable symmetries
Example
Ben Bitdiddle is the memory designer for the Motoroil 68W86,
an embedded automotive processor. Help Ben design the
A[3:0] A[3:0]
decoder for a register file. 32 bits
Decoder specifications:
4:16 Decoder
16 words
16
Register File
– 16 word register file
– Each word is 32 bits wide
– Each bit presents load of 3 unit-sized transistors
– True and complementary address inputs A[3:0]
– Each input may drive 10 unit-sized transistors
Ben needs to decide:
– How many stages to use?
– How large should each gate be?
– How fast can decoder operate?
Delay in a Logic Gate
Express delays in process-independent unit d = d abs
Delay has two components: d = f + p τ
τ = 3RC
f: effort delay = gh (a.k.a. stage effort)
≈ 3 ps in 65 nm process
– Again has two components 60 ps in 0.6 μm process
g: logical effort
– Measures relative ability of gate to deliver current
– g ≡ 1 for inverter
h: electrical effort = Cout / Cin
– Ratio of output to input capacitance
– Sometimes called fanout
p: parasitic (intrinsic) delay
– Represents delay of gate driving no load
– Set by internal parasitic capacitance
Delay Plots
d =f+p 2-input
= gh + p 6
NAND Inverter
g = 4/3
Normalized Delay: d
5 p=2
What about d = (4/3)h + 2
4 g=1
NOR2? p=1
3 d=h+1
2 Effort Delay: f
1
Parasitic Delay: p
0
0 1 2 3 4 5
Electrical Effort:
h = Cout / Cin
Computing Logical Effort
DEF: Logical effort is the ratio of the input
capacitance of a gate to the input capacitance of an
inverter delivering the same output current.
Measure from delay vs. fanout plots
Or estimate by counting transistor widths
2 2 A 4
Y
2 B 4
A 2
A Y Y
1 B 2 1 1
Cin = 3 Cin = 4 Cin = 5

g = 3/3 g = 4/3 g = 5/3
Catalog of Gates
Logical effort of common gates
Gate type Number of inputs

1 2 3 4 n
Inverter 1
NAND 4/3 5/3 6/3 (n+2)/3
NOR 5/3 7/3 9/3 (2n+1)/3
Tristate / mux 2 2 2 2 2
XOR, XNOR 4, 4 6, 12, 6 8, 16, 16, 8
Catalog of Gates
Parasitic delay of common gates
– In multiples of pinv (≈1)
Gate type Number of inputs
1 2 3 4 n
Inverter 1
NAND 2 3 4 n
NOR 2 3 4 n
Tristate / mux 2 4 6 8 2n
XOR, XNOR 4 6 8
Example: Ring Oscillator
Estimate the frequency of an N-stage ring oscillator
Logical Effort: g=1 31 stage ring oscillator in

0.6 μm process has
Electrical Effort: h=1 frequency of ~ 200 MHz
Parasitic Delay: p=1
Stage Delay: d=2
Frequency: fosc = 1/(2*N*d) = 1/4N
Example: FO4 Inverter
Estimate the delay of a fanout-of-4 (FO4) inverter
d
Logical Effort: g=1

Electrical Effort: h=4 The FO4 delay is about
Parasitic Delay: p=1 300 ps in 0.6 μm process
Stage Delay: d=5 15 ps in a 65 nm process
Logical effort generalizes to multistage networks
Path Logical Effort G= gi ∏
Cout-path
Path Electrical Effort H=
Cin-path
Path Effort F = ∏ f i = ∏ gi hi
10
x z
y
20
g1 = 1 g2 = 5/3 g3 = 4/3 g4 = 1
h1 = x/10 h2 = y/x h3 = z/y h4 = 20/z
Logical effort generalizes to multistage networks
Path Logical Effort G= gi ∏
Cout − path
Path Electrical Effort H=
Cin − path
Path Effort F = ∏ f i = ∏ gi hi
Can we write F = GH?
Paths that Branch
No! Consider paths that branch:
15
G =1 90
5
H = 90 / 5 = 18
GH = 18 15
90
h1 = (15 +15) / 5 = 6
h2 = 90 / 15 = 6
F = g1g2h1h2 = 36 = 2GH
Branching Effort
Introduce branching effort
– Accounts for branching between stages in path
Con path + Coff path
b=
Con path
B = ∏ bi
Note:
∏h i = BH
Now we compute the path effort
– F = GBH
Multistage Delays
Path Effort Delay DF = ∑ f i
Path Parasitic Delay P = ∑ pi
Path Delay D = ∑ d i = DF + P
Designing Fast Circuits
D = ∑ d i = DF + P
Delay is smallest when each stage bears same effort
1
fˆ = gi hi = F N
Thus minimum delay of N stage path is

1
D = NF + P N
This is a key result of logical effort

– Find fastest possible delay
– Doesn’t require calculating gate sizes
Gate Sizes
How wide should the gates be for least delay?
fˆ = gh = g CCoutin
gi Couti
⇒ Cini =
fˆ
Working backward, apply capacitance
transformation to find input capacitance of each gate
given load it drives.
Check work by verifying input cap spec is met.
Example: 3-stage path
Select gate sizes x and y for least delay from A to B
y
x
45
A 8
x
y B
45
x
y
x
45
A 8
x
y B
45
Logical Effort G = (4/3)*(5/3)*(5/3) = 100/27

Electrical Effort H = 45/8
Branching Effort B=3*2=6
Path Effort F = GBH = 125
Best Stage Effort fˆ = 3 F = 5
Parasitic Delay P=2+3+2=7
Delay D = 3*5 + 7 = 22 = 4.4 FO4
Work backward for sizes
y = 45 * (5/3) / 5 = 15
x = (15*2) * (5/3) / 5 = 10
y
x
45
45
A P:
84 P:
x 4
N: 4 P:
y 12 B
N: 6 45
N: 3 45
Best Number of Stages
How many stages should a path use?
– Minimizing number of stages is not always fastest
Example: drive 64-bit datapath with unit inverter
Initial Driver 1 1 1 1
8 4 2.8
D = NF1/N + P 16 8
= N(64)1/N + N
23
Datapath Load 64 64 64 64
N: 1 2 3 4
f: 64 8 4 2.8
D: 65 18 15 15.3
Fastest
Derivation
Consider adding inverters to end of path
– How many give least delay? N - n1 ExtraInverters
Logic Block:
n1 n1Stages
D = NF + ∑ pi + ( N − n1 ) pinv
1
N Path Effort F
i =1
∂D 1 1 1
= − F N ln F N + F N + pinv = 0
∂N
ρ=F
1
Define best stage effort N
pinv + ρ (1 − ln ρ ) = 0
Best Stage Effort
pinv + ρ (1 − ln ρ ) = 0 has no closed-form solution
Neglecting parasitics (pinv = 0), we find ρ = 2.718 (e)

For pinv = 1, solve numerically for ρ = 3.59
Sensitivity Analysis
How sensitive is delay to using exactly the best
number of stages? 1.6
1.51
D(N) /D(N)
1.4
1.26
1.2 1.15
1.0
(ρ=6) (ρ =2.4)
0.0
0.5 0.7 1.0 1.4 2.0
N/ N
2.4 < ρ < 6 gives delay within 15% of optimal

– We can be sloppy!
– I like ρ = 4
Example, Revisited
Ben Bitdiddle is the memory designer for the Motoroil 68W86,
an embedded automotive processor. Help Ben design the
A[3:0] A[3:0]
decoder for a register file. 32 bits
Decoder specifications:
4:16 Decoder
16 words
16
Register File
– 16 word register file
– Each word is 32 bits wide
– Each bit presents load of 3 unit-sized transistors
– True and complementary address inputs A[3:0]
– Each input may drive 10 unit-sized transistors
Ben needs to decide:
– How many stages to use?
– How large should each gate be?
– How fast can decoder operate?
Number of Stages
Decoder effort is mainly electrical and branching
Electrical Effort: H = (32*3) / 10 = 9.6
Branching Effort: B=8
If we neglect logical effort (assume G = 1)

Path Effort: F = GBH = 76.8
Number of Stages: N = log4F = 3.1
Try a 3-stage design
Gate Sizes & Delay
Logical Effort: G = 1 * 6/3 * 1 = 2
Path Effort: F = GBH = 154
Stage Effort: fˆ = F 1/ 3 = 5.36
Path Delay: D = 3 fˆ + 1 + 4 + 1 = 22.1
Gate sizes: z = 96*1/5.36 = 18 y = 18*2/5.36 = 6.7
A[3] A[3] A[2] A[2] A[1] A[1] A[0] A[0]
10 10 10 10 10 10 10 10
y z word[0]
96 units of wordline capacitance
y z word[15]
Comparison
Compare many alternatives with a spreadsheet
D = N(76.8 G)1/N + P
Design N G P D
NOR4 1 3 4 234
NAND4-INV 2 2 5 29.8
NAND2-NOR2 2 20/9 4 30.1
INV-NAND4-INV 3 2 6 22.1
NAND4-INV-INV-INV 4 2 7 21.1
NAND2-NOR2-INV-INV 4 20/9 6 20.5
NAND2-INV-NAND2-INV 4 16/9 6 19.7
INV-NAND2-INV-NAND2-INV 5 16/9 7 20.4
NAND2-INV-NAND2-INV-INV-INV 6 16/9 8 21.6
Review of Definitions
Term Stage Path
number of stages 1 N
logical effort g G = ∏ gi
H=
Cout-path
electrical effort h= Cout
Cin Cin-path
Con-path + Coff-path
branching effort b= Con-path B = ∏ bi
effort f = gh F = GBH
effort delay f DF = ∑ f i
parasitic delay p P = ∑ pi
delay d= f +p D = ∑ d i = DF + P
Method of Logical Effort
1) Compute path effort F = GBH
2) Estimate best number of stages N = log 4 F
3) Sketch path with N stages
1
4) Estimate least delay D = NF + P N
5) Determine best stage effort ˆf = F N1
gi Couti
6) Find gate sizes Cini =
fˆ
Limits of Logical Effort
Chicken and egg problem
– Need path to compute G
– But don’t know number of stages without G
Simplistic delay model
– Neglects input rise time effects
Interconnect
– Iteration required in designs with wire
Maximum speed only
– Not minimum area/power for constrained delay
Summary
Logical effort is useful for thinking of delay in circuits
– Numeric logical effort characterizes gates
– NANDs are faster than NORs in CMOS
– Paths are fastest when effort delays are ~4
– Path delay is weakly sensitive to stages, sizes
– But using fewer stages doesn’t mean faster paths
– Delay of path is about log4F FO4 inverter delays
– Inverters and NAND2 best for driving large caps
Provides language for discussing fast circuits
– But requires practice to master
– Pipelining

EEC 118 Lecture #8:
CMOS Logic Transient
Characteristics
Jeff Parkhurst
Intel Corporation
Announcements
• Quiz 2 on Monday, April 26
• Midterm on Monday, May 3
– Covers material through Lecture (Monday 4/26)
• HW4 due Friday, 4PM in box, Kemper 2131
• Lab 3, Part 2 report due next week

Outline
• Review: Static CMOS Logic
• Finish equivalent inverter discussion
6.2, 7.1-7.3 (Kang & Leblebici, 7.1-7.4)

Review: Static CMOS
network (PDN)
time B PUN
C
F
– Why? VOH = VDD A
C
– Why? VOL = 0 V
networks

Review: Dual Networks
versa
A F
B
logic function F:
series
=F

Review: Equivalent Inverter
estimation, VTC analysis
• Use worse-case conditions for delays
– Worse-case (slowest) pull-up: only 1 PMOS “on”
WP WP WP
WN ½ WN
WN

Graph-Based Dual Network
• Use graph theory to help design gates
– Mostly implemented in CAD tools
• Draw network for PUN or PDN
– Circuit nodes are vertices
– Transistors are edges
F
F
A B
A B
gnd

Graph-Based Dual Network (2)
• To derive dual network:

– Create new node in each enclosed region of graph
– Draw new edge intersecting each original edge
– Edge is controlled by inverted input
A B A
A B B
F

Propagation Delay Analysis - The Switch Model
RON
=
VDD VDD
VDD
Rp Rp Rp
Rp
A B B
A F
Rn Rp
F CL
B A
Rn
CL F
Rn Rn Rn
A CL
A B
A
(a) Inverter (b) 2-input NAND (c) 2-input NOR
tp = 0.69 Ron CL
(assuming that CL dominates!)

Switch Level Model
• Model transistors as switches with
series resistance
• Resistance Ron = average resistance
for a transition RP
A
• Capacitance CL = average load
capacitance for a transition (same as
we analyzed for transient inverter RN CL
delays) A

What is the Value of Ron?

Switch Level Model Delays
Delay estimation using switch-level
model (for general RC circuit):
dV C
I =C → dt = dV
RN CL dt I
V RC
I= → dt = dV
R V
V1
RC
t1 − t0 = t p = ∫ dV
V0
V
⎛ V1 ⎞
t p = RC [ln(V1 ) − ln(V0 )] = RC ln⎜⎜ ⎟⎟
⎝ V0 ⎠
Switch Level Model RC Delays
• For fall delay tphl, V0=VDD, V1=VDD/2
⎛ V1 ⎞ ⎛ 12 VDD ⎞
t p = RC ln⎜⎜ ⎟⎟ = RC ln⎜⎜ ⎟⎟
⎝ V0 ⎠ ⎝ VDD ⎠
t p = RC ln(0.5)
t phl = 0.69 RnC L Standard RC-delay
t plh = 0.69 R p C L equations from literature

Numerical Examples
• Example resistances for 1.2 μm CMOS

Analysis of Propagation Delay
VDD 1. Assume Rn =Rp = resistance of minimum
Rp Rp sized NMOS inverter
A B 2. Determine “Worst Case Input” transition

F (Delay depends on input values)
Rn
CL 3. Example: tpLH for 2input NAND
B - Worst case when only ONE PMOS Pulls
up the output node
Rn
- For 2 PMOS devices in parallel, the
A
resistance is lower
tpLH = 0.69Rp CL
2-input NAND 4. Example: tpHL for 2input NAND
- Worst case : TWO NMOS in series
tpHL = 0.69(2Rn)CL
Design for Worst Case
V DD
VDD
1 1 B 4
A A 2
B
F C 4
2 CL
B D 2
F
2 A 2
D 1
A
B 2C 2
NAND Gate Complex Gate
Here it is assumed that Rp = Rn

Fan-In and Fan-Out
V
DD Fan-Out
Number of logic gates
A B C D connected to output
(2 FET gate capacitances
per fan-out)
A
Fan-In
B Number of logical inputs
Quadratic delay term due to:
C 1. Resistance increasing
2. Capacitance increasing
D
for tpHL (series NMOS)
tp proportional to a1FI + a2FI2 + a3FO

Fast Complex Gates - Design Techniques
• Increase Transistor Sizing:
Works as long as Fan-out capacitance
dominates self capacitance (S/D cap increases
with increased width)
• Progressive Sizing:
Out
InN MN CL
M 1 > M 2 > M 3 > MN
In3 C3
M3
Distributed RC-line
In2 M2 C2
Can Reduce Delay by more

In1 M1 C1 than 30%!
• Transistor Ordering
Place last arriving input closest to output node
critical path critical path
CL CL
In3 M3 In1 M1
In2 M2 C2 C2
In2 M2
In1 M1 C1 C3
In3 M3
(a) (b)
• Improved Logic Design
Note Fan-Out capacitance is the same, but Fan-In

resistance lower for input gates (fewer series FETs)

• Buffering: Isolate Fan-in from Fan-out
CL CL
Keeps high fan-in resistance isolated from large

capacitive load CL
4 Input NAND Gate
VDD VDD
In1 In2 In3 In4

Out
In1
In2
Out
In3
In4
GND
In1 In2 In3 In4

Capacitances in a 4 input NAND Gate
VDD
Cgs5 Cgs6 Csb6 Cgs7

Csb5 Csb7 Cgs8 Csb8
In1 In2 In3 In4
Cgd5 Cgd6 Cdb6 Cgd7
Cdb5 Cdb Cgd8
7 Cdb8
Vout
Cgd Cdb1
In1 1 Note that the value of Cload for calculating
Cgs1 Csb1 propagation delay depends on which capacitances
2
Cgd Cdb2 need to be discharged or charged when the critical
In2 2 signal arrives.
Cgs2 Csb2
3 Example: In1 = In3 = In4 = 1. In2 = 0. In2 switches from low
Cgd Cdb3 to high. Hence, Nodes 3 and 4 are already discharged to
In3 3
ground. In order for Vout to go from high to low… Vout
Cgs3 Csb3
4 node and node 2 must be discharged.
Cgd Cdb4 CL =
In4 4 Cgd5+Cgd7+Cgd8+2Cgd6(Miller)+Cdb5+Cdb6+Cdb7+Cd
Cgs4 Csb4 b8 +Cgd1+ Cdb1+ Cgs1+ Csb1+ 2Cgd2+ Cdb2+ Cw

– Pipelining

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EEC 116 Lecture #3:

Amirtharajah, EEC 116 Fall 2011 3

Vin Inverter Vout

Ideal digital inverter:

Vout • VOL = output voltage when

Amirtharajah, EEC 116 Fall 2011 5

• In transfer function terms:

VOH – VOH = f(VOL)

Amirtharajah, EEC 116 Fall 2011 6

Vout – Represents the point at

Amirtharajah, EEC 116 Fall 2011 7

Amirtharajah, EEC 116 Fall 2011 8

Vout = VDS Vdd 0 1 2 Vin 3 4

• Output goes completely to Vdd and Gnd

Amirtharajah, EEC 116 Fall 2011 12

Amirtharajah, EEC 116 Fall 2011 13

kp=0.2kn • For VM = VDD/2

Amirtharajah, EEC 116 Fall 2011 14

Amirtharajah, EEC 116 Fall 2011 15

kn (VIL −VT 0,n ) = k p (2Vout −VIL +VT 0, p −VDD )

2Vout + VT 0, p − VDD + k RVT 0,n kn

(VGS ,n − VT 0,n ) = (VGS , p − VT 0, p )2

• Assuming VT0,n = VT0,p, k R ,ideal =1

• Assuming VT0,n=-VT0,p, and kR = 1,

NM L = VIL − VOL = VIL

NM H = VOH − VIH = VDD − VIH = VIL

• Rabaey Section 3.5 (Kang & Leblebici Section 3.5)

Amirtharajah, EEC 116 Fall 2011 22

Amirtharajah, EEC 116 Fall 2011 23

source Ldrawn drain

– xd is overlap length on each side of channel

– CGS = CGD = CoxWxd

– Total Gate Capacitance = CG = CoxWL

Amirtharajah, EEC 116 Fall 2011 25

Amirtharajah, EEC 116 Fall 2011 27

Reverse-biased P-N junctions!

Amirtharajah, EEC 116 Fall 2011 28

m = grading coefficient (0.5 for abrupt junctions)

Amirtharajah, EEC 116 Fall 2011 30

Ceq = ⎜⎜1 − ⎟⎟ − ⎜⎜1 − ⎟⎟ = AK eq C j 0

Cdb = AK eq C j 0 + PX j K eqswC jsw0

Amirtharajah, EEC 116 Fall 2011 31

• Find capacitance of drain-bulk junction when

Amirtharajah, EEC 116 Fall 2011 32

– AC Characteristics: Designing for speed

Amirtharajah, EEC 116 Fall 2011 33

Amirtharajah/Parkhurst, EEC 118 Spring 2011 2

Amirtharajah/Parkhurst, EEC 118 Spring 2011 3

Vin Inverter Vout

Ideal digital inverter:

Vout • VOL = output voltage when

Amirtharajah/Parkhurst, EEC 118 Spring 2011 5

• In transfer function terms:

VOH – VOH = f(VOL)

Amirtharajah/Parkhurst, EEC 118 Spring 2011 6

Vout – Represents the point at

Amirtharajah/Parkhurst, EEC 118 Spring 2011 7

Amirtharajah/Parkhurst, EEC 118 Spring 2011 8

Vout = VDS Vdd 0 1 2 Vin 3 4

• Output goes completely to Vdd and Gnd

Cload = 2Cgd,n + 2Cgd,p + Cdb,n + Cdb,p + Cint