Built-in Self-Test (BIST)

• Introduction
• Test Pattern Generation
• Test Response Analysis
• BIST Architectures
• Scan-Based BIST

Built-in self test.1

 Built-in Self-Test (BIST)
• Capability of a circuit to test itself
• On-line:
– Concurrent : simultaneous with normal
operation
– Nonconcurrent : idle during normal operation
• Off-line:
– Functional : diagnostic S/W or F/W
– Structural : LFSR-based
• We deal primarily with structural off-line testing
here.

Built-in self test.2

 Basic Architecture of BIST

TPG

Circuit Under Test

(CUT)

ORA

• TPG: Test pattern generator

• ORA Output response analyzer
Built-in self test.3
 Glossary of BIST

• TPG - Test pattern generator

• PRPG - pseudorandom pattern generator
(Pseudorandom number generator)
• SRSG – Shift register sequence generator (a
single output PRPG)
• ORA – Output response analyzer
• SISR – Single-input signature register
• MISR – Multiple-input signature register
• BILBO – Built-in logic block observer

Built-in self test.4

 Built-in Self Testing

• Test pattern generation

– Exhaustive
– Pseudoexhaustive
– Pseudorandom
• Test response compression
– One’s count
– Transition count
– Parity checking
– Syndrome checking
– Signature analysis

Built-in self test.5

 Test Pattern Generation for BIST

• Exhaustive testing
• Pseudorandom testing
– Weighted and Adaptive TG
• Pseudoexhaustive testing
– Syndrome driver counter
– Constant-weight counter
– Combined LFSR and shift register
– Combined LFSR and XOR
– Cyclic LFSR

Built-in self test.6

 Exhaustive Testing

• Apply all 2n input vectors, where n = # inputs to

CUT
• Impractical for large n
• Detect all detectable faults that does not cause
sequential behavior
• In general not applicable to sequential circuits
• Can use a counter or a LFSR for pattern
generator

Built-in self test.7

 Linear Feedback Shift Register
(LFSR)
• Example

Z
Z
F/F F/F 0 1 1
S1 0 0 1
S1 1 0
S2 1 0 0
S2 0 1
S3 0 1 0
S1 1 0
S4 1 0 1
:
S5 1 1 0
S6 1 1 1
S7 = S0 0 1 1
:
Z=0101… Z=1100101…
2 states 7 states
Built-in self test.8
 Two Types of LFSRs

• Type 1: External type

C 1 C2 C n-1 C n = 1

D Q

• Type 2: Internal type

Cn =1 Cn-1 Cn-2 C 1

D Q
Q1 Q2 Qn
Built-in self test.9
Mathematical Operations over GF(2)
• Multiplication (• ) • 0 1
0 0 0
• Addition ( ⊕ or simply +) 1 0 1

⊕ 0 1
0 0 1
1 1 0

Example:

= 

 = 

 =
 −
= 
 −  = 
 −  = 

if   =  −  •
 +  −  •
 +  −
•


then


=
+  +  =

Built-in self test.10
Analysis of LFSR using Polynomial
Representation

• A sequence of binary numbers can be

represented using a generation function
(polynomial)
• The behavior of an LFSR is determined by its
initial “seed” and its feedback coefficients, both
can be represented by polynomials.

Built-in self test.11

 Characteristic Polynomials

•








 : sequence of binary

numbers.

∞
 
 = 
+ 
+ 
+


+ 

+


= ∑ 


• Generating function : 

=

 Let 

 =









be output sequence of an LFSR of type1


= ∑    
− 
 =

Built-in self test.12

 • Let initial state be
− 

− 


−

∞ ∞ 
 

= ∑

 = ∑ ∑  
−  

=

=
 =
 ∞
= ∑ 
 ∑  
−  

− 


 =
=

 ∞
= ∑ 
  −  
− +  +  −  
− + ∑ 




 =
=

∑ 


  −  
−
+  +  −

−




=  =



 + ∑


∴  

 =

depends on initial state and feedback
coefficients
Built-in self test.13
 Denominator
    =  +

 +

  +  +




is called the characteristic polynomial of the
LFSR

Example:


3 2 1 0

  = +  +   

Built-in self test.14

 LFSR Theory

• Definition: If period p of sequence generated by an

LFSR is  −  , then it is a maximum length

sequence
• Definition: The characteristic polynomial associated
with a maximum length sequence is a primitive
polynomial
• Theorem: # of primitive polynomials for an n-stage
LFSR is given by
λ     = φ    −   
where 
φ   =  ∏
 

 −


Built-in self test.15
 Primitive Polynomial
• # primitive polynomials of degree n N λ



1 1
2 1
4 2
8 16
16 2048
• Some primitive polynomials 32 67108864

1: 0 13: 4 3 1 0 25: 3 0
2: 1 0 14: 12 11 1 0 26: 8 7 1 0
3: 1 0 15: 1 0 27: 8 7 1 0
4: 1 0 16: 5 3 2 0 28: 3 0
5: 2 0 17: 3 0 29: 2 0
6: 1 0 18: 7 0 30: 16 15 1 0
7: 1 0 19: 6 5 1 0 31: 3 0
8: 6 5 1 0 20: 3 0 32: 28 27 1 0
9: 4 0 21: 2 0 33: 13 0
10: 3 0 22: 1 0 34: 15 14 1 0
11: 2 0 23: 5 0 35: 2 0
12: 7 4 3 0 24: 4 3 1 0 36: 11 0
Built-in self test.16
 Primitive Polynomial (Cont.)
• Characteristic of maximum-length sequence:
– Pseudorandom though deterministic and
periodic
– # 1’s = # 0’s + 1

Can be used as a (pseudo)-random or exhaustive

number generator.

Built-in self test.17

 LFSR Example






 1
0
0
0
0
0
0
1
0 0 1 1
0 1 1 1
3 2 1 0 1 1 1 1
1 1 1 0
1 1 0 1
1 0 1 0
0 1 0 1
1 0 1 1
0 1 1 0

  = +  + 
  1 1 0 0
1 0 0 1
0 0 1 0
0 1 0 0
1 0 0 0 (repeat)

• 
−
=
 “near” complete patterns are generated

Built-in self test.18

 LFSR Example (Cont.)

• To generate 2n patterns using LFSR



 3 2 1 0

• Sequence becomes:
 

 

…

Built-in self test.19
 What to Do if 2n is too Large?

• Using “pseudorandom”
e.g. generate 232 pattern only

• Partitioning   

Circuit
under
test (CUT)

• Using pseudo-exhaustive

Built-in self test.20

 Constant Weight Patterns
(for pseudoexhaustive testing)

• T, set of binary n-tuples, exhaustively covers all

k-subspaces if for all subsets of k bits positions,
each of the 2k binary patterns appears at least
once in T, where
• Example:
 ≤

    
   = 




=  


   = 
 


  = 

T can be a pseudoexhaustive test for a (n,w)-CUT

if  ≥

Built-in self test.21
 Constant Weight Patterns (Cont.)

• A binary n-tuple has weight k if it contains exactly

k 1’s
There are

binary n-tuples having weight k.

• Theorem: Given n and k, T exhausitvely covers all

binary k-subspaces if it contains all binary n-
tuples of weight(s) w such that w=c mod (n-k+1)
for some integer c, where
≤  ≤
− 

≤≤

Built-in self test.22

 Compression Techniques

• Bit-by-bit comparison is inefficient

• Compress information into “signature”
Response compacting or compressing

Input Output
test Circuit response Signature
Data S( R’)
sequence T under sequence R’
Compression
test
unit
(CUT)
Error
indicator
Comparator
Correct Signature S( R0 )

Built-in self test.23

Compression Techniques to be
Discussed

• Ones Count
• Transition Count
• Parity Checking
• Syndrome Checking
• Signature Analysis

Built-in self test.24

 Practical Compression Techniques
• Easy to implement, part of BIST logic
• Small performance degradation
• High degree of compaction
• No or small aliasing errors
• Problems:
1. Aliasing error:
signature (faulty ckt) = signature (fault-free ckt)
2. Reference (good) signature calculation:
!Simulation
!Golden unit
!Fault tolerant

Built-in self test.25

 Ones-count Compression

• C: single-output circuit
• R: output response  =








• 1C(R) = # ones in  =

∑

s-a-0 fault f2
x1 11110000
11001100 10000000 = R2
x2 11000000 = R1 Signature (ones count)

Counter
10000000 = R0
z
x3
10101010  

 = 
Raw output
 
 = 
Input test
s-a-1 fault f1
test response  
  =

pattern
sequence T

Built-in self test.26

 Transition-count Compression


  
= ∑
=


 ⊕
 +

Signature
10000000 = R2 (transition count)

Counter
11000000 = R1
T Network 10000000 = R0  
  = 
D Q
 
  = 
 

 =



−
−

•     =

−

• Does not guarantee the detection of single-bit
errors
 − 
• Prob. (single-bit error masked) =  
−
• Prob. (masking error) π  

Built-in self test.27
 Parity-check Compression
Signature
00000000 = R2
11000000 = R1 (parity)
10000000 = R0
D Q
T Network   =

  = 
Clock   
 = 

• Detect all single bit errors

• All errors consisting of odd number of bit errors
are detected
• All errors consisting of even number of bit errors
are masked
• Prob. (error masked) ≈


Built-in self test.28
 Syndrome Checking

• Apply random patterns.

• Count the probability of 1.
• The property is similar to that of ones count.

random
test CUT
pattern

Clock Syndrome counter

Counter /
Syndrome

Built-in self test.29

 Signature Analysis
• Based on linear feedback shift register (LFSR)
• A linear ckt. composed of
! unit delay or D FFs
! Modulo-2 scalar multipliers or adders

+/- 0 1 * 0 1
0 0 1 0 0 0
1 1 0 1 0 1
• Linear ckt.:
Response of linear combination of inputs
= Linear combination of responses of individual
inputs

+


=

+



Built-in self test.30
 Use LFSR as Signature Analyzer
• Single-input LFSR

… …


⊕ Internal Type LFSR

• Initial state
=

• Final state 






=

+ or 
= 

+ 







: The remainder, or the signature
Built-in self test.31
 Signature Analyzer (SA)

Input sequence:


1 1 1 1 0 1 0 1 (8 bits)
( ) =  +  +  +   +   + 1 ( ) = 1 +   +   + 
Time Input stream Register contents Output stream

12345
0 10101111 00000 Initial state
1 1010111 10000
: : :
5 101 01111
6 10 00010 1
7 1 00001 01
8 Remainder 00101 101
Quotient
Remainder  (  ) =  + 
() = 1+ 
Built-in self test.32
Signature Analyzer (SA) (Cont.)

+
+
+

×


+

=  +  +  + 


 +
 =
+
+
+
+

+
=


Built-in self test.33

 Multiple-input Signature Register
(MISR)
D 1 D 2 D 3 D n

D Q

Cn Cn-1 Cn-2 C 1

• Implementation: Original Modified

N N

R R*

Built-in self test.34

 Storage Cell of a SA

… ⊕ …

Ci
i D Q D Q

 C 
⊕ I
i
A B

Normal: CK, B
Shift: S/T=0, A, B
MISR: S/T=1, A, B

Built-in self test.35

Performance of Signature Analyzer
• For a test bit stream of length m :
# possible response = 2m, of which only one is
correct
The number of bit stream producing a specific
signature is

−



=

Built-in self test.36

Performance of Signature Analyzer
(Cont.)

• Among these stream , only one is correct.

−
 −

     =
≅ −
 −

• If n=16, then
− −  
 = 
of erroneous response are detected.
(Note that this is not % of faults !)

Built-in self test.37

 Generic Off-line BIST
Architecture
• Categories of architectures
– Centralized or Distributed
– Embedded or Separate BIST elements
• Key elements in BIST architecture
– Circuit under test (CUTs)
– Test pattern generators (TPGs)
– Output-response analyzers (ORAs)
– Distribution system for data transmission
between TPGs, CUTs and ORAs
– BIST controllers
Built-in self test.38
Centralized/ Separate BIST

Chip, board, or system

CUT
D D
I I
TPG ORA
S S
T T
CUT

BIST
controller

Built-in self test.39

Distributed / Separate BIST

Chip, board, or system

TPG CUT ORA

TPG CUT ORA

Built-in self test.40

Distributed / Embedded BIST

Chip, board, or system

TPG ORA

CUT

TPG ORA

Built-in self test.41

Factors Affecting the Choice of
BIST

• Degree of test parallelism

• Fault coverage
• Level of packaging
• Test time
• Complexity of replaceable unit
• Factory and field test-and-repair strategy
• Performance degradation
• Area overhead

Built-in self test.42

 Specific BIST Architectures

• Ref. Book by Abramovici, Breuer and Friedman

• Centralized and Separate Board-Level BIST (CSBL)

• Built-in Evaluation and Self-Test (BEST)
• Random-Test Socket (RTS)
• LSSD On-Chip Self-Test (LOCST)
• Self-Testing Using MISR and Parallel SRSG (STUMPS)

Built-in self test.43

 Specific BIST Architectures
(Cont.)

• Concurrent BIST (CBIST)

• Centralized and Embedded BIST with Boundary
Scan (CEBS)
• Random Test Data (RTD)
• Simultaneous Self-Test (SST)
• Cyclic Analysis Testing System (CATS)
• Circuit Self-Test Path (CSTP)
• Built-In Logic-Block Observation (BILBO)

Built-in self test.44

 Built-In Logic Block Observation
(BILBO)[1]

• Distributed
• Embedded
• Combinational “Kernels”
• Chip level
• “Clouding” of circuit
• Registers based description of circuit
• BILBO registers

• [1]. B. Konemann, et al., “Built-In Logic_Block Observation

Technique,” Digest of papers 1979 Test Conf., pp.37-41, Oct.,
1979
Built-in self test.45
 BILBO Registers
...
B1

...
B2

Si 0
MUX

D Q D Q D Q D Q

1
...
Q Q Q Q S0

Q1
Q2 Qn-1 Qn

...

B1 B2 BILBO
0 0 shift register
0 1 reset
1 0 MISR (input ∗ constant ∗ LFSR)
1 1 parallel load (normal operation)
Built-in self test.46
 Applications of BILBO

• Bus-oriented structure
BUS

R11 R1n

C1 … Cn

R21 R2n

Built-in self test.47

 Applications of BILBO (Cont.)
PIs
• Pipeline-oriented
…
structure C1

BILBO

C2

…
BILBO

Cn
…

POs Built-in self test.48

 Problems with BILBO

R1
C
C1
BILBO

R2

MISR or TPG ? R2 ?

Using CBILBO

Built-in self test.49

Transistor Level Implementation of
CBILBO
 

  



 

  +
 +











 


 

TPG mode: C1, A2, B=0
MISR mode: C1, A1, C2=0

(c) A simultaneous TPG/MISR S-Cell

Built-in self test.50
Combination of LFSR and Scan Path

LFSR Scan Path

CUT

OR SA

LFSR Scan Path SA

CUT

• Problem: Some hard-to-detect faults may never

be exercised
Built-in self test.51
 Example 1

1 0 0

S-a-0
1 0 0

0 1 0

1 0 1

1 1 0

1 1 1

0 1 1

0 0 1

• The fault can never be detected

Built-in self test.52
 Example 2

32 bits
….. …..

S-a-0
Or
S-a-1
S-a-0

• The faults are difficult to detect

Built-in self test.53
 Solutions:
• Exhausting testing
• Weighted random testing
• Mixed mode vector pattern generation
• Pseudorandom vectors first
• Deterministic tests followed
Do not consider the fact that the test vectors
are given in a form of testcubes with many
unspecified inputs.
4. Reseeding
• Change the seeds as needed
5. Reprogram the characteristic polynomial
6. Combination of two or more of the above
methods
Built-in self test.54
 Memory Testing
• Introduction
• Memory Architecture & Fault Models
• Test Algorithms
• DC / AC / Dynamic Tests
• Built-in Self Testing Schemes
• Built-in Self Repair Schemes

Memory testing.1
Memory Market Share in 1999

17
• DRAM: 8 X 10
16
• Flash: 6 X 10
16
• ROM: 2 X 10
15
• SRAM: 9 X 10

Memory testing.2
 DRAM Price per Bit

1991: US$ 400 / Mega bits

1995: US$ 3.75 / Mega bits

1999: US$ 0.1~0.3 / Mega bits

Memory testing.3
Test Time as a Function of Memory Size
Cycle time: 10 ns

Testing time (in seconds)

Size n
64n n log2n n3/2 n2
16k 0.01 0.0023 0.021 2.7
64k 0.04 0.01 0.168 42
256k 0.17 0.047 1.34 11.4 Mins
1M 0.67 0.21 10.7 183 Mins
4M 2.68 0.92 85.9 49.2 Hrs
16M 10.8 4.03 11.4 Mins 36.5 Days
64M 43.2 16.2 91.6 Mins 584 Days
Memory testing.4
Architecture of a DRAM Chip
Address

Address latch Column decoder Refresh logic

Memory
Row cell
decoder Write driver
array

Sense amplifiers Data register

Data
Data Data Read/write
Control Signal out in

Memory testing.5
 Fault Models

1. SAF Stuck-At Fault

2. TF Transition Fault
3. CF Coupling Fault
4. NPSF Neighborhood Pattern Sensitive Fault
5. AF Address decoding fault

Memory testing.6
 Stuck-At Fault
• The logic value of a cell or a line is always 0 or 1.

Transition Fault
• A cell or a line that fails to undergo a 0 1 or a 1 0
transition.

Coupling Fault
• A write operation to one cell changes the content of
a second cell.

Memory testing.7
Neighborhood Pattern Sensitive Fault
• The content of a cell, or the ability to change its
content, is influenced by the contents of some other
cells in the memory.

Address Decoder Fault (AF)

• Any fault that affects address decoder:
• With a certain address, no cell will be accessed.
• A certain cell is never accessed.
• With a certain address, multiple cells are accessed
simultaneously.
• A certain cell can be accessed by multiple addresses.
Memory testing.8
 Memory Chip Test Algorithms
• Traditional tests
• Tests for stuck-at, transition and coupling faults
• Tests for neighborhood pattern sensitive faults

Memory testing.9
 Traditional Tests
Algorithm Test length Test Time Order
• Zero-One


• Checkerboard




• GALPAT

+






• Walking 1/0

+





• Sliding Diagonal 
+

⋅

⋅

• Butterfly

+ 


−   
⋅ 



• n is the number of bits of the memory array.

Memory testing.10
 March Algorithms

Algorithm March X
Step1: write 0 with up addressing
order;
Step2: read 0 and write 1 with up
addressing order;
Step3: read 1 and write 0 with down
addressing order;
Step4: read 0 with down addressing
order.

Memory testing.11
Notation of March Algorithms

: address 0 to address n-1

: address n-1 to address 0
: either way

w0 : write 0
w1 : write 1
r0 : read a cell whose value should be 0
r1 : read a cell whose value should be 1

Memory testing.12
 March Algorithms

EX:
MATS ( modified algorithmic Test Sequence)

(w0); (r0,w1); (r1);

s1: write 0 to all cells
s2: for each cell
read 0 ;
write 1;
s3: read 1 from all cells

Memory testing.13
 Some March Algorithms

MATS : (w0); (r0,w1); (r1)

MATS+: (w0); (r0,w1); (r1,w0)
Marching 1/0 : (w0); (r0,w1,r1); (r1,w0,r0);
(w1); (r1,w0,r0); (r0, w1, r1);

MATS++ : (w0); (r0,w1); (r1,w0,r0);

MARCH X : (w0); (r0,w1); (r1,w0); (r0)
MARCH C : (w0); (r0,w1); (r1,w0); (r0);
(r0,w1); (r1,w0); (r0);

Memory testing.14
Some March Algorithms (Cont.)

MARCH A : (w0); (r0,w1,w0,w1); (r1,w0,w1);

(r1,w0,w1,w0); (r0,w1,w0);

MARCH Y : (w0); (r0,w1,r1); (r1,w0,r0); (r0)

MARCH B : (w0); (r0,w1,r1,w0,r0,w1); (r1,w0,w1);

(r1,w0,w1,w0); (r0,w1,w0)

Memory testing.15
 Tests for Stuck-At, Transition and
Coupling Faults
March alg. Test len. Fault coverage
MATS 4n Some AFs, SAFs
MATS+ 5n AFs, SAFs
Marching 1/0 14n AFs, SAFs, TFs
MATS++ 6n AFs, SAFs, TFs
March X 6n AFs, SAFs, TFs, Some CFs
March C- 10n AFs, SAFs, TFs, Some CFs
March A 15n AFs, SAFs, TFs, Some CFs
March Y 8n AFs, SAFs, TFs, Some CFs
March B 17n AFs, SAFs, TFs, Some CFs

Memory testing.16
 NPSF
n n n b: base cell
n b n n: neighbor cells
n n n

ANPSF: PNPSF: SNPSF:

Active Neighborhood Passive Neighborhood Static Neighborhood
Pattern Sensitive Fault Pattern Sensitive Fault Pattern Sensitive Fault

n changes Contain n patterns Contain n patterns

b changes b cannot change b is forced to a certain

value
Ex: Ex: Ex:
n: 0 1 n: 00000000 n: 11111111
b: 1 0 b: 0 or 1 b: 1

Memory testing.17
 DC Parametric Testing
• Contains:
1. Open / Short test.
2. Power consumption test.
3. Leakage test.
4. Threshold test.
5. Output drive current test.
6. Output short current test.

Memory testing.18
 AC Parametric Testing
• Output signal: - the rise & fall times.
• Relationship between input signals:
– the setup & hold times.
• Relationship between input and output signals:
– the delay & access times.
• Successive relationship between input and output
signals:
– the speed test.

Memory testing.19
 Dynamic Faults
• Recovery faults:
− Sense amplifier recovery
− Write recovery.
− Retention faults:
− Sleeping sickness
− Refresh line stuck-at
− Static data loss.
− Bit-line precharge voltage imbalance faults.

Memory testing.20
 BIST: Pros & Cons
• Advantages:
– Minimal use of testers.
– Can be used for embedded RAMs.
• Disadvantages:
– Silicon area overhead.
– Speed; slow access time.
– Extra pins or multiplexing pins.
– Testability of the test hardware itself.
– A high fault coverage is a challenge.

Memory testing.21
Typical Memory BIST Architecture
Using Mentor’s Architecture
sys_addr

Pattern Generator
Algorithm-Based
di
sys_d addr Memory data
isys_wen wen
Module
rst_l

Compressor
clk q
compress_h clk
hold_l
rst
test_h si so
se

BIST Circuitry

Memory testing.22
Multiple Memory BIST Architecture
sys_addr1
sys_addr2
sys_di2 addr1 ROM4KX4 4

Pattern Generator
data

Algorithm-Based
sys_wen2 Module
sys_addr3
di2
sys_di3 addr2 RAM8KX8 8 data
sys_wen3 wen2 Module
rst_ di3
l clk addr3 RAM8KX8 8 data
wen3 Module
hold_l
test_h compress_h
BIST
Circuitry
q
se
Compressor so
si

Memory testing.23
Serial Testing of Embedded RAM
Go
BIST mode Done

Control Block
Timing
Counters Generator
BIST on
S0 S1
msb
Mission Control Read/Write
mode
interface { Data out
Data in
Address
1sb

c-1
Clock

Multiplexers Multiplexers Multiplexers

log W c c 2
2

Address Data In Data Out Control

RAM
(w words c bits)

Memory testing.24
 Built-in Self-Repair

• BIST can only identify faulty chip.

• Laser cut may be infeasible in some cases, e.g., field
testing.
• Two types:
– Use fault-array comparator
! Repair by cell
! Repair by column (or row)
– Use switch array

Memory testing.25
 BISR Using Switch Array

BISR module

Fault-Address BIST module

Buffers Select

Address
input RAM RAM-Array
Decoder Switch Array module
Data
Out
Data
input

Memory testing.26
BISR via Fault-Address Comparison

BISR module

Fault-Address BIST module

Buffers

Address
input Fault-Address RAM RAM-Array
Compare Decoder module
Data
Out
Data
input

Memory testing.27
Chapter 4: Memory Built-In
Built In
Self Test
Self-Test

Jin Fu Li
Jin-Fu
Dept. of Electrical Engineering
National Central University
Jhongli, Taiwan
 Outline
• ROM BIST
• RAM BIST
• Serial BIST for RAMs
• Processor
Processor-Based
Based RAM BIST
• RAM BISTs in SOCs
• References

EE, National Central University Jin-Fu Li 2

 Introduction
• Characteristics of today’s SOC designs
− Typically more than 30 embedded memories on a
chip
hi
− Memories scattered around the device rather than
concentrated in one location
− Different types and sizes of memories
− Memories doubly embedded inside embedded cores
− Test access to these memories from only a few chip
I/O pins
p
• Built-in self-test (BIST) is considered the best
solution for testing embedded memories within
SOCs
− It offers a simple and low-cost
low cost means without
significantly impacting performance
EE, National Central University Jin-Fu Li 3
 General BIST Architecture

Test Circuit Under Test Response

Generator (CUT) Verification

Test Controller

EE, National Central University Jin-Fu Li 4

 ROM Functional Block Diagram
Inputs

Buffer

NOR/NAND
Decoder
(ROM Array)

Buffer

Outputs
O t t
EE, National Central University Jin-Fu Li 5
 An Example of ROM BIST

Counter
ROM

Controller MISR

Go/No-Go Status

EE, National Central University Jin-Fu Li 6

 Typical RAM BIST Architecture

Normal I/Os

T t Controller
Test C t ll

Test Collar
C
RAM
Test Pattern
Generator

Go/No-Go
Comparator

EE, National Central University Jin-Fu Li 7

 RAM BIST
• In general, two BIST approaches have been
proposed for the RAMs
− FSM-based RAM BIST
− ROM-based RAM BIST

• Controller
− Generate control signals to the test pattern
generator & the memory under test
• Test pattern generator (TPG)
− Generate the required test patterns and Read/Write
signals
g
• Comparator
− Evaluate the response
EE, National Central University Jin-Fu Li 8
 ROM-Based RAM BIST
• The features of ROM-based BIST scheme
− The ROM stores test procedures for generating test
patterns
− Self-test is executed by using BIST circuits controlled
by the microprogram ROM
− A wide range of test capabilities due to ROM
programming
p g g flexibility
y
• The BIST circuits consists of the following
functional blocks
− Microprogram ROM to store the test procedure
− Program counter which controls the microprogram
ROM
− TPG
− Comparator
EE, National Central University Jin-Fu Li 9
 ROM-Based RAM BIST Architecture

Normal I/Os

E d
End Mi
Microprogram

Test Collar
ROM

RAM
TPG

Go/No-Go
Comparator

EE, National Central University Jin-Fu Li 10

 March-9N Test Procedure & Microcodes
• M h 9N
March-9N:
STEP OPERATION MICROCODE
CLEAR 0000000010
WRITE(D), INC AC, IF AC=MAX THEN INC PC 1010000100
READ(D) 0000000100
WRITE(D’), INC AC, IF AC=MAX THEN INC PC ELSE DEC PC 1110010100
READ(D’))
READ(D 0000011000
WRITE(D), INC AC, IF AC=MAX THEN INC PC ELSE DEC PC 1110000100
DEC AC 0001000000
READ(D) 0000001000
WRITE(D’) DEC AC
WRITE(D’), AC, IF AC=0 THEN INC PC ELSE DEC PC 1101010100
READ(D’) 0000011000
WRITE(D), DEC AC, IF AC=0 THEN INC PC ELSE DEC PC 1101000100
STOP 0000000001

IF AC=MAX/0
ELSE DEC PC
INCREMENT AC
DECREMENT AC
EXCLUSIVE OR
INVERT/NORMAL
COMPARE/MASK
WRITE/READ
CLEAR
TEST END
EE, National Central University Jin-Fu Li 11
 FSM-Based RAM BIST

Normal I/Os

E d
End
FSM

Test Collar
RAM
TPG

Go/No-Go
Comparator

EE, National Central University Jin-Fu Li 12

 FSM-Based RAM BIST
• A example
An l off the
h state di
diagram off controller
ll
W0 S0 NOT last address?

R0 S1
NOT last address?

W1 S2

R1 S3
NOT last address?

W0 S4

R0 S5
NOT last address?

W1 S4

End S4
EE, National Central University Jin-Fu Li 13
 Programmable RAM BIST
• A example
An l off the
h programmable
bl RAM BIST

Normal I/Os

CMD

T
TPG
BSI

Test Collar
Con
TGO

& Compar
BSC RAM

C
ntroller

C
ENA
BRS

rator
DONE
BGO

CLK
BNS

EE, National Central University Jin-Fu Li 14

 FSM State Diagram of the Controller

Idle BRS=1

BSC=1
DONE=1 Shift
Shift_cmd
d

BSC=0

Get_cmd

Apply ENA=1

DONE=0

EE, National Central University Jin-Fu Li 15

 Programmability
• The programmability
Th bili can b
be achieved
hi dbby using
i
test command
• The test command format
− U/D OP Data background
− U/D: ascending/descending address
sequence
− OP: test operations
∗ For
o example,
e a p e, wa,
a, rawa’,
a a , rawa’ra,
a a a, warawa’ra’,
a a a a , etc.
− Data backgrounds
• The width
Th idth off each
h field
fi ld affects
ff t the
th
programmability of the BIST design
− For
F example,
l if 4 bit
bits are used
d ffor OP
OP, th
then only
l 16
possible test operations
EE, National Central University
can be generated
Jin-Fu Li 16
 FSM State Diagram of the TPG

Idle ENA=0

ENA=1

Init DONE/GO
Null=1
Null=0

Ifetch

Exec

Dfetch

Error=1 Error=0
No-Go Compare

EE, National Central University Jin-Fu Li 17

 Serial BIST
• Today’s telecommunication ICs often have a
variety if multiport memories on one chip
• Typical RAM BISTs evaluate all the bits of a
memory word in parallel as it is read
• We can encounter significant problems when
applying these BIST schemes to chips that have
multiple embedded RAMs of varying sizes and
port configurations
− The area cost of these BIST designs would be
unacceptably high
• One better solution is a serial BIST technique
− To
T share
h BIST d
design
i among severall RAM
RAMs
EE, National Central University Jin-Fu Li 18
 Benefits of Serial BIST
• Only a small amount of additional circuitry is
required
• Only a few lines are needed to connect the RAM
to the test controller
• Several RAM blocks easilyy share the BIST
controller hardware
• The serial
serial-access
access mode does not compromise
the RAM cycle time
• Existing
E i ti memory d
designs
i d
do nott need
d any
modification to use the serial interface

EE, National Central University Jin-Fu Li 19

 Serial-Data-Path Connection

Row de
Ci Ci+1

ecoder
Column decoder

Latch Latch
Write
Read
BIST on
To next test input
From previous output or serial input
or serial input
Ii Oi Ii+1 Oi+1
EE, National Central University Jin-Fu Li 20
 Serial Shift Operation
• An example of serial shift operations for the
match element (R0W1)
Time Operation Serial Word Serial
in content out

0 X 0 0 0 0 X
1 R0 X 0 0 0 0 0

0
11 00 00 00 2 W1 1 1 0 0 0 0
3 R0 1 1 0 0 0 0
4 W1 1 1 1 0 0 0
5 R0 1 1 1 0 0 0
010 000 000 000
6 W1 1 1 1 1 0 0
7 R0 1 1 1 1 0 0
1
X
1 0
X
8 W1 1 1 1 1 1 0

EE, National Central University Jin-Fu Li 21

 Serial March (SMarch)
• Assume that a RAM has W words, and each
word contains C bits
• A Read operation is denoted by R0, R1, or Rx,
depending on the expected value at the serial
output (x=do’t care)
• For a write operation
operation, the terms W0 or W1 are
used and only the serial input is forced to the
value indicated
• The SMarch modified from March C- is as
f llc ( RxW 0 ) C ( R 0, W 0 ) C ; ⇑ ( R 0, W 1) C ( R1, W 1) C
follows
− ⇑ ( R1, W 0 ) C ( R 0 , W 0 ) C ; ⇓ ( R 0 , W 1) C ( R1, W 1) C
⇓ ( R1, W 0 ) C ( R 0 , W 0 ) C ; ⇓ ( R 0 , W 0 ) C ( R 0 , W 0 ) C
EE, National Central University Jin-Fu Li 22
 Serial BIST Architecture
BIST GO Done

Controller Timing
Counters
generator
SO SI
Control
lsb msb
Data out
Data in
Address C-1

Multiplexer Multiplexer Multiplexer

C C

Address Data in Data out Control

RAM (W words of C bits)

EE, National Central University Jin-Fu Li 23

 Sharing BIST in Daisy-Chain Style
BIST GO Done

Controller Timing
Counters
generator
g
SO SI

Add
Address R d/W it
Read/Write

Test Collar Test Collar Test Collar

RAM1 RAM2 RAM3

Serial Interface Serial Interface Serial Interface

SI SO SI SO SI SO

EE, National Central University Jin-Fu Li 24

 Sharing BIST in Parallel Style
GO
BIST Done
DeMux

SO SI Timing
g
C
Counters
t Controller generator

Address Read/Write

Test Collar Test Collar Test Collar

RAM1 RAM2 RAM3

Serial Interface Serial Interface Serial Interface

SI SO SI SO SI SO

EE, National Central University Jin-Fu Li 25

 BIST Using Data Decoding/Encoding

n
m wire
n

n
e
m wire

EE, National Central University Jin-Fu Li 26

 Processor-Based RAM BIST

Normal I/Os

Processor

Test Collar
RAM
TPG

Go/No-Go
Comparator

EE, National Central University Jin-Fu Li 27

 NTHU Processor-Programmable BIST

ADDR_cpu
ADDR
ADDR_bist

DATAO
DATAO_sys
DATAO
DATAO_bist
Embedded On-chip Embedded
CPU
Clock_cpu
BIST core Mux_sel
bus Memory

Ctrl_bist control
Ctrl_cpu

DATAI_bist DATAI_sys DATAI

DATAI_cpu

Source: Prof. C. W. Wu, NTHU

EE, National Central University Jin-Fu Li 28

 NTHU Processor-Programmable BIST
• BIST core
DATAO_cpu
DATAO_bist
RBG

RAL L
Lowest/highest
t/hi h t addr
dd ADDR_bist
Address
ADDR_cpu Address counter
RAH REA
decorder Up/down
RME RFLAG Read/Write
Control
RIR RED Controller

Match/unmatch
DATAI_bist
DATAI sys
DATAI_sys
Comparator
Data background

Source: Prof. C. W. Wu, NTHU

EE, National Central University Jin-Fu Li 29

 NTHU Processor-Programmable BIST
• Data registers

Register Function
RBG Store background data
RAL Store lowest address
RAH Store highest address
RME Store current March element
RIR Instruction register of BIST circuit
RFLAG Status register of BIST circuit
RED Erroneous response of defective cell
REA Address of defective cell

Source: Prof. C. W. Wu, NTHU

EE, National Central University Jin-Fu Li 30

 NTHU Processor-Programmable BIST
• BIST procedure Source: Prof. C. W. Wu, NTHU

Test program write data background to RBG

Test program write lowest/highest address to RAL/RAH
Performed by
test program

Test program write March instructions to RME

Test program write START to RIR

↑(Wa) ↑(Ra,Wa’) ↑(Ra’,Wa) ↓(Ra,Wa’) ↓(Ra’,Wa) ↓(Ra)

Compare yes Write ERROR to RFLAG

Data error Write error response to RED
Performed by Write faulty addr to REA
BIST circuit No
No March element
complete

yes
Test program
Write FINISH to RFLAG
take over
EE, National Central University Jin-Fu Li 31
 SOC Testing
• A typical SOC chip
ADC FPGA
Flash Memoryy
Wrapper
CPU UDL
DSP
Sink
TAM
Source Test Access Mechanism (TAM)

DRAM
MPEG SRAM SRAM

Source: Y. Zorian, et al.-ITC98

EE, National Central University Jin-Fu Li 32

 SOC Test Access
ADC FPGA
Flash
Off-chip Source/Sink
Wrapper Memory 1. Pins determine bandwidth
CPU UDL DSP 2. More TAM area
Sink
TAM TAM 3. Requires expensive ATE
Source

DRAM
MPEG SRAM SRAM

ADC FPGA
Flash
Wrapper Memory
On chip Source/Sink
On-chip UDL
CPU DSP
1. Close to Core-under-test Sink Sink
2 Less TAM area
2. Source Source

3. BIST IP area DRAM

MPEG SRAM SRAM
4. Requires lightweight ATE

Source: Y. Zorian and E.J. Marinissen

EE, National Central University Jin-Fu Li 33
 1500 Scalable Test Architecture

Source User Defined Parallel TAM Sink

TAM-in TAM-out TAM-in TAM-out

1500 Wrapper
W 1500 Wrapper
W

Fin Fout Fin Fout

Core1 CoreN

WSI WIR WSO WSI WIR WSO

WIP

User-Defined
Test Controller

EE, National Central University Jin-Fu Li 34

 1500 Test Wrapper

Test stimuli WPI WPO Test response

W
WBR

W
WBR
Core
Functional Functional
data data

WBY
WSO
WSI WIR

WSC

EE, National Central University Jin-Fu Li 35

 Memories in SOCs

ADC FPGA
Flash Memory

CPU UDL DSP

DRAM
SRAM SRAM SRAM
BIST
BIST

DRAM
MPEG SRAM SRAM
BIST BIST

N BIST memory cores

Non-BIST BIST
BIST-ready
d memory cores

EE, National Central University Jin-Fu Li 36

 RAM BIST in SOCs
• Memory cores in an SOC can be categorized
into two types in term of testability
− BIST-ready memory cores
− Non-BIST memory cores

• An SOC can contain tens or even hundreds of

memory
e o y cores
co es
− Although a BIST usually have only about 8
controlling pins
− The total BIST controlling pins is huge if each BIST-
ready memory cores has its own BIST controlling pins
• The BIST controlling pins should be shared
− One solution is using
g memory
y BIST interface

EE, National Central University Jin-Fu Li 37

 Sharing BIST Controlling Pins

ADC FPGA
Flash Memory

CPU UDL
DSP

DRAM
SRAM SRAM SRAM BIST
BIST MBI
MBI MBI
BIST
MBI
BIST
MPEG SRAM DRAM
SRAM

EE, National Central University Jin-Fu Li 38

 Memory BIST Interface (MBI)

EE, National Central University Jin-Fu Li 39

 Memory BIST Interface (MBI)
• Instruction Register
− Store the instructions
∗ RUN_BIST, RUN_DIAGN, EXPORT_STATUS, TAM_CONTROL

• Bypass
yp Register
g
− It is selected if the corresponding memory core is not
tested
• Monitor Register
− Monitor
o to the
t e error
e o flag
ag ((indicating
d cat g whether
et e a memory
e oy
fault is detected or not)
• Status Register
− Record the key status values, such as Fail output from
the BIST

EE, National Central University Jin-Fu Li 40

 Testing Multiple Memories with MBI

• Using RUN_BIST instruction, we can test multiple

memory cores concurrently
− When one or more BIST circuits detect faults, the primary
MSO_N will be high after N-K clock cycles if the concurrent
output of the (K+1) through the N memory cores are fault free

EE, National Central University Jin-Fu Li 41

 Sharing BIST Hardware
BIST controlling signals

TPG &
BIST Controller Comparator

BIST C ll
Collar BIST C
Collar
ll BIST C ll
Collar

RAM 1 RAM 2 RAM N

EE, National Central University Jin-Fu Li 42

 RAM BIST Compiler

S
Source: P
Prof.
f C.
C W
W. Wu,
W NTHU

EE, National Central University Jin-Fu Li 43

 1500-Compilant BIST

T
TAP

Wrapper
Con
TAP

ntroller
P

BIST RAM

EE, National Central University Jin-Fu Li 44

Programmable BISD for RAMs in SOCs
• General test architecture

ATE

SOC TAP controller

TAM
Wrapper

Processor + Test Program Memory

Embedded Memory Core

S
Source: A
Appello
ll DD., et. al.l ITC03

EE, National Central University Jin-Fu Li 45

Programmable BISD for RAMs in SOCs
• Test Processor

Processor
Wrapper
Control
P1500 Test Program
Instructions Unit

P1500 Address Bus

Memory
Output Data Data Bus
Adapter g
Control Signals

S
Source: A
Appello
ll DD., et. al.l ITC03

EE, National Central University Jin-Fu Li 46

Programmable BISD for RAMs in SOCs
• Control Unit
− Manage the test program execution
− Include an Instruction Register (IR) and
Program Counter (PC)
− The control unit allows the correct update of
some registers located in Memory Adapter
− This part simplifies the processor reuse in
different applications without the need for any
re-design

EE, National Central University Jin-Fu Li 47

Programmable BISD for RAMs in SOCs
• Memory Adapter
− Control Address registers
g (Current
( _address))
− Control Memory registers
∗ Current_data
∗ Received_data
R i d d t
− Control Test registers
∗ Dbg
g_index,, Step,
p, Direction flag,
g, and Timer registers
g
− Result registers
∗ Status, Error, and Result registers
− Some constant value registers
∗ Add_Max, Add_Min, DataBackGround, Dbg_max

EE, National Central University Jin-Fu Li 48

Programmable BISD for RAMs in SOCs
• Processor instruction set

I t ti
Instruction M
Meaning
i
Current_address ⇐ Add_Max
SET_ADD
Direction flag ⇐ BACKWARD
Current_address ⇐ Add_Min
RST_ADD
g ⇐ FORWARD
Direction flag
Current_data ⇐ DataBackGround[Dbg_index]
STORE_DBG
Dbg_index ⇐ Dbg_index+1
INV_DBG Current_data ⇐ NOT (Current_data)

READ Current data ⇐ Memory[Current_address]

Current_data Memory[Current address]

WRITE Memory[Current_address] ⇐ Current_data

Source: Appello D., et. al. ITC03

EE, National Central University Jin-Fu Li 49
Programmable BISD for RAMs in SOCs
• Wrapper

WSI

WRCK W
WRSTN C
TAP controller

D
W W

Me
ShiftWR W R

emory
D
c

UpdateWR I Processor B
R R R
CaptureWR
W
SelectWIR B Test
Y Program CORE

WSO

Wrapper

Source: Appello D., et. al. ITC03

EE, National Central University Jin-Fu Li 50
 Summary

• ROM BIST has been presented

p
• ROM-based and FSM-based RAM BIST have
been introduced
• Serial BIST methodology for embedded
memories
i h has also
l presented
t d
• BIST approaches
pp for testing
g multiple
p RAMs in an
SOC have also been addressed

EE, National Central University Jin-Fu Li 51

 References
• [1] A. K. Sharma,”Semiconductor memories – technology, testing, and
reliability”,
li bilit ” IEEE P
Press, 1997
1997.
• [2] B. Nadeau-Dostie, A. Silburt, and V. K. Agarwal,”Serial interfacing for
embedded-memory testing”, IEEE D&T, pp.52-63, apr. 1990.
• [3] C. W. Wu,”VLSI testing & design for testability II: Memory built-in self-
test”, http://larc.ee.nthu.edu.tw/~cww/
• [4]C. H. Tsai and C.-W.
[4]C.-H. C. W. Wu, ``Processor-programmable
Processor programmable memory BIST for
bus-connected embedded memories'', in Proc. Asia and South Pacific
Design Automation Conf. (ASP-DAC), Yokohama, Jan. 2001, pp. 325-330
• [5]C.-W
[5]C W. Wang,
Wang C C.-F
F. Wu,
Wu JJ.-F
F. Li,
Li CC.-W
W. Wu,
Wu TT. Teng,
Teng KK. Chiu,
Chiu and H.
H -P
P. Lin
Lin, ``A
A
built-in self-test and self-diagnosis scheme for embedded SRAM'', in Proc.
9th IEEE Asian Test Symp. (ATS),Taipei, Dec. 2000, pp. 45-50
• [6]D. Appello,
[6]D Appello FF. Corno
Corno, M.
M Giovinetto,
Giovinetto M
M. Rebaudengo
Rebaudengo, and M
M. S
S. Reorda
Reorda,”A
A
P1500 compliant BIST-Based approach ro embedded RAM diagnosis”,
pp.97-102, MTDT, 2001.
• [7]J. F
[7]J F. Li
Li, H
H. JJ. H
Huang, JJ. B
B. Ch
Chen, C.
C P.
P Su,
S C.C W.
W Wu,
W C.
C Cheng,
Ch S.
S I.
I Chen,
Ch C.
C Y.
Y
Hwang, and H. P. Lin,”A hierarchical test methodology for systems on chip”,
IEEE Micro, pp. 69-81, Sep./Oct., 2002.
• [8]S. Mourad and Y. Zorian,”Principles off Testing Electronic Systems”, John
Wiley & Sons, 2000.
EE, National Central University Jin-Fu Li 52