Rambus'S Opp. To Joint Mot. For Summary Judgment of Invalidity (MSJ #2) C 05-00334 RMW C 05-02298 RMW C 06-00244 RMW

Case 5:05-cv-00334-RMW Document 2537 Filed 11/14/2008 Page 1 of 22
1 Gregory P. Stone (SBN 078329) Rollin A. Ransom (SBN 196126)

Andrea Weiss Jeffries (SBN 183408) SIDLEY AUSTIN LLP
2 Fred A. Rowley, Jr. (SBN 192298) 555 West Fifth Street, Suite 4000
MUNGER, TOLLES & OLSON LLP Los Angeles, CA 90013-1010
3 355 South Grand Avenue, 35th Floor Telephone: (213) 896-6000
Los Angeles, CA 90071-1560 Facsimile: (213) 896-6600
4 Telephone: (213) 683-9100 Email: [email protected]
Facsimile: (213) 687-3702
5 Email: [email protected] Pierre J. Hubert (Pro Hac Vice)
Email: [email protected] Craig N. Tolliver (Pro Hac Vice)
6 Email: [email protected] McKOOL SMITH PC
300 West 6th Street, Suite 1700
7 Peter A. Detre (SBN 182619) Austin, TX 78701
Rosemarie T. Ring (SBN 220769) Telephone: (512) 692-8700
8 Jennifer L. Polse (SBN 219202) Facsimile: (512) 692-8744
MUNGER, TOLLES & OLSON LLP Email: [email protected]
9 560 Mission Street, 27th Floor Email: [email protected]
San Francisco, CA 94105
10 Telephone: (415) 512-4000
Facsimile: (415) 512-4077
11 Email: [email protected]
Email: [email protected]
12 Email: [email protected]
13 Attorneys for RAMBUS INC.
14 UNITED STATES DISTRICT COURT
15 NORTHERN DISTRICT OF CALIFORNIA, SAN JOSE DIVISION
16
RAMBUS INC., CASE NO. C 05-00334 RMW
17
Plaintiff, RAMBUS INC.’S OPPOSITION TO JOINT
18 MOTION OF HYNIX, MICRON AND
v. SAMSUNG FOR SUMMARY JUDGMENT
19 OF INVALIDITY UNDER 35 U.S.C. § 102
HYNIX SEMICONDUCTOR INC., et al., OF CLAIM 14 OF THE ’184 PATENT,
20 CLAIM 33 OF THE ’120 PATENT, CLAIM
Defendants. 16 OF THE ’863 PATENT, CLAIM 3 OF
21 THE ’446 PATENT, CLAIM 43 OF THE
’051 PATENT, AND CLAIM 34 OF THE
22 ’037 PATENT (MSJ #2)
23 Date: December 11, 2008
Time: 2:00 p.m.
24 Ctrm: 6 (Hon. Ronald M. Whyte)
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RAMBUS’S OPP. TO JOINT MOT. FOR SUMMARY
JUDGMENT OF INVALIDITY (MSJ #2)
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2 RAMBUS INC., CASE NO. C 05-02298 RMW

Plaintiff,
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v.
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SAMSUNG ELECTRONICS CO., LTD.,
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et al.,
6 Defendants.
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CASE NO. C 06-00244 RMW
8 RAMBUS INC.,
9 Plaintiff,
10 v.
11 MICRON TECHNOLOGY INC., et al,
12 Defendants.
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JUDGMENT OF INVALIDITY (MSJ #2)
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1 TABLE OF CONTENTS
2 Page
3 I. INTRODUCTION .............................................................................................................. 1
II. ARGUMENT ...................................................................................................................... 1
4
A. The Manufacturers Must Prove Anticipation by Clear and Convincing Evidence............. 1
5 B. Novak Does Not Disclose an External Clock Signal .......................................................... 2
6 C. Novak Does Not Disclose a Write Request or an Operation Code..................................... 4
D. Novak Does Not Disclose Receiving or Sampling an Operation Code, or Sampling
7 Block Size Information, Synchronously with Respect to an External Clock Signal ......... 6
8 E. Novak Does Not Disclose Sampling or Inputting Data in Response to a Write
Request or Operation Code ................................................................................................. 7
9 F. Novak Does Not Disclose a Synchronous Memory Device ............................................... 8
10 G. Novak Does Not Disclose Block Size Information............................................................. 9
H. Novak Does Not Disclose Sampling Data After a Predetermined Number of Clock
11 Cycles or After a Delay Time Transpires ......................................................................... 10
12 I. Novak Does Not Disclose Precharge Information ............................................................ 11
J. Novak Does Not Disclose Precharge Information or a Precharge Instruction as Part
13 of an Operation Code ........................................................................................................ 12
14 K. Novak Does Not Anticipate the Claims at Issue............................................................... 13
1. Novak Does Not Anticipate Claim 14 of the ’184 Patent..................................... 13
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16 3. Novak Does Not Anticipate Claim 16 of the ’863 Patent..................................... 15
17 4. Novak Does Not Anticipate Claim 3 of the ’446 Patent....................................... 16
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19 III. CONCLUSION ................................................................................................................. 18
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1 TABLE OF AUTHORITIES
2 Page
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FEDERAL CASES
4
Electro Med. Sys., S.A. v. Cooper Life Scis., Inc.,
5 34 F.3d 1048 (Fed. Cir. 1994)................................................................................................... 2
Net MoneyIN, Inc. v. Verisign, Inc.,
6 ---F.3d---, No. 2007-1565, 2008 WL 4614511 (Fed. Cir. Oct. 20, 2008) ................................ 2
7 Schumer v. Lab. Computer Sys., Inc.,
308 F.3d 1304 (Fed. Cir. 2002)............................................................................................. 1, 2
8 Scripps Clinic & Research Found. v. Genentech, Inc.,
927 F.2d 1565 (Fed. Cir. 1991)................................................................................................. 2
9
10 STATUTES AND RULES

11 35 U.S.C. § 102 ............................................................................................................................... 2
12 35 U.S.C. § 282 ............................................................................................................................... 1
Fed. R. Civ. P. 56(c)........................................................................................................................ 2
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1 I. INTRODUCTION
2 The Manufacturers move for summary judgment of anticipation of six Rambus
3 patent claims based on U.S. Patent No. 4,663,735 (“Novak”).1 Novak is, however, not directed to
4 a synchronous memory device as claimed by Rambus’s patents. Rather, Novak discloses a
5 conventional, asynchronous DRAM, with a shift register appended that is capable of serial input
6 and output of data. The Manufacturers focus their arguments on the operation of this shift
7 register in their arguments. However, not surprisingly given the significantly different structure
8 of the Novak invention from the synchronous devices claimed by Rambus’s patents, Novak fails
9 to disclose numerous limitations of the claims at issue.
10 Much of the Manufacturers’ motion is devoted to arguing that the Court’s decision
11 with respect to disclosure of certain claim elements by Novak should be dictated by the Court’s
12 holding in Hynix I that those claim elements were disclosed by a patent issued to Redwine. The
13 disclosure of the Redwine patent is, however, different in significant material respects from
14 Novak. Moreover, the Court denied summary judgment in Hynix I based on Redwine, and the
15 reasons for that denial are applicable to certain limitations of the claims at issue here. Further,
16 each of the claims at issue here contain limitations that the Court did not consider in Hynix I and
17 that are not disclosed by Novak. Indeed, there are at least four limitations in each of the claims at
18 issue that are not disclosed by Novak. Especially in light of the heavy burden the Manufacturers
19 bear in seeking to invalidate Rambus’s patents on summary judgment, the Court should deny their
20 motion.
21 II. ARGUMENT
22 A. The Manufacturers Must Prove Anticipation by Clear and Convincing
Evidence.
23
United States patents are presumed valid. 35 U.S.C. § 282. Accordingly,
24
“evidence of invalidity must be clear as well as convincing.” Schumer v. Lab. Computer Sys.,
25
26 1
Rambus has moved to strike the Manufacturers’ motion as plainly improper under the Court’s
27 schedule which required motions for summary judgment dependent on claim construction issues
to be brought over a year ago. Nevertheless, Rambus is compelled to respond on the merits
28 because the hearing on Rambus’s motion will not take place until after this opposition is due.
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1 Inc., 308 F.3d 1304, 1315 (Fed. Cir. 2002) (reversing district court’s grant of summary judgment
2 of invalidity).
3 Anticipation under 35 U.S.C. § 102 is a question of fact. Scripps Clinic &
4 Research Found. v. Genentech, Inc., 927 F.2d 1565, 1576 (Fed. Cir. 1991). Anticipation requires
5 that each and every element of the claimed invention be disclosed in a single prior art reference,
6 arranged or combined in the same way as recited in the claim, either expressly or inherently. Net
7 MoneyIN, Inc. v. Verisign, Inc., ---F.3d---, No. 2007-1565, 2008 WL 4614511, at *8 (Fed. Cir.
8 Oct. 20, 2008). A limitation is present in a prior art reference inherently only if a person of
9 ordinary skill in the art would recognize that the limitation, although not expressed, is necessarily
10 present. See Electro Med. Sys., S.A. v. Cooper Life Scis., Inc., 34 F.3d 1048, 1052 (Fed. Cir.
11 1994) (“[T]he mere fact that a certain thing may result from a given set of circumstances is
12 insufficient to prove anticipation . . . . [The challenger] was required to prove that [the limitation]
13 is necessarily present.”) (emphasis in original) (internal citations omitted).
14 A party is entitled to summary judgment only when there are no genuine disputes
15 as to material facts concerning an issue. Fed. R. Civ. P. 56(c). On a motion for summary
16 judgment, all reasonable inferences must be drawn in favor of the non-movant. Accordingly,
17 “[t]he burden of proving invalidity on summary judgment is high.” Schumer, 308 F.3d at 1316;
18 see also Scripps Clinic, 927 F.2d at 1578 (reversing district court’s grant of summary judgment of
19 anticipation and noting that “[t]rial by document is an inadequate substitute for trial with
20 witnesses, who are subject to examination and cross-examination in the presence of the decision-
21 maker”).
22 B. Novak Does Not Disclose an External Clock Signal.
23 The Manufacturers’ argument that Novak discloses an external clock signal relies
24 entirely on the Court’s holding in Hynix I that a different specification in a different patent, the
25 Redwine patent, disclosed an external clock signal. Mot. at 7-8. However, the portions of the
26 Redwine specification that the Court relied on in so holding are not present in Novak; contrary to
27 the Manufacturers’ argument, the Court’s analysis of Redwine is not applicable here.
28 The signal Φ that the Manufacturers assert is an external clock signal is used to
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1 shift data into and out of Novak’s serial shift register. Col. 6:32-36.2 As the timing diagram of
2 Figure 4 of Novak shows, however, Φ (Fig. 4f) transitions in a regular manner only during the
3 period of time that serial data is being input or output (Figs. 4d, 4e). See Murphy Declaration, Ex.
4 A (Supplemental Expert Report of Robert J. Murphy Regarding Validity) (hereinafter “Supp.
5 Murphy Report”), ¶ 25. During other times, Φ is flat. As the Manufacturers concede, such a
6 signal is not an external clock signal under the Court’s construction of the term. See, e.g.,
7 Bagherzadeh report, ¶ 104 (“This DQ strobe is not a clock signal, because the DQ strobe is not a
8 continuously periodic signal. It achieves periodicity for the duration of read or write command,
9 providing edge alignment with read data and centered with respect to write data.”)3
10 In Hynix I, the Court accepted Hynix’s argument that the Φ signal in Redwine
11 continues to run periodically at all times, but is “gated (internally on the device) by the CS\
12 signal.” Order Denying Hynix’s Motion for Summary Judgment of Invalidity, 2/28/06
13 (hereinafter “Redwine Order”), at 4-5 (quoting the declaration of Hynix’s expert David Taylor).
14 Regardless of the merits of this argument,4 it cannot apply to Novak which, in contrast to
15 Redwine, does not disclose a CS\ signal. Supp. Murphy Report, ¶ 27. Nor is there an analog in
16 Novak to the upper left portion of Figure 3 in Redwine, which the Court relied on in holding that
17 the CS signal acts as a gate for Φ. Id.
18
2
19 Citations to columns and lines are all to Novak.
3
The Bagherzadeh Report was attached as Exhibit B to the Declaration of Peter A. Detre in
20 Support of Rambus Inc.’s Motion to Preclude the Manufacturers’ Rebuttal Expert Reports on
Infringement, filed Oct. 3, 2008.
21 4
Rambus respectfully submits that Hynix’s argument regarding Redwine was incorrect and that
22 the Court erred in accepting it. As shown in the upper left portion of Figure 3 of Redwine, Φ is
an input to a transistor controlled by the signal CS (chip select) – if CS is high, the chip at issue is
23 selected and Φ will pass through the transistor and be received by the chip. Supp. Murphy
Report, ¶ 28. Although Figure 3 has the word “input” under the Φ symbol, this is not a different
24 symbol name, but simply identifies Φ as an input to the transistor. Any ambiguity on this point is
resolved by Figure 1 of Redwine which shows Φ being input to device without the “input”
25 designation. Thus CS can have no bearing on whether Φ runs continuously or not, because Φ is
input to the transistor – it exists and is either running continuously or not before the transistor
26 controlled by CS can have any effect on it. Id. When CS is high, the signal is passed through to
the chip (thus, the same symbol, Φ, appears as the output of the transistor on Figure 3 also), but,
27 since the same symbol is used to designate the input and the output of the transistor, it is clear that
no changes are made to the signal. As shown in Figure 2 of Redwine, Φ does not run
28 continuously.
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1 C. Novak Does Not Disclose a Write Request or an Operation Code.

2 The Manufacturers argue that Novak receives a write request (“a series of bits used
3 to request a write of data to a memory device”) and an operation code (“one or more bits to
4 specify a type of action”) in the form of values on certain signal lines. The Manufacturers are
5 unable to decide which signal lines allegedly transmit the request or operation code, asserting at
6 various times that it is the signal W\ (Mot. at 12), the signals W\ and TR\ (Mot. at 8, 12), and the
7 signals W\, TR\, and RAS\ (Mot. at 19). In fact, it is clear from the description in Novak that, in
8 order to specify a serial write operation all three signals, as well as Φ, are involved: Φ must
9 toggle to load the data into the shift register, after which TR\ must transition to a low level,
10 followed by W\ transitioning to a low level, followed by RAS\ transitioning to a low level to
11 transfer the data into the array. Fig. 4a, 4b, 4e; Col. 6:50-54; Supp. Murphy Report, ¶ 29. For a
12 serial read operation, W\ must be held high, while TR\ transitions to a low level, followed by
13 RAS\ transitioning to a low level, followed by Φ toggling to output the data. Fig. 4a, 4b, 4d; Col
14 6:54-67; Col. 8:21-36; Supp. Murphy Report, ¶ 29.
15 As is readily seen from these descriptions, the serial write and read operations
16 cannot be specified simply by a code consisting of a series of bits, i.e. 0s and 1s, because the
17 order of the transitions of the signals and the time periods for which they are held is crucial to
18 correctly specify the operations. Supp. Murphy Report, ¶29. This is in marked contrast to the
19 synchronous protocol described in Rambus’s patents and used in the accused products. In such
20 synchronous systems, the signals transmitting the operation code are “sampled” – that is, their
21 values are obtained at a discrete point in time – resulting in a code of 0s and 1s specifying a
22 particular operation. Id. Examining the states of the signal lines in Novak will likewise yield a
23 series of 0s and 1s, but will not specify a particular operation. For example, suppose one were to
24 examine the state of W\, TR\, and RAS\ and determine that they were all low, corresponding to
25 the series of bits 0,0,0. This could have resulted from the specification of a serial write operation
26 if, in fact, TR\ had transitioned low first, followed by W\ and then RAS\. Id. But, if the signals
27 had reached their states of 0,0,0 in a different order, they would not specify a serial write
28 operation. Id. In short, while one could interpret the states of the Novak signal lines at a given
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1 point in time as bits, those bits would not specify a type of action because more information
2 would be required; hence, those bits would not constitute a write request or an operation code.
3 The Manufacturers rely on the Court’s holding in Hynix I that the W signal in
4 Redwine constitutes an operation code. Mot. at 11-12. Regardless of whether the Court’s
5 conclusion in Hynix I was correct,5 the holding does not apply to the Manufacturers’ argument
6 regarding Novak. The Manufacturers’ argument that the Court should simply adopt its prior
7 holding regarding Redwine ignores the fact that different signals are involved in specifying read
8 and write operations in Novak. In particular, Redwine does not include a TR\ signal, Supp.
9 Murphy Report, ¶ 30, but the Manufacturers acknowledge that TR\, as well as W\, is necessary to
10 specify a serial read or write operation in Novak. Mot. at 6 (arguing that TR\ and W\ together
11 constitute a serial write request); Mot. at 13 (arguing that TR\ and W\ together constitute an
12 operation code). Elsewhere in their motion, the Manufacturers admit that, in Novak, RAS\ is also
13 necessary to specify a serial read or write operation. Mot. at 19 (“In Novak, the operation code
14 not only includes the bit values of W\ and TR\ signals but also includes the bit value of RAS\
15 signal.”) As discussed above, it is not only the states of W\, TR\ and RAS\ at a given time, but
16 also their relative times of transitioning, that specify a serial read or write operation in Novak – an
17 issue that the Court did not consider in Hynix I because relative times of transitioning did not
18 arise in connection with Hynix’s argument based on a single signal, W\. The states of the signal
19 lines at a particular point in time could be interpreted as one or more bits, but they would not
20 indicate the relative transitions of the signals and thus are insufficient to specify an operation in
21 Novak. Supp. Murphy Report, ¶ 30. Thus, those signals do not specify a write request or an
22 operation code.
23
24
25 5
Rambus respectfully submits that the Court’s conclusion in Hynix I that the W signal constitutes
26 an operation code was not correct. W – or more accurately, W\ – in Redwine does not suffice to
specify a serial read or write operation. Rather, as shown in Figure 2 of Redwine, to specify a
27 write operation, for example, RAS\ must transition low, after W\ transitions low, and while W\ is
being held low. Supp. Murphy Report, ¶ 31. Thus, the state of W\, by itself, does not specify an
28 operation. Id.
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1 D. Novak Does Not Disclose Receiving or Sampling an Operation Code, or

Sampling Block Size Information, Synchronously with Respect to an
2 External Clock Signal.
3 The Manufacturers assert that Novak discloses receiving or sampling an operation
4 code synchronously with respect to an external clock signal, and sampling block size information
5 synchronously with respect to an external clock signal, but there is no such disclosure in Novak.
6 Even if the states of the control signals in Novak constituted an operation code,
7 which they do not, and even if Φ were an external clock signal, which it is not, Novak does not
8 disclose a known timing relationship between the control signals and Φ. The Manufacturers
9 make a two-fold argument that such a known timing relationship is disclosed. First, they assert
10 that there is a known timing relationship between Φ and control signals such as W\ and TR\
11 because “Φ governs the timing of the generation of control signals.” Mot. at 9. But, this cannot
12 be true. The timing diagram shown in Figure 4 of Novak plainly shows that various control
13 signals, including both W\ and TR\, transition at times when Φ is not active and could not
14 possibly govern their timing. Murphy Report, ¶ 34. Even during the time when Φ is being
15 asserted, comparing the transitions of the W\, TR\, and RAS\, and CAS\ signals with transitions
16 of Φ makes it clear that there is no synchronous relationship between any of those control signals
17 and Φ. Id.
18 Second, relying solely on the opinion of their expert, Mr. McAlexander, the
19 Manufacturers assert that “one skilled in this art would know the W\, TR\ and Φ signals are
20 generated in relation to a system clock, and therefore have a known timing relationship (as
21 interpreted by Rambus) with one another.” Mot. at 9. Novak never discusses a system clock and
22 the Manufacturers can point to nothing in Novak that discloses a single system clock generating
23 W\, TR\ and Φ. In fact, there is no reason that the signals could not be generated independently.
24 Murphy Decl. ¶ 35. At a minimum, there is a material dispute of fact as to whether Novak
25 discloses a known timing relationship between the control signals and Φ precluding summary
26 judgment. Indeed, the Court previously found in Hynix I, in connection with an analogous issue
27 raised by the Redwine patent, that Hynix could not establish for purposes of summary judgment
28 that the W and Φ signals in Redwine had to be generated in relation to a system clock. Redwine
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1 Order at 7.
2 Similarly, Novak does not disclose sampling block size information synchronously
3 with respect to an external clock. While, as discussed below, the A6 and A7 signals identified by
4 the Manufacturers do not constitute block size information, even if they did, there is no disclosure
5 in Novak of a known timing relationship between these signals and Φ. Supp. Murphy Report, ¶
6 36. Indeed, while the Manufacturers point to portions of Novak that purportedly show that the
7 A6 and A7 signals are received by the memory device, they can point to nothing to suggest that it
8 is received synchronously with respect to Φ. Mot. at 17-18.
9 Novak does not disclose “sampling” an operation code for an additional reason.
10 The control signals in Novak that the Manufacturers incorrectly equate with an operation code are
11 sensed rather than sampled. Supp. Murphy Report, ¶ 33. That is, rather than the values of the
12 control signals being obtained at discrete points in time as required for sampling, the control
13 signals must be continuously held and sensed, as shown in the timing diagram in Figure 4. See
14 also, e.g., Col. 8:32-34 (“For a serial read operation, TR\ goes to active-low and the W\ signal is
15 held high during the period seen in Fig. 4b . . . .”) (emphasis added). The Court previously found
16 in Hynix I, in connection with a similar argument made by Hynix, that Hynix could not establish
17 as a matter of law that there is no distinction between “sampling” and “sensing” (Redwine Order
18 at 6-7); neither can the Manufacturers.
19 E. Novak Does Not Disclose Sampling or Inputting Data in Response to a Write
Request or Operation Code.
20
As discussed above, Novak does not disclose a write request or an operation code,
21
however, even if the TR\ and W\ signals did constitute a write request or operation code
22
designating a write operation as the Manufacturers argue, Novak still would not disclose inputting
23
data or sampling data – that is, obtaining the data at discrete points in time, according to the
24
Court’s construction – in response to those signals. A serial write operation in Novak, as shown
25
in the timing diagram of Figure 4, begins with up to 256 bits being input into the shift register.
26
Supp. Murphy Report, ¶ 37. It is this part of the operation that the Manufacturers associate with
27
inputting or sampling the data using the Φ signal. Mot. at 8 (“As indicated at Figure 4e and 4f,
28
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1 the write data is obtained at discrete points of time by the transitions of the external clock signal
2 Φ.”) Only after the data has been loaded into the shift register do TR\ and W\ (as well as RAS\)
3 transition, directing the memory device to transfer the data in the shift register into the memory
4 array. See Fig. 4a, 4b, and 4e (showing the transitions on the control lines designating a write
5 operation on 4a and 4b occurring after the data has been loaded into the shift register on 4e);
6 Supp. Murphy Report, ¶ 37. Since the transitions that the Manufacturers identify with the write
7 request or operation code occur after what the Manufacturers identify with the input or sampling
8 of data, it is clear that the sampling cannot have been “in response to” the write request or
9 operation code. Supp. Murphy Report, ¶ 37.
10 F. Novak Does Not Disclose a Synchronous Memory Device.
11 The Court has construed “synchronous memory device” as “a memory device that
12 receives an external clock signal which governs the timing of the response to a transaction
13 request.” A “transaction request,” in turn, is “a series of bits used to request performance of a
14 transaction with a memory device.” As discussed above, Novak does not disclose an external
15 clock signal. Moreover, for the same reasons that Novak does not disclose a write request or an
16 operation code, it does not disclose a transaction request. Thus, Novak does not disclose a
17 synchronous memory device.
18 In addition, even if the Φ signal could be considered to be an external clock, and
19 even if the serial read and write operations identified by the Manufacturers could be considered to
20 be transaction requests, Novak still would not disclose a synchronous memory device. As the
21 Manufacturers note, Novak discloses a Video Random Access Memory, or VRAM. Mot. at 1.
22 This is simply a conventional, asynchronous DRAM, permitting the usual asynchronous read and
23 write operations, with a shift register appended to allow for the additional serial read and write
24 operations on which the Manufacturers focus. Col. 5:3-12; Supp. Murphy Report, ¶39. But the
25 control signals that the Manufacturers associate with transaction requests (namely, serial read and
26 write operations) in Novak – RAS\, CAS\, W\, and TR\ – are received asynchronously and are not
27 governed by Φ. Supp. Murphy Report, ¶ 39. Indeed, they cannot be governed by Φ because
28 Figure 4 shows the relevant transitions of those control signals occurring at times when Φ is not
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1 active – in fact, as noted above, the transitions of the control signals that the Manufacturers
2 identify with a write request occur after Φ has ceased being active and the data has already been
3 loaded into the shift register. Id. Φ cannot govern the timing of response to a transaction request
4 specifying a serial write operation when what the Manufacturers identify with the response occurs
5 prior to the transaction request itself. Nor could Φ govern the timing of the response to a
6 transaction request specifying a serial read operation because, as Φ is not active at the time of the
7 request, it cannot be used to time the period between that request and the output of data from the
8 shift register which the Manufacturers’ identify as the response. Thus, the VRAM disclosed by
9 Novak is not a synchronous memory device.6
10 G. Novak Does Not Disclose Block Size Information.
11 The Manufacturers argue that two bits received on the A6 and A7 lines in Novak
12 constitute block size information. The two bits in question, however, do not specify an amount of
13 data transferred; rather they specify the location from which, or to which, data will be transferred.
14 Novak includes a 256-bit shift register which is divided into four parts, each being
15 a 64-bit shift register. Col. 7:3-5. Novak describes four “taps” that are used to select “whether
16 one, two, three, or all four 64-bit shift registers are accessed.” Col. 7:16-17. As Novak explains,
17 the purpose of selecting only certain portions of the shift register to be accessed is not to control
18 the amount of data transferred but to make it easier to reach certain bits stored in the shift register.
19 Supp. Murphy Report, ¶ 41. Since the data in the shift register must be shifted in or out in order,
20 by dividing the shift register into four 64-bit portions and allowing the user to tap into the one of
21 interest, “any bit of data may be accessed in 64 shifts or less, rather than 256 shifts.” Col. 7:38-
22 40.
23 The two bits that the Manufacturers assert correspond to block size information
24 simply select the tap:
25 6
That a VRAM would not be considered a synchronous memory device by a person of skill in the
26 art is also supported by the fact that, later on, when a memory was introduced that was specially
suited for video applications in which the control signals were received synchronously with
27 respect to an external clock, it was designated a synchronous VRAM or SVRAM. Supp. Murphy
Report, Ex. 3. Of course, this would make no sense if the prior VRAMs had already been
28 considered to be synchronous memory devices.
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1
[I]f the two bits are both 0, then all 256 bits in the shift register may
2 be shifted out. If the two bits are 01, then 192 bits, starting at bit
64, may be shifted out. If the two bits are 10, then 128 bits, starting
3 at bit 128, may be shifted out. The two bit code 11, selects the last
64 bits starting at bit number 192 and then these last 64 bits may be
4 shifted out.
5 Col. 7:48-54. Thus, the two bits at issue identify the starting point for data transfer in the shift
6 register (the 0th bit, the 64th bit, the 128th bit, or the 192nd bit), but do not specify how much data is
7 to be transferred beginning at that point. Supp. Murphy Report, ¶ 42. For example, if the two
8 bits are 01, then we know that the data transfer starts at bit 64 of the shift register, but whether
9 one bit, or two bits, or 192 bits are transferred beginning at that point is not specified. Id. As
10 Novak states, in that circumstance “192 bits, starting at bit 64, may be shifted out.” Col. 7:50-51
11 (emphasis added). In other words, 192 bits is the maximum that may be shifted out starting at
12 that point of the shift register; Novak does not specify the actual amount to be shifted out.
13 Novak fails to disclose block size information for an additional reason. The Court
14 has construed block size information as “information that specifies the total amount of data that is
15 to be transferred on the bus in response to a transaction request.” The “bus” at issue is the set of
16 signal lines that connect the memory controller to the memory devices, i.e. the “address/data bus”
17 combined with the “control bus” in Figure 1 of Novak, the controller corresponding to the
18 “microcomputer chip.” But data transferred from the shift register is not transferred on the bus.
19 Rather, it is transferred on a separate signal line that connects directly to the video display or CRT
20 tube. Fig. 1; Col. 4:2-6; Supp. Murphy Report, ¶ 43.
21 H. Novak Does Not Disclose Sampling Data After a Predetermined Number of

Clock Cycles or After a Delay Time Transpires.
22
The Manufacturers argue that Novak discloses sampling data, in response to an
23
operation code, after a predetermined number of clock cycles of the external clock, or after a
24
delay time transpires, because when data is being read from the Novak shift register at the same
25
time that new data is being written into the shift register, “[i]t would be known to one of ordinary
26
skill in the art . . . that the start of writing data is delayed by at least one half clock cycle (a
27
‘predetermined number’) from the start of reading data.” Mot. at 13; see also Mot. at 24 (making
28
- 10 - JUDGMENT OF INVALIDITY (MSJ #2)
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1 the same argument with respect to “delay time”). In effect, the Manufacturers choose an event –
2 in this case the start of data being output from the Novak shift register – and argue that writing
3 data to the shift register cannot begin until half a clock cycle later. Regardless of whether this is
4 true or not, it is entirely irrelevant to Rambus’s claims which require that there be a
5 predetermined number of clock cycles, or a delay time, between when an operation code
6 specifying a write operation is transmitted and when the corresponding data is input. Supp.
7 Murphy Report, ¶ 44. The Manufacturers do not even attempt to show that such a predetermined
8 number of clock cycles or delay time is disclosed by Novak. Moreover, no such predetermined
9 number of clock cycles or delay time could exist because, as discussed in Section II.F above,
10 what the Manufacturers identify as the operation code occurs after the time that they allege the
11 data is sampled.
12 I. Novak Does Not Disclose Precharge Information.
13 The Court has construed “precharge information” as “one or more bits indicating
14 whether the sense amplifiers and/or bit lines (or a portion of the sense amplifiers and/or bit lines)
15 should be precharged.” The Manufacturers assert that the RAS\ signal in Novak constitutes
16 precharge information because “when RAS\ goes high, the precharge portion of the read or write
17 cycle is activated.” Mot. at 19. As an initial matter, RAS\ does not constitute a “bit” of
18 information contained in an operation code because, as discussed above, the control signals in
19 Novak must transition in a particular order and be sensed over extended periods of time for the
20 device to operate correctly. Supp. Murphy Report, ¶ 45.
21 Moreover, even if the state of RAS\ were a bit, the Manufacturers concede that
22 Novak does not disclose any relationship between RAS\ and precharging; instead, they assert that
23 “Novak specifically references the operation of the memory device described in U.S. Pat. No.
24 4,239,993,” and that that patent “describes the use of RAS\ to start a precharge operation.” Id.
25 But Novak simply states that the device in the ’993 patent is “[o]ne example of a memory device”
26 which, with the addition of an appropriate shift register, could be used in the disclosed invention.
27 Col. 5:3. This is hardly an incorporation by reference of the full disclosure of the ’993 patent into
28 Novak.
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1 Most importantly, however, even if RAS\ were a bit, and even if the
2 Manufacturers were entitled to rely on the disclosure of the ’993 patent in support of their
3 anticipation arguments, the Manufacturers simply assert that whenever RAS\ goes high at the end
4 of a read or write operation, precharging is performed. Mot. at 19-20. This is not precharge
5 information. Rather, as the Court’s construction indicates by its use of the word “whether,”
6 precharge information must allow for precharging or not depending on the content of the
7 information. The Court’s construction of precharge information is carried over from Hynix I,
8 where the Court made this quite clear:
9 [T]he precharge information does not simply convey a value
representing the establishment of a pre-defined voltage state [i.e.
10 precharging]. Instead it conveys whether the device should
precharge the “sense amps (and hence the bit lines)” (’263 patent,
11 cl. 10 l. 43), or not precharge the sense amps so that they can retain
the data to be sensed on the next read (’263 patent, cl. 10, ll 25-30).
12 . . . [T]he court finds that the specification implies “precharge
information” as information relating specifically to whether or not a
13 component of the device should be precharged.
14 Hynix I Claim Construction Order at 22-23 (emphasis added). Since, according to the
15 Manufacturers’ argument, RAS\ simply signals the end of a read or write operation at which time
16 the device always precharges, Novak does not disclose precharge information.7 Supp. Murphy
17 Report, ¶ 46.
18 J. Novak Does Not Disclose Precharge Information or a Precharge Instruction
as Part of an Operation Code.
19
Even if the RAS\ signal going high could constitute precharge information, as the
20
Manufacturers argue, Novak still would not disclose precharge information being transmitted as
21
part of an operation code specifying a read or write operation. Likewise, Novak does not disclose
22
such an operation code further specifying that sense amplifiers be precharged. As discussed
23
above in Section II.C, the serial read and write operations on which the Manufacturers rely for
24
their arguments are specified by RAS\going low after appropriate transitions of the TR\ and W\
25
7
26 The Manufacturers argue, alternatively, that Novak discloses a refresh operation whenever there
is a serial read or write, which necessarily includes precharging. Mot. at 20. This is, in effect, the
27 same argument – the end of a serial read or write operation is signaled by the RAS\signal going
high, at which time precharging takes place. Supp. Murphy Report, ¶ 47. Thus, this argument
28 suffers from the same infirmities as the one relying on the RAS\ signal directly.
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1 signals. RAS\ must then be held low during the duration of the operation, and, finally, transition
2 to a high voltage to signal end of the operation, after which precharging occurs. Supp. Murphy
3 Report, ¶ 48. Thus, although RAS\must go low in order for the serial read or write operation to
4 occur, the Manufacturers argument requires that a later transition of RAS\ to high must actually
5 be part of the same operation code specifying the serial read or write operation in the first place.
6 This is nonsensical. Not only is it clear that RAS\ going high could not be part of any operation
7 code specifying a read or write operation, the Manufacturers’ argument to the contrary exposes
8 the incoherence that results from trying to identify the voltage values in a transition-based
9 asynchronous system with bit values in a synchronous system. In this case, it has the
10 Manufacturers arguing that RAS\ going low (bit=0?) and RAS\ later going high (bit=1?) are part
11 of the same operation code.
12 K. Novak Does Not Anticipate the Claims at Issue.
13 For at least the reasons set forth above, Novak does not disclose numerous claim
14 elements in each of the claims that are the subject of the Manufacturers’ motion. It follows that
15 Novak cannot anticipate any of those claims. At a minimum, and especially in light of the high
16 burden that the Manufacturers must meet, there can be no doubt that there remains a genuine
17 dispute of material fact as to anticipation of each of claims at issue. A number of limitations of
18 each of those claims that are not disclosed by Novak are set forth below.
19 1. Novak Does Not Anticipate Claim 14 of the ’184 Patent.
20 Claim 14 of the ’184 patent depends on claim 13 as follows:
21 13. A method of operation of a memory device, wherein the
memory device includes a plurality of memory cells, the method of
22 operation of the memory device comprises:
23 receiving first block size information from a master, wherein the
first block size information defines a first amount of data to be
24 sampled by the memory device in response to a write request;
25 receiving a first write request from the master; and
26 sampling a first portion of the first amount of data synchronously
with respect to a first transition of an external clock signal and a
27 second portion of the first amount of data synchronously with
respect to a second transition of the external clock signal.
28
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1 14. The method of claim 13 wherein the first transition of the

external clock signal is a rising edge transition and the second
2 transition of the external clock signal is a falling edge transition.
3 For the reasons set forth above, numerous elements of claim 14 are not disclosed
4 in Novak. First, as set forth in Section II.G, Novak does not disclose receiving block size
5 information and, consequently, does not disclose sampling a first amount of data (since the first
6 amount of data is defined by the non-existent block size information). Second, as forth in Section
7 II.C, Novak does not disclose a write request. Third, as set forth in Section II.E, Novak does not
8 disclose sampling data in response to a write request. Fourth, as set forth in Section II.B, Novak
9 does not disclose an external clock signal.

11 Claim 33 of the ’120 patent depends on claims 26 and 29 as follows:
12 26. A synchronous dynamic random access memory device

having at least one memory section including a plurality of memory
13 cells, the memory device comprising:
14 clock receiver circuitry to receive an external clock signal;
15 input receiver circuitry, including a first plurality of input receivers
to sample block size information synchronously with respect to the
16 external clock signal, wherein the block size information defines an
amount of data to be output by the memory device in response to a
17 first operation code; and
18 a plurality of output drivers to output the amount of data in
response to the first operation code.
19
29. The memory device of claim 26 wherein the input receiver
20 circuitry samples the first operation code synchronously with
respect to the external clock signal.
21
33. The memory device of claim 29 wherein the first operation
22 code includes precharge information.
24 in Novak. First, as set forth in Section II.F, Novak does not disclose a synchronous memory
25 device. Second, as set forth in Section II.B, Novak does not disclose an external clock signal.
26 Third, as set forth in Section II.G, Novak does not disclose block size information and,
27 consequently, does not disclose an amount of data (since the amount of data is defined by the
28 non-existent block size information). Fourth, as forth in Section II.C, Novak does not disclose an
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1 operation code. Fifth, as set forth in Section II.D, Novak does not disclose sampling block size
2 information, or sampling an operation code, synchronously with respect to an external clock
3 signal. Sixth, as set forth in Section II.I, Novak does not disclose precharge information.
4 Seventh, as set forth in Section II.J, Novak does not disclose precharge information as part of an
5 operation code.
8 14. A method of operation in a synchronous memory device,
wherein the memory device includes a plurality of memory cells,
9 the method of operation of the memory device comprises:
10 receiving first block size information from a memory controller,
wherein the memory device is capable of processing the first block
11 size information, wherein the first block size information represents
a first amount of data to be input by the memory device in response
12 to an operation code;
13 receiving the operation code, from the memory controller,
synchronously with respect to an external clock signal; and
14
inputting the first amount of data in response to the operation code.
15
15. The method of claim 14 wherein inputting the first amount
16 of data includes receiving the first amount of data synchronously
with respect to the external clock signal
17
16. The method of claim 15 wherein the first amount of data is
18 sampled over a plurality of clock cycles of the external clock signal.
20 in Novak. First, as set forth in Section II.F, Novak does not disclose a synchronous memory
21 device. Second, as set forth in Section II.G, Novak does not disclose block size information and,
22 consequently, does not disclose a first amount of data (since the first amount of data is defined by
23 the non-existent block size information). Third, as forth in Section II.C, Novak does not disclose
24 an operation code. Fourth, as set forth in Section II.B, Novak does not disclose an external clock
25 signal. Fifth, as set forth in Section II.D, Novak does not disclose receiving an operation code
26 synchronously with respect to an external clock signal. Sixth, as set forth in Section II.E, Novak
27 does not disclose inputting data in response to an operation code.
28
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3 1. A synchronous integrated circuit device having a memory array

which includes dynamic random access memory cells, wherein the
4 integrated circuit device comprises:
5 a clock receiver to receive an external clock signal;
6 a plurality of sense amplifiers, coupled to the memory array, to
sense data from the dynamic random access memory cells; and
7
a plurality of input receivers to sample an operation code
8 synchronously with respect to the external clock signal, the
operation code including precharge information, wherein, in
9 response to the precharge information, the plurality of sense
amplifiers is automatically precharged after the data is sensed.
10
2. The integrated circuit device of claim 1 wherein the operation
11 code specifies a read operation, and wherein the integrated circuit
device further includes a plurality of output drivers to output first
12 and second portions of the data in response to the operation code
specifying a read operation.
13
3. The integrated circuit device of claim 2 wherein:
14
the plurality of output drivers output the first portion of the data
15 synchronously with respect to a rising edge transition of the
external clock signal; and
16
the plurality of output drivers output a second portion of the data
17 synchronously with respect to a falling edge transition of the
external clock signal.
18
For the reasons set forth above, numerous elements of claim 3 are not disclosed in
19
Novak. First, as set forth in Section II.F, Novak does not disclose a synchronous memory device,
20
and, for the same reasons, does not disclose a synchronous integrated circuit device having a
21
memory array. Second, as set forth in Section II.B, Novak does not disclose an external clock
22
signal. Third, as forth in Section II.C, Novak does not disclose an operation code. Fourth, as set
23
forth in Section II.D, Novak does not disclose sampling an operation code synchronously with
24
respect to an external clock signal. Fifth, as set forth in Section II.I, Novak does not disclose
25
precharge information. Sixth, as set forth in Section II.J, Novak does not disclose precharge
26
information as part of an operation code.
27
28
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2 Claim 43 of the ’051 patent depends on claims 34 as follows:
3 34. A memory device having a plurality of memory arrays, the

memory device comprising:
4
first input receiver circuitry to receive an operation code
5 synchronously with respect to an external clock; and
6 second input receiver circuitry to sample data, in response to the
operation code, after a predetermined number of clock cycles of the
7 external clock.
8 43. The memory device of claim 34 wherein the memory device is a
synchronous dynamic random access memory.
9
For the reasons set forth above, numerous elements of claim 33 are not disclosed
10
in Novak. First, as set forth in Section II.B, Novak does not disclose an external clock. Second,
11
as forth in Section II.C, Novak does not disclose an operation code. Third, as set forth in Section
12
II.D, Novak does not disclose receiving an operation code, synchronously with respect to an
13
external clock. Fourth, as set forth in Section II.E, Novak does not disclose sampling data in
14
response to an operation code. Fifth, as set forth in Section II.H, Novak does not disclose
15
sampling data after a predetermined number of clock cycles.
16
6. Novak Does Not Anticipate Claim 34 of the ’037 Patent.
17
Claim 34 of the ’037 patent claims:
18
34. A method of operation of a synchronous dynamic random
19 access memory device, wherein the method comprises:
20 sampling an operation code synchronously with respect to an
external clock signal, wherein the operation code specifies that the
21 memory device sample data to be written into a plurality of
dynamic memory cells, and wherein the operation code further
22 specifies that the memory device precharge a plurality of sense
amplifiers;
23
sampling the data, in response to the operation code, after a delay
24 time transpires;
25 sampling address information to identify a subset of the plurality of
dynamic memory cells;
26
writing the data to the subset of the plurality of dynamic memory
27 cells using the plurality of sense amplifiers; and
28 precharging the plurality of sense amplifiers in response to the
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1 operation code, wherein the plurality of sense amplifiers is

precharged automatically after the data is written.
2
For the reasons set forth above, numerous elements of claim 34 are not disclosed
3
in Novak. First, as set forth in Section II.F, Novak does not disclose a synchronous memory
4
device. Second, as set forth in Section II.B, Novak does not disclose an external clock signal.
5
Third, as forth in Section II.C, Novak does not disclose an operation code. Fourth, as set forth in
6
Section II.D, Novak does not disclose sampling an operation code synchronously with respect to
7
an external clock signal. Fifth, as set forth in Section II.J, Novak does not disclose an operation
8
code specifying a write operation (i.e. that the memory device sample data) and further specifying
9
precharging. Sixth, as set forth in Section II.H, Novak does not disclose sampling data after a
10
delay time transpires.
11
III. CONCLUSION
12
For the reasons set forth above, the Court should deny the Manufacturers’ motion
13
for summary judgment of invalidity of the claims at issue based on Novak.
14
15 DATED: November 14, 2008 MUNGER, TOLLES & OLSON LLP

SIDLEY AUSTIN LLP
16 McKOOL SMITH PC
17
18
By: /s/ Peter A. Detre
19 PETER A. DETRE
20 Attorneys for RAMBUS INC.
21
22
23
24
25
26
27
28
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Rambus'S Opp. To Joint Mot. For Summary Judgment of Invalidity (MSJ #2) C 05-00334 RMW C 05-02298 RMW C 06-00244 RMW

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Case 5:05-cv-00334-RMW Document 2537 Filed 11/14/2008 Page 1 of 22

1 Gregory P. Stone (SBN 078329) Rollin A. Ransom (SBN 196126)

15 NORTHERN DISTRICT OF CALIFORNIA, SAN JOSE DIVISION

2 RAMBUS INC., CASE NO. C 05-02298 RMW

11 MICRON TECHNOLOGY INC., et al,

10 STATUTES AND RULES

4 a synchronous memory device as claimed by Rambus’s patents. Rather, Novak discloses a

9 to disclose numerous limitations of the claims at issue.

1 C. Novak Does Not Disclose a Write Request or an Operation Code.

10 followed by W\ transitioning to a low level, followed by RAS\ transitioning to a low level to

14 6:54-67; Col. 8:21-36; Supp. Murphy Report, ¶ 29.

1 D. Novak Does Not Disclose Receiving or Sampling an Operation Code, or

20 tube. Fig. 1; Col. 4:2-6; Supp. Murphy Report, ¶ 43.

21 H. Novak Does Not Disclose Sampling Data After a Predetermined Number of

1 14. The method of claim 13 wherein the first transition of the

9 does not disclose an external clock signal.

10 2. Novak Does Not Anticipate Claim 33 of the ’120 Patent.

12 26. A synchronous dynamic random access memory device

1 4. Novak Does Not Anticipate Claim 3 of the ’446 Patent.

3 1. A synchronous integrated circuit device having a memory array

1 5. Novak Does Not Anticipate Claim 43 of the ’051 Patent.

3 34. A memory device having a plurality of memory arrays, the

1 operation code, wherein the plurality of sense amplifiers is

15 DATED: November 14, 2008 MUNGER, TOLLES & OLSON LLP

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