MODULE IV

Synchronous and Asynchronous sequential circuit

Asynchronous sequential circuit: Synchronous sequential circuit:
 These circuits do not use a clock signal but uses the  These circuits use clock signal
pulses of the inputs.  The output pulse is the same duration as the
 These circuits are faster than synchronous sequential clock pulse for the clocked sequential
circuits.
circuits.
 We use asynchronous sequential circuits when speed of
operation is important   Since they wait for the next clock pulse to
 Circuits are used in low power and high speed operations arrive to perform the next operation, so these
circuits are bit slower compared to
asynchronous.
 Synchronous circuits are used in counters,
shift registers, memory units.

Latches
 Latches are digital circuits that store a single bit of information and hold its value until it is updated by new
input signals.
 It is is a special type of logical circuit and have two stable states low and high (1 or 0)
 Types of Latches
S-R (Set-Reset) Latches:
 The SR latch is a circuit with two cross-coupled NOR
gates or two cross- coupled NAND gates
 Two inputs labeled S for set and R for reset.
 The outputs Q and Q’ must be compliment to each other

SR latch with NOR-gate

 When output Q = 1 and Q’ = 0, the latch is said to be in
the set state .
 When Q = 0 and Q’ = 1, it is in the reset state

SR latch with NAND-gate

 When output Q = 0 and Q’ = 1, the latch is said to be in
the set state .
 When Q = 1 and Q ‘= 0, it is in the reset state
 When Q = 1 and Q ‘= 1, it is in not used latch is said to be
in a forbidden state

D (Data) Latches:
 D latches are also known as transparent latches and are
implemented using two inputs: D (Data) and a clock
signal. The output of the latch follows the input at the D
terminal as long as the clock signal is high. When the
clock signal goes low, the output of the latch is stored and
held until the next rising edge of the clock
FLIP FLOPS:
 Difference between flip-flop and latch is that the flip-flop
is an edge- triggered type of memory circuit while the
latch is a level-triggered type.
 It means that the output of a latch changes whenever the
input changes.
 Flip-flops and latches are fundamental building blocks of
digital electronics systems used in computers,
communications, and many other types of systems. Both
are used as data storage elements

Types of Flip–Flops

• S-R flip-flop
• J-K flip-flop
• D flip-flop
• T flip-flop
 S-R Flip Flop( SET-RESET Flip Flop)
It has a set input (S) and a reset input
(R).When in this circuit when S is set as
active, the output Q would be high and the
Q’ will be low.
If R is set to active then the output Q is low
and the Q’ is high.

J-K Flip-flop- Jack Kilby flip flop

Because of the invalid state corresponding to

S=R=1 in the SR flip-flop, there is a need of
another flip-flop.

The JK flip-flop operates with only positive

or negative clock transitions.

The operation of the JK flip-flop is similar

to the SR flip-flop.

If both J and K are high, then at the clock

edge, the output will toggle from one state to
the other.

T Flip-flop- Toggle flip flop

• The T flop is obtained by connecting the J and K
inputs together.
• The flip-flop has one input terminal and clock input.
• These flip-flops are said to be T flip-flops because
of their ability to toggle the input state.
• Toggle flip-flops are mostly used in counters
 D FLIP FLOP-Data flip flop
• In a D flip-flop, the output can only be changed at positive
or negative clock transitions, and when the inputs
changed at other times, the output will remain unaffected.
• The output (Q) is same as input and changes only at
active transition of clock

Master slave J K- Flip Flop

Race Around Condition in JK Flip-Flop

• In "JK Flip Flop", when both the inputs and CLK set to 1
for a long time, then Q output toggle until the CLK is 1.
Thus, unreliable output produces. This problem is referred
to as a race-around condition in JK flip-flop. To overcome
race around condition MSFF has been designed.
• Master-slave flip flop is constructed by combining two JK
flip flops.
• Master Slave JK Flip Flop has two JK Flip Flops
connected together in series combination along with an
inverter which gives inverted clock pulse to slave flip flop.
• In these two flip flops, the 1st flip flop work as "master",
called the master flip flop, and the 2nd work as a "slave",
called slave flip flop.

Triggering in Flip Flop 1. Level Triggering

• Clock Signal and Triggering There are two levels present in the clock signal –
• The clock signal refers to a periodic signal where the ON the logic Low and the logic High.
and OFF times do not need to be the same.
• Thus, whenever the ON and OFF times of the clock signal • Positive Level Triggering
happen to be the same, we use a square wave to represent If the sequential circuit is operated with the
the clock signal. clock signal when it is in logic high, then that
Types of Triggering type of triggering is known as a positive level
• Level triggering triggering.
• Edge Triggering

• Negative Level Triggering

If the sequential circuit is operated with the
clock signal when it is in logic low, then that
type of triggering is known as a negative level
triggering.
 Edge Triggering
This transition either occurs from Logic High
to Logic Low or from Logic Low to Logic
High.
• Positive edge triggering
If the sequential circuit is operated with the
clock signal transit from low to high. then that
type of triggering is known as a positive edge
triggering

• Negative edge triggering

If the sequential circuit is operated with the
clock signal transit from low to high. then that
type of triggering is known as a positive edge
triggering

COUNTERS
Counters are used in digital electronics for counting
purpose, they can count specific event happening in the
circuit.

Counter works in two modes

Up counter
Down counter

Asynchronous Counter --Ripple counter

In asynchronous counter don’t use universal clock, only
first flip flop is driven by main clock and the clock input
of rest of the following flip flop is driven by output of
previous flip flops.

Q0 is changing as soon as the rising edge of clock pulse is

encountered, Q1 is changing when rising edge of Q0 is
encountered(because Q0 is like clock pulse for second
flip flop) and so on.

In this way ripples are generated through Q0,Q1,Q2,Q3

hence it is also called RIPPLE counter.

A ripple counter is a cascaded arrangement of flip flops

where the output of one flip flop drives the clock input of
the following flip flop
 Asynchronous 4 bit UP Counter

SYNCHRONOUS 4 BIT BINARY DOWN COUNTER

3 bit Asynchronous Binary Counter

 3 bit asynchronous counter has 8 states due to its 3
flipflops
 Counter progresses through a binary count of 0 through
7 then recycles to the zero state
 Asynchronous MOD 10 (BCD/ DECADE Counter)
 Counter with 10 states in their sequence are called Decade
counter.
 It has a count sequence of 0 through 9 is a BCD decade
counter because its 10 state sequence produces the BCD
code.
 Decade counter requires 4 flipflops and NAND gate is
connected to them

Synchronous Counter
Synchronous counter has one global clock which drives
each flip flop so output changes in parallel.The one
advantage of synchronous counter over asynchronous
counter is, it can operate on higher frequency than
asynchronous counter as it does not have cumulative delay
because of same clock is given to each flip flop.
 RING COUNTER
 A ring counter is a Shift Register (a cascade
connection of flip-flops) with the output of the last
flip flop connected to the input of the first.
 QD and QD’ are connected to the J and K inputs of
the flipflop A

Shift Register
Types of shift regosters:
A group of flip flops which is used to store
multiple bits of data and the data is moved 1. Serial In Serial Out
from one flip flop to another is known as Shift
2. Serial In Parallel Out
Register.
A Shift Register can shift the bits either to the
3. Parallel In Serial Out
left or to the right.
A Shift Register, which shifts the bit to the left,
4. Parallel In Paralell Out
is known as "Shift left register", and it shifts the
bit to the right, known as " Shift Right register"
 1. Serial In Serial Out

 In "Serial Input Serial Output", the data is

shifted "IN" or "OUT" serially.

 In SISO, a single bit is shifted at a time in

either right or left direction under clock
control.

Serial IN Parallel OUT

 In the "Serial IN Parallel OUT" shift register, the

data is passed serially to the flip flop, and
outputs are fetched in a parallel way.
 In SIPO, the input of the second flip flop is the
output of the first flip flop, and so On. The same
clock signal is applied to each flip flop

Parallel-in to Serial-out (PISO)

 In Parallel-in to Serial-out shift register
data is loaded
into the register in a parallel format in which all the
data bits enter their inputs simultaneously, to the
parallel input pins PA to PD of the register. The data
is then read out sequentially

Parallel IN Parallel OUT

In "Parallel IN Parallel OUT", the inputs and the
outputs come in a parallel way in the register