Logicgates
Logicgates
Contents
Digital Logic Gates and Truth Tables .............................................................................................................................. 2
Basic Logic Gates................................................................................................................................................................ 2
Combinational Gates ........................................................................................................................................................ 3
Universal Gates ................................................................................................................................................................... 4
Simplification of Logic expressions.................................................................................................................................. 6
Laws of Boolean Algebra................................................................................................................................................. 6
Standard Logical Expressions ........................................................................................................................................ 7
Simplify Logic Expressions (Boolean Expression Simplification) ...................................................................... 8
Digital Circuits Design......................................................................................................................................................... 13
Design Circuits for the following expressions ....................................................................................................... 13
Design Circuits for the following expressions using only NAND gates ...................................................... 15
Design Circuits for the following expressions using only NOR gates .......................................................... 16
CPU and Memory with Logic Gates ............................................................................................................................... 17
Building blocks of CPU (Combinational Circuits) ................................................................................................. 17
Storing Bits in Digital Circuits (Memory – Sequential Circuits) ....................................................................... 18
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OR Gate
Represents logical addition (+). The OR gate is an electronic circuit that gives a high output (1) if one
or more of its inputs are high. A plus (+) is used to show the OR operation.
A Q A B Q
0 0 0
B
0 1 1
1 0 1
Q=A+B
1 1 1
AND Gate
Represents logical multiplication. The AND gate is an electronic circuit that gives a high output (1)
only if all its inputs are high. A dot (.) is used to show the AND operation i.e. A.B. Bear in mind that
this dot is sometimes omitted i.e. AB
A A B Q
Q 0 0 0
B 0 1 0
1 0 0
1 1 1
Q = A.B
XOR Gate
Represents logical exclusive addition. The 'Exclusive-OR' gate is a circuit which will give a high output
if either, but not both, of its two inputs are high. An encircled plus sign ( ) is used to show the EOR
operation.
A A B Q
Q 0 0 0
B 0 1 1
1 0 1
1 1 0
Q=A B
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NOT Gate
The NOT gate is an electronic circuit that produces an inverted version of the input at its output. It is
also known as an inverter. If the input variable is A, the inverted output is known as NOT A. This is
also shown as A', or A with a bar over the top, as shown at the outputs. The NAND logic gate can be
configured to produce a NOT gate. It can also be done using NOR logic gates in the same way.
A Q
0 1
A Q 1 0
Q=A
̅
COMBINATIONAL GATES
These are formed by combining the basic logic gates except not gate, with not gate.
NAND Gate
This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The outputs of all
NAND gates are high if any of the inputs are low. The symbol is an AND gate with a small circle on
the output. The small circle represents inversion.
A A B Q
Q 0 0 1
B 0 1 1
1 0 1
1 1 0
Q = ̅̅̅̅̅
A. B
NOR Gate
This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs of all NOR
gates are low if any of the inputs are high. The symbol is an OR gate with a small circle on the output.
The small circle represents inversion.
A A B Q
Q 0 0 1
B 0 1 0
1 0 0
1 1 0
Q = ̅̅̅̅̅̅̅
A+B
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XNOR Gate
The 'Exclusive-NOR' gate circuit does the opposite to the EOR gate. It will give a low output if either,
but not both, of its two inputs are high. The symbol is an EXOR gate with a small circle on the output.
The small circle represents inversion.
A A B Q
Q
0 0 1
B 0 1 0
1 0 0
1 1 1
Q = ̅̅̅̅̅̅
A B
UNIVERSAL GATES
The NAND gate and the NOR gate can be said to be universal gates since combinations of them can
be used to accomplish any of the basic operations and can thus produce an inverter, an OR gate or
an AND gate. In practice, this is advantageous since NAND and NOR gates are economical and easier
to fabricate and are the basic gates used in all IC digital logic families.
OR using NAND
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OR using NOR
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Associative
Distributive
Identity
Redundancy
De Morgan’s
*Laws from TIM: Idempotent Law, Inverse/Complement Law, Double Complement Law
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Fill the following table with Minterms and Maxterms based on A, B and C.
A B C Minterm Maxterm
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
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A B C F (Output)
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1
F (A, B, C) =
F (A, B, C) =
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DESIGN CIRCUITS FOR THE FOLLOWING EXPRESSIONS USING ONLY NAND GATES
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DESIGN CIRCUITS FOR THE FOLLOWING EXPRESSIONS USING ONLY NOR GATES
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Half Adder
With the help of half adder, we can design circuits that are capable of performing simple addition with
the help of logic gates.
A B S C
0 0
0 1
1 0
1 1
Full Adder
The main difference between a half-adder and a full-adder is that the full-adder has three inputs and
two outputs. The first two inputs are A and B and the third input is an input carry designated as Carry
In. When a full adder logic is designed we will be able to string eight of them together to create an 8-
bit adder and cascade the carry bit from one adder to the next. However there are two versions which
performs the same function.
A B C in S C out
0 0
0 1
1 0
1 1
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A B C in S C out
0 0
0 1
1 0
1 1
𝐒̅ ̅
𝐑 𝐐 ̅
𝐐
1 0
0 0
0 1
0 0
1 1
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𝐒 𝐑 𝐐 ̅
𝐐
1 0
0 0
0 1
0 0
1 1
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