Laptop Chip Level Repair Guide 478

Chapter 19

Analysis of AMD Platform

Timing Sequence

AMD platform mainly has nVIDIA and AMD two chipsets, at present, only
AMD is selling on the market although nVIDIA has quit, but there is still a part of
the amount of nVIDIA maintenance. In this chapter, use as the "the standard
timing sequence diagram and analysis of the circuit of using this chipset models" to
analyze the timing sequence features of two chipsets.

19.1: The Standard Timing Sequence of

nVIDIA
This section describes nVIDIA chipset motherboard matched AMD CPU. The
standard timing sequence of nVIDIA chipset is shown in figure 19-1, the
explanation of the signal in the figure is below.

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Figure 19-1: The standard timing sequence of nVIDIA chipset

+3.3V_VBAT: the RTC circuit power supply of the South bridge, is same as
VCCRTC of Intel.
RTC_RST#: the reset of RTC circuit, 3V.
32.768 kHz: the clock of RTC circuit.
+3.3V_DUAL/+1.5V_DUAL:the standby voltage of 3.3V and 1.5V, some of
the latter is 1.2V_DUAL, and some is 1.1V_DUAL.
SUSCLK: The South Bridge sends 32 kHz clock after the standby voltage
being normal.
25MHz xtal: 25MHz crystal of the South Bridge of nVIDIA, it will affect
power-on.
PWRGD_SB: the standby voltage good, is equal to RSMRST#, 3.3V.

PWRBTN#: the trigger signal sent to the South Bridge.

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SLP_S5#: the South bridge sends the signal of exiting the power off state,3.3V, is
usually used to open the memory power supply.

+1.8V_SUS/+0.9V_SUS: the memory power supply and the memory load

power supply.
MEM-VLD: the memory power supply good, sends 3.3V to the South Bridge it
means that the voltage opened by SLP 35# has normal.

SLP_S3#: 3.3V sent by the South Bridge, the signal of exiting the sleep state, is
usually used to open the power supply of the bridge and VDDA power supply.

VDDA2.5V/CORE Power: VDDA2.5V is a PLL power supply needed by CPU,

CORE Power refers to the core power supply of the bridge.

PWRGD: after the power supply of the bridge being normal, sends 3.3V to the
South Bridge, it means that the voltage opened by SLP_S3# has normal.

*_CLK: after the power supply of the bridge being normal, the bridge internal
integrated of the clock chip starts to work, and sends the each clock.

CPUVDD_EN: the South bridge sends the high level 3.3V,is used to open CPU
power supply.

+V_CPU: the core power supply of CPU.

CPU VLD: CPU power management chip sends 3.3V to the South Bridge, it
means that CPU power supply has normal.

HTVDD_EN: The South Bridge sends the high level 3.3Vis used to open bus
power supply 1.2V.

+ 1.2V_HT: the bus power supply 1.2V.

HT_VLD: after the bus power supply being normal. Returned 3.3V high level
to the South Bridge, it means that the bus power supply has normal.

PCIRST#: after the South Bridge receiving HT_VLD, sends 5 of 3.3V reset (4
of PCIRST#, 1 of LPCRST#).

CPUPWROK: single bridge is that the bridge sends directly

HT_MCP_PWRGD to CPU. The double bridge is that the South Bridge sends

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HT_MCP_PWRGD to the North Bridge, and the North Bridge sends

HT_CPU_PWRGD again to CPU.

CPURST#: single bridge is that the bridge sends directly HT_MCP_RST# to

CPU. The double bridge is that the South Bridge sends HT_MCP_RST# to the
North Bridge, and the North Bridge sends HT_MCP_RST# again to CPU.

19.2: The Explanation of nVIDIA Chipset

Timing Sequence (MSI MS-16352)
As MSI MS-163 52 an example to analyze nVIDIA chipset timing sequence,
skip the RTC circuit.

First, the adapter interface CN1 inputs 19V, through the inductance PFL1 to
produce +DC_IN to send to the S pole of PQ1, through PR 146 and PR 148
divided into pressure to get 3.1V to control PQ1 to be conducted, produces
DC_IN, is shown in figure 19- 2. (AC_CTL is sent by EC, uses the adapter
alone, EC does not work, only when the battery is inserted, if EC does not
detect the adapter, and then it will send the high level of AC_CTL to make PQ3
conducted. PQ2 is also conducted, +DC_TN is added directly to the G pole of
PQ1, PQ is cut off.)

Figure 19-2: The adapter insert circuit

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The first path of DC_IN through PR158 to produce SDC_IN, the second path
through PD5 sends to DCIN of MAX1772, the third path through PR160 and
PQ161 divides into pressure MAX1772_ACIN of 2.24V to send to 11 pin
ACIN, is shown in figure 19-3.

Figure 19-3: The adapter detection part circuit of the charging chip
Figure 19-4 is the screenshot of part of pin definition of MAX 1772. When
ACIN pin is less than 2.048V (REF/2), ACOK will open drain output, and when
ACIN is higher than 2.048V, ACOK will output low level. The relationship
between ACIN and REF/2, ACOK is shown in figure 19-5.

Figure 19-4: The screenshot of part of pin detection of MAX1772

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Figure 19-5: ACOK internal block diagram of MAX1772

The low level of AC_OK#, one path is sent to EC, and another path is sent to
PQ5, is shown in figure 19-6. PQ5 is a dual N-channel composite tube. When
AC_OK# is low level, D2 and S3 are cut off, D2 is pulled up to be high level
AC_OK by +3VALW, is sent again to GL so Dl and SI will be conducted, Dl
becomes to be low level.
SDC_IN+ through PQ4A body diode produces the small current PWR_SRC,
trough PR153 and PR152 divides into pressure to be the relative low level
1.73V, controls PQ4A to be conducted completely and produces the large
current common point PWR_SRC.

Figure 19-6: The production circuit of the common point

Next, analyze the production of +3VALW and +5VALW: PWR_SRC through
PR184 insurance resistance sends to 22 pin VIN of PU2 as the main power
supply, is shown in figure 19-7.

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Figure 19-7: TPS51120 circuit

In the figure 19-7, EN3 and ENS are vacant, default open 3V/5V linear voltage.
The screenshot of the pin definition of EN3 and EN5 is shown in figure 19-8.

Figure 19-8: The screenshot of the pin definition of EN3 & EN5 of TPS51120
The screenshot of part of TPS51120 internal principle is shown in figure 19-
9.After VIN entering, through P-channel tube produces VREG3 and VREG5. P-
channel tube is controlled by the comparator, the reverse input end of the
comparator is 1.25V internal reference source, and the non-inverting input end is
from the output voltage through dividing into pressure.

TPS51120 outputs +3VALW to send to EC as the standby power supply, is

shown in figure 19-10.

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EC supplies power to the crystal, the crystal oscillates to send 32 kHz frequency
to EC, is shown in figure 19-11. +3VALW through R424 and C864 delays send
high level of ECRST# as the reset of EC, is shown in figure 19-12.

Figure 19-9: The screenshot of the part of TPS51120 internal principle

Figure 19-10: EC gets the power supply

Figure 19-11: EC gets the standby clock

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Figure 19-12: EC gets the standby reset

EC starts to read the program in the U8 (BIOS), is shown in figure 19-13.

Figure 19-13: EC reads BIOS

After EC receiving the adapter signal AC__OK#, outputs SUS_ON from 155
pin, is shown in figure 19-14.

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Figure 19-14: EC sends SUS_ON

SUS_ON is sent to TPS51120, controls the production of+3VSUS and +5VSUS,
is shown in figure 19-15. After two path of PWM being normal, open drain
outputs +3.3VSUS_PG, then renames to be SUSPWROK later.

Figure 19-15: The standby voltage control circuit (Control outputs +3VSUS &
+5VSUS)

One path of +3VSUS is sent to the South bridge as the main standby voltage
3.3V, another path through PU3 voltage regulator produces +1.5VSUS as the
second standby voltage of the South bridge, is shown in figure 19-16.

Figure 19-16: The production circuit of the second standby voltage of the South
Bridge

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Next, as shown in figure 19-17, 25MHz crystal of the South Bridge oscillates,
this crystal is the necessary condition for nVIDIA to power-on.

Figure 19-17: 25MHz crystal of the South Bridge

After 3SVSUSand 5VSUS producing normally from TPS51120, sends
SUSPWROK to the South Bridge PWRGD_SB, it means that the standby
voltage is normal, is shown in figure 19-18.

Figure 19-18: The South Bridge receives that the standby voltage is normal
The trigger switch produces PWRSW- to send to EC, is shown in figure 19-19.

Figure 19-19: The switch trigger circuit

EC sends the low level of PWRBT- through D15 to pull PM_PWRBTN# low, is
shown in figure 19-20. PM_PWRBTN# is sent to the South Bridge, that is to
say, the South Bridge received the trigger signal.

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Figure 19-20: EC sends the trigger signal

After the South Bridge receiving PWRBTN#, sends SLP_S5# to rename to be
PM_SLP_S5#, one path is sent to EC, another path is sent to PU4 (OZ813) to
control production of The memory main power supply CPU_VDDIO_SUS, and
sends VTT_VDDIO_PG, is shown in figure 19-21.

Figure 19-21: The memory power supply circuit

The memory main power supply is sent to PU7, produces CPU_VTT_SUS.is
shown in figure 19-22. The specific working process: +5VSUS supplies power
to 5,6,7,8 pin of PU7, CPU_VDDIO_SUS supplies power to 1 pin of PU7,
CPU_VDDIO_SUS through PR231 and PR232 divided into pressure gets 0.9V
to send to 3 pin of PU7 as the reference voltage input, at last,PU7 outputs
CPU_VTT_SUS with 0.9V from 4 pin.

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Figure 19-22: The production circuit of the memory VTT

VTT_VDDIO_PG is sent to the South bridge MEM_VLD, it means that the

memory power supply has normal, is shown in figure 19-23.

Figure 19-23: The South Bridge receives that the memory power is normal

The South bridge sends SLP_S3#, renames to be PM_SLP_S3#, one path is sent to
EC, and another path through R434 generates directly RUN_ON (R436 is not
installed), is shown in figure 19-24.

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Figure 19-24: The production circuit of RUN_ON

One path of RUN_ON through twice opposition of PQ16 and PQ19 produces
RUND, from PWR_SRC through PR200 and PR204 dividing into pressure to
be 15.6V, is shown in figure 19-25.

Figure 19-25: The production circuit of RUND

RUND controls PQ14 conducted, converts +5VSUS to be +5VRUN, control

PQ15 to be conducted, and converts +3VSUS to be +3VRUN, is shown in
figure 19-26.

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Figure 19-26: The production circuit of +5VRUN and +3VRUN

+3VRUN is sent to PU6 to produces +2.5VRUN, is shown in figure 19-27.

Figure 19-27: The production circuit of +2.5VRUN

Another path of high level of RUN_ON makes PD10 to be cut off, +2.5VRUN
through PR226 and PR293 divides into pressure to be 2.4V to send to PU4,
controls production of +1.2VRUN as the core power supply of the bridge, and
sends +l_2VRUN_PG, is shown in figure 19-28.

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Figure 19-28: The production circuit of +1.2VRUN

+1_2VRUN_PG is sent to PU9, opens the core power supply G73M_CORE of
the independent graphics, sends +1V_VGA_PG after being normal, is shown in
figure 19-29.

Figure 19-29: The production circuit of G73M_CORE

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+1 V_VGA_PG is sent back to 6 pin of PU9, is used to open +1.8VRUN to

supply power to the graphics and video memory, sends +1_8VRUN_PG after
being normal, is shown in figure 19-30.

Figure 19-30: The production circuit of +1.8VRUN

+1_8VRUN_PG is sent PU10 and PU12 to control production of +1.5VRUN to

supply power to the South bridge and +1_2VRUN_G73M to supply power to
the graphics, is shown in figure 19-31 and 19-32.

Figure 19-31: The production circuit of +1.5VRUN

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In the figure 19-31 and figure 19-32, after PU10 and PU12 working normally,
sends respectively +1_5VRUN_PG and +l_2VG73M_PG, phase with
RUN_ON to form RUN_PWRGD, is shown in figure 19-33.

Figure 19-32: The production circuit of +1_2VRUN_G73M

Figure 19-33: The production circuit of RUN_PWRGD

RUN_PWRGD is sent to PWRGD pin of the South Bridge, is shown in figure

19-34.

Figure 19-34: South Bridge receives RUN_PWRGD

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RUN_PWRGD is sent to Q33, makes D2 and S2 conducted, D2 connects SI, as

long as DVI_A_HPD of G1 has high level (DVI interface hot drawing insert
detection signal), D1 will be pulled down, Q34 will be conducted, and produces
IFPCD IOVDD, as the power supply of DVI display module of G73 graphics, is
shown in figure 19-35. In addition, RUN_PWRGD is also used to control
CPU_HT_RESET#, we don't explain in detail here again.

Figure 19-35: The production circuit of IFPCD IOVDD

After the South Bridge receiving PWRGD, sends the clock signal and
CPUVDD_EN, renames to be VDD_EN, is shown in figure 19-36.

Figure 19-36: The South Bridge sends CPUVDD_EN

VDD_EN is sent to MAX8774 (PU11) to open CPU core power supply

CPU_VDD_RUN, after CPU core power supply being normal, sends VDD_ PG, is
shown in figure 19-37.

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Figure 19-37: CPU core power supply circuit

VDD_PG is sent back to CPU_VLD pin of the South Bridge, the South Bridge sends
HTVDD_EN, renames to be VLDT_EN, as shown in figure 19-38.

The high level of VLDT_EN makes D1 pin of PU1 to be pulled down, D1 connects
G2, D2 and S2 will be cut off, D2 is pulled up to be 15.6V high level by RUND,
controls PQ24 to be conducted completely and produce +VLDT, the voltage is
1.2V, as shown in figure 19-39.

Figure 19-38: The South Bridge sends the bus power supply open signal

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Figure 19-39: The production circuit of the bus power supply

+VLDT through PR230 added to the B pole of PQ26, PQ26 conducted and
pulled PQ25 grid low, PQ25 is cut off, +3VRUN through PR228 pulled up
VLDT_PG as shown in figure 19-40.

Figure 19-40: The production circuit of VLDT_PG

VLDT_PG is sent to HT_VLD pin of the South Bridge, is shown in figure 19-
41.

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Figure 19-41: The South Bridge received VLDT_PG

At last, the South Bridge sends PCI_RESET#, LPC_REEST to EC and other

load chip, the South Bridge does not send MCP_PWRGD and MCP_RST#, is
shown in figure 19-42.

Figure 19-42: The South Bridge sends PG and Reset

MCP_PWRGD and MCP_RST# through OR gate converts to be

HT_MCP_PWRGD and HT_MCP_RST# to send to the North bridge is shown in
figure 19-43.

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Figure 19-43: The circuit screenshot location of U48

After the North Bridge reading BIOS correctly, sends HTCPU_STOP#,
HTCPU_RST#, HTCPU_ PWRGD, is shown in figure 19-44.
Three of high level signal are sent to U019, RUN_PWRGD is also sent to U019,
is shown in figure 19-45.Three signals are high, when RUN_PWRGD is also
high, U019 open drain outputs. CPU_ALL_PWROK, CPU_LDTSTOP#,
CPU_HT_RESET# are pulled up to be 1.8V by CPU_VDDIO_SUS, sends to
CPU. Then, the timing sequence is completed.

Figure 19-44: The North Bridge sends PG and reset

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Figure 19-45: The production circuit of PG and reset of CPU

19.3: The Standard Timing Sequence of AMD

Chipset
AMD chipset mainly refers to A50M, A70M and other new chipset matched
with APU, the standard timing sequence of this chipset is shown in figure 19-46.
In the figure 19-46, the explanation of signal is below.

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Figure 19-46: The standard timing sequence of AMD chipset

VDDBT_RTC_G: the power supply of RTC circuit, 3V. If RTC circuit of
AMD chipset is wrong, it will lead to no reset, do not run the code, sometime is
light and sometime is not light and other failures.

RTC clock In: the crystal oscillates to supply 32.768kHz frequency to the
bridge. If RTC circuit is wrong, it will lead to no reset.

VDDIO_33_S: the main standby voltage of the bridge, 3.3V.

VDDCR_1l_S: the second standby voltage of the bridge, 1.1V.

RSMRST#: the standby voltage good of the bridge, 3.3V.

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PWR_BTN#: after the power switch triggering, it's sent the trigger signal to the
bridge at last, is high-low-high pulse.

WAKE#: awaken signal, is usually from the network card chip, the function is
similar to PWR_BTN#.
SLP_S5#: the bridge sends the signal of exiting the shutdown state, 3.3V, is
used to control the production of the memory power supply.
SLP_S3#: the bridge sends the signal of exiting the sleep state, 3.3V, is used to
control all of S0 voltage.
All Power Rails: all power are opened, including the memory power supply,
the bridge power supply, and more power supply required by CPU, the single
bridge chipset has no power supply.
PWR_GOOD: inform the bridge that the voltage of S0 state is normal at this
time.
CLK: the clock integrated within the bridge starts to work.
APU_PG: the bridge sends the power good to CPU. A50 platform is also called
LDT_PG.
A_RST#: the bridge sends the platform reset, is equivalent to PLTRST# of Intel,
3.3V.
PCIE_RST#: the bridge sends PCI-E reset, 3.3V.
PCIRST#: the bridge sends PCI reset, 3.3V.

APU_RST#: the bridge sends the reset to CPU directly. A50 platform is also
called LDT_RST#.

19.4: The Timing Sequence of AMD Chipset

(ACER 4235, Quanta ZQE)
ACER 4235 is produced by Quanta, the board number is ZQE, uses AMD
chipset, and the timing sequence of the chipset is shown in figure 19-47.

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Figure 19-47: The timing sequence of Quanta ZQE

0: RTC circuit supplies the voltage and 32 kHz frequency to FCH Bridge.
+3VPCU supplies power to EC, and supplies the reset to VCC_POR# pin of EC.

1: the trigger switch produces NBSWON# to EC.

2: EC sends S5_ON.

2-1: S5_ON is sent to PQ10 to open +3V_S5, S5_ON is sent to PU8 to control
the production of +1.1V_S5.

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2-2: after PIS outputting +1.1 V_S5 normally, then sends HWPG_1.1 V.
3: EC delays send ICH_RSMRST# to the bridge.
4: EC delays send DNBSWON# to PWRJBTN# of the bridge.
5/6: the bridge sends SLP_S5# and SLP_S3# to EC.
5-1: after EC receiving SUSC#, then sends SUSON to the circuit of PQ36 and
PQ40 and PU10.
5-2: PQ40 converts & output +5VSUS; PU10 controls to produce the memory
main power supply +1.5V_SUS, the reference voltage +SMDDR_VREF and
the memory load power supply +0.75V_DDR_VTT.
5-3: after PU10 working normally, then sends HWPG_1.5V.
6-l: after EC receiving SUSB#, then sends MAINON to PU7, PU4, and
produces MAIND signal to PQ18, at the same time, EC sends VR_ON to send
to PU6.
6-2: PU7 controls the production of+1V,PU4 controls the production of +1.8V,
MAIND controls the production of +5V, +3V, +1.1V, +1.5V, PU6 controls the
production of CPU core power supply +VCORE and +NBCORE.

6-3: after PU7 and PU4 working normally, is sent to HWPG_1V and
HWPG_1.8V; after PU6 working normally, sends CPU_COREPG.

7: all of HWPG_* joints together to form HWPG and send to EC, is shown in
figure 19-48.

Figure 19-48: The production circuit of HWPG

8: after EC receiving HWPG then sends PWROK_EC.

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9: PWROK_EC and phase with CPU_COREPG sent by PU6, forms

SB_PWRGD_IN to send to the Bridge, as the condition of the Bridge sending
reset.
10: the bridge sends APU_PWRGD to APU, it means that all power supply are
normal.
11: the bridge sends A_RST#, PCIE_RST#, LDT_RST#. A_RST# and
PCIE_RST# is sent to the onboard chip slot and others, LDT_ RST# is sent to
APU, CPU starts to work.

19.5: The Explanation of AMD A70M (Lenovo

G485, Compal LA-8681P)
AMD A70M is the chipset developed by the super micro company for the
second generation APU platform, about the standard timing sequence of it, we
can refer to AMD standard timing sequence in 19.3 section. Next, analyze the
machine used this chipset, its Lenovo G485, is OEM produced by Compal, the
board number is LA-8681P.

19.5.1 RTC circuit

RTC circuit of AMD platform will cause all kinds of strange problem, such as
no reset, sometime is light (starts-up) and sometime is no light (can't starts-up)
and others. About machines (AMD platform laptop) with wrong (strange
problem), please note if RTC circuit is normal (check their RTC circuit first).
As shown in figure 19-49, when the adapter and the large battery are not
plugged, CMOS battery of JRTC2 through PR131, PR132 produces CHGRTC,
then through PD109 produces +RTCBATT. After plugging the power,
RTCVREF will replace the power supply of the battery, and can charge CMOS
battery.

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Figure 19-49: RTC power supply circuit

+RTCBATT through R105 supplies power to VDDBT_RTC_G of the bridge is
shown in figure 19-50.

Figure 19-50: FCH gets RTC power supply

After the bridge getting +RTCBATT, the crystal Y1 connected by 32K_X1 and
32K_X2 gets the power supply, the crystal oscillates to produce 32.768kHz
clock to the bridge, is shown in figure 19-51.

Figure 19-51: RTC crystal circuit

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19.5.2 Protective Isolation circuit

Plug the adapter, producing VIN, is shown in figure 19-52.

Figure 19-52: The production circuit of VIN

As shown in figure 19-53,VIN through PQ301 body diode produces P2 first,

PQ301 and PQ302 must be conducted completely, then it will produce the
common point B+, the condition of conducting is that the voltage of P2-1 point is
less than 14V.Any of the field effect tube PQ308 and PQ307B is conducted,
then it can form partial pressure, and produce P2-1 been less than 14V.The
signal of controlling PQ308 is that BATT_OUT is high; and controlling
PQ307B to be conducted is that PACIN and ACON are high, and ACOFF must be
low.

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Figure 19-53: The production circuit of the common point

Look at BATT_OUT first, if it wants to be high level, PQ202 and PQ203 must
be cut off, and is pulled up by +3VALW. During analyzing, the battery voltage
VMB2 must be less than 8.95V, and EC sends BATT_LEN#, then BATT_OUT
will be high, at the same time, +3VALW must be power on, is shown in figure
19-54. That is to say, before the common point not produced, this circuit didn't
control the production of the common point.

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Figure 19-54: The circuit of BATT_OUT

Next, look at PACIN, ACON, ACOFF. ACON is connected to other places, it
means that this machines has no power supply in advance(ignition loop) owned
by Compal. ACOFF connects EC, at this time, the common point is not
produced, EC is no power, and ACOFF is low.

VIN through PQ301 MOSFET produces P2 to send to VCC, VIN through

PR314 and PR317 divides into pressure to ACDET is shown in figure 19-55.

ACOK# output internal block diagram of BQ24727 is shown in figure 19-56.

Analyze the internal block diagram of BQ24727, when the voltage of ACDET
is higher than 0.6V, VCC voltage is higher than 3.75V, the chip outputs the
linear voltage REGN,6V, renamed to be BQ24727VDD; when ACDET voltage
is higher than 2.4V, the chip outputs the low level of ACOK#, renamed to be
ACPRN.

The low level of ACPRN makes PQ316 to be cut off, BQ24727VDD divides
into pressure to produce PACIN about 3.3V, then converts out ACIN to send to
EC at the same time, is shown in figure 19-57. Only when the system program
corrects the electric quantity of the battery, then EC will send the high level of
ACOFF, under other cases, ACOFF is low.

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Figure 19-55: The circuit screenshot location of the charging circuit

Figure 19-56: The screenshot of BQ24727 internal block diagram

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Figure 19-57: The production circuit of PACIN and ACIN

19.5.3 The standby power supply

One path of the common point B+ is renamed to be RT8205_B+ to send to VIN
of RT8205, another path through PR411 and PR412 divided into pressure to
send to EN is shown in figure 19-58.

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Figure 19-58: +B is renamed to be RT8205_B+ and sent to the standby chip

According to RT8205 (PU401) data manual, after RT8205 getting VIN and EN,
then it can output linear VREG3, VREG5, and REF.
VREG3 output by the chip renames to be +3 VLP, is shown in figure 19-59.

Figure 19-59: RT8205 outputs the linear voltage

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In RT8205 data manual, EN threshold value is the lowest, 1V, so the lowest
voltage of B+ is 6V, is shown in figure 19-60.

Figure 19-60: The screenshot of the description of electrical specification of EN

threshold value in RT8205 data manual

+3VLP supplies power to U3l (EC), is shown in figure 19-61.

Figure 19-61: EC gets the standby power supply

After EC identifying ACIN, EC sends EC_ON (if EC does not identify ACIN, it
needs to receive ON/OFF, then sends EC_ON), is shown in figure 19-62.

Figure 19-62: EC sends EC_ON

EC_ON through PR418 added to the B pole of PQ406, PQ406 is conducted,

PQ405A and PQ405B are cut off (MAINPWON connects to the temperature
control circuit, when there is no over-temperature, it won't be low), "@" means
no part, is shown in figure 19-63.

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Figure 19-63: EC_ON control circuit

ENTRIP1 and ENTRIP2 of RT8205 are not pulled down directly, and through
each resistance PR406 and PR405 to be grounded, as the over-current threshold
value setting, and opens two path of PWM (pull up internal), is shown in figure
19-64.

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Figure 19-64: RT8205 gets the open by PWM

RT8205 outputs +3VALWP and +5VALWP, through the isolation point PJ402
and PJ403 renamed to be +3VALW and +5VALW, is shown in figure 19-65.

Figure 19-65: The isolation of +3VALW and +5VALW

After RT8205 producing +3VALW and +5VALW normally, open drain outputs
SPOK, is shown in figure 19-66.

Figure 19-66: RT8205 outputs SPOK

Pulled up to be high level by VL to control PQ204 conducted, makes PR218
and PRR220 to divide into pressure, controls PQ205 conducted, produces
+VSBP, through the isolation point PJ201 to rename to be +VSB, is shown in
figure 19-67.
+3VALW supplies power to EC directly, and through L45 converts to be
+EC_AVCC to supply power to EC, is shown in figure 19-68.

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Figure 19-67: The production circuit of +VSB

Figure 19-68: EC gets the standby power supply

EC of this machine is not need the standby clock, +3VALW through delaying to
reset EC, is shown in figure 19-69.

Figure 19-69: EC gets the reset

EC reads the pin vacancy of ROM; it means that EC has its own program in it,
as shown in figure 19-70.

Figure 19-70: SPI pin of EC is vacant

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+3VALW supplies power to the bridge at the same time, as shown in figure 19-
71.

Figure 19-71: FCH gets the standby power supply

+5VALW supplies power to PU601, SPOK is sent to EN of PU601, PU601
outputs +1.1VALWP, through the isolation point to convert to be +1.1VALW, is
shown in figure 19-72.

Figure 19-72: The production circuit of +1.1VALW

+1.1VALW is sent to the bridge as the second standby voltage, is shown in
figure 19-73.

Figure 19-73: The bridge gets the standby voltage with 1.1V

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19.5.4 The trigger switch

Press the switch, producing ON/OFFBTN#, is shown in figure 19-74.

Figure 19-74: The switch interface

ON/OFFBTN# through R720 produces ON/OFF, is shown in figure 19-75.

Component with "@" in the figure is not installed, such as D24, R535 and
others.

Figure 19-75: The production circuit of ON/OFF

ON/OFF is sent to EC, is shown in figure 19-76.

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Figure 19-76: EC receives the trigger signal

After EC receiving ON/OFF, sends EC_RSMRST# first, when detects that

LID_SW# of 115 pin is high, then sends PBT OUT#, is shown in figure 19-77.

Figure 19-77: The screenshot of the trigger circuit of EC

EC_RSMRST# and PBTN_OUT# are sent respectively to RSMRST# and

PWR_BTN# of the bridge, after the bridge receiving PWR_BTN#, sends
PM_SLP_S5#, PM_SLP_S3#, is shown in figure 19-78.

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Figure 19-78: The screenshot of the trigger circuit of FCH

PM_SLP_S5# and PM_SLP_S3# are sent to EC, is shown in figure 19-79.

Figure 19-79: EC receives the power-on signal

19.5.5 Produce Power Supply

After EC receiving SLP_S5#, sends the high level of SYSON, is shown in

figure 19-80.

Figure 19-80: EC sends SYSON

SYSON is sent to EN pin of PU501 (TPS51212), is shown in figure 19-81.

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Figure 19-81: The memory power supply chip

After PUT501 receiving EN and the power supply sent by +5VALW, produces
+1.5VP, through the isolation point to rename to be +1.5V, is shown in figure
19-82.

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Figure 19-82: The production of the memory power supply

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After EC receiving SLP_S3#, sends the high level of SUSP#, is shown in figure
19-83.

Figure 19-83: EC sends SUSP#

One path of SUSP# controls Q61 conducted, pulls 1.5VS_GATE low, makes
the G pole of Q55 to be low level. Q55 is P-channel, the G pole low level can be
conducted, +1.5V through Q55 produces +1.5VS, is shown in figure 19-84.

Figure 19-84: The production circuit of +1.5VS

SUSP# is sent to PU502, is used to control the production of +1.8VSP, through

the isolation point to rename to be +1.8VS, as shown in figure 19-85.

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Figure 19-85: The production circuit of +1.8VS

SUSP# is sent to PU602, controls the production of +1.05VSP, through the

isolation point to rename to be +1.05VS, as shown in figure 19-86.

Figure 19-86: The production circuit of +1.05VS

SUSP# through Q63 inverts to be the low level of SUSP is shown in figure 19-
87.

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Figure 19-87: The production circuit of SUSP

SUSP is used to open +5VS, +3.3VS, +1.1VS, is shown in figure 19-88, figure
19-89, figure 19-90. As +5VS an example to analyze: the low level of SUSP
controls Q59 to be cut off, +VSB through R584 and R587 pulls up the G pole of
Q34. U34 is N-channel, +VSB with 19V is enough to make it conducted
completely, +5VALW through U34 produces +5VS.

Figure 19-88: The production circuit of +5VS

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Figure 19-89: The production circuit of +3VS

Figure 19-90: The production circuit of +1.1VS

SUSP controls PQ701 to be cut off. +3VALW and +1.5V supplies power to
PU701, +1.5V is divided into pressure to be 0.75V to VREF, PU701 produces
+0.75VSP, through the isolation point renamed to be+0.75VS, as shown in
figure 19-91.

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Figure 19-91: The production circuit of +0.75VS

19.5.6 APU power supply

After EC receiving PM_SLP_S3#, delays send VR_ON, is shown in figure 19-
92. VR_ON is sent to ISL6265, is shown in figure 19-93.

Figure 19-92: EC sends VR_ON

Figure 19-93: VR_ON is sent to APU core power supply

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ISL6265 gets the power supply and receives SVD/SVC, the chip produces APU
core +APU_CORE and +ACPU_CORE_NB (note, at this time, SVC/SVD is
pulled up by 1.8V, is only used as PVID to use, APU power supply is about
1.4V, only when APU power supply chip gets PWROK, then it will start to
decode SVID). After power supply being normal, ISL6265 sends VGATE, is
shown in figure 19-94.
VGATE is sent to EC, is shown in figure 19-95.
After EC receiving VGATE, sends FCH_PWRGD, is shown in figure 19-96.
FCH_PQRGD is sent to PWR_GOOD of the bridge, is shown in figure 19-97.

19.5.7 Clock, PG & Reset

After the power supply of the bridge being normal, 25MHz crystal Y4 oscillates
is shown in figure 19-98. After the bridge receiving FCH_PWRGD, the clock
integrated internal starts to work, and sends each clock.

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Figure 19-94: APU power supply chip

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Figure 19-95: EC receives VGATE

Figure 19-96: EC sends FCH_PWRGD

Figure 19-97: FCH receives PWR_GOOD

Figure 19-98: 25 MHz crystal

The bridge sends APU_PWRGD, is shown in figure 19-99.

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Figure 19-99: FCH sends APU_PWRGD

One path is sent to ISL6265, is used to activate the SVI interface of ISL6265,
runs I2C protocol, decodes SVID, and is shown in figure 19-100.

Figure 19-100: ISL6265 receives APU_PWRGD

The original of the explanation of PWROK pin of ISL6265:

System power good input. When this pin is high, the SVI interface is active and
I2C protocol is running. While this pin is low, the SVC, SVD, and VFIXEN
input states determine the pre-PWROK metal VID or VFIX mode voltage. This
pin must be low prior to the ISL6265 PGOOD output going high per the AMD
SVI Controller Guidelines. Another path of APU_PWRGD is sent to APU, is
shown in figure 19-101.

Figure 19-101: Another part of APU_PWRGD is sent to APU

The bridge sends A_RST#, PCIRST#, PCIE_RST# again. Only A_RST# is
used, and renames to be PLT_RST#, is shown in figure 19-102.

Figure 19-102: The Bridge sends the reset

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PLT_RST# is sent to the network card and EC, is shown in figure 19-103 and
figure 19- 104.

Figure 19-103: The network card receives the reset

Figure 19-104: EC receives the reset

PLTRST# convert to be APU_PCIE_RST#, is shown in figure 19-105.

Figure 19-105: PLTRST# renames to be APU_PCIE_RST#

APU_PCIERST# is sent to JWLN1 (MINI PCI-E), is shown in figure 19-106.

Figure 19-106: MINI PCI-E slot receives the reset

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APU_PCIE_RST# is also sent to U7, phase with PXS_RST# to produce

GPU_RST#, and is shown in figure 19-107.

Figure 19-107: The production circuit of GPU_RST#

At last, the Bridge sends APU_RST# and sent to APU, as shown in figure 19-
108.

Figure 19-108: The Bridge sends APU_RST# to APU

19.5.8 The independent graphics working timing sequence

EC sends the low level of VGA_GATE# to control Q112 to be cut off, the
bridge sends the high level of PXS_PWREN, is shown in figure 19-109.

Figure 19-109: The circuit screenshot location of PXS_PWREN

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PXS_PWREN controls the production of +3VGS and is shown in figure 19-110.

Figure 19-110: The production circuit of +3VGS

PXS+PWREN through Q26 converts to be PXS_PWREN#, is shown in figure

19-111.

Figure 19-111: The production circuit of PXS_PWREN#

PXS_PWREN# is used to open +1.0VGS and +1.8VGS, is shown in figure 19-

112 and figure 19-113.

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Figure 19-112: The production circuit of +1.0VGS

Figure 19-113: The production circuit of +1.8VGS

PXS_PWREN is also sent to the OR gate U10, phase with +3VGS, produces
PX_MODE (PX_EN is from the graphics card chip), as shown in figure 19-114.

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Figure 19-114: The production circuit of PX_MODE

One path of PX_MODE is used to control the production of +1.5VGS, is shown in

figure 19-115.

Figure 19-115: The production circuit of +1.5VGS

Another path of PX_MODE is sent to PU801, is shown in figure 19-116.

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Figure 19-116: PU801 receives PX_MODE

PU801 controls the production of the graphics card core power supply
+VGA_COREP, through the isolation point renames to be +VGA_CORE. After
the power supply being normal, sends VGA_ PWRGD, is shown in figure 19-
117.
VGA_PWRGD is sent to U9,phase with PX_MODE, outputs the high level to
control Q68 conducted, pulls 1.0V_ON# low, and makes Q68 to be cut off at
the same time, makes VDDC_ON# to be high level of invalid state, is shown in
figure 19-118.

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Figure 19-117: The production circuit of +VGA_CORE

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Figure 19-118: The circuit screenshot location of U9

The low level of 1.0V_ON# controls Q18 and Q19 to be cut off, the high level
of VDDC_ON# controls Q22 and Q23 to be conducted, converts +VGA_CORE to
be +BIF_VDDC, is shown in figure 19-119.

Figure 19-119: The production circuit of +BIF_VDDC

VGA_PWRGD is sent to the Bridge, is shown in figure 19-120.

Figure 19-120: FCH receives VGA_PWRGD

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After the bridge receiving VGA_PWRGD, because PEG_CLKREQ#_R is

forced to be pulled down to be the low level by the resistance R183, the bridge
sends automatically 100MHz difference clock CLK_PCE_VGA and
CLK_PCIE_VGA# to VGA, is shown in figure 19-121.
The bridge sends the high level of reset signal PXS_RST# of the graphics card
again, is shown in figure 19-122.
PXS_RST# phases with APU_PCIE_RST# to produce GPU_RST# to send to
the graphics card, is shown in figure 19-123.

Figure 19-121: FCH sends the graphic card clock

Figure 19-122: The Bridge sends the graphics card reset

Figure 19-123: The graphics card receives the reset

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