Laptop Chip Level Repair Guide 319

Chapter 14

Analysis of Intel PCH

Sequence (i3/i5/i7)

PCH is the platform controller hub. Intel PCH is the single bridge chipset in the
Intel company. The product of the first generation PCH is Intel 5 series, such as
Intel HM55 and so on. matches the first generation 13/15/17 CPU; the second
generation and the third generation is Intel 6 and Intel 7 series, matches the
second generation and the third generation 13/15/17 CPU, these two of
generations is almost the same, CPU is in common used. The newest fourth
generation has been released is Intel 8 series.PCH chip has all functions of the
original ICH, also has the function of management the engine of the original
MCH. It does not matter to call PCH the North Bridge or the South bridge. In
this chapter, we mainly introduce the main feature of Intel 5 series.6 series and
7 series sequence.

14.1: About Intel ME and Intel AMT

Intel ME is the Intel Management Engine, is the independent hardware inset the
North Bridge or PCH.ME firmware (ME FW) and the BIOS motherboard are
usually kept in the same chip, but they are independent mutually. The
architecture of Intel ME and ME firmware is shown in figure 14-1.

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Figure 14-1: The architecture figure of Intel ME and ME firmware

Intel starts introduce the management technology called "iAMT" in ICHT. Intel
AMT (Intel Active Management Technology) is the embedded system
integrated in the chipset in effect, it does not depend the specific the operating
system. It is the biggest difference between iAMT and the remote control
software.
The embedded operating system of AMT technology integrates in the BIOS
chip, the function is realized by ME. This technology cannot to depend the real-
time status of the hardware. It can start up, maintain, shutdown independently
and other operation. Even if it's in the system with crash, power off or blue
screen or even been closed, it can still work! Of course, it also can enter into
BIOS to operate. AMT needs to match the special server- side software to
work.
Intel AMT technology can appear as a subsystem been independent of existing
operating system, because of the environment independent of the operating
system, when the operating system is broke down, the administrator can remote
monitoring and manage client-side. By this technology, the computer been
controlled also can remote manage and detect system when the operating

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system is damaged or the system is broke down, or when the system goes wrong,
it can send the warning message ,to detect the software and hardware, remote
update BIOS and virus code and the operating system, even when the system is
power off, it can also manage work by the website, then it has worked out the
problem troubled IT manager: users closed the safety and management software
on the PC deliberately or by accident, which leads to unacceptable management.
These features can significantly reduce the administrative cost for the company
user.

When the system supported AMT is in the S5 sleeping state, ME module, the
clock chip Intel PHY LAN, SPI BIOS, MEMORY (CHANNEL0 DIMM0) need
to be powered on.

Inter Chipset starts from ICH8M, in the ACPI, dormant logical control signal is
added SLP_M #. The pin definition screenshot of SLP_M# is shown in figure
14-2.

Figure 14-2: The pin definition screenshot of SLP_M#

[Explanation] This signal is used to control the power of Inter AMT subsystem.
When the ME firmware does not exist, the timing step of SLP_M# is consistent
with SLP_S3# (while generating on / off). ICH8 & ICH9 also redefined the
functions of SLP_S4#, increased S4_STATE#. The pin definition screenshot of
SLP_S4# of ICH8 & ICH9 is shown in figure 14-3.

Figure 14-3: The pin definition screenshot of SLP_S4#

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[Explanation] SLP_S4#: when the system is in the state of S4 &S5 sleeping, it

is used to control the switch (on/off) of the voltage controlled by itself.

Comment: when the system opens the AMT function, is used to control the
switch of the memory voltage. In the state of Ml (when the main platform is in
the state of S3~S5 and the subsystem of ME is running), SLP_S4# is forced to
be pulled up by SLP_M=.is used to open the memory voltage when the system
is in the state of AMT.

The pin definition screenshot of S4_STATE# of ICH8JCH9 is shown in figure

14-4.

Figure 14-4: The pin definition screenshot of S4_STATE#

[Explanation] the index signal of S4 state: when this signal is low level, it
means that the main platform is in the state of S4 or S5.When ME forced to pull
up SLP_S4#, this signal can be used to inform that the equipment system on-
board is in the state before S3.

It added CLPWROK from ICH starting, and renamed to be MEPWROK after 5

series chipset the 6 series chipset renamed to be APWROK. The pin definition
screenshot of MEPWROK is shown in figure 14-5.

Figure 14-5: The pin definition screenshot of MEPWROK

Explanation] ME Power Good: when this signal is effective, it means that ME

module supply has been stable.

When the AMT function is closed, the sequential relationship of each sleeping
control signal is shown in figure 14-6.After triggering, SLP_S5# is set up to be
high first, then SLP_S4# and S4_STATE# are set up to be high, SLP_S3# is set
up to be high at last, the timing sequence of SLP M# and SLP S3# is same.

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Figure 14-6: When AMT function is closed, the timing sequence of each
sleeping control signal
When AMT function is opened, the timing sequence of each sleeping control
signal is shown in figure 14-7.SLP_M# is set up to be high in advance,
SLP_S4# is also set up to be high .After receiving triggering or other awakening
signal, SLP_S5# is set up to be high first, then S4_STATE# is set up to be high to
replace the original SLP_S4#, SLP_S3# is set up to be high at last.

Figure 14-7: When AMT function is opened. The timing sequence of each
sleeping control signal

When AMT function is opened, the logic of each sleeping control signal is
shown in the table 14-1.

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When AMT function is opened, the system is in the state of S5 sleeping,

SLP_S4# is used to control the reservation of the memory voltage. SLP_M# is
used to control the clock chip, part of C-LINK, the reservation of Intel PHY
LAN, SPI BIOS or other voltage. We can open or shield AMT function in the
CMOS settings.
After PCH, SLP_S4# no longer follows SLP_M# to start, and cancel
S4_STATE#.When the chipset of PCH opened AMT function, only ME module,
network card and BIOS need to be supplied power.

The 5 series chipset still retains SLP_ M#, the 6 series chipset renamed it to be
SLP_A#, but it still used to control the power supply of ME module. The 5
series and 6 series chipset also add SLP_LAN#, the pin definition is shown in
figure 14-8.

Figure 14-8 the pin definition screenshot of SLP_LAN#

[Explanation] LAN subsystem sleeping control, when SLP_LAN# is ineffective.

The power of the network card must to be retained; when SLP_LAN# is
effective, the power supply of the network can be closed. When SLP_LAN# is
in the state of S0 and SLP_M#/SLP_A# is ineffective, it keeps being ineffective
all the time.

Added ACPRESENT adapter detection signal and SUS_PWR_DN_ACK signal, is

shown in figure 14-9.

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Figure 14-9: The pin definition screenshot of ACPRESENT and

SUS_PWR_DN_ACK

[Explanation]
ACPRESENT: is used for the mobile system. The signal sent from EC, to indicate
that the power supply origin is alternating current or the system battery. The
high level refers to alternating current power supply.
SUS_PWRJDN_ACK: the signal sent from ME module to EC; the high level
means that it does not need to hang the power.

14.2: Analysis of Intel HM55 Series Chipset

Timing Sequence
The timing sequence of Intel 5 series chipset is shown in figure 14-10, the
explanation of the signal in the figure is below.

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Figure 14-10: The timing sequence of Intel 5 series chipset

VCCRTC: 3V power supply sent from the motherboard to PCH Bridge,

supplies the power to RTC circuit of the bridge, to save the CMOS parameter.

RTCRST#/SRTCRST#: 3V high level sent from the mainboard to the bridge,

the reset signal of RTC circuit start from ICH9, there have two resets.

32.768kHz: the 32.768 kHz crystal next to the bridge, the bridge supplies the
power to the crystal, and the crystal supplies the frequency to the bridge.

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VCCSUS3_3: the motherboard supplies the power to the bridge, 3.3V.

RSMRST#: the motherboard sent the ACPI reset signal with 3.3V high level to
the bridge, it means to inform the bridge that the standby voltage has been
normal at this time.
SUSCLK: the bridge sends 32.768 kHz clock if EC is built-in crystal, SUSCLK
is usually sent to EC, synchronous clock.
PWRBTN#: the bridge receives the falling edge trigger signal, 3.3V-OV-3.3V,
to inform the bridge that it can exit the sleep state.
SLP_S5#: after the bridge receiving PWRBTN#, set up SLP_S5# high to be
3.3V, it means that it exits the shutdown state.
SLP_S4#: the bridge set up SLP_S4# high to be 3.3V, it means that it exits the
sleep state.
SLP_S3#: the bridge set up SLP_S3# high to be 3.3V, it means that it exits the
standby state and enter the SO boot state.

SLP_M#: start from ICHS, added SLP_M#. It is sent by the bridge and used to
open the control signal of ME module, 3.3V.

If there have ME firmware on the mainboard, when it opens AMT function, this
signal will produce before triggered: when it closes AMT function, this signal
timing sequence is consistent with SLP_S3#.

If there have not ME firmware on the mainboard, not support AMT, SLP_M#
hung is not to be used.

SLP_LAN#: LAN subsystem sleeps control and controls the power supply of
the network card. If the Motherboard not uses Intel integrated network card, this
signal is not to be used. If the motherboard uses Intel integrated network card,
and supports network awaken, then this signal is high in the standby; when it
not supports the network awaken. This signal follows SLP_M# or SLP_S3#.

VCCME: the power supply (power supply to achieve AMT function) of ME

module, is controlled by SLP-M#. When SLP_M# is hung up (there haven't ME
module on the motherboard), VCCME uses the power supply of SO state
directly, such as the bus power supply and VCC3-3.

VDIMM: refers to the memory power supply, is controlled by SLP_S4#.

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VCC: refers to the voltage in the SO state of the bridge power supply and the
bus power supply is controlled by SLP_S3#.
VCC_CPU: the motherboard sends the core power supply to CPU is also
controlled by SLP_S3#, it will delay.
SYS_PWROK: sent 3.3V high level to the bridge by CPU power management
chip is equal to VRMPWRGD.
PWROK: the motherboard sends 3.3V high level to the bridge, it means that
the voltage of S0 state is normal (the bridge an d the bus power supply).
MEPWORK: ME module power good, 3.3V. When there have ME firmware,
MEPWROK is controlled by ME module power supply; and when there haven't
ME firmware. MEPWROK connects together with PWROK.
LAN_RST#: after the network card power supply being normal, the
motherboard sent the reset signal to the network card controller of the bridge,
we can understand that it is the power good signal of the network card. If the
motherboard not uses Intel integrated network card, this signal is forced to be
grounded.
Clock Chip Outputs: the clock chip is opened and outputs each group of the
clock.
PROCPWRGD: the bridge sent PG to CPU, it means that the core voltage of
CPU is normal.
DRAMPWROK: the bridge sent PG to CPU, it means that the memory module
power supply of CPU is normal. Open drain outputs, it should be external
pulled up.

PLTRST#: the platform reset 3.3V sent by the bridge, as CPU reset by
conversing (is usually series partial pressure).

14.3: Analysis of The Chipset Timing Sequence

Above Intel HM65 Series
The timing sequence of Intel 6 series chipset is shown in figure 14-11.the
explanation of the signal in the figure is below.

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Figure 14-11: The timing sequence of Intel 6 series chipset

VCCRTC: sent 3V power supply to PCH bridge from the motherboard,

supplies the power to RTC of the bridge, to save CMOS parameter.
RTCRST#/SRTCRST#: sent 3V high level to the bridge from the motherboard,
the reset signal of RTC circuit. Start from ICH9 and there have two resets.
32.768kHz: 32.768 kHz crystal next to the bridge, the bridge supplies the power
to the crystal, and the crystal provides the frequency to the bridge.
VCCDSW3_3: the motherboard provides the deep sleep well power
supply to the bridge, 3-3V.When it not supports the deep sleep, this voltage
connects with VCCSUS3_3.

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DPWROK: the motherboard sent 3.3V high level to the bridge, refers to the
VCCDSW3_3 power good, 3.3V. When it not supports the deep sleep, this
signal connects with RSMRST#.

SLP_SUS#: deep sleep state indicator signal, it can be used to open the voltage
of S5 state. Such as VCCSUS3_3.When it not supports the deep sleep,
SLP_SUS# is hung up.

VCCSUS3_3: the motherboard sent the standby power supply to the bridge,
3.3V.

RSMRST#: the motherboard sent ACPI reset signal of 3.3V high level of the
bridge, to inform the bridge that the standby voltage is ready now.
SUSCLK: the bridge sent 32.768 kHz clock, but it not necessarily be adopted
by the motherboard.

PWRBTN#: the bridge received the falling edge trigger signal,3.3V-OV-

3.3V,informed the bridge that it can exit the sleep state.

SLP_S5#: after the bridge receiving PWRBTN#, set up SLP_S5# to be 3.3V,it

means that it exits the shutdown state.

SLP_S4#: the bridge sets up SLP_S4# to be 3.3V, it means that it exits the
sleep state.

SLP_S3#: the bridge sets up SLP_S3# to be 3.3V, it means that it exits the
standby state, and Enters the SO boot state.

SLP_A#: The bridge sent the power open signal of the active sleep circuit, used
to open ME module power supply.

If there have ME firmware on the mainboard, when it opens AMT function, this
signal will produce before triggered; when it closes AMT function this signal
timing sequence is consistent with SLP_S3# .

If there haven't ME firmware, it is not support AMT, SLP_A# hung not uses.

SLP_LAN#: LAN subsystem sleeps control; controls the network card power
supply. If the motherboard not uses Intel integrated network card, this signal is
not adopted. lf the motherboard uses Intel integrated network card, and supports
the network awaken, this signal is high when it is in standby; when it not
supports the network awaken, this signal follows SLP_A# or SLP_S3#.

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VCCASW: the power supply of the active sleep circuits controlled by SLP_A#.
When SLP_A# is hung up (there haven't ME firmware on the mainboard),
VCCASW adopts the power supply of S0 state directly.

VDIMM: refers to the memory power supply, is controlled by SLP_S4#.

VCC: refers to the voltage of SO state or the main power supply or others of the
bridge is controlled by SLP_S3#.

PWROK: the motherboard sent 3.3V high level to the bridge. It means that the
voltage of S0 state is ready for the bridge and the bus power supply.

APWROK: ASW power good. When it opens AMT function, APWROK is

controlled by AMT voltage, when it closes AMT function. APWROK is
consistent with PWROK.

DRAMPWROK: the bridge sent PG to CPU. Informs CPU that memory

module power supply is ready.

25MHz Crystal Osc: 6 series chipset has not available the clock chip; the
bridge added 25MHz crystal to supplied the reference frequency to the external
clock module.

PCH Output Clocks: the bridge outputs each group of clock.

PROCPWRGD: the bridge sent PG to CPU, it means that the non-core voltage
of CPU is ready.

CPU SVID: CPU_SVID is a group of signal sent to CPU power supply chip by
CPU. It is function of the standard serial bus consisted of DATA and CLK and
ALERT# signal with the function of reminder; it is used to control CPU core
voltage and the integrated graphics power supply.

After PROCPWRGD being effective, CPU sent SVID.

VCCCORE_CPU: the core voltage of CPU.

SYS_PWROK: CPU power supply chip sent 3.3V high level to the bridge it
means that CPU core voltage is ready.

PLTRST#: the bridge sent the platform reset 3.3V, as CPU reset by conversing.

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The timing sequence of Intel 7 series and 8 series is almost consistent with Intel 6
series. We don't explanation it again.

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