Laptop Chip Level Repair Guide 101

Chapter 8
The Basic Working Process
of Laptop Computer

As professional laptop computer maintenance, personnel, in addition to have a

certain basic knowledge, also need to understand the working process and Intel
chipset standard timing of the laptop and other maintenance theories knowledge.
This chapter focuses on the boot process and Intel standard timing.

8.1: The General Boot Process of Laptop

Computer

The working process of the laptop follows a certain sequence. In the repair of
the laptop, in most cases, Timing applied on the power-on part in the system
boot, so also called Power Sequence. Mainly refers to a laptop motherboard
having done from standby to CPU get RESET signal. So literally, timing is time
and sequence. The motherboard from standby to power-on, and then to CPU
work, we feel just a short time.is almost a second, but in the work of the
motherboard, it will happen a lot of things in a second, from the standby voltage
producing.to press the switch, and to the motherboard received the switch signal,
then to send out each working voltage. And the motherboard made so much
action; it will strictly obey an established order, that is to say, in the process of
these steps, if the first step isn't completed. Then the next step is not start. And
there is a strict time requirement between each step, some will be accurate to a
few milliseconds, for example, PWRGD Signal generation requires that each
voltage stabilize about 5ms will be sent.

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From the above introduction, we can see that the timing has very important
significance for the normal working of a motherboard, the most common fault,
such as no electricity, no boot and others, there have an important relationship
with the timing. It can be said that if you master the timing, then you have a
basic idea of maintenance for all kinds of faults of the laptop.

8.1.1 Hard starting process and Intel chipset standard

timing
1. Hard starting process in general.

The boot process of the laptop with Intel chipset (below series 4) is as follows:

(a) Without any electrical equipment supply power (no battery and no power),
through 3V button battery to produce VCCRTC to supply RTC circuit of the
South bridge, to keep the operation of the internal time and save the CMOS
information.

(b) After plugging in the battery or adapter, produce the common point.

(c) Then produce the EC standby power supply (usually linear voltage), after
the standby power supply is normal, EC supply power to crystal oscillator to
produce the EC standby clock, the standby power supply delay produce EC
reset, EC reads the program configuration own pin(BIOS chip select waveform
as shown in figure 8-1).

Figure 8-1: BIOS chip select waveform

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(d) If EC detected the power adapter, it will automatically send a signal to open
the standby power supply of the South bridge (VCCSUS3_3, V5REF_SUS),
and send RSMRST# signal to the South bridge to notice the South bridge that
the standby voltage is normal; if EC is not detected the adapter (battery mode),
EC need to receive the switch trigger signal, then will open the South bridge
standby power supply, to save power.

(e) Press the switch, after EC receiving the switch signal, delayed send a high-
low-high boot signal to the South bridge PWRBTN# pin.

(f) After the standby condition of the South Bridge is normal and receiving
PWRBTN# signal, raising SLP_S5#, SLP_S4#, and SLP_S3 #signal in turn.

(g) SLP_S5# or SLP_S4# control the production of the memory main power
supply etc,SLP_S3#control the production of the bridge power supply. The bus
power supply (VCCP), the independent graphics power supply etc. (some is
controlled directly by SLP signal. And some is controlled by EC after SLP
sending to ECX

(h) EC delay send signal or other circuit switching to open CPU core voltage
(VCORE).Thus, the voltage of the machine has been fully opened.

(i) After CPU power supply being normal, CPU power management chip send
PG to the South Bridge VRMPWRGD pin at last.

(j) After CPU power supply being normal, open the clock chip through the
conversion circuit then produce various clocks.

(k) The South bridge received the power supply, clock, VRMPWRGD, and
received EC or power supply circuit delay conversion PWROK, the South
bridge will send CPUPWRGD to inform CPU that its core voltage has been
successfully opened, and send PLTRST# and PCIRST# signal at the same time.

(l) After the North bridge receiving PLTRST#, send CPURST# signal to CPU,
then CPU officially start to work.

The above is the hard start process of the laptop. In the process of hard start we
can divide the power supply of the laptop into 4 levels.

(1) G3 power: voltage generated just plug the power, generally supply to power
switch and EC, is usually produced by linear way.

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(2) S5 power: the standby voltage of the South bridge, supply to VCCSUS3_3
of the South Bridge, power in the state of power off is usually produced by
PWM way.

(3) S3 power: the power supply of the memory, the power in the state of S3
sleeping.

(4) SO power: the main power supply to the normal operation of the machine
also called RUN power, including the bridge main power supply, the bus power
supply, CPU power supply and others.

Sometimes, 3V, 5V produced by PWM way under the condition of G3 or S5 are

also called the system power supply. For example, Quanta series PCU voltage is
the system power supply. But it exits under the condition of G3.And for
example: ASUS A8E South bridge standby voltage is produced by PWM way it is
the system power supply.

2. Intel
The Intel chipset standard timing as figure 8-2 is Intel chipset standard sequence
diagram.

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Figure 8-2: Intel Series-4 Chipset Standard Sequence Diagram

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According to the sequence diagram shown in figure, 8-2 is explained as follows.

(1) System State

G3: the power of the whole system are closed.

(2) The interpretation of the signals

 VCCRTC: the power supply of the South bridge RTC circuit, 3V, supply
power to CMOS chip (RAM) inside the South Bridge.
 RTCRST#: the reset signal of the South bridge RTC circuit, 3 V.1CH9
added another RTC reset signal later, the name is SRTCRST#.
 32.768 kHz: after the South Bridge receiving VCCRTC and RTCRST #,
supply power to the crystal oscillator. The crystal oscillator running. The
voltage of two pins of the crystal oscillator is 0.1-0.5 V.
 V5REF_SUS:5V standby voltage.
 VCCSUS3_3: 3.3V standby voltage.
 VCCSUS1_05: The South Bridge internally produced the power supply
1.05V for itself, not to consider this voltage when we analyze the timing.
 RSMRST#: inform the South Bridge that 3.3V standby voltage is normal.
The external circuit controls voltage 3.3V.
 SUSCLK: after the South bridge receiving RSMRST#, then send the
32kHz clock, most machines do not use, it can be ignored.
 PWRBTN#: POWER BUTTON, 3.3V-0-3.3V pulse signal.
 SLP_S5#: 3.3V, the control signal when the South Bridge exit the power
off state.
 SLP_S4#: 3.3V, the control signal when the South Bridge exit the
dormant state. (Usually just use S5# or S4#, used to control the
production of the memory power supply, and another is idle.)
 SLP_S3#: 3.3V, the control signal when the South bridge exit the
sleeping state. (usually used to control the bridge power supply, the bus
power supply, the independent graphics power supply, CPU power
supply etc.)
 VDIMM: the memory power supply.
 VCORE/VCC: refers to the bridge power supply, the bus power supply,
the independent power supply, CPU power supply etc.
 VRMPWRGD: inform the South Bridge that CPU power supply is
normal, 3.3V. CLK GEN: the clock chip starts to work, send various
clock.

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 PWROK: inform the South bridge that power supply is normal

(SLP_S3# complete task), 3.3V. CPUPWRGD: The South Bridge sends
PG to CPU, 1.05V.
 PLTRST#: the platform reset, the South bridge send the first reset, 3.3V
is generally sent to the North bridge, EC, MINI slot etc.
 PCIRST#: PCI reset, the South bridge send the second resettle 3.3V
computer is not usually used.
 CPURST#: after the North bridge receiving PLTRST#, send the reset of
CPU, 1.05V.

8.1.2 The soft start process

Next to the Intel Bridge (such as GM45) as an example, see CPURST#,
addressing process of CPU and power-on self-test process. In the process of the
computer hard start, CPURST reset signal is sent and keep a low level of a
certain time, when the power supply circuit has been stable, then removed the
RESRT low level and keep a high level, CPU start to work, the hard start
finished, and start to the soft start.
1) CPU will check FSB front bus line is busy or not through the DBSY# signal
of the interface circuit. When DBSY# is low level, it means that FSB bus is
busy, only released it, CPU will be the next step work; when DBSY# is high
level, it means that FSB is not busy, CPU will through ADS# address strobe
signal line to tell the North Bridge ready to send the data.
ADS waveform is as shown in figure 8-3.
2) After the North bridge receiving this signal, if it's in good condition and has
been ready, the North bridge will send a low level of H_TRDY# to CPU, told
the CPU is ready, and can receive the data. Then CPU will through A31~AO
send FFFFOH address signal, which is a jump instruction in the BIOS.AO-A31
to FSB front bus interface of the North Bridge, through FSB frequency
conversion. Level conversion and address decoding send to the North Bridge.
After the North, bridge receiving CPU addressing instruction. Through DMI,
bus sends to the South Bridge.
The North bridge and the South bridge DMI bus consists of 16 lines, point to
point transmission, signal lines including DMI _RXP(0:3), DMI_RXN(0:3),
DMI_RXN(0:3), DMI_TXN(0:3), as shown in figure 8-4.

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Figure 8-3: ADS# Waveform

Figure 8-4: DMI bus signal diagram

3) After the South Bridge receiving the addressing instruction of the North
Bridge. Then start to search BIOS, first search whether there is BIOS on the PCI
bus (see figure 8- 5).When there is no BIOS on PCI bus. According to the PCI
bus signal set to determine where BIOS is. If the BIOS is under EC, after the
South Bridge through PCI decoding module, then to communicate with EC on
the LPC bus. When EC receiving the addressing instruction, after that through
X-BUS or SPI bus to BIOS. BIOS returns the data to the CPU, CPU running
POST self-check program in the BIOS, and start self-check action.

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Figure 8-5: BIOS location settings

The key signal to determine whether PCI bus action: PCI_FRAME# (Cycle
Frame).

PCI frame period signal is low level; it means that PCI bus start work. And
when it is high level, it means that PCI bus is not to work.

The key signal to determine whether LPC bus action: LPC_FRAME# (LPC
frame period).

The key signal to determine whether BIOS action: CS# (chip select).Selected
when low level, and is not selected when high level.

4) After CPU reading BIOS self-test correctly, and then start to execute the
process of POST instruction.
(a) When CPU addressing is normal, received POST self-test program returned
by BIOS, then start initialized the chipset(the South bridge and the North
bridge),and also initialized PCI-E bus(independent graphics).
(b) After the South Bridge initializing, grab the memory through SMBUS bus to
be initialized, the waveform is shown in figure 8-6.
(c) After the memory self-test finishing, BIOS stores the self-test program into
the memory.
(d) Then called the BIOS program from the memory to test each device one by
one, such as the keyboard controller, network cards, sound cards etc.
(e) Testing the graphics cards, find BIOS of the graphics cards, and call them to
complete the initialization of the graphics cards.
(f) The graphics cards starts to read the screen information through ED1D bus
(shown in figure 8-7), after reading the screen, then sends a signal to open the
screen power supply and backlight.

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Figure 8-6: SMBUS waveform of the memory

Figure 8-7: EDID waveform

(g) Display the boot picture, and start to test the extended memory and give the
corresponding address.
(h) Test some standard equipment, including hard disk, CD drives, serial ports,
parallel ports, floppy drive etc.
(i) After testing the standard equipment, the plug and play code supported by
the system will start to test and configure the plug and play equipment in the

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system, and distributes the interrupt address, DMA channel and I/O port and
other resources for this equipment.
(j) After all hardware testing and being assigned the interrupts address, that is,
all the hardware set up a hardware system, then it will generate a ESCD file (it
is the method that the system BIOS exchange hardware configuration
information for the operation system, the data is in CMOS), CPU will compare
the generated ESCD with the last ESCD if finds the difference, it will update
the data in ESCD.
(k) After updating ESCD, CPU will complete POST and the interrupt service
routine. Then carry out the bootstrap program of the system. The boot code of
the system BIOS start the operating system according to the boot sequence
specified by users, find the boot files in the starting device first then write in the
memory, BIOS give the control power of the computer to the boot files. The
operation system guided by the boot files, such as Windows XP, Windows 7
and so on.

8.2: About ACPI Specification

8.2.1 ACPI summarize

ACPI (Advanced Configuration & Power Interface) is the standard of the

advanced configuration and the power interface. Before ACPI proposed, the
universal power management standard is APM with a BIOS level developed by
Microsoft. ACPI is to replace the previous APM.
ACPI is jointly developed by Intel, Microsoft, Toshiba, is to have a common
power management interface between the operating system and the hardware,
and to improve the disunity interface developed by the different manufacturers
on the power management before.
From Windows 98/SE, Windows ME and Windows 2000, Windows XP starting
to support ACPI. From the laptops to the desktops and servers are included in
this specification.
ACPI can make the system to enter a low power consumption of "sleep state",
such as standby and sleep; the purpose is to control the power consumption of
the computer.
All state of ACPI can be divided into G (Global), D (Device), S (Sleeping), C
(CPU).

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8.2.2 G (Global) State of ACPI

Global refers to all system, and can be divided into the following 4 kinds.

1) GO: Working state. The user program can be executed normally. But the
device dynamically allocates their own state. When not used this device. This
device can enter other non-operating state. Under this state, the system responds
the external events in real time. And the machine cannot be disassembled and
assembled under this state.

2) G1: Sleeping state. Under this condition, the system consumes less power,
and no user's program is executed. The system looks like in the shutdown state.
Because the display screen is turned off at this time. As long as any wake-up
activation events message into the system, it will soon be restored to a working
state. Under this state, the machine cannot be disassembled and assembled.

3) G2/S5: Soft Off state. System only keeps very little power under this state, no
users and the operating system programs are executed. The state takes a long
time to return to a working state. Under this state, the machine cannot be
disassembled and assembled.
4) G3: Mechanical Off state. Under this state, the power of the whole system is
closed, there is no current through the system, and the system can only reopen
the power supply switch to active. Under this state, the power consumption is
zero.

8.2.3 D (Device) State

Device refers to some devices, such as modems. Hard drives, CD-ROM, etc.
also can be divided into the following 4 kinds.
1) DO: Fully On. The normal working state.
2) Dl: It can save less power consumption; the device function with keeping
activities is much more than which in D2 state. The device itself determines this
state. And some devices cannot enter into the Dl state.
3) D2: Some functions are shut down; it can save a lot of power. The device
itself determines this state; some devices cannot enter into the D2 state.
4) D3: Off. The power of the device under this state is completely removed, so
the next time when the power is supplied once again, it needs the operating

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system to make a setting again. Under this state, the device does not decode the
addressing line. This state needs the longest wake-up time. All devices can enter
into this state.

8.2.4 S (Sleeping) State of ACPI

S state means Sleeping, and refers the system enter into the sleeping state in G1,
also can be divided into SO, S1, S2, S3, S4, S5.

1) SO: In fact, this is our normal working state, all devices are fully open, and
the power consumption is generally more than 80 W.

2) SI: CPU internal clock has been shut down under this state, but the contents
of the system (CPU, Cache, chipset) are not lost, the other parts are still
working normally. At this time, the power consumption is generally below 30W.
In fact, some of CPU cooling software is developed in this working principle.

3) S2: Similar to SI, at this time. CPU is in the state of stop, the content of CPU
and Cache has been lost, and the bus clock is also shut down, but the rest of the
device is still running.

4) S3:This is STR(Suspend to RAM) we familiar with, in addition to the

information of the memory, the content of CPU, Cache, chipset is lost the
content of the memory is provided by the hardware, the power service data is
exist. The power consumption is less than 10W at this time.
5) S4: is also called STD (Suspend to Disk), the system main power supply is
shut down, but the system information will stored in the hard disk. By the
operating system implementation after Windows 2000, all the data of the
memory saved to hiberfil.sys file in the hard disk, the hard disk is not charged.
6) S5:A11 devices are shut down. Which is soft shutdown, the power
consumption is closed to 0.
The most commonly used is the S3 state, that is Suspend to RAM state, referred
to STR.As the name implies, STR is that to save the data of the working state
before the system entering STR into the memory. Under the state of STR, the
power still continues to supply the power for the most necessary devices, such
as memory, to ensure that the data is not lost, while other devices are in a closed
state, the power consumption of the system is very low. Once we press the
power button, the system will be awakened immediately read the data from the
memory and return to before working state of STR. The read-write speed of the

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memory is very fast, so users feel that it takes just a few seconds to enter and
leave STR state. And S4 state, that is, STD, the data is stored in the hard disk.
Because the read/write speed of the hard disk is much slower than the memory,
so it does not so fast like STR in using.

8.2.5 C State of ACPI

The C state of ACPI refers to the state of CPU, and can be divided into the
following 5 kinds.
1) C0: the normal working state of CPU.
2) C1: CPU suspends work automatically, the software is completely unaffected
under this state, and there is a minimum time to wake up. The hardware wake-
up time in this state must be small enough, so the operating software can
completely ignore the hardware wake-up time in this state when determine
whether use this device or not.
3) C2: Similar to Cl, the South bridge send STPCLK# to CPU, and stop CPU
internal clock, but CPU continues to monitor the consistency of the bus and
cache. The sequence of CO-C2-CO is shown in figure 8-8.

Figure 8-8: The sequence of C0-C2-C0

5) C4: Similar to C3 sleeping state, after the South Bridge sending STP_CPU
and closing CPU clock, the South bridge send DPRSLPVR and DPRSTP#
signal to CPU power management chip, to close the CPU core voltage. The
sequence of CO-C4-CO is shown in figure 8-10.

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Figure 8-10: The sequence of C0-C4-C0

8.2.6 The power and the control signal of ACPI

1) 3VSB:3.3V standby voltage, supply the power to the wake-up of ACPI

controller, the network card, PCI and others in the South bridge.3SVSB is the
customary name, the name of each manufacture is different, but the same
chipset, the name in the South bridge is the same.
The standard name of 3VSB in the three chipset: Intel is VCCSUS3_3; nVIDIA
is +3.3V_DUAL; AMD is S5_3.3V or VDDIO_33_S.
2) RSMRST#: the normal signal of the standby voltage. The voltage is 3.3V.
The name of RSMRST# in the three chipset: lintel and AMD are RSMRST;
nVIDIA id PWRGD SB.

3) SLP_S3#, SLP_S4#, SLP_S5#: the signal of the low level control enter
S3,S4,S5state.Forexample,the system is in the state of SO when running
normally, three signals should be invalid, is 3.3V. SUSB#, SUSC# and others

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are similar to SLP_S*# signal. The state of the sleep signal in each sleeping
state is shown in figure 8-11.

Figure 8-11: The state of the sleep signal in each sleeping state
PWRBTN#: Power Button. At shutdown, pull low PWRBTN# signal, ACPI
will set high SLP_S5#> SLP_S4#^ SLP_S3# to 3.3V in turn. If PWRBTN#
continues being the low level for 4s, the system will be forced into the S5 state.

8.3: Clock, PWRGD and The Reset Circuit

If we analogy to the each device of the computer system is a group of people,

then the clock chip is like a password. But this is not a password, is the group
with integrated multiple password. It provides the different frequency to the
main system chip and the slot on the motherboard, but there will have the same
frequency between connected devices, then it can exchange data information
normally between these chips. PG and the reset in this section are for the South
Bridge. One is the working condition of the South Bridge. And another is the
affair the South Bridge done after getting this working condition.

8.3.1 The clock circuit

1. The working condition of the clock chip.

1) As shown in figure 8-12, the working condition of the clock chip is following:
The power supply: +3VS produces +CLK_VDD> +CLK_VDD1 through L16
and L32 and provides 3.3V, +1.05V produces +CLK_VDDSRC through L15
and provides 1.05V.
2) The open signal CK_PWRGD/PD#: the high-level 3.3V opened.

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3) 14.318MHz reference crystal Y2.

4) CPUJSTOP^ PCI_STOP#: CPU and PCI clock stop instructions needs to be
the high level when working normally.
5) SMBCLK SMBDATA system management bus: used to transfer BIOS
instructions.
6) FSLA> FSLB> FSLC frequency selection: according to the different CPU to
produce the different front bus clock.

2. GM45 -The clock signal distribution of GM45 chipset

The clock signal distribution of GM 45 chipset is shown in figure 8-12, the
specific is following.
1) CLK_CPU_BCLK, CLK_CPU_BCLK# of 71, 70 pin is the front bus clock
that the clock chip send to CPU, more than 100MHz, the specific value is set by
FSA/FSB/FSC.
2) CLK_MCH_BCLK> CLK_MCH_BCLK# of 68,67 pin is the front bus clock
that the clock chip send to the North bridge, more than 100MHz,the specific is
set by FSA/FSB/FSC.
3) 24,25,28,29 pin is the set display clock that the clock chip sends to the North
bridge, 96MHz and 100MHz.
4) 32, 33 pin is the SATA controller clock that the clock chip sends to the South
Bridge, 100MHz.
5) 35, 36 pin is the PCI-E module clock that the clock chip sends to the South
Bridge, 100MHz.
6) 57, 56 pin is 100MHz core clock that the clock chip sends to the North
Bridge.
7) 44, 45 pin is 100MHz clock that the clock chip sends to MIMI PCI-E slot,
used for wireless network cards, etc.
8) 48.47 pin is 100MHz clock that the clock chip sends to the onboard card. 9)
15 pin is 33MHz clock that the clock chip sends to the EC chip.
10) 17 pin is 33MHz clock that the clock chip sends to the South Bridge, used
in the reset circuit in the South Bridge.

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11) 20 pin is 48MHz clock that the clock chip sends to the SD card reader chip
and USB controller in the South Bridge.

12) 7 pin is 14.328MHz reference clock that the clock chip sends to the South
Bridge.

13) 58, 43, 46, 21 pin is the request signal of each clock, the low level is
effective.

Figure 8-12: The clock signal distribution of GM45 chipset

3. HM55 The clock signal distribution of HM55 chipset

The clock signal distribution of HM55 is shown in figure 8-13, the

characteristic is that the clock chip is just sent to PCH clock, and then sent out
each clock by PCH to other devices. If it supports the display stand, the display
set supports DVI/DP/HDMI/e-DP interface. The bridge needs 25MHz crystal.

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Figure 8-13

4. The clock signal distribution of above HM65 chipset

The clock signal distribution of above HM65 chipset is shown in figure 8-14,
the characteristic is that it must be 25MHz crystal when the bridge integrates the
clock chip.

Figure 8-14: The clock signal distribution of above HM65 chipset

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5. AMD- The clock signal distribution of AMD double bridge chipset

The clock signal distribution of AMD double bridge chipset is shown in figure
8-15, the clock chip sends each clock, but is just not responsible for sending
33MHz clock, 33MHz clock is sent by the South bridge.

Figure 8-15: The clock signal distribution of AMD double bridge chipset

6. AMD- The clock signal distribution of AMD single bridge

The clock signal distribution of AMD single bridge is shown in figure 8-16, the
characteristic is | that the bridge integrates the clock chip.

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Figure 8-16: The clock signal distribution of AMD single bridge chipset

7. nVIDIA- The clock signal distribution of nVIDIA chipset

The clock signal distribution of nVIDIA chipset is shown in figure 8-17; the
characteristic is that the bridge integrates the clock.

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Figure 8-17: The clock signal distribution of nVIDIA chipset

8.3.2 PWRGD and the reset circuit

The explanation of VRMPWRGD, PWROK, CPUPWRGD, PLTRST#,
PCIRST# signal in the South Bridge is following:

VRMPWRGD: this signal should be connected to the PWRGD signal of CPU

power supply chip, used to indicate that the CPU core voltage is stable. This
signal phase with PWROK signal is in the South Bridge. The text of
VRMPWRGD pin definition is shown in figure 8-18.

VRMPWRGD I VRM Power Good: This should be connected to be the

processor's VRM is stable. This signal is internally
ANDed with the PWROK input.
Figure 8-18: The screenshot the text about VRMPWRGD pin definition

PWROK: when the signal is effective, PWROK inform that all power of ICH
has been generated ' and stable for 99ms, PCICLK has been stable for

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 Laptop Chip Level Repair Guide 123

1ms.When PWROK becomes lower level, ICH produces PLTRST# with low
level. Note: PWROK must be inactive for three RTCCLK clock cycles at least.
The screenshot of the text about PWROK pin definition is shown in figure 8-19.
CPUPWRGD: CPU power good, this signal should be connected to
PWRGOOD pin of the processor, indicates that CPU power supply is effective.
This is an output signal, formed by the phase of PWROK and VRMPWRGD. The
text of CPUPWRGD pin definition is shown in figure 8-20.

Figure 8-19: The screenshot of the text about PWROK pin definition

Figure 8-20: The screenshot of the text about CPUPWRGD pin definition

PLTRST#: ICH produces PLTRST# signal to reset all devices (such as SIO,
FWH, LAN, GMCH, TPM, etc.) on the entire hardware platform. When
PWROK and VRMPWRGD are high level, ICH will delay 1ms and drive
PLTRST# to be high level. The text of PLTRST# pin definition is shown in
figure 8-21.

Figure 8-21: The screenshot of the text about PLTRST# pin definition

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 Laptop Chip Level Repair Guide 124

PCIRST#: This is the second reset signal, which is produced by the PLTRST#
delayed buffer. The text of PCIRST# pin definition is show in figure 8-22.

Figure 8-22: The screenshot of the text about PCIRST# pin definition

At last, after the RST1N# pin (the pin definition is shown in figure 8-23) of the
North bridge receiving PLTRST# sent by the South bridge. Delayed 1ms send
CPURST# to CPU, to complete the hard start. HCPURST# pin definition is
shown in figure 8-24.

Figure 8-23: The screenshot of the text RSTIN# pin definition

Figure 8-24: The screenshot of the text about HCPURST# pin definition

The sequence of the reset circuit is as shown in figure 8-25.

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 Laptop Chip Level Repair Guide 125

Figure 8-25: The sequence of the reset circuit

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