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Ecet146 Lab4 F24

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22 views10 pages

Ecet146 Lab4 F24

Uploaded by

kero adel
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Lab 4

Semester : Fall Year : 2024


Course Title : Introduction to Digital System Design II
Course Code : ECET146
Instructor(s) : Ahmad Abdullah, Suheyla Dabbour, Gulden Eleyan
(Includes names of all instructors teaching
this course)

Grading Scheme

Project Setup with different Verilog files 20%


Verilog Coding of sub-block 25%
Verilog Coding of top level 25%
Waveform simulations 10%
Upload the combinational logic circuit code to FPGA Kit 20%

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Important Notes:
- Any attempt at plagiarism or cheating will be reported. All ACM handbook academic misconduct rules will be applied.
- It is the responsibility of the student to submit this online assessment paper to the instructed online platform (Moodle,
Turnitin) if applicable.

1. Objectives
1. To learn how to write structural descriptions Verilog code
2. To learn how to simulate Verilog code and generate the corresponding waveform 3.
To learn how to interpret the output of Verilog code simulation

2. Equipment
Simulator: Quartus II
FPGA Board

3. Pre-Lab Preparation
1. Lecture 3
2. Follow carefully the explanation of the instructor
3. Read the given manuals regarding Quartus II software
4. Read this document in its entirety

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Question 1. Consider the below Full Subtractor combinational logic circuit. This circuit
performs the subtraction between the two 1-bit binary numbers (minuend A and
subtrahend B) and considers the borrow of the previous bit (Bin). There are two
outputs, one corresponds to the difference (Diff) output and the other borrow output
(Bout).

Figure 2. Full Subtractor block diagram

Figure 3. Half Subtractor circuit Use


below given Verilog code for the Half Subtractor.

module HalfSubtractor(x,y,b,d);
input x,y; output d,b; wire w1; xor gate1(d,x,y); not gate2 (w1, x);
and gate3 (b, y, w1);
endmodule

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a. Write the structural description Verilog code for the Full Subtractor.

module HalfSubtractor (x, y, b, d);


input x, y;
output d, b;
wire w1;

xor gate1(d, x, y);


not gate2(w1, x);
and gate3(b, y, w1);
endmodule

module FullSubtractor (A, B, Bin, Diff, Bout);


input A, B, Bin;
output Diff, Bout;
wire w1, w2, w3;

// Instantiating the first Half Subtractor

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HalfSubtractor Hs1 (.x(A), .y(B), .d(w1), .b(w2));

// Instantiating the second Half Subtractor


HalfSubtractor Hs2 (.x(w1), .y(Bin), .d(Diff), .b(w3));

// Bout output using OR gate for borrow


or (Bout, w2, w3);

endmodule

b. Perform the waveform simulation of your circuit. All the possible combinations
between the 3 inputs to be considered. Order of pins should be: A, B, Bin, Diff, Bout.

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Question 2.
Consider below circuit.

Figure1. Block diagram of ECET146CIRCUIT Consider


the Verilog code for the two sub-blocks of given circuit:

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module HalfAdder (x,y,cout,s); module FullAdder (x,y,cin,cout,s);
input x,y; output s,cout; input x, y,cin; output s, cout;
assign s = x^y; wire c1,c2,s1;
assign cout = x&y; endmodule
HalfAdder HA1 (x,y,c1,s1);
HalfAdder HA2 (s1,cin,c2,s);
assign cout = c1|c2; endmodule

a. Write the structural level Verilog code for the top level.
module HalfAdder (x,y,cout,s);

input x,y;

output s,cout;

assign s = x^y;

assign cout = x&y;

endmodule

module FullAdder (x,y,cin,cout,s);

input x, y,cin;

output s, cout;

wire c1,c2,s1;

HalfAdder HA1 (x,y,c1,s1);

HalfAdder HA2 (s1,cin,c2,s);

assign cout = c1|c2;

endmodule

module ECET146CIRCUIT(A0, B0, A1, B1, sum0, sum1, sum2);

input A0, B0, A1, B1;

output sum0, sum1, sum2;

wire carry0, carry1;


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// Instantiate Half Adder for the lower bits

HalfAdder HA1 (.x(A0), .y(B0), .s(sum0), .cout(carry0));

// Instantiate Full Adder for the upper bits

FullAdder FA1 (.x(A1), .y(B1), .cin(carry0), .s(sum1), .cout(carry1));

// Connect carry1 to sum2 as the final carry out

assign sum2 = carry1;

endmodule

Perform the waveform simulation of your circuit and insert a clear screenshot with the
below requirements:

- All the possible combinations between the 4 inputs to be considered.


- Order of pins should be: A0, B0, A1, B1, sum0, sum1, sum2.

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Follow the instructions given in the manual (4. Pin Planner) for configuring the pins
of the circuit with the FPGA board.

PIN Name of PIN in FPGA


board
A1 SW3
B1 SW2

A0 SW1
B0 SW0
sum2 LDR2
sum1 LDR1
sum0 LDR0

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* Upload the configuration on the FPGA board. (Graded as part of the experiment).
Call your instructor to show your work

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