R-23 DIGITAL LOGIC DESIGN AND COMPUTER ORGANIZATION II B.

Tech - I Sem

UNIT-V

INPUT-OUTPUT ORGANIZATION

Course Objectives

• To familiarize with the concept of I/O organization and interaction with processor & memory,
peripheral devices.

Course Outcome

• Explain I/O system and their interaction with processor, memory, peripheral devices.

• Differentiate between synchronous and asynchronous transfer.

Syllabus:

5.1 Accessing I/O Devices

5.1.1 Memory mapped I/O

5.1.2 I/O mapped I/O

5.1.3 Program Controlled I/O

5.1.4 Mechanisms Used For Interfacing I/O Operations

5.2 Interrupts

5.2.1 Interrupt Hardware

5.2.2 Enabling and Disabling Interrupts

5.3 Processor Examples

5.3.1 ARM Interrupt Structure

5.3.1.1 Introduction to ARM

5.3.1.2 Sources for Exceptions in ARM

5.3.2 68000 Interrupt Structure

5.3.2.1 Introduction

5.3.2.2 Interrupt structure

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5.4 Direct Memory Access

5.4.1 Modes of DMA Transfer

5.4.2 Use of DMA Controller

5.4.3 Bus Arbitration

5.4.3.1 Centralized Arbitration

5.4.3.2 Distributed Arbitration

5.5 Buses

5.5.1 Synchronous Bus

5.5.2 Asynchronous Bus

Introduction:

Peripheral devices

• The input-output subsystem of a computer, referred to as I/O.

• Input or output devices attached to the computer are also called peripherals.

• Among the most common peripherals are keyboards, display units, and printers.

• Devices that are under the direct control of the computer are said to be connected on-line.

• Video monitors are the most commonly used peripherals. They consist of a keyboard as the input

device and a display unit as the output device.

5.1 Accessing I/O Devices

Fig 5.1: A single-bus structure

The I/O devices are connected by using a single bus which enables data transaction between each

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deviceas shown in Fig 5.1

• Bus consists of 3 sets of lines used to carry address, data and control signals.

• Each I/O device is assigned a unique set of address. When the processor places a particular
address on the address lines, the device that recognizes this address responds to the commands
issued on the control lines.
• The processor requests either a read or a write operation which is transferred over the data lines.
When I/O devices and the memory share the same address space, the arrangement is called
memory-mapped I/O. There are two ways to deal with I/O devices.

5.1.1 Memory mapped I/O

• The Memory and I/O devices are sharing information by a common address-space. Any data-
transfer instruction (like Move, Load) can be used to exchange information. For example,
Move DATAIN, R0

• This instruction reads data from DATAIN (address of input-buffer associated with Keyboard) &
stores them into processor-register R0.
Move R0, DATAOUT

• This instruction sends the contents of register R0 to location DATAOUT, which may be the
output data buffer of a display unit or a printer.

5.1.2 I/O mapped I/O

• In I/O mapped I/O, the memory and I/0 address-spaces are different. Special instructions are
used fordata transfer such as IN and OUT.

• The I/O devices use special I/O address space or memory address space.
• The I/O devices examine the low-order bits of the address bus to determine whether they should
respond.
• Advantage of separate I/O space: I/O devices deal with fewer address-lines.
• The hardware required to connect an I/O device to the bus as shown in the Fig 5.2

• The address decoder enables the device to recognize its address when this address appears on the
address lines.
• The data register holds the data being transferred to or from the processor.
• The status register contains information relevant to the operation of the I/O device.
• Both the data and status registers are connected to the data bus and assigned unique addresses.

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The address decoder, the data and status registers, and the control circuitry required to coordinate
I/O transfers constitute the device's interface circuit.

Fig 5.2: I/O interface for an input device

5.1.3 Program Controlled I/O

• Processor repeatedly checks a status-flag to achieve required synchronization between processor

& input/output device. (We say that the processor polls the device).
Drawback: The processor wastes its time in checking the status of the device before actual data
transfer takes place.

5.1.4 Mechanisms Used For Interfacing I/O Operations:

Interrupt I/O
• Synchronization is achieved by having I/O device send a special signal over bus whenever it is
ready for a data transfer operation.

Direct Memory Access (DMA)

• This involves having the device-interface transfer data directly to or from the memory without
continuous involvement by the processor. This technique is used for high-speed I/O devices.

5.2 Interrupts

• There are many situations where other tasks can be performed while waiting for an I/O device to
become ready. A hardware signal called an Interrupt will alert the processor when an I/O device
becomes ready. It can do so by sending a hardware signal called an interrupt to the processor.

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Fig 5.3: Schematic of Interrupt I/O

• For example, consider, COMPUTE and PRINT routines. The routine executed in response to an
interrupt request is called interrupt-service routine.
• Transfer of control through the use of interrupts happens. The processor must inform the device
that its request has been recognized by sending interrupt-acknowledge signal.

Fig 5.4: Transfer of control through the interrupts

• One must therefore know the difference between Interrupt Vs Subroutine. Interrupt latency is
concerned with saving information in registers will increase the delay between the time an
interrupt request is received and the start of execution of the interrupt-service routine.
• Processor is executing the instruction located at address i when an interrupt occurs.
• Routine executed in response to an interrupt request is called the interrupt-service routine.
• When an interrupt occurs, control must be transferred to the interrupt service routine.
• But before transferring control, the current contents of the PC (i+1), must be saved in a known
location.
• This will enable the return-from-interrupt instruction to resume execution at i+1.

• Return address, or the contents of the PC are usually stored on the processor stack.

Interrupt latency: Delay between the time an interrupt request is received and the start of execution of
the interrupt service routine.

5.2.1 Interrupt Hardware

• An I/O device requests an interrupt by activating a bus-line called interrupt-request (IR).

• A single interrupt request line may be used to serve n devices as depicted. All devices are

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connected to the line via switches to ground. To request an interrupt, a device closes its
associated switch. Thus, if all interrupt-request signals INTR1 to INTRn are inactive, that is, if
all switches are open, the voltage on the interrupt-request line will be equal to Vdd.
• This is the inactive state of the line. Since the closing of one or more switches will cause the line
voltage to drop to 0, causing the interrupt request signal, INTR received by the processor to go
to 1.
• The value of INTR is the logical OR of the requests from individual devices, that is,
INTR = INTR1 + ………+INTRn

It is customary to use the complemented form, INTR, to name the interrupt-request signal on the
common line, because this signal is active when in the low-voltage state.

Fig 5.5: An equivalent circuit for an open-drain bus used to implement a common interrupt-request line

• The Fig 5.5 shows that special gates known as open-collector (for bipolar circuits) or open-drain
(for MOS circuits) are used to drive the INTR line. The output of an open-collector or an open-
drain gate is equivalent to a switch to ground that is open when the gate‟s input is in the 0 state
and closed when it is in the 1 state. Resistor R is called a pull-up resistor because it pulls the line
voltage up to the high-voltage state when the switches are open.

5.2.2 Enabling and Disabling Interrupts

• The facilities provided in a computer must give the programmer complete control over the events
that take place during program execution. The arrival of an interrupt request from an external

device causes the processor to suspend the execution of one program and start the execution of
another.
• Because interrupts can arrive at any time, they may alter the sequence of events from the
envisaged by the programmer. Hence, the interruption of program execution must be carefully
controlled.
• Let us consider in detail the specific case of a single interrupt request from one device. When a
device activates the interrupt-request signal, it keeps this signal activated until it learns that the

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processor has accepted its request.

• This means that the interrupt-request signal will be active during execution of the interrupt-
service routine, perhaps until an instruction is reached that accesses the device .

• This activated signal, if not deactivated, may lead to successive interruptions, causing the system
to enter into an infinite loop.

To prevent the system from entering into an infinite-loop because of interrupt, there are 3 possibilities

First Option

• The first possibility is to have the processor hardware ignore the interrupt-request line until the
execution of the first instruction of the interrupt-service routine has been completed.
• Then, by using an Interrupt-disable instruction as the first instruction in the interrupt-service
routine, the programmer can ensure that no further interruptions will occur until an Interrupt-
enable instruction is executed.
• Typically, the Interrupt-enable instruction will be the last instruction in the interrupt-service
routine before the Return-from-interrupt instruction. The processor must guarantee that
execution of the Return-from-interrupt instruction is completed before further interruption can
occur.

Second Option

• The second option is to have the processor automatically disable interrupts before starting the
execution of the ISR.
• After saving the contents of the PC and the processor status register (PS) on the stack, the
processor performs the equivalent of executing an Interrupt-disable instruction. It is often the
case that one bit in the PS register, called Interrupt-enable, indicates whether interrupts are
enabled.

Third option

• In the third option, the processor has a special interrupt-request line for which the interrupt-
handling circuit responds only to the leading edge of the signal. Such a line is said to be edge-
triggered. Processor will receive only one request hence there will not be multiple interruption.

Sequence of events involved in handling an interrupt-request from a single device is as follows:

1. The device raises an interrupt request.

2. The processor interrupts the program currently being executed.

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3. Interrupts are disabled by changing the control bits in the PS (except in the case of edge-
triggeredinterrupts).
4. The device is informed that its request has been recognized, and in response, it
deactivates theinterrupt-request signal.

5. The action requested by the interrupt is performed by the interrupt-service routine.

6. Interrupts are enabled and execution of the interrupted program is resumed.

5.3 Processor Examples

5.3.1 ARM Interrupt Structure
5.3.1.1 Introduction to ARM
• A collection of Reduced Instruction Set Computer (RISC) instruction set architectures for
computer processors that are tailored for different contexts is known as ARM (stylized in
lowercase as an arm; originally an abbreviation for Advanced RISC Machines.
• For light, portable, battery-powered devices like smartphones, laptops, and tablet computers, as
well as other embedded systems, ARM processors are preferred because they are less expensive,
consume less power, and generate less heat than their competitors.
• Modes of operation
ARM processor has 7 modes of operation.
➢ Switching between modes can be done manually through modifying the mode bits in the
CPSR register.
➢ Most application programs execute in user mode
➢ Non user modes (called privileged modes) are entered to serve interrupts or exceptions
➢ The system mode is special mode for accessing protected resources. It don‘t use registers used
by exception handlers, so it can‘t be corrupted by any exception handler error.

Fig 5.6: ARM Modes of operation

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• ARM register set

➢ ARM processor has 37 32-bit registers.

➢ 31 registers are general purpose registers.
➢ 6 registers are control registers
➢ Registers are named from R0 to R16 with some registers banked in different modes
➢ R13 is the stack pointer SP (Banked)
➢ R14 is subroutine link register LR (Banked)
➢ R15 is progrm counter PC
➢ R16 is current program status register CPSR (Banked)

Fig 5.7: Accessible registers in different modes of the ARM processor

5.3.1.2 Sources for Exceptions in ARM

• The term exception is used to refer to any event that causes an interruption
• ARM processor has five sources for exceptions, only two of which are external interrupt
request lines, IRQ(Interrupt ReQuest) and FIQ (Fast Interrupt reQuest).

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• There is one software interrupt instruction, SWI and two exceptions that may be caused by
abnormal conditions encountered during program execution. These exceptions are an
external abort following a bus error and an attempt to execute an undefined instruction.
• The Reset condition is included in this structure because it must override all other conditions
to bring the processor to a known starting condition.
• There are two abort conditions. Data Abort arises from an error in reading or writing data,
and Prefetch abort arises from an error when prefetching instructions from the memory.

Table 5.1 Interrupt Vector Addresses for ARM Processor

Address (Hex) Exception Mode entered
0 Reset Supervisor
4 Undefined instruction Undefined
8 Software interrupt Supervisor
C Abort during prefetch Abort
10 Abort during data Abort
14 Reserved
18 IRQ IRQ
1C FIQ FIQ

• All interrupts are disabled on startup for the ARM CPU until the initialization code turns them
on.
• The Processor Status Registers’ bit can be changed to enable or disable the interrupts (PSR or
CPSR where C stands for current).

Fig 5.8: CPSR Structure

• The CPSR also determines whether the processor is decoding Thumb instructions and the
processor mode (SVC, System, User, etc.).
• The application can read and write to the CPSR in its entirety when operating in privileged
mode, but it can only read the CPSR when operating in non-privileged mode.

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• The processor enters the appropriate interrupt or exception mode in response to an interrupt or
exception, which causes a portion of the main registers to be banked, swapped out, or replaced
with set mode registers.
• The interrupt masks’ ability to be enabled and disabled is controlled by bits. The two interrupt
inputs on the ARM processor can both be regarded as general-purpose interrupts. Interrupt
Request (IRQ) and Fast Interrupt Request are the names of the first and second, respectively
(FIQ)

• The regular sequential execution of instructions can be stopped by one of seven events on the
ARM processor. Since not all events are created equal, the processor must adopt a priority
strategy because these events may occur simultaneously.
• Exceptions are handled according to the following priority structure
1. Reset (Highest Priority)
2. Data Abort
3. FIQ
4. IRQ
5. Prefetch Abort
6. Undefined Instruction (Lowest Priority)

5.3.2 68000 Interrupt Structure

5.3.2.1 Introduction
• Motorola 68000 is a 16/32-bit complex instruction set computer (CISC) Microprocessor.
• It has 32-bit data and address registers. Externally the processor has 16-bit data bus and 24-bit
address bus, which limits the size of addressable memory to 16 MB.
• It uses a 16-bit data arithmetic logic unit (ALU). The Register architecture of 68000 is shown in
Fig 5.9.
• The data registers can be used to handle (8-bit) bytes, (16-bit) words, or 32-bit long words.
• There are seven general purpose Address registers (A0-A6). These registers can handle either 16-
bit word or 32-bit long word operands.
• A 16-bit status register is divided into two 8-bit bytes : The system byte and the user byte. Fig.
shows the bit assignments for the status register. The system byte of the status register contains
status information that is system-related. The user byte, on the other hand, contains the condition
code status bits (X, N, Z, V and C) which are instruction or program related. Bits in the system
byte of the Status register can only be altered when the MC 68000 is in the supervisor mode.

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Fig 5.9: Register Architecture of 68000

Fig 5.10: Status register bit pattern

• Bit 13 of the status register is the S-bit, which specifies whether the MC68000 is in the supervisor or
user mode of operation. When the bit is 1, the MC68000 is in the supervisor mode, and when it is 0
the microprocessor is in the user mode.
• The most significant bit of the status register is the Trace (T) flag. If this bit is 0 then the MC68000
operates normally. However, if the bit is 1, the microprocessor is in the trace mode of operation.
After each instruction is executed in the trace mode, a trap is forced so that a debugging program
can monitor the results of that instruction’s execution.

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5.3.2.2 Interrupt structure

• The 68000 has eight interrupt priority levels. The priority at which the processor is running at
any given time is encoded in three bits of the processor status word (I2, I1, I0) With level 0
being the lowest priority.

Table 5.2: Interrupt Levels

• Levels 1 through 6 are the mask-enabled levels.

• For example, if you set the mask to 100 then only levels 5, 6 and 7 will be enabled; interrupt
‘levels 1 through 4 are disabled.
• An interrupt request is accepted only if its priority is higher than that of the processor, with one
exception: An interrupt request at level 7 is always accepted. This is an edge triggered non
maskable interrupt.
• When the processor accepts an interrupt request, the priority level indicated in the Processor
Status (PS) register is automatically raised to that of the request before interrupt request routine is
executed. This requests of equal or lower priority are disabled, except for level-7 interrupts, which
are always enabled.
• The processor automatically saves the contents of the program counter and the processor status
word at the time of interruption. The PC is pushed on to the processor stack followed by the PS,
using register A7 as the stack pointer.
• A Return from interrupt instruction, called Return-from-exception(RTE), pops the top element of
the stack into the PS and pops the next element into the PC.
• The 68000 processor uses vectored interrupts. When it accepts an interrupt request, it obtains the
starting address of the interrupt-service routine from an interrupt vector stored in main memory.
• There are 256 interrupt vectors, numbered o through 255. Each vector consists of 32 bits that

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constitute the required starting address.

5.4 Direct Memory Access (DMA)

• A special control unit will be provided to allow the transfer of large block of data at high speed
directly between the external device and main memory, without continuous intervention by the
processor. This approach is called direct memory access (DMA). DMA transfers are performed
by a control circuit called the DMA Controller.

Fig 5.11: Registers in a DMA Interface

• To initiate the transfer of a block of words, the processor sends, are Starting address, Number of
words in the block and Direction of transfer.
• When a block of data is transferred, the DMA controller increment the memory address for
successive words and keep track of number of words and it also informs the processor by raising
an interrupt signal.

• While DMA control is taking place, the program requested the transfer cannot continue and the
processor can be used to execute another program. After DMA transfer is completed, the
processor returns to the program that requested the transfer.

• The above Fig 5.11 shows an example of the DMA controller registers that are accessed by the
processor to initiate transfer operations. Two registers are used for storing the Starting address
and the word count. The third register contains status and control flags. The R/W bit determines
the direction of the transfer. When

➢ R/W =1, DMA controller read data from memory to I/O device.
➢ R/W =0, DMA controller perform write operation.
➢ Done Flag=1, the controller has completed transferring a block of data and is ready to
receiveanother command.
➢ IE=1, it causes the controller to raise an interrupt (interrupt Enabled) after it has
completedtransferring the block of data.

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➢ IRQ=1, it indicates that the controller has requested an interrupt.

• A DMA controller connects a high speed network to the computer bus. The disk controller two
disks, also has DMA capability and it provides two DMA channels. To start a DMA transfer of a
block of data from main memory to one of the disks, the program write s the address and the
word count information into the registers of the corresponding channel of the disk controller.
When DMA transfer is completed, it will be recorded in status and control registers of the
DMA channel (i.e.) done bit=IRQ=IE=1.

5.4.1 Modes of DMA Transfer

5.4.1.1 Cycle Stealing:

• Memory accesses by the processor and the DMA controller are inter woven. Requests by DMA
devices for using the bus are always given higher priority than processor requests.
• Among different DMA devices, top priority is given to high-speed peripherals such as a disk, a
high-speed network interface, or a graphics display device.
• Since the processor originates most memory access cycles, the DMA controller can be said to
“steal” memory cycles from the processor. Hence, the interweaving technique is usually called
cycle stealing.

5.4.1.2 Burst Mode:

• The DMA controller may be given exclusive access to the main memory to transfer a block of
data without interruption. This is known as Burst/Block Mode.

5.4.2 Use of DMA Controller

• An example of computer system is given in Fig 5.12, showing how DMA controllers may be
used.

• A DMA controller connects a high speed network to the computer bus. The disk controller,
which controls two disks, also has DMA capability and provides two DMA channels. It can
perform two independent DMA operations, as if each disk had its own DMA controller.

• The registers needed to store the memory address, the word count, and so on are duplicated, so
that one set can be used in each device.

• To start a DMA transfer of a block of data from the main memory to one of the disks, a program
writes the address and word count information into the registers of the corresponding channel of
the disk controller. It also provides the disk controller with information to identify the data for

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future retrieval.

• The DMA controller proceeds independently to implement the specified operation. When the
DMA transfer is completed, the done bit is set. At the same time IE bit is set, the controller sends
an interrupt request to the processor and sets the IRQ bit.

• The status register can also be used to record other information, such as whether the transfer took
place correctly or errors occurred.

Fig 5.12: Use of DMA controllers in a computer system

5.4.3 Bus Arbitration

• The device that is allowed to initiate data transfers on the bus at any given time is called the bus
master.

• Bus Arbitration is the process by which the next device to become the bus master is selected
and the bus mastership istransferred to it.

There are 2 approaches to bus arbitration. They are,

1. Centralized arbitration (A single bus arbiter performs arbitration)

2. Distributed arbitration (all devices participate in the selection of next bus master).

5.4.3.1 Centralized Arbitration:

• Here the processor is the bus master and it may grants bus mastership to one of its DMA
controller. A DMA controller indicates that it needs to become the bus master by activating the

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̅̅̅̅) which is an open drain line. The signal on Bus Request is the logical OR
Bus Request line (𝐵𝑅
of the bus request from all devices connected to it.
• When Bus Request is activated, the processor activates the Bus Grant Signal (BG1) and indicates
the DMA controller that they may use the bus when it becomes free. This signal is connected to
all DMA controllers using a daisy chain arrangement.
• If DMA controller 1 requests the bus, it blocks the propagation of Grant Signal to other devices
and it indicates to all devices that it is using the bus by activating open collector line, Bus Busy
(BBSY). Otherwise it passes the grant downstream by asserting BG2.

Fig 5.13: A simple arrangement for bus arbitration using a daisy chain

• The timing diagram shows the sequence of events for the devices connected to the processor is
shown in Fig 5.14. DMA Controller 2 requests and acquires bus mastership and later releases the
bus. During its tenure as bus master, it may perform one or more data transfer operations,
depending on whether it is operating in the cycle stealing or block mode. After it releases the
bus, the processor resumes bus mastership.

Fig 5.14: Sequence of signals during transfer of bus mastership for the devices

5.4.3.2 Distributed Arbitration:

• Distributed arbitration means that all devices waiting to use the bus have equal responsibility in
carrying out the arbitration process, without using a central arbiter.

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• Each device on the bus is assigned a 4 bit Identification number. When one or more devices
request the bus, they assert the ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝑆𝑡𝑎𝑟𝑡 − 𝐴𝑟𝑏𝑖𝑡𝑟𝑎𝑡𝑖𝑜𝑛 signal and place their 4 bit ID number on
four open collector lines, ̅̅̅̅̅̅̅̅
𝐴𝑅𝐵0 to ̅̅̅̅̅̅̅̅
𝐴𝑅𝐵3
• A winner is selected as a result of the interaction among the sig.nals transmitted over these lines.
The net outcome is that the code on the four lines represents the request that has the highest ID
number. The drivers are of open collector type.
• Hence, if the input to one driver is equal to 1, the input to another driver connected to the same
bus line is equal to “0” the bus will be in low-voltage state.
Example:

• Assume two devices A and B have their ID 5 (0101), 6(0110) and their code is 0111. Each
device compares the pattern on the arbitration line to its own ID, starting from most significant
bit (MSB).
• If it detects a difference at any bit position, it disables the drivers at that bit position and for all
lower-order bits. It does this by placing “0” at the input of these drivers. In our example, device
“A” detects a difference in line ̅̅̅̅̅̅̅̅
𝐴𝑅𝐵1.

Fig 5.15: A distributed arbitration scheme

• Hence it disables the drivers on lines ̅̅̅̅̅̅̅̅
𝐴𝑅𝐵1 and ̅̅̅̅̅̅̅̅
𝐴𝑅𝐵0. This causes the pattern on the
arbitrationline to change to 0110 which means that “B” has won the contention.
• It has the advantage of offering higher reliability, because operation of the bus is not dependent
on any single device.

5.5 Buses
• A bus protocol is the set of rules that govern the behavior of various devices connected to the

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bus as to when to place information on the bus, assert control signals, and so on. The bus lines
used for transferring data is grouped into 3 types. They are Address line, Data line and Control
line.
• Control signals Specifies that whether read or write operation has to perform and also carries
timing information. They specify the time at which the processor & I/O devices place the data
onthe bus and receive the data from the bus.
• During data transfer operation, one device plays the role of a “Master”. Master device initiates
the data transfer by issuing read or write command on the bus. Hence it is also called as
“Initiator”. The device addressed by the master is called as Slave or Target.

• There are 2 types of buses. They are Synchronous Bus and Asynchronous Bus.

5.5.1 Synchronous Bus

• In synchronous bus, all devices derive timing information from a common clock line. Equally
spaced pulses on this line define equal time intervals. In the simplest form of a synchronous
bus, each of these intervals constitutes a bus cycle during which one data transfer can take
place. Such scheme is shown in Fig 5.16.

Fig 5.16: Timing of an input transfer on a synchronous bus

5.5.1.1 Sequence of events during a read operation:

• At time t0, the master places the device address on the address lines and sends an appropriate
command on the control lines. In this case, the command will indicate an input operation and
specify the length of the operand to be read.

• The clock pulse width t1 – t0 must be longer than the maximum delay between devices
connected to the bus. The clock pulse width should be long to allow the devices to decode the
address and control signals so that the addressed device can respond at time t1. The slaves take no
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action or place any data on the bus before t1.

• The information on the bus is unreliable during the period t0 – t1 because signals are changing
state. The addressed slave places data on the data lines at time t1.

• The Fig 5.17 gives more realistic picture of what happens in practice. It shows two views of the
signal except the clock.

• One view shows the signal seen by the master and the other is seen by the slave. T The dthe
master sends the address and command signals on the rising edge at the beginning of clock
period (t0). These signals do not actually appear on the bus until tAM. A while later, at tAS the
signals reach the slave. The slave decodes the address and at t1, it sends the requested data. The
data signals do not appear on the bus until tDS . They travel toward the master and arrive at tDM .
• At t2, the master loads the data into its input buffer. Hence the period t2 - tDM is the setup time
for the masters input buffer. The data must be continued to be valid after t2, for a period equal to
the hold time of that buffers.

Fig 5.17: A detailed timing diagram for the input transfer

Demerits:

1. The device does not respond.

2. The error will not be detected.

5.5.1.2 Multiple Cycle Transfer

• During, clock cycle1, the master sends address and command information. On the bus requesting
a “read” operation. The slave receives this information and decodes it. At the active edge of the
clock (i.e.) the beginning of clock cycel2, it makes accession to respond immediately.

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• The data become ready and are placed in the bus at clock cycle3. At the same times, the slave
asserts a control signal called “slave-ready”. The master device has been waiting for this signal,
strobes, and the data to its input buffer at the end of clock cycle3.
• The bus transfer operation is now complete & the master sends a new address to start a new
transfer in clock cycle4. The „slave-ready‟ signal is an acknowledgement form the slave to the
master confirming that valid data has been sent.

Fig 5.18: An input transfer using multiple clock cycles

5.5.2 Asynchronous Bus

• An alternate scheme for controlling data transfer on the bus is based on the use of
“handshake” between Master and the Slave. The common clock is replaced by two timing
control lines. They are Master–ready and Slave ready.

Fig 5.19: Handshake control of data transfer during an input operation

• The handshake protocol proceeds as follows:

➢ At t0: The master places the address and command information on the bus and all devices
on the bus begin to decode the information.

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➢ At t1: The master sets the Master ready line to 1 to inform the I/O devices that the address
and command information is ready.

▪ The delay t1 – t0 is intended to allow for any skew that may occur on the bus.

▪ The skew occurs when two signals simultaneously transmitted from one source
arrive at the destination at different time.
▪ Thus to guarantee that the Master ready signal does not arrive at any device a head
of the address and command information the delay t1 – t0 should be larger than the
maximum possible bus skew.
➢ At t2: The selected slave having decoded the address and command information performs
the required i/p operation by placing the data from its data register on the data lines. At the
same time, it sets the “slave – Ready” signal to 1.

➢ At t3:The slave ready signal arrives at the master indicating that the input data are available
on the bus.

➢ At t4: The master removes the address and command information on the bus. The delay
between t3 and t4 is again intended to allow for bus skew. Erroneous addressing may take
place if the address, as seen by some device on the bus, starts to change while the master –
ready signal is still equal to 1.

➢ At t5: When the device interface receives the 1 to 0 transitions of the Master–ready signal,
it removes the data and the slave – ready signal from the bus. This completes the input
transfer.

• In Fig 5.20, the master place the output data on the data lines and at the same time it transmits
the address and command information. The selected slave strobes the data to its output buffer
when it receives the Master ready signal and it indicates this by setting the slave–ready signal to
1. At time t0 to t1 and from t3 to t4, the Master compensates for bus.

• In the above and below timing diagrams, it is assumed that the master compensates for bus skew
and address decoding delay. It introduces the delays from t0 to t1 and from t3 to t4 for this
purpose. If this delay provides sufficient time for the I/O device interface to decode the address,
the interface circuit can use the Master-ready signal directly to gate other signals to or from the
bus,

• A change of state is one signal is followed by a change is the other signal. Hence this scheme is
called asFull Handshake. It provides the higher degree of flexibility and reliability.

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Fig 5.20: Handshake control of data transfer during an output operation

Advantages of asynchronous bus:

• Eliminates the need for synchronization between the sender and the receiver.
• Can accommodate varying delays automatically, using the Slave-ready signal.

Disadvantages of asynchronous bus:

▪ Data transfer rate with full handshake is limited by two-round trip delays.
▪ A data transfer using a synchronous bus involves only one round trip delay, and hence a
synchronous bus can achieve faster rates.

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Assignment cum Tutorial Questions
5.1 Accessing I/O Devices

Objective Questions

1. Which of the following is correct in I/O mapped I/O [ ]

a) The memory and I/0 address-spaces are different

b) The memory and I/0 address-spaces are same

c) None of the above

2. Which of the following is correct in Memory mapped I/O [ ]

a) The memory and I/0 address-spaces are different

b) The memory and I/0 address-spaces are same

c) None of the above

3. The bus used in I/O devices consists of the three sets of lines used to carry [ ]

a) Address, data and control signals b) Address and data

c) Data and control signals d) None of the above

4. The usual BUS structure used to connect the I/O devices is ___________ [ ]
a) Star BUS structure b) Multiple BUS structure
c) Single BUS structure d) Node to Node BUS structure

5. In memory-mapped I/O ____________ [ ]

a) The I/O devices and the memory share the same address space
b) The I/O devices have a separate address space
c) The memory and I/O devices have an associated address space
d) A part of the memory is specifically set aside for the I/O operation

6. The method of accessing the I/O devices by repeatedly checking the status [ ]
flags is ___________
a) Program-controlled I/O b) Memory-mapped I/O
c) I/O mapped d) None of the mentioned

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Descriptive Questions

S.No. Name of the question BL

1. How to access I/O devices and explain in detail. L2

2. Differentiate between Memory Mapped and I/O mapped I/O. L2

5.2 Interrupts
Objective Questions

1. An I/O device requests an interrupt by activating a bus-line called [ ]

a) Interrupt-routine
b) Interrupt-request
c) None of the above

2. The method of synchronizing the processor with the I/O device in which the [ ]
device sends a signal when it is ready is?
a) Exceptions b) Signal handling
c) Interrupts d) DMA

3. The interrupt-request line is a part of the ___________ [ ]

a) Data line b) Control line
c) Address line d) None of the mentioned

4. The signal sent to the device from the processor to the device after receiving [ ]
an interrupt is ___________
a) Interrupt-acknowledge b) Return signal
c) Service signal d) Permission signal

5. The time between the receiver of an interrupt and its service is ______ [ ]
a) Interrupt delay b) Interrupt latency
c) Cycle time d) Switching time

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6. An interrupt that can be temporarily ignored is ___________ [ ]

a) Vectored interrupt b) Non-maskable interrupt
c) Maskable interrupt d) High priority interrupt

An interrupt breaks the execution of instructions and diverts its execution to

7. [ ]
a) Interrupt service routine b) Counter word register
c) Execution unit d) control unit

Descriptive Questions

S.No. Name of the question BL

1. Explain the Interrupt hardware in detail. L2

2. Explain about the enabling and disabling interrupts. L2

5.3 Processor examples

Objective Questions

1. How many interrupt levels are supported in the MC68000? [ ]

a) 2 b) 3 c) 4 d) 7

2. ARM stands for _____________ [ ]

a) Advanced Rate Machines b) Advanced RISC Machines
c) Artificial Running Machines d) Aviary Running Machines

3. RISC stands for _________ [ ]

a) Restricted Instruction Sequencing Computer
b) Restricted Instruction Sequential Compiler
c) Reduced Instruction Set Computer
d) Reduced Induction Set Computer

4. The ARM core uses ________ architecture. [ ]

a) RISC b) CISC c) both d) none

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Descriptive Questions

S.No. Name of the question BL

1. Explain the ARM Interrupt Structure. L2

2. Explain the 68000 Interrupt structure L2

5.4 DMA

Objective Questions
1. The DMA transfers are performed by a control circuit called as __________ [ ]
a) Device interface b) DMA controller
c) Data controller d) Over looker

2. After the completion of the DMA transfer, the processor is notified by ____ [ ]
a) Acknowledge signal b) Interrupt signal
c) WMFC signal d) None of the mentioned

3. The DMA controller has _______ registers. [ ]

a) 4 b) 2 c) 3 d) 1

4. When the R/W bit of the status register of the DMA controller is set to 1. [ ]
a) Read operation is performed
b) Write operation is performed
c) Read & Write operation is performed
d) None of the mentioned

5. Can a single DMA controller perform operations on two different disks [ ]

simultaneously?
a) True b) False

6. The technique whereby the DMA controller steals the access cycles of the [ ]
processor to operate is called __________
a) Fast conning b) Memory Con
c) Cycle stealing d) Memory stealing

7. The technique where the controller is given complete access to main memory [ ]
is __________
a) Cycle stealing b) Memory stealing

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c) Memory Con d) Burst mode

8. To overcome the conflict over the possession of the BUS we use ______ [ ]
a) Optimizers b) BUS arbitrators
c) Multiple BUS structure d) None of the mentioned

Descriptive Questions

S.No. Name of the question BL

1. With a neat sketch explain the registers in DMA transfer. L2

2. Explain the Bus arbitration-centralized and distributed. L2

3. How to access Main memory by processor and DMA? Explain different modes. L3

5.5 Buses

Objective questions

1. The primary function of the BUS is __________ [ ]

a) To connect the various devices to the CPU
b) To provide a path for communication between the processor and other
devices
c) To facilitate data transfer between various devices
d) All of the mentioned

2. The classification of BUSes into synchronous and asynchronous is based on [ ]

__________
a) The devices connected to them b) The type of data transfer
c) The Timing of data transfers d) None of the mentioned

3. In synchronous BUS, the devices get the timing signals from __________ [ ]
a) Timing generator in the device b) A common clock line
c) Timing signals are not used at all d) None of the mentioned

4. The delays caused in the switching of the timing signals is due to [ ]

__________
a) Memory access time b) WMFC

c) Propagation delay d) Processor delay

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5. The transmission on the asynchronous BUS is also called _____ [ ]
a) Switch mode transmission b) Variable transfer
c) Bulk transfer d) Hand-Shake transmission

Descriptive Questions

S.No. Name of the question BL

1. What is BUS? Explain different types of BUS transfers. L2

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