UNIT-1

8086 Architecture and Programming

Features of 8- bit Processor(8085)

The salient features of 8085 μp are:

 It is a 8 bit microprocessor.
 It is manufactured with N-MOS technology.
 It has 16-bit address bus and hence can address up to 216 = 65536 bytes (64KB)
 memory locations through A0-A15.
 The first 8 lines of address bus and 8 lines of data bus are multiplexed AD0 –
AD7.
 Data bus is a group of 8 lines D0 – D7.
 It supports external interrupt request.
 A 16 bit program counter (PC)
 A 16 bit stack pointer (SP)
 •Six 8-bit general purpose register arranged in pairs: BC, DE, HL.
 It requires a signal 5V power supply and operates at 3.2 MHZ single phase
clock.
 It is enclosed with 40 pins DIP (Dual in line package).
8085 Pin Diagram

Figure: 8085 Pin Diagram

All signals can be classified into six groups:

1.Address Bus
2. Data Bus
3. Control & Status Signals
4. Power Supply & Frequency signals
5. Externally initiated signals
6. Serial I/O Ports
1) Address Bus (pin 12 to 28)
 16 signal lines are used as address bus.
 However these lines are split into two segments: A15 - A8 and AD7 - AD0
 A15 - A8 are unidirectional and are used to carry high-order address of 16-bit address.
 AD7 - AD0 are used for dual purpose.

2) Data Bus/ Multiplexed Address (pin 12 to 19)

 Signal lines AD7-AD0 are bidirectional and serve dual purpose.
 They are used as low-order address bus as well as data bus.
 The low order address bus can be separate from these signals by using a latch.
 3) Control & Status Signals
 To identify nature of operation
 Two Control Signals
1) RD’ (Read-pin 32)
 This is a read control signal (active low)
 This signal indicates that the selected I/O or Memory device is to be
read & data are available on data bus.
2) WR’ (Write-pin 31)
 This is a write control signal (active low)
 This signal indicates that the selected I/O or Memory device is to be write.
 Three
Status
Signals
1) S1
(pin
33)
2) S0 (pin 29)

 S1 and S0 status signals can identify various operations, but they are rarely
used in small systems.

S1 S0 Mode
0 0 HLT
0 1 WRITE
1 0 READ
1 1 OPCODE
FETCH

3) IO/M’ (pin 34)

 This is a status signal used to differentiate I/O and memory operation
  When it is high, it indicates an I/O operation
 When it is low, it indicates a memory operation
 This signal is combined with RD’ and WR’ to generate I/O & memory control
signals
 To indicate beginning of operation
o One Special Signal called ALE (Address Latch Enable-Pin 30)
o This is positive going pulse generated every time the 8085 begins an operation
(machine cycle)
o It indicates that the bits on AD7-AD0 are address bits
o This signal is used primarily to latch the low-address from multiplexed bus
& generate a separate set of address lines A7-A0.

4) Power Supply & Frequency Signal

 Vcc Pin no. 40, +5V Supply
 Vss Pin no.20, Ground Reference
 X1, X2 Pin no.1 & 2, Crystal Oscillator is connected at these two pins. The
frequency is internally divided by two; Therefore, to operate a system at
3MHz, the crystal should have a frequency of 6MHz.
 CLK (OUT) Clock output. Pin No.37: This signal can be used as the system clock
for other devices.

5) Externally Initiated Signals including Interrupts

 INTR (Input) Interrupt Request. It is used as general purpose interrupt
 INTA’ (Output) Interrupt Acknowledge. It is used to acknowledge an interrupt.
 RST7.5, RST6.5, RST5.5 (Input) Restart Interrupts.
o These are vector interrupts that transfer the program control to specific memory
locations.
o They have higher priorities than INTR interrupt.
o Among these 3 interrupts, the priority order is RST7.5, RST6.5, RST5.5
 TRAP (Input) This is a non maskable interrupt & has the highest priority.
 HOLD (Input) This signal indicates that a peripheral such as DMA
Controller is requesting the use of address & data buses
 HLDA (Output) Hold Acknowledge. This signal acknowledges the HOLD request
 READY (Input) This signal is used to delay the microprocessor read or write
cycles until as low- responding peripheral is ready to send or accept data. When
the signal goes low, the microprocessor waits for an integral no. of clock cycles
until it goes high.
 RESET IN’ (Input) When the signal on this pin goes low, the Program
Counter is set to zero, the buses are tri-stated & microprocessor is reset.
 RESET OUT (Output) This signal indicates that microprocessor is being
reset. The signal can be used to reset other devices.

6) Serial I/O Ports

 Two pins for serial transmission
1) SID (Serial Input Data-pin 5)
2) SOD (Serial Output Data-pin 4)
 In serial transmission, data bits are sent over a single line, one bit at a time.

Features of 8086
 It is a 16-bit Microprocessor (μp).It’s ALU, internal registers works with 16bit binary
word.
 8086 has a 20 bit address bus can access up to 220= 1 MB memory locations.
 8086 has a 16bit data bus. It can read or write data to a memory/port either 16bits or 8 bit
at a time.
 It can support up to 64K I/O ports.
 It provides 14, 16 -bit registers.
 Frequency range of 8086 is 6-10 MHz
 It has multiplexed address and data bus AD0- AD15 and A16 – A19.
 It requires single phase clock with 33% duty cycle to provide internal timing.
 It can prefetch upto 6 instruction bytes from memory and queues them in order to speed
up instruction execution.
 It requires +5V power supply.
 A 40 pin dual in line package.
 8086 is designed to operate in two modes, Minimum mode and Maximum mode.
o The minimum mode is selected by applying logic 1 to the MN / MX# input pin.
This is a single microprocessor configuration.
o The maximum mode is selected by applying logic 0 to the MN / MX# input pin.
This is a multi micro processors configuration.
Register Organization of 8086 General
purpose registers
The 8086 microprocessor has a total of fourteen registers that are accessible to the
programmer. It is divided into four groups. They are:
 Four General purpose registers
 Four Index/Pointer registers
 Four Segment registers
 Two Other registers
General purpose registers:

Accumulator register consists of two 8-bit registers AL and AH, which can be combined
together and used as a 16-bit register AX. AL in this case contains the low order byte of the
word, and AH contains the high-order byte. Accumulator can be used for I/O operations and
string manipulation.

Base register consists of two 8-bit registers BL and BH, which can be combined together
and used as a 16-bit register BX. BL in this case contains the low-order byte of the word, and BH
contains the high-order byte. BX register usually contains a data pointer used for based, based
indexed or register indirect addressing.

Count register consists of two 8-bit registers CL and CH, which can be combined together
and used as a 16-bit register CX. When combined, CL register contains the low order byte of
the word, and CH contains the high-order byte. Count register can be used in Loop,
shift/rotate instructions and as a counter in string manipulation

Data register consists of two 8-bit registers DL and DH, which can be combined together
and used as a 16-bit register DX. When combined, DL register contains the low order byte of the
word, and DH contains the high-order byte. Data register can be used as a port number in I/O
operations. In integer 32-bit multiply and divide instruction the DX register contains high-order
word of the initial or resulting number.

Index or Pointer Registers

These registers can also be called as Special Purpose registers.

Stack Pointer (SP) is a 16-bit register pointing to program stack, i.e. it is used to hold the
address of the top of stack. The stack is maintained as a LIFO with its bottom at the start of the
stack segment (specified by the SS segment register).Unlike the SP register, the BP can be used
to specify the offset of other program segments.

Base Pointer (BP) is a 16-bit register pointing to data in stack segment. It is usually used
by subroutines to locate variables that were passed on the stack by a calling program. BP register
is usually used for based, based indexed or register indirect addressing.

Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register
indirect addressing, as well as a source data address in string manipulation instructions. Used in
conjunction with the DS register to point to data locations in the data segment.

Destination Index (DI) is a 16-bit register. Used in conjunction with the ES register in
string operations. DI is used for indexed, based indexed and register indirect addressing, as well
as a destination data address in string manipulation instructions. In short, Destination Index and
SI Source Index registers are used to hold address.

Segment Registers
Most of the registers contain data/instruction offsets within 64 KB memory segment.
There are four different 64 KB segments for instructions, stack, data and extra data. To specify
where in 1 MB of processor memory these 4 segments are located the processor uses four
segment registers.

Code segment (CS) is a 16-bit register containing address of 64 KB segment with

processor instructions. The processor uses CS segment for all accesses to instructions referenced
by instruction pointer (IP) register. CS register cannot be changed directly. The CS register is
automatically updated during far jump, far call and far return instructions.

Stack segment (SS) is a 16-bit register containing address of 64KB segment with
program stack. By default, the processor assumes that all data referenced by the stack pointer
(SP) and base pointer (BP) registers is located in the stack segment. SS register can be changed
directly using POP instruction.

Data segment (DS) is a 16-bit register containing address of 64KB segment with program
data. By default, the processor assumes that all data referenced by general registers (AX, BX,
CX, DX) and index register (SI, DI) is located in the data segment. DS register can be changed
directly using POP and LDS instructions.

Extra segment (ES) used to hold the starting address of Extra segment. Extra segment is
provided for programs that need to access a second data segment. Segment registers cannot be
used in arithmetic operations.

Other registers of 8086

Instruction Pointer (IP) is a 16-bit register. This is a crucially important register which is used
to control which instruction the CPU executes. The IP, or program counter, is used to store the
memory location of the next instruction to be executed. The CPU checks the program counter to
ascertain which instruction to carry out next. It then updates the program counter to point to the
next instruction. Thus the program counter will always point to the next instruction to be
executed.

Flag Register contains a group of status bits called flags that indicate the status of the CPU or
the result of arithmetic operations. There are two types of flags:
1. The status flags which reflect the result of executing an instruction. The programmer cannot
set/reset these flags directly.
2. The control flags enable or disable certain CPU operations. The programmer can set/reset
these bits to control the CPU's operation.

Nine individual bits of the status register are used as control flags (3 of them) and status
flags (6 of them).The remaining 7 are not used.
A flag can only take on the values 0 and 1. We say a flag is set if it has the value
1. The status flags are used to record specific characteristics of arithmetic and of logical
instructions.

Control Flags: There are three control flags

1. The Direction Flag (D): Affects the direction of moving data blocks by such
instructions as MOVS, CMPS and SCAS. The flag values are 0 = up and 1 = down and
can be set/reset by the STD (set D) and CLD (clear D) instructions.

2. The Interrupt Flag (I): Dictates whether or not system interrupts can occur.
Interrupts are actions initiated by hardware block such as input devices that will interrupt
the normal execution of programs. The flag values are 0 = disable interrupts or 1 =
enable interrupts and can be manipulated by the CLI (clear I) and STI (set I)
instructions.

3. The Trap Flag (T): Determines whether or not the CPU is halted after the execution
of each instruction. When this flag is set (i.e. = 1), the programmer can single step
through his program to debug any errors. When this flag = 0 this feature is off. This
flag can be set by the INT 3 instruction.

Status Flags: There are six status flags

1. The Carry Flag (C): This flag is set when the result of an unsigned arithmetic operation is
too large to fit in the destination register. This happens when there is an end carry in an addition
operation or there an end borrows in a subtraction operation. A value of 1 = carry and 0 = no
carry.

2. The Overflow Flag (O): This flag is set when the result of a signed arithmetic operation is too
large to fit in the destination register (i.e. when an overflow occurs). Overflow can occur when

3. adding two numbers with the same sign (i.e. both positive or both negative). A value of 1
=
overflow and 0 = no overflow.

4. The Sign Flag (S): This flag is set when the result of an arithmetic or logic operation is
negative. This flag is a copy of the MSB of the result (i.e. the sign bit). A value of 1 means
negative and 0 = positive.
5. The Zero Flag (Z): This flag is set when the result of an arithmetic or logic operation is equal
to zero. A value of 1 means the result is zero and a value of 0 means the result is not zero.
6. The Auxiliary Carry Flag (A): This flag is set when an operation causes a carry from bit 3 to
bit 4 (or a borrow from bit 4 to bit 3) of an operand. A value of 1 = carry and 0 = no carry.

7. The Parity Flag (P): This flags reflects the number of 1s in the result of an operation. If the
number of 1s is even its value = 1 and if the number of 1s is odd then its value = 0.

Architecture of 8086 or Functional Block diagram of 8086

 8086 has two blocks Bus Interface Unit (BIU) and Execution Unit (EU).

 The BIU performs all bus operations such as instruction fetching, reading and writing
operands for memory and calculating the addresses of the memory operands. The
instruction bytes are transferred to the instruction queue.

 EU executes instructions from the instruction system byte queue.

 Both units operate asynchronously to give the 8086 an overlapping instruction fetch and
execution mechanism which is called as Pipelining. This results in efficient use of the
system bus and system performance.

 BIU contains Instruction queue, Segment registers, Instruction pointer, Address adder.
 EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag
register.
 Figure: 8086 Architecture
Explanation of Architecture of 8086

Bus Interface Unit:

 It provides a full 16 bit bidirectional data bus and 20 bit address bus.

 The bus interface unit is responsible for performing all external bus operations.

 Specifically it has the following functions:

 Instruction fetch Instruction queuing, Operand fetch and storage, Address relocation and Bus
control.
 The BIU uses a mechanism known as an instruction stream queue to implement pipeline
architecture.

 This queue permits prefetch of up to six bytes of instruction code. Whene ver the queue of
 the BIU is not full, it has room for at least two more bytes and at the same time the EU is not
requesting it to read or write operands from memory, the BIU is free to look ahead in the
program by prefetching the next sequential instruction.
 These prefetching instructions are held in its FIFO queue. With its 16 bit data bus, the BIU
fetches two instruction bytes in a single memory cycle.

 After a byte is loaded at the input end of the queue, it automatically shifts up through the
FIFO to the empty location nearest the output.

 The EU accesses the queue from the output end. It reads one instruction byte after the
other from the output of the queue. If the queue is full and the EU is not requesting access to
operand in memory.

 These intervals of no bus activity, which may occur between bus cycles are known as Idle
state.

 If the BIU is already in the process of fetching an instruction when the EU request it to read
or write operands from memory or I/O, the BIU first completes the instruction fetch bus cycle
before initiating the operand read / write cycle.

 The BIU also contains a dedicated adder which is used to generate the 20bit physical
address that is output on the address bus. This address is formed by adding an appended 16
bit segment address and a 16 bit offset address.

 For example: The physical address of the next instruction to be fetched is formed by
combining the current contents of the code segment CS register and the current contents of the
instruction pointer IP register.
 The BIU is also responsible for generating bus control signals such as those for memory read
or write and I/O read or write.

Execution Unit

 The Execution unit is responsible for decoding and executing all instructions.

 The EU extracts instructions from the top of the queue in the BIU, decodes them,
generates operands if necessary, passes them to the BIU and requests it to perform the read or
write bus cycles to memory or I/O and perform the operation specified by the instruction on
the operands.

 During the execution of the instruction, the EU tests the status and control flags and
updates them based on the results of executing the instruction.

 If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted
to top of the queue.
 When the EU executes a branch or jump instruction, it transfers control to a location
corresponding to another set of sequential instructions.
 Whenever this happens, the BIU automatically resets the queue and then begins to fetch
instructions from this new location to refill the queue.
General Bus Operation

 The 8086 has a combined address and data bus commonly referred as a time multiplexed
address and data bus.

 The main reason behind multiplexing address and data over the same pins is the
maximum utilization of processor pins and it facilitates the use of 40 pin standard DIP
package.

 The bus can be demultiplexed using a few latches and transceivers, when ever required.

 Basically, all the processor bus cycles consist of at least four clock cycles. These are
referred to as T1, T2, T3, and T4. The address is transmitted by the processor during T1. It is
present on the bus only for one cycle.

 The negative edge of this ALE pulse is used to separate the address and the data or status
information. In maximum mode, the status lines S0, S1 and S2 are used to indicate the type of
operation.
 Status bits S3 to S7 are multiplexed with higher order address bits and the BHE signal.
Address is valid during T1 while status bits S3 to S7 are valid during T2 through T4.

Maximum mode

 In the maximum mode, the 8086 is operated by strapping the MN/MX pin to ground.

 In this mode, the processor derives the status signal S2, S1, S0. Another chip called bus
controller derives the control signal using this status information.
  In the maximum mode, there may be more than one microprocessor in the system
configuration.

Minimum mode

 In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum

mode by strapping its MN/MX pin to logic 1.

 In this mode, all the control signals are given out by the microprocessor chip itself.

 There is a single microprocessor in the minimum mode system.

Pin Diagram of 8086 and Pin description of 8086

Figure shows the Pin diagram of 8086. The description follows it.

 The Microprocessor 8086 is a 16-bit CPU available in different clock rates and packaged
in a 40 pin CERDIP or plastic package.

 The 8086 operates in single processor or multiprocessor configuration to achieve high

performance. The pins serve a particular function in minimum mode (single processor
mode) and other function in maximum mode configuration (multiprocessor mode).

 The 8086 signals can be categorized in three groups.

o The first are the signal having common functions in minimum as well as
maximum mode.

o The second are the signals which have special functions for minimum mode

o The third are the signals having special functions for maximum mode.
 The following signal descriptions are common for both modes.

 AD15-AD0: These are the time multiplexed memory I/O address and data lines.

o Address remains on the lines during T1 state, while the data is available on the data
bus during T2, T3, Tw and T4. These lines are active high and float to a tristate
during interrupt acknowledge and local bus hold acknowledge cycles.

 A19/S6, A18/S5, A17/S4, and A16/S3: These are the time multiplexed address and
status lines.

o During T1 these are the most significant address lines for memory operations.

o During I/O operations, these lines are low.

o During memory or I/O operations, status information is available on those lines for
T2, T3, Tw and T4.

o The status of the interrupt enable flag bit is updated at the beginning of each clock
cycle.

o The S4 and S3 combine indicate which segment registers is presently being used for
memory accesses as in below fig

o These lines float to tri-state off during the local bus hold acknowledge. The status line
S6 is always low.

o The address bit is separated from the status bit using latches controlled by the
ALE signal.
 BHE/S7: The bus high enable is used to indicate the transfer of data over the higher order
(D15-D8) data bus as shown in table. It goes low for the data transfer over D15-D8 and is used
to derive chip selects of odd address memory bank or peripherals. BHE is low during
T1 for read, write and interrupt acknowledge cycles, whenever a byte is to be transferred
on higher byte of data bus. The status information is available during T2, T3 and T4. The
signal is active low and tristated during hold. It is low during T1 for the first pulse of the
interrupt acknowledge cycle.

 RD – Read: This signal on low indicates the peripheral that the processor is performing
memory or I/O read operation. RD is active low and shows the state for T2, T3, Tw of any
read cycle. The signal remains tristated during the hold acknowledge.

 READY: This is the acknowledgement from the slow device or memory that they have
completed the data transfer. The signal made available by the devices is synchronized by the
8284A clock generator to provide ready input to the 8086. the signal is active high.

 INTR-Interrupt Request: This is a triggered input. This is sampled during the last clock
cycles of each instruction to determine the availability of the request. If any interrupt
request is pending, the processor enters the interrupt acknowledge cycle. This can be
internally masked by resulting the interrupt enable flag. This signal is active high and
internally synchronized.

 TEST: This input is examined by a ‘WAIT’ instruction. If the TEST pin goes low,
execution will continue, else the processor remains in an idle state. The input is
synchronized internally during each clock cycle on leading edge of clock.
 CLK- Clock Input: The clock input provides the basic timing for processor operation and
bus control activity. It’s an asymmetric square wave with 33% duty cycle.

Figure shows the Pin functions of 8086.

The following pin functions are for the minimum mode operation of 8086.
 M/IO – Memory/IO: This is a status line logically equivalent to S2 in maximum mode.
When it is low, it indicates the CPU is having an I/O operation, and when it is high, it
indicates that the CPU is having a memory operation. This line becomes active high in the
previous T4 and remains active till final T4 of the current cycle. It is tristated during local
bus “hold acknowledge “.
 INTA – Interrupt Acknowledge: This signal is used as a read strobe for interrupt
acknowledge cycles. i.e. when it goes low, the processor has accepted the interrupt.

 ALE – Address Latch Enable: This output signal indicates the availability of the valid
address on the address/data lines, and is connected to latch enable input of latches. This
signal is active high and is never tristated.

 DT/R – Data Transmit/Receive: This output is used to decide the direction of data flow
through the transceivers (bidirectional buffers). When the processor sends out data, this
signal is high and when the processor is receiving data, this signal is low.

 DEN – Data Enable: This signal indicates the availability of valid data over the address/data
lines. It is used to enable the transceivers (bidirectional buffers) to separate the data from the
multiplexed address/data signal. It is active from the middle of T2 until the middle of T4. This
is tristated during ‘hold acknowledge’ cycle.

 HOLD, HLDA- Acknowledge: When the HOLD line goes high; it indicates to the
processor that another master is requesting the bus access. The processor, after receiving the
HOLD request, issues the hold acknowledge signal on HLDA pin, in the middle of the next
clock cycle after completing the current bus cycle.

 At the same time, the processor floats the local bus and control lines. When the processor
detects the HOLD line low, it lowers the HLDA signal. HOLD is an asynchronous input, and
is should be externally synchronized. If the DMA request is made while the CPU is
performing a memory or I/O cycle, it will release the local bus during T4 provided :

1. The request occurs on or before T2 state of the current cycle.

2. The current cycle is not operating over the lower byte of a word.

3. The current cycle is not the first acknowledge of an interrupt acknowledge sequence.
4. A Lock instruction is not being executed.

The following pin functions are applicable for maximum mode operation of 8086.

 S2, S1, and S0 – Status Lines: These are the status lines which reflect the type of
operation, being carried out by the processor. These become activity during T4 of the
previous cycle and active during T1 and T2 of the current bus cycles.

 LOCK: This output pin indicates that other system bus master will be prevented from
gaining the system bus, while the LOCK signal is low. The LOCK signal is activated by the
‘LOCK’ prefix instruction and remains active until the completion of the next instruction.
When the CPU is executing a critical instruction which requires the system bus, the LOCK
prefix instruction ensures that other processors connected in the system will not gain the
control of the bus.
 The 8086, while executing the prefixed instruction, asserts the bus lock signal output,
which may be connected to an external bus controller. By prefetching the instruction, there is a
considerable speeding up in instruction execution in 8086. This is known as instruction
pipelining.

 At the starting the CS: IP is loaded with the required address from which the execution is
to be started. Initially, the queue will be empty and the microprocessor starts a fetch
operation to bring one byte (the first byte) of instruction code, if the CS: IP address is odd
or two bytes at a time, if the CS: IP address is even.

 The first byte is a complete opcode in case of some instruction (one byte opcode instruction)
and is a part of opcode, in case of some instructions (two byte opcode instructions), the
remaining part of code lie in second byte.

 The second byte is then decoded in continuation with the first byte to decide the instruction
length and the number of subsequent bytes to be treated as instruction data. The queue is
updated after every byte is read from the queue but the fetch cycle is initiated by BIU
only if at least two bytes of the queue are empty and the EU may be concurrently
executing the fetched instructions.

 The next byte after the instruction is completed is again the first opcode byte of the next
instruction. A similar procedure is repeated till the complete execution of the program. The
fetch operation of the next instruction is overlapped with the execution of the current
instruction. As in the architecture, there are two separate units, namely Execution unit and
Bus interface unit.

 While the execution unit is busy in executing an instruction, after it is completely decoded,
the bus interface unit may be fetching the bytes of the next instruction from memory,
depending upon the queue status.

 RQ/GT0, RQ/GT1 – Request/Grant: These pins are used by the other local bus master
in maximum mode, to force the processor to release the local bus at the end of the
processor current bus cycle.
  Each of the pin is bidirectional with RQ/GT0 having higher priority than RQ/GT1.
RQ/GT pins have internal pull-up resistors and may be left unconnected. Request/Grant
sequence is as follows:

1. A pulse of one clock wide from another bus master requests the bus access to
8086.

2. During T4(current) or T1(next) clock cycle, a pulse one clock wide from 8086 to
the requesting master, indicates that the 8086 has allowed the local bus to float
and that it will enter the ‘hold acknowledge’ state at next cycle. The CPU bus
interface unit is likely to be disconnected from the local bus of the system.
3. A one clock wide pulse from another master indicates to the 8086 that the hold
request is about to end and the 8086 may regain control of the local bus at the
next clock cycle. Thus each master to master exchange of the local bus is a
sequence of 3 pulses. There must be at least one dead clock cycle after each bus
Exchange. The request and grant pulses are active low. For the bus request those
are received while 8086 is performing memory or I/O cycle, the granting of the
bus is governed by the rules as in case of HOLD and HLDA in minimum mode.

Minimum Mode 8086 System

 In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum

mode by strapping its MN/MX pin to logic 1.

 In this mode, all the control signals are given out by the microprocessor chip itself. There
is a single microprocessor in the minimum mode system.

 The remaining components in the system are latches, transceivers, clock generator,
memory and I/O devices. Some type of chip selection logic may be required for selecting
memory or I/O devices, depending upon the address map of the system.
 Latches are generally buffered output D-type flip-flops like 74LS373 or 8282. They are
used for separating the valid address from the multiplexed address/data signals and are
controlled by the ALE signal generated by 8086.
  Transceivers are the bidirectional buffers and sometimes they are called as data
amplifiers. They are required to separate the valid data from the time multiplexed
address/data signals.

 They are controlled by two signals namely, DEN and DT/R.

 The DEN signal indicates the direction of data, i.e. from or to the processor. The system
contains memory for the monitor and users program storage.

 Usually, EPROM is used for monitor storage, while RAM for users program storage. A
system may contain I/O devices.

Write Cycle Timing Diagram for Minimum Mode

 The working of the minimum mode configuration system can be better described in terms
of the timing diagrams rather than qualitatively describing the operations.

 The opcode fetch and read cycles are similar. Hence the timing diagram can be
categorized in two parts, the first is the timing diagram for read cycle and the second is
the timing diagram for write cycle.

 The read cycle begins in T1 with the assertion of address latch enable (ALE) signal and also
M / IO signal. During the negative going edge of this signal, the valid address is latched
on the local bus.
 The BHE and A0 signals address low, high or both bytes. From T1 to T4 , the M/IO
signal indicates a memory or I/O operation.
 At T2, the address is removed from the local bus and is sent to the output. The bus is then tri-
stated. The read (RD) control signal is also activated in T2.

 The read (RD) signal causes the address device to enable its data bus drivers. After RD goes
low, the valid data is available on the data bus.
 The addressed device will drive the READY line high. When the processor returns the read
signal to high level, the addressed device will again tristate its bus drivers.

 A write cycle also begins with the assertion of ALE and the emission of the address. The
M/IO signal is again asserted to indicate a memory or I/O operation. In T2, after sending the
address in T1, the processor sends the data to be written to the addressed location.

 The data remains on the bus until middle of T4 state. The WR becomes active at the
beginning of T2 (unlike RD is somewhat delayed in T2 to provide time for floating).

 The BHE and A0 signals are used to select the proper byte or bytes of memory or I/O
word to be read or write.

 The M/IO, RD and WR signals indicate the type of data transfer as specified in table
below.

Bus Request and Bus Grant Timings in Minimum Mode System of 8086

 Hold Response sequence: The HOLD pin is checked at leading edge of each clock pulse.
If it is received active by the processor before T4 of the previous cycle or during T1 state
of the current cycle, the CPU activates HLDA in the next clock cycle and for succeeding
bus cycles, the bus will be given to another requesting master.

 The control of the bus is not regained by the processor until the requesting master does
not drop the HOLD pin low. When the request is dropped by the requesting master, the
HLDA is dropped by the processor at the trailing edge of the next clock.

Maximum Mode 8086 System

 In the maximum mode, the 8086 is operated by strapping the MN/MX pin to ground.

 In this mode, the processor derives the status signal S2, S1, S0. Another chip called bus
controller derives the control signal using this status information.

 In the maximum mode, there may be more than one microprocessor in the system
 configuration.

 The components in the system are same as in the minimum mode system.

 The basic function of the bus controller chip IC8288 is to derive control signals like RD
and WR (for memory and I/O devices), DEN, DT/R, ALE etc. using the information by
the processor on the status lines.
 The bus controller chip has input lines S2, S1, S0 and CLK. These inputs to 8288 are
driven by CPU.

 It derives the outputs ALE, DEN, DT/R, MRDC, MWTC, AMWC, IORC, IOWC and
AIOWC. The AEN, IOB and CEN pins are especially useful for multiprocessor systems.

 AEN and IOB are generally grounded. CEN pin is usually tied to +5V. The significance of
the MCE/PDEN output depends upon the status of the IOB pin.
 If IOB is grounded, it acts as master cascade enable to control cascade 8259A, else it acts as
peripheral data enable used in the multiple bus configurations.

 INTA pin used to issue two interrupt acknowledge pulses to the interrupt controller or to an
interrupting device.

 IORC, IOWC are I/O read command and I/O write command signals respectively.

 These signals enable an IO interface to read or write the data from or to the address port.

 The MRDC, MWTC are memory read command and memory write command signals
 respectively and may be used as memory read or write signals.
 All these command signals instructs the memory to accept or send data from or to the
bus.

 For both of these write command signals, the advanced signals namely AIOWC and
AMWTC are available.

 Here the only difference between in timing diagram between minimum mode and
maximum mode is the status signals used and the available control and advanced
command signals.

 R0, S1, S2 are set at the beginning of bus cycle.8288 bus controller will output a pulse as
on the ALE and apply a required signal to its DT / R pin during T1.

 In T2, 8288 will set DEN=1 thus enabling transceivers, and for an input it will activate
MRDC or IORC. These signals are activated until T4. For an output, the AMWC or
AIOWC is activated from T2 to T4 and MWTC or IOWC is activated from T3 to T4.

 The status bit S0 to S2 remains active until T3 and become passive during T3 and T4.

 If reader input is not activated before T3, wait state will be inserted between T3 and T4.

Memory Read Timing Diagram in Maximum Mode of 8086

Memory Write Timing in Maximum mode of 8086

RQ/GT Timings in Maximum Mode

 The request/grant response sequence contains a series of three pulses. The request/grant
pins are checked at each rising pulse of clock input.

 When a request is detected and if the condition for HOLD request is satisfied, the
processor issues a grant pulse over the RQ/GT pin immediately during T4 (current) or T1
(next) state.
 When the requesting master receives this pulse, it accepts the control of the bus, it sends a
release pulse to the processor using RQ/GT pin.
Minimum Mode Interface

 When the Minimum mode operation is selected, the 8086 provides all control
signals needed to implement the memory and I/O interface.

 The minimum mode signal can be divided into the following basic groups :

1. Address/data bus

2. Status

3. Control

4. Interrupt and

5. DMA.

Each and every group is explained clearly.

Address/Data Bus:

 These lines serve two functions. As an address bus is 20 bits long and consists of
signal lines A0 through A19. A19 represents the MSB and A0 LSB. A 20bit address
gives the 8086 a 1Mbyte memory address space. More over it has an independent
I/O address space which is 64K bytes in length.

 The 16 data bus lines D0 through D15 are actually multiplexed with address lines
A0 through A15 respectively. By multiplexed we mean that the bus work as an
address bus during first machine cycle and as a data bus during next machine cycles.

 D15 is the MSB and D0 LSB. When acting as a data bus, they carry read/write data
for memory, input/output data for I/O devices, and interrupt type codes from an
interrupt controller.

Status signal:
 The four most significant address lines A19 through A16 are also multiplexed but in
this case with status signals S6 through S3.

 These status bits are output on the bus at the same time that data are transferred over
the other bus lines.
  Bit S4 and S3 together from a 2 bit binary code that identifies which of the 8086
internal segment registers is used to generate the physical address that was output on
the address bus during the current bus cycle. Code S4S3 = 00 identifies a register
known as extra segment register as the source of the segment address.

 Status line S5 reflects the status of another internal characteristic of the 8086. It is
the logic level of the internal enable flag. The last status bit S6 is always at the logic 0
level.

Control Signals:

 The control signals are provided to support the 8086 memory I/O interfaces. They
control functions such as when the bus is to carry a valid address in which direction data
are to be transferred over the bus, when valid write data are on the bus and when to put
read data on the system bus.

 ALE is a pulse to logic 1 that signals external circuitry when a valid address word is on
the bus. This address must be latched in external circuitry on the 1-to-0 edge of the pulse
at ALE.

 Another control signal that is produced during the bus cycle is BHE bank high enable.
Logic 0 on this used as a memory enable signal for the most significant byte half of the
data bus D8 through D1. These lines also serve a second function, which is as the S7
status line.
 Using the M/IO and DT/R lines, the 8086 signals which type of bus cycle is in progress
and in which direction data are to be transferred over the bus. The logic level of M/IO
 tells external circuitry whether a memory or I/O transfer is taking place over the bus.
Logic 1 at this output signals a memory operation and logic 0 an I/O operation.

 The direction of data transfer over the bus is signaled by the logic level output at DT/R.
When this line is logic 1 during the data transfer part of a bus cycle, the bus is in the
transmit mode. Therefore, data are either written into memory or output to an I/O device.
On the other hand, logic 0 at DT/R signals that the bus is in the receive mode. This
corresponds to reading data from memory or input of data from an input port.
 The signals read RD and write WR indicates that a read bus cycle or a write bus cycle is
in progress. The 8086 switches WR to logic 0 to signal external device that valid write or
output data are on the bus.

 On the other hand, RD indicates that the 8086 is performing a read of data of the bus.
During read operations, one other control signal is also supplied. This is DEN (data
enable) and it signals external devices when they should put data on the bus. There is one
other control signal that is involved with the memory and I/O interface. This is the
READY signal.

 READY signal is used to insert wait states into the bus cycle such that it is extended by a
number of clock periods. This signal is provided by an external clock generator device
and can be supplied by the memory or I/O sub-system to signal the 8086 when they are
ready to permit the data transfer to be completed.

Interrupt signals:

 The key interrupt interface signals are interrupt request (INTR) and interrupt
acknowledge (INTA).

 INTR is an input to the 8086 that can be used by an external device to signal that it
need to be serviced.

 Logic 1 at INTR represents an active interrupt request. When an interrupt request

has been recognized by the 8086, it indicates this fact to external circuit with pulse to
logic 0 at the INTA output.
 The TEST input is also related to the external interrupt interface. Execution of a
WAIT instruction causes the 8086 to check the logic level at the TEST input.

 If the logic 1 is found, the MPU suspend operation and goes into the idle state. The
8086 no longer executes instructions; instead it repeatedly checks the logic level of
the TEST input waiting for its transition back to logic 0.

 As TEST switches to 0, execution resume with the next instruction in the program.
This feature can be used to synchronize the operation of the 8086 to an event in
external hardware.
 There are two more inputs in the interrupt interface: the nonmaskable interrupt NMI
and the reset interrupt RESET.

 On the 0-to-1 transition of NMI control is passed to a nonmaskable interrupt

service routine. The RESET input is used to provide a hardware reset for the 8086.
Switching RESET to logic 0 initializes the internal register of the 8086 and initiates a
reset service routine.
DMA Interface signals:

 The direct memory access DMA interface of the 8086 minimum mode consist of the HOLD
and HLDA signals.

 When an external device wants to take control of the system bus, it signals to the 8086 by
switching HOLD to the logic 1 level. At the completion of the current bus cycle, the 8086 enters
the hold state. In the hold state, signal lines AD0 through AD15, A16/S3 through A19/S6, BHE,
M/IO, DT/R, RD, WR, DEN and INTR are all in the high Z state.

 The 8086 signals external device that it is in this state by switching its HLDA output to logic 1
level.

Maximum Mode Interface

 When the 8086 is set for the maximum-mode configuration, it provides signals for implementing a
multiprocessor / coprocessor system environment.
 By multiprocessor environment we mean that one microprocessor exists in the system and that
each processor is executing its own program.

 Usually in this type of system environment, there are some system resources that are common
to all processors. They are called as global resources. There are also other resources that are
assigned to specific processors. These are known as local or private resources.
 Coprocessor also means that there is a second processor in the system. In these two
processors does not access the bus at the same time. One passes the control of the system bus to
the other and then may suspend its operation.

 In the maximum-mode 8086 system, facilities are provided for implementing allocation of global
resources and passing bus control to other microprocessor or coprocessor.

8288 Bus Controller – Bus Command and Control Signals:

 8086 does not directly provide all the signals that are required to control the memory, I/O and interrupt
interfaces.
 Specially the WR, M/IO, DT/R, DEN, ALE and INTA, signals are no longer produced by the 8086.
Instead it outputs three status signals S0, S1, S2 prior to the initiation of each bus cycle. This 3- bit
bus status code identifies which type of bus cycle is to follow.

 S2S1S0 are input to the external bus controller device, the bus controller generates the appropriately
timed command and control signals.

 The 8288 produces one or two of these eight command signals for each bus cycles. For instance, when
the 8086 outputs the code S2S1S0 equals 001; it indicates that an I/O read cycle is to be performed.

 In the code 111 is output by the 8086, it is signaling that no bus activity is to take place.
 The control outputs produced by the 8288 are DEN, DT/R and ALE. These 3 signals
provide the same functions as those described for the minimum system mode.

 This set of bus commands and control signals is compatible with the Multibus and
industry standard for interfacing microprocessor systems.

 The output of 8289 are bus arbitration signals:

Bus busy (BUSY), common bus request (CBRQ), bus priority out (BPRO), bus priority in (BPRN),
bus request (BREQ) and bus clock (BCLK).

 They correspond to the bus exchange signals of the Multibus and are used to lock other
processor off the system bus during the execution of an instruction by the 8086.
 In this way the processor can be assured of uninterrupted access to common system resources
such as global memory.

 Queue Status Signals: Two new signals that are produced by the 8086 in the maximum- mode
system are queue status outputs QS0 and QS1. Together they form a 2-bit queue status code,
QS1QS0.

 Following table shows the four different queue status.

 Local Bus Control Signal – Request / Grant Signals: In a maximum mode

configuration, the minimum mode HOLD, HLDA interface is also changed

QS1 QS0 Queue Status

 0 (Low) 0 Queue Empty. The queue has been reinitiated as a
result of the execution of a transfer instruction.
0 1 First Byte. The byte taken from the queue was the
first byte of the instruction.
1 0 Queue Empty. The queue has been reinitiated as a
result of the execution of a transfer instruction.
1 1 (High) Subsequent Byte. The byte taken from the queue
was the subsequent byte of the instruction.

 . These two are replaced by request/grant lines RQ/ GT0 and RQ/ GT1, respectively. They
provide a prioritized bus access mechanism for accessing the local bus.

Interrupts

Definition: The meaning of ‘interrupts’ is to break the sequence of operation. While the CPU is executing
a program, on ‘interrupt’ breaks the normal sequence of execution of instructions, diverts its execution
to some other program called Interrupt Service Routine (ISR).After executing ISR , the control is
transferred back again to the main program. Interrupt processing is an alternative to polling.
Need for Interrupt: Interrupts are particularly useful when interfacing I/O devices that provide or
require data at relatively low data transfer rate.

Types of Interrupts: There are two types of Interrupts in 8086. They are: (i)
Hardware Interrupts and

(ii)Software Interrupts

(i) Hardware Interrupts (External Interrupts). The Intel microprocessors support hardware
interrupts through:

 Two pins that allow interrupt requests, INTR and NMI

 One pin that acknowledges, INTA, the interrupt requested on
INTR. INTR and NMI

 INTR is a maskable hardware interrupt. The interrupt can be enabled/disabled using STI/CLI
instructions or using more complicated method of updating the FLAGS register with the help of
the POPF instruction.

 When an interrupt occurs, the processor stores FLAGS register into stack, disables further
interrupts, fetches from the bus one byte representing interrupt type, and jumps to interrupt
processing routine address of which is stored in location 4 * <interrupt type>. Interrupt processing
routine should return with the IRET instruction.

 NMI is a non-maskable interrupt. Interrupt is processed in the same way as the INTR
interrupt. Interrupt type of the NMI is 2, i.e. the address of the NMI processing routine is stored in
location 0008h. This interrupt has higher priority than the maskable interrupt.

 – Ex: NMI, INTR.

(ii) Software Interrupts (Internal Interrupts and Instructions) .Software interrupts can be caused by:

 INT instruction - breakpoint interrupt. This is a type 3 interrupt.

 INT <interrupt number> instruction - any one interrupt from available 256 interrupts.

 INTO instruction - interrupt on overflow

  Single-step interrupt - generated if the TF flag is set. This is a type 1 interrupt. When the CPU
processes this interrupt it clears TF flag before calling the interrupt processing routine.

 Processor exceptions: Divide Error (Type 0), Unused Opcode (type 6) and Escape opcode (type 7).

 Software interrupt processing is the same as for the hardware interrupts.

 - Ex: INT n (Software Instructions)

 Control is provided through:

o IF and TF flag bits

IRET and IRETD

o
Performance of Software Interrupts

1. It decrements SP by 2 and pushes the flag register on the stack.

2. Disables INTR by clearing the IF.
3. It resets the TF in the flag Register.
4. It decrements SP by 2 and pushes CS on the stack.
5. It decrements SP by 2 and pushes IP on the stack.
6. Fetch the ISR address from the interrupt vector table.

Interrupt Vector Table

Functions associated with INT00 to INT04 INT 00 (divide error)

 INT00 is invoked by the microprocessor whenever there is an attempt to divide a number by

zero.

 ISR is responsible for displaying the message “Divide Error” on the screen
 INT 01

 For single stepping the trap flag must be 1

 After execution of each instruction, 8086 automatically jumps to 00004H to fetch 4 bytes for
CS: IP of the ISR.
 The job of ISR is to dump the registers on to the screen
INT 02 (Non maskable Interrupt)

 When ever NMI pin of the 8086 is activated by a high signal (5v), the CPU Jumps to
physical memory location 00008 to fetch CS:IP of the ISR associated with NMI.
INT 03 (break point)

 A break point is used to examine the CPU and memory after the execution of a group of
Instructions.
 It is one byte instruction whereas other instructions of the form “INT nn” are 2 byte
instructions.
INT 04 (Signed number overflow)

 There is an instruction associated with this INT 0 (interrupt on overflow).

 If INT 0 is placed after a signed number arithmetic as IMUL or ADD the CPU will
activate INT 04 if 0F = 1.
 In case where 0F = 0, the INT 0 is not executed but is bypassed and acts as a NOP.

Performance of Hardware Interrupts

 NMI : Non maskable interrupts - TYPE 2 Interrupt

 INTR : Interrupt request - Between 20H and FFH

Interrupt Priority Structure

Intel 8087
Intel 8087 is known to be a specially designed coprocessor used for performing mathematical
calculations of data that contains integer and floating-point values. It is sometimes also called Math
Processor or Numeric Data Processor (NDP).
The use of a coprocessor along with the microprocessor facilitates the speeding up of calculations
thereby saving the overall time the CPU takes to perform the operation.
A coprocessor works parallelly with the microprocessor. The 80*87 series of coprocessors developed by Intel
is used for the 80*86 family of microprocessors i.e., 16-bit processors. To work with Intel 8086/8088
microprocessor, Intel developed 8087 coprocessor that operates in maximum mode while 80287 coprocessor
is designed for 80286 processor.
As the coprocessor works in conjunction with the microprocessor, therefore, the calculations part can be
managed by the coprocessor and this permits the CPU to use the resources to perform various other activities.
The coprocessor consists of 60 new instructions and the mnemonics of the coprocessor is differentiated from
the standard 8086 instructions in a way that these instructions contain ‘F’ in the beginning.

For example, The 8086 instruction ADD is represented as FADD in 8087.

Some other names given to this processor are Numeric Processor Extension, Floating Point Unit, Numeric
Data Processor, etc.

Architecture of Coprocessor 8087

We have mentioned at the beginning itself that the instructions of the microprocessor and coprocessor are
executed individually at the same time. The normal instruction sets are executed by the microprocessor and
the coprocessor instructions are executed by the coprocessor.

The figure below represents the internal architecture of Intel 8087:

Here the two major units consisting of the architecture are:

 Control Unit
 Numeric Execution Unit (NEU)

The various units that constitute the control unit are data buffer, shared operand queue, control, and status
word register, addressing and bus tracking unit, and exception pointer. While the Numeric Execution Unit
includes register stack, microcode control unit, programmable shifter, arithmetic module, temporary registers,
shared operand queue, exponent module.
The control unit of the coprocessor controls the instruction execution for which NEU is responsible. Basically,
the control unit of the NEU gets the numeric instructions from the control unit of the coprocessor. The 8087
has a total of eight registers of 80 bits each and these are used in the LIFO stack. The operands over which the
coprocessor instructions will take place to reside within the register stack.
The current top of the stack is pointed by the 3-bit stack pointer which holds the binary values
from 000 to 111 so as to show the eight registers of the stack. It operates in a circular stack manner in LIFO
mode. However, when reset action takes place then the pointer is initialized with 000 of the binary value.
The three classifications of numeric data over which the coprocessor operates are binary integers, packed
decimal numbers, and real numbers. The binary integers can be of three types namely word integer (16-bit),
short integer (32-bit), and long integer (64-bit). BCD format of 80 bit represents the packed decimal numbers
whereas real numbers are of three types namely short real (32-bit), long real (64-bit), temporary real (80-bit).

In order to transfer the numeric data within the coprocessor either a 64-bit mantissa bus or 16-bit exponent bus
is used.

The math processor has a 16-bit control word and a 16-bit status word. The control word is to be written into
the control register and this takes place in a way that the processor first writes the control word in the memory
location and then the coprocessor reads the control word from the memory location and store it into the
control register.
In a similar way, the status word is read in a way that the coprocessor sends the data within the status register
to a memory location, and further the processor reads that status register from that particular memory location.
This means the microprocessor and coprocessor communicate with each other through the main memory.

The figure below represents the format of the control word:

 IM/IE: Invalid Operation

 DM/DE: Denormalized Operand
 ZM/ZE: Zero Divide
 OM/OE: Overflow
 UM/UE: Underflow
 PM/PE: Precision
 Blank: Reserved
 IEM: Interrupt Enable Mask
 PC: Precision Control
 RC: Rounding Control
 IC: Infinity Control
Here we have shown the format of the status word:

 IR: Interrupt Request

 C0, C1, C2, C3: Condition Code
 ST: Stack Top Pointer
 B: Busy
How Coprocessor 8087 works with 8086?

We have mentioned at the beginning itself that there is a separate set of instructions of the 8087 coprocessor.
When the microprocessor works in conjunction with the coprocessor then at the time of writing the program
the instructions of both microprocessor and 8087 are included in it. In the assembly language program, the
instructions that have F, in the beginning, represent the coprocessor instructions, and those without a prefix ‘F’
shows the microprocessor instructions.

First, the microprocessor fetches the instructions from the memory location and load sequentially them in the
queue, simultaneously, 8087 also reads and stores the instructions in an internal queue. This means every
single instruction is read by both processor and coprocessor but at the time of execution both microprocessor
and coprocessor perform the execution of their respective instructions.

This means that instruction is read and decoded and after decoding if the microprocessor checks that there is
coprocessor instruction then that instruction is treated as NOP i.e., No-operation. Likewise, if the coprocessor
comes across any microprocessor instruction then it will be handled as no-operation

ADDRESSING MODES:
The way of specifying data to be operated by an instruction is known as
addressing modes. This specifies that the given data is an immediate data or an
address. It also specifies whether the given operand is register or register pair.

1. Immediate addressing mode:

The addressing mode in which the data operand is a part of the instruction itself is
known as immediate addressing mode.

Example: MOV AX, 0005H

In the above example, 0005H is the immediate data. The immediate data may be 8-bit or 16-bit in
size.

2. Register mode:
In this type of addressing mode both the operands are registers.

Or
It means that the register is the source of an operand for an instruction.

Example:
 MOV CX, AX ; copies the contents of the 16-bit AX register into
the 16-bit CX register
 ADD BX, AX

3. Displacement or direct mode:

In this type of addressing mode the effective address is directly given in the instruction
as displacement.

Example:
 MOV AX, [DISP]
 MOV AX, [0500]

4. Register indirect addressing mode:

This addressing mode allows data to be addressed at any memory location through an
offset address held in any of the following registers: BP, BX, DI & SI.
Example
 MOV AX, [BX] ; Suppose the register BX contains 4895H, then the contents
4895H are moved to AX
 ADD CX, [BX]
 ADD AL, [BX]

5. Based addressing mode:

In this addressing mode, the offset address of the operand is given by the sum of
contents of the BX/BP registers and 8-bit/16-bit displacement.

Example:

 MOV DX,[BX+04]
 ADD CL, [BX+08]

6. Indexed addressing mode:

In this addressing mode, the operands offset address is found by adding the contents of
SI (Index register) or DI (displacement) register and 8-bit/16- bit displacements.

Example:
 MOV BX, [SI+16]
 ADD AL, [DI+16]

7. Based-index addressing mode:

In this addressing mode, the offset address of the operand is computed by summing the
base register (BX or BP) to the contents of an Index register (SI or DI).Offset= [BX or BP]+
[SI or DI]

BX is used as a base register for data segment, and BP is used as a base register for
stack segment.

Example:
ADD AX, [BX+SI]

MOV CX,[BX+SI]

MOV AX,[AX+DI]

Based indexed with displacement mode:

In this type of addressing mode the effective address is the sum of index register,
base register and displacement.

Offset= [BX+BP] + [SI or DI] +8-bit or 16-bit displacement.

Example:
MOV AX, [BX+SI+05] an example of 8-bit displacement.

MOV AX, [BX+SI+1235H] an example of 16-bit displacement.

MOV AL, [SI+BP+2000]

 INSTRUNCTION SET:
The 8086 instructions are categorized into the following main types
 Data transfer instructions
 Arithmetic instructions
 Program control transfer instructions
 Machine control instructions
 Shift/rotate instructions
 Flag manipulation instructions
 String instructions

1. DATA COPY /TRANSFER INSTRUCTIONS:

 These type of instructions are used to transfer data from source operand to destination
operand. All the store, load, move, exchange input and output instructions belong to this
category.
MOV instruction

 It is a general purpose instruction to transfer byte or word from register to register, memory
to register, register to memory or with immediate addressing
 MOV destination, source
 Here the source and destination needs to be of the same size that is both 8-bit and both
16-bit.
 MOV instruction does not affect any flags.
MOV BX, 00F2H ; load the immediate number 00F2H in BX
Register
MOV CL, [2000H] ; Copy the 8 bit content of the memory
Location, at a displacement of 2000H from
data segment base to the CL register

MOV [589H], BX ; Copy the 16 bit content of BX register on

to the memory location, which at a
displacement of 589H from the data
segment base.

MOV DS, CX ;
Move the content of CX to DS

PUSH instruction:

 The PUSH instruction decrements the stack pointer by two and copies the word from
source to the location where stack pointer now points. Here the source must of word
size data. Source can be a general purpose register, segment register or a memory
location.
  The PUSH instruction first pushes the most significant byte to sp-1, then the least
significant to the sp-2.

 Push instruction does not affect any flags.

 Example:-
 PUSH CX ; Decrements SP by 2, copy content of CX to the stack (figure shows
execution of this instruction)
 PUSH DS ; Decrement SP by 2 and copy DS to stack

POP instruction:

 The POP instruction copies a word from the stack location pointed by the stack pointer to
the destination. The destination can be a General purpose register, a segment register or a
memory location. Here after the content is copied the stack pointer is automatically
incremented by two.

 The execution pattern is similar to that of the PUSH instruction.

 Example:
 POP CX; Copy a word from the top of the stack to CX and increment SP by 2.

IN & OUT instructions

The IN instruction will copy data from a port to the accumulator. If 8 bit is read the data will
go to AL and if 16 bit then to AX. Similarly OUT instruction is used to
copy data from accumulator to an output port.
Both IN and OUT instructions can be done using direct and indirect addressing modes.

 Example:
 IN AL, 0F8H ; Copy a byte from the port 0F8H to AL

 MOV DX, 30F8H ; Copy port address in DX

 IN AL, DX ; Move 8 bit data from 30F8H port

 IN AX, DX ; Move 16 bit data from 30F8H port

 OUT 047H, AL ; Copy contents of AL to 8 bit port

047H
 MOV DX, 330F8H ; Copy port address in DX

 OUT DX, AL ; Move 8 bit data to the 30F8H port

 OUT DX, AX ; Move 16 bit data to the 30F8H port

XCHG instruction
 The XCHG instruction exchanges contents of the destination and source. Here destination
and source can be register and register or register and memory location, but XCHG cannot
interchange the value of 2 memory locations.
 XCHG Destination, Source

 Example:

 XCHG BX, CX ; exchange word in CX with the word in BX

; exchange byte in CL with the byte in AL
; Here physical address, which is DS
+SUM+ [BX]. The content at physical
address and the content of AX are
interchanged
2. Arithmetic and Logical instructions:
All the instructions performing arithmetic, logical, increment, decrement, compare
and ASCII instructions belong to this category.

ADD instruction:
 Add instruction is used to add the current contents of destination with that of source and
store the result in destination. Here we can use register and/or memory locations.
 AF, CF, OF, PF, SF, and ZF flags are affected.

ADD Destination, Source
 Example:
o ADD AL, 0FH ; Add the immediate content, 0FH to the content of AL
and store the result in AL
o ADD AX, BX ; AX <= AX+BX
o ADD AX,0100H – IMMEDIATE
o ADD AX,BX – REGISTER
o ADD AX,[SI] – REGISTER INDIRECT OR INDEXED
o ADD AX, [5000H] – DIRECT
o ADD [5000H], 0100H – IMMEDIATE
o ADD 0100H – DESTINATION AX (IMPLICT)

ADC: ADD WITH CARRY

This instruction performs the same operation as ADD instruction, but adds the carry
flag bit (which may be set as a result of the previous calculation) to the result. All the
condition code flags are affected by this instruction. The examples of this instruction along
with the modes are as follows:
Example:
o ADC AX,BX – REGISTER
o ADC AX,[SI] – REGISTER INDIRECT OR INDEXED
o ADC AX, [5000H] – DIRECT
o ADC [5000H], 0100H – IMMEDIATE
o ADC 0100H – IMMEDIATE (AX IMPLICT)

SUB instruction:

 SUB instruction is used to subtract the current contents of destination with that of
source and store the result in destination. Here we can use register and/or memory
locations. AF, CF, OF, PF, SF, and ZF flags are affected
 SUB Destination, Source
  Example:

o SUB AL, 0FH ; subtract the immediate content, 0FH from the content of AL
and store the result in AL
o SUB AX, BX ; AX <= AX-BX
o SUB AX,0100H – IMMEDIATE (DESTINATION AX)
o SUB AX,BX – REGISTER
o SUB AX,[5000H] – DIRECT
o SUB [5000H], 0100H – IMMEDIATE

SBB: SUBTRACT WITH BORROW:

 To subtract with borrow instruction subtracts the source operand and the borrow flag
(CF) which may reflect the result of the previous calculations, from the destination
operand. Subtraction with borrow, here means subtracting 1 from the subtraction
obtained by SUB, if carry (borrow) flag is set.

 The result is stored in the destination operand. All the flags are affected (condition
code) by this instruction. The examples of this instruction are as follows:

 Example:

 SBB AX, 0100H – IMMEDIATE (DESTINATION AX)

 SBB AX, BX – REGISTER
 SBB AX,[5000H] – DIRECT
 SBB [5000H], 0100H – IMMEDIATE

CMP: COMPARE:
 The instruction compares the source operand, which may be a register or an
immediate data or a memory location, with a destination operand that may be a
register or a memory location.
 For comparison, it subtracts the source operand from the destination operand but
does not store the result anywhere. The flags are affected depending upon the
result of the subtraction.
 If both of the operands are equal, zero flag is set. If the source operand is greater
than the destination operand, carry flag is set or else, carry flag is reset. The
examples of this instruction are as follows:

 Example:
 CMP BX, 0100H – IMMEDIATE
 CMP AX, 0100H – IMMEDIATE
 CMP [5000H], 0100H – DIRECT
 CMP BX,[SI] – REGISTER INDIRECT OR INDEXED
 CMP BX, CX – REGISTER

INC & DEC instructions:

1. INC and DEC instructions are used to increment and decrement the content of
the specified destination by one. AF, CF, OF, PF, SF, and ZF flags are
 affected.

2. Example:

INC AL ; ALAL + 1
INC AX ; AXAX + 1

DEC AL ; AL AL – 1
DEC AX ; AXAX – 1

AND instruction:

 This instruction logically ANDs each bit of the source byte/word with the corresponding bit
in the destination and stores the result in destination. The source can be an immediate
number, register or memory location, register can be a register or memory location.

 The CF and OF flags are both made zero, PF, ZF, SF are affected by the
operation and AF is undefined.
 AND Destination, Source

 Example:

 AND BL, AL; suppose BL=1000 0110 and AL = 1100 1010 then after the
operation BL would be BL= 1000 0010.
 AND CX, AX; CX  CX AND AX
 AND CL, 08; CL CL AND (0000 1000)

OR instruction:
 This instruction logically ORs each bit of the source byte/word with the corresponding bit
in the destination and stores the result in destination. The source can be an immediate
number, register or memory location, register can be a register or memory location.

 The CF and OF flags are both made zero, PF, ZF, SF are affected by the
operation and AF is undefined.

 OR Destination, Source
 Example:
 OR BL, AL ; suppose BL=1000 0110 and AL = 1100 1010 then after the
operation BL would be BL= 1100 1110.
 OR CX, AX ; CXAX AND AX
 OR CL, 08 ; CLCL AND (0000 1000)

NOT instruction:
 The NOT instruction complements (inverts) the contents of an operand register or a
memory location, bit by bit. The examples are as follows:
1. Example:
2. NOT AX (BEFORE AX= (1011)2= (B) 16 AFTER EXECUTION AX=
(0100)2= (4)16).
 3. NOT [5000H]

XOR instruction:

 The XOR operation is again carried out in a similar way to the AND and OR
operation. The constraints on the operands are also similar. The XOR operation gives a
high output, when the 2 input bits are dissimilar. Otherwise, the output is zero. The
example instructions are as follows:

 Example:
 XOR AX, 0098H
 XOR AX, BX
 XOR AX, [5000H]
1. Shift / Rotate Instructions:
1) Shift instructions move the binary data to the left or right by shifting them within the register
or memory location. They also can perform multiplication of powers of 2+n and division of
powers of 2-n.

2) There are two type of shifts logical shifting and arithmetic shifting, later is used with signed
numbers while former with unsigned.

SHL/SAL instruction:
 Both the instruction shifts each bit to left, and places the MSB in CF and LSB is made
0. The destination can be of byte size or of word size, also it can be a register or a memory location.
Number of shifts is indicated by the count.

 All flags are affected.

 SAL/SHL destination, count

Example:

MOV BL, B7H ; BL is made B7H

SAL BL, 1 ; Shift the content of BL register one place to left.

Before Execution

CY B7 B6 B5 B4 B3 B2 B1 B0
0 1 0 1 1 0 1 1 1

After Execution,

CY B7 B6 B5 B4 B3 B2 B1 B0

1 0 1 1 0 1 1 1 0
 SHR instruction:

 This instruction shifts each bit in the specified destination to the right and 0
is stored in the MSB position. The LSB is shifted into the carry flag. The destination
can be of byte size or of word size, also it can be a register or a memory location.
Numberof shifts is indicated by the count.

 All flags are affected

 Before
execution,
B7 B6 B5 B4 B3 B2 B1 B0 CY 10
1 1 0 1 1 1 0

 After execution,
B7 B6 B5 B4 B3 B 2 B 1 B0 CY 0

1 0 1 1 0 1 11

ROL instruction:
 This instruction rotates all the bits in a specified byte or word to the left some number
of bit positions. MSB is placed as a new LSB and a new CF. The destination can be of
byte size or of word size, also it can be a register or a memory location. Number of
shifts is indicated by the count.
 All flags are affected

 ROL destination, count

Example:

MOV BL, B7H ; BL is made B7H

ROL BL, 1 ; rotates the content of BL register one place to the left.

Before Execution:

CY B7 B6 B5 B4 B3 B2 B1 B0

0 1 0 1 1 0 1 1 1

After the execution,

CY B7 B6 B5 B4 B3 B2 B1 B0

1 0 1 1 0 1 1 1 1
ROR instruction:
 This instruction rotates all the bits in a specified byte or word to the rightsome
number of bit positions. LSB is placed as a new MSB and a new CF. The destination can
be of byte size or of word size, also it can be a register or a memory location. Number
of shifts is indicated by the count.
 All flags are affected.
 ROR destination, count
 Example:
MOV BL, B7H ; BL is made B7H

ROR BL, 1 ; shift the content of BL register one place to the right.

 Before execution,

B7 B6 B5 B4 B3 B2 B1 B0 CY 1 0

1 1 0 1 1 1 0

 After execution,
B7 B6 B5 B4 B3 B2 B 1 B0 CY

1 1 0 1 1 0 1 1 1

RCR instruction

 This instruction rotates all the bits in a specified byte or word to the right some number of
bit positions along with the carry flag. LSB is placed in a new CF and previous carry
is placed in the new MSB. The destination can be of byte size or of word size, also it
can be a register or a memory location. Number of shifts is indicated by the count.
 All flags are affected

 General Format: RCR destination, count

 Example:
MOV BL, B7H ; BL is made B7H

RCR BL, 1 ; shift the content of BL register one place to the

right.

 Before execution,

B7 B6 B5 B4 B3 B2 B1

B0 CY 1 0 1 1 0 1 1
 1 0

 After execution,

B7 B6 B5 B4 B3 B2 B1

B0 CY 0 1 0 1 1 0 1
1 1

2. PROGRAM CONTROL TRANSFER INSTRUCTIONS:

 These instructions transfer control of execution to the specified address. All the
call, jump, interrupt and return instruction belong to this class.
 There are 2 types of such instructions.

1. Unconditional transfer instructions – CALL, RET, JMP

2. Conditional transfer instructions – J condition

CALL instruction:
 The CALL instruction is used to transfer execution to a subprogram or procedure.
There are two types of CALL instructions, near and far.

 A near CALL is a call to a procedure which is in the same code segment as the CALL
instruction. 8086 when encountered a near call, it decrements the SP by 2 and copies the
offset of the next instruction after the CALL on the stack. It loads the IP with the offset of
the procedure then to start the execution of the procedure.

 A far CALL is the call to a procedure residing in a different segment. Here value of CS
and offset of the next instruction both are backed up in the stack. And then branches to the
procedure by changing the content of CS with the segment base containing procedure and
IP with the offset of the first instruction of the procedure.

 Example:

Near call

CALL PRO ; PRO is the name of the procedure

CALL CX ; Here CX contains the offset of the first

instruction
of the procedure, that is replaces the content
IP with the content of CX

Far call

CALL DWORD PTR [8X]; New values for CS and IP are fetched from four
Memory locations in the DS. The new value for CS is fetched from [8X] and [8X+1], the new
IP is fetched from [8X+2] and [8X+3].
RET instruction:

 RET instruction will return execution from a procedure to the next instruction after the
CALL instruction in the calling program. If it was a near call, then IP is replaced with the
value at the top of the stack, if it had been a far call, then another POP of the stack is
required. This second popped data from the stack is Put in the CS, thus resuming the
execution of the calling program.
  RET instruction does not affect any flags.

JMP INSTRUCTION:

 This is also called as unconditional jump instruction, because the processor jumps
to the specified location rather than the instruction after the JMP instruction. Jumps
can be short jumps when the target address is in the same segment as the JMP
instruction or far jumps when it is in a different segment.

Conditional Jump (J cond)

 Conditional jumps are always short jumps in 8086. Here jump is done only if the
condition specified is true/false. If the condition is not satisfied, then the execution
proceeds in the normal way.

Iteration control instructions:

 These instructions are used to execute a series of instructions some number of times. The
number is specified in the CX register, which will be automatically decremented in course of
iteration. But here the destination address for the jump must be in the range of -128 to 127
bytes.

Example:

LOOP : loop through the set of instructions until CX is 0

LOOPE/LOOPZ : here the set of instructions are repeated until CX=0 or
ZF=0 LOOPNE/LOOPNZ: here repeated until CX=0 or ZF=1

3. MACHINE CONTROL INSTRUCTIONS:

 These instructions control the machine status. NOP, HLT, WAIT and LOCK
instructions belong to this class.
HLT instruction
 The HLT instruction will cause the 8086 microprocessor to fetching and executing
instructions.
 The 8086 will enter a halt state. The processor gets out of this Halt signal upon an interrupt
signal in INTR pin/NMI pin or a reset signal on RESET input

WAIT instruction
 When this instruction is executed, the 8086 enters into an idle state. This idle state is
continued till a high is received on the TEST input pin or a valid interrupt signal is
received. Wait affects no flags. It generally is used to synchronize the 8086 with a
peripheral device(s).
ESC instruction
 This instruction is used to pass instruction to a coprocessor like 8087. There is a 6 bit
instruction for the coprocessor embedded in the ESC instruction. In most cases the 8086
treats ESC and a NOP, but in some cases the 8086 will access data items in memory for the
coprocessor

LOCK instruction
 In multiprocessor environments, the different microprocessors share a system bus, which
is needed to access external devices like disks. LOCK Instruction is given as prefix in the
case when a processor needs exclusive access of the system bus for a particular instruction.
  It affects no flags.

 LOCK XCHG SEMAPHORE, AL : The XCHG instruction requires two

Bus accesses.
 The lock prefix prevents another processor from taking control of the system bus between
the 2 accesses

NOP instruction
 At the end of NOP instruction, no operation is done other than the fetching and decoding of
the instruction. It takes 3 clock cycles. NOP is used to fill in time delays or to provide space
for instructions while trouble shooting. NOP affects no flags.

4. FLAG MANIPULATION INSTRUCTIONS:

 All the instructions which directly affect the flag register come under this group of
instructions. Instructions like CLD, STD, CLI, STI etc.., belong to this category of
instructions.

 STC instruction
This instruction sets the carry flag. It does not affect any other flag.

 CLC instruction
This instruction resets the carry flag to zero. CLC does not affect any other flag.
CMC instruction
This instruction complements the carry flag. CMC does not affect any other flag.

 STD instruction
This instruction is used to set the direction flag to one so that SI and/or DI can be
decremented automatically after execution of string instruction. STD does not affect any
other flag.

 CLD instruction
This instruction is used to reset the direction flag to zero so that SI and/or DI can be
incremented automatically after execution of string instruction. CLD does not affect any
other flag.

 STI instruction
This instruction sets the interrupt flag to 1. This enables INTR interrupt of the 8086. STI
does not affect any other flag.

 CLI instruction
This instruction resets the interrupt flag to 0. Due to this the 8086 will not respond to an
interrupt signal on its INTR input. CLI does not affect any other flag.

5. STRING MANIPULATION INSTRUCTIONS:

These instructions involve various string manipulation operations like Load, move, scan,
compare, store etc.

 MOVS/MOVSB/MOVSW
 These instructions copy a word or byte from a location in the data segment to a
location in the extra segment. The offset of the source is in SI and that of destination
is in DI. For multiple word/byte transfers the count is stored in the CX register.
  When direction flag is 0, SI and DI are incremented and when it is 1, SI and DI are
decremented.
 MOVS affect no flags. MOVSB is used for byte sized movements while
MOVSW is for word sized.

Example:

CLD ; clear the direction flag to auto increment SI

andDI MOV AX, 0000H;

MOV DS, AX ; initialize data segment

register to 0 MOV ES, AX ; initialize extra
segment register to 0 MOV SI, 2000H ; Load the
offset of the string1 in SI MOV DI, 2400H ; Load the offset
of the string2 in DI MOV CX, 04H ;
load length of the string in CX
REP MOVSB ; decrement CX and MOVSB until CX will be 0

 REP/REPE/REP2/REPNE/REPNZ
 REP is used with string instruction; it repeats an instruction until the specified
condition becomes false.

Example: Comments
REP CX=0
REPE/REPZ CX=0 OR ZF=0
REPNE/REPNZ CX=0 OR ZF=1

 LODS/LODSB/LODSW
 This instruction copies a byte from a string location pointed to by SI to AL or a word from
a string location pointed to by SI to AX.LODS does not affect any flags. LODSB copies
byte and LODSW copies word.

Example:

CLD ; clear direction flag to auto increment SI MOVSI,

OFFSET S_STRING ; point SI at string
LODS S_STRING ;

 STOS/STOSB/STOSW
 The STOS instruction is used to store a byte/word contained in AL/AX to the offset
contained in the DI register. STOS does not affect any flags. After copying the content DI is
automatically incremented or decremented, based on the value of direction flag.

Example:
 MOV DL, OFFSET D_STRING; assign DI with destination address.

 STOS D_STRING ; assembler uses string name to determine byte or

Word, if byte then AL is used and if of word size, AX is used.
5. CMPS/CMPSB/CMPSW
 CMPS is used to compare the strings, byte wise or word wise. The comparison is affected by
subtraction of content pointed by DI from that pointed by SI. The AF, CF, OF, PF, SF and ZF
flags are affected by this instruction, but neither operand is affected.
Example: Comments
MOV SI, ; Point first string
OFFSET
STRING_A
MOV DI, ; Point second string
OFFSET
STRING_B
MOV CX, 0AH ; Set the counter as 0AH
CLD ; Clear direction flag to auto
increment
REPE CMPSB ; Repeatedly compare till
unequal or counter =0
ASSEMBLER DIRECTIVES AND OPERATOR:
 There are some instructions in the assembly language program which are not a part of
processor instruction set. These instructions are instructions to the assembler, linker and
loader. These are referred to as pseudo-operations or as assembler directives. The assembler
directives enable us to control the way in which a program assembles and lists. They act
during the assembly of a program and do not generate any executable machine code.
 There are many specialized assembler directives. Let us see the commonly used assembler
directive in 8086 assembly language programming.

ASSUME: It is used to tell the name of the logical segment the assembler to use for a specified segment.

 E.g.: ASSUME CS: CODE tells that the instructions for a program are in a logical
segment named CODE.
DB -Define Byte:

 The DB directive is used to reserve byte or bytes of memory locations in the available
memory. While preparing the EXE file, this directive directs the assembler to allocate the
specified number of memory bytes to the said data type that may be a constant, variable,
string, etc. Another option of this directive also initializes the reserved memory bytes with the
ASCII codes of the characters specified as a string. The following examples show how the
DB directive is used for different purposes.
 RANKS DB 01H, 02H, 03H, 04H
This statement directs the assembler to reserve four memory locations for a list named
RANKS and initialize them with the above specified four values.

 MESSAGE DB „GOOD MORNING‟

This makes the assembler reserve the number of bytes of memory equal to the number
of characters in the string named MESSAGE and initializes those locations by the
ASCII equivalent of these characters.

 VALUE DB 50H
This statement directs the assembler to reserve 50H memory bytes and leave them
uninitialized for the variable named VALUE.
DD:
 Define Double word - used to declare a double word type variable or to reserve
memory locations that can be accessed as double word.
E.g.: ARRAY _POINTER DD 25629261H declares a
double word named ARRAY_POINTER.

DQ -Define Quad word:

 This directive is used to direct the assembler to reserve 4 words (8 bytes) of
memory for the specified variable and may initialize it with the specified values.

DT -Define Ten Bytes:

 The DT directive directs the assembler to define the specified variable requiring 10-bytes for
its storage and initialize the 10-bytes with the specified values. The directive may be used in
case of variables facing heavy numerical calculations, generally processed by
numericalprocessors.
DW -Define Word:
 The DW directives serves the same purposes as the DB directive, but it now makes the
assembler reserve the number of memory words (16-bit) instead of bytes. Some examples
are given to explain this directive.

 WORDS DW 1234H, 4567H, 78ABH, 045CH

This makes the assembler reserve four words in memory (8 bytes), and initialize the
words with the specified values in the statements. During initialization, the lower bytes
are stored at the lower memory addresses, while the upper bytes are stored at the higher
addresses.

 NUMBER1 DW 1245H
This makes the assembler reserve one word in memory.

END-End of Program:
 The END directive marks the end of an assembly language program. When the assembler
comes across this END directive, it ignores the source lines available
later on. Hence, it should be ensured that the END statement should be the last statement in
the file and should not appear in between. Also, no useful program statement should lie in
the file, after the END statement.

ENDP:

 End Procedure - Used along with the name of the procedure to indicate the end of a
procedure.
 E.g.: SQUARE_ROOT PROC: start of procedure
SQUARE_ROOT ENDP: End of procedure

ENDS-End of Segment:
 This directive marks the end of a logical segment. The logical segments are assigned with
the names using the ASSUME directive. The names appear with the ENDS directive as
prefixes to mark the end of those particular segments. Whatever are the contents of the
segments, they should appear in the program before ENDS. Any statement appearing after
ENDS will be neglected from the segment. The structure shown below explains the fact
 more clearly.

EQU:
 Equate - Used to give a name to some value or symbol. Each time the assembler finds the
given name in the program, it will replace the name with the vale.
 E.g.: CORRECTION_FACTOR EQU 03H
MOV AL, CORRECTION_FACTOR

EVEN:
 Tells the assembler to increment the location counter to the next even address if it is not
already at an even address.
 Used because the processor can read even addressed data in one clock cycle
EXTRN:
 Tells the assembler that the names or labels following the directive are in some other
assembly module.
 For example if a procedure in a program module assembled at a different time from that
which contains the CALL instruction ,this directive is used to tell the assembler that the
procedure isexternal
GLOBAL:
 Can be used in place of a PUBLIC directive or in place of an EXTRN directive.

 It is used to make a symbol defined in one module available to other modules.

 E.g.: GLOBAL DIVISOR makes the variable DIVISOR public so that it can be
accessed from other modules.
GROUP:
 Used to tell the assembler to group the logical statements named after the directive into one
logical group segment, allowing the contents of all the segments to be accessed from the
same group segment base.
 E.g.: SMALL_SYSTEM GROUP CODE, DATA, STACK_SEG
INCLUDE:
 Used to tell the assembler to insert a block of source code from the named file into the
current source module.
 This will shorten the source code.

LABEL:
 Used to give a name to the current value in the location counter.
 This directive is followed by a term that specifies the type you want associated with that
name.
 E.g: ENTRY_POINT LABEL FAR
 NEXT: MOV AL, BL
NAME:
 Used to give a specific name to each assembly module when programs
consisting of several modules are written.
 E.g.: NAME PC_BOARD

OFFSET:
  Used to determine the offset or displacement of a named data item or
procedure from the start of the segment which contains it.
 E.g.: MOV BX, OFFSET PRICES

ORG:
 The location counter is set to 0000 when the assembler starts reading a segment.
The ORG directive allows setting a desired value at any point in theprogram.
 E.g.: ORG 2000H

PROC:
 Used to identify the start of a procedure.
 E.g.:SMART_DIVIDE PROC FAR identifies the start of a procedure named
SMART_DIVIDE and tells the assembler that the procedure is far

PTR:
 Used to assign a specific type to a variable or to a label.
 E.g.: NC BYTE PTR[BX]tells the assembler that we want to increment the byte
pointed to by BX

PUBLIC:
 Used to tell the assembler that a specified name or label will be accessed from
other modules.
 E.g.: PUBLIC DIVISOR, DIVIDEND makes the two variables DIVISOR and
DIVIDEND available to other assembly modules.

SEGMENT:
 Used to indicate the start of a logical segment.
 E.g.: CODE SEGMENT indicates to the assembler the start of a logical segment called
CODE

SHORT:
 Used to tell the assembler that only a 1 byte displacement is needed to code a jump
instruction.
 E.g.: JMP SHORT NEARBY_LABEL
TYPE:
 Used to tell the assembler to determine the type of a specified variable.
 E.g.: ADD BX, TYPE WORD_ARRAY is used where we want to increment BX to
point to the next word in an array of words.

5.7 SIMPLE ASSEMBLY LANGUAGE PROGRAMMING USING 8086

INSTRUCTIONS: PROGRAM-1: (ADDITION)

EFFECTIV MNEMONI LABLE MNEMONIC OPERANDS COMMENTS

E C S
ADDRESS CODES
2000 8B,06,00,17 MOV AX,[1700] Move the contents
of 1700 in register
AX
2004 8B,1E,02,17 MOV BX, [1702] Move the contents
of 1702 in register
BX
2008 01,D8 ADD AX,BX Data of AX and BX
 are added and
result stored in AX
200A CC INT 3 Interrupt program

PROGRAM-2: (SUBTRACTION)

EFFECTIV MNEMONI LABLE MNEMONIC OPERANDS COMMENTS

E C S
ADDRESS CODES
2000 8B,06,00,17 MOV AX,[1700] Move the contents
of 1700 in register
AX
2004 8B,1E,02,17 MOV BX, [1702] Move the contents
of 1702 in register
BX
2008 29,D8 SUB AX,BX Data of AX and
BX are added and
result stored in AX
200A CC INT 3 Interrupt program
PROGRAM-3: (MULTIPLICATION)

EFFECTIV OPCODES MNEMONICS OPERAND COMMENTS

E S
ADDRESS
1100 BE 00 15 MOV SI,1500 Load 1500
into SI
1103 AD LOD SW Load the
multiplicand
value
1104 89 C3 MOV BX, AX Load AX value
into BX
1106 AD LOD SW Load the
multiplier
value
1107 F7 E3 MUL BX Multiply two
data
1109 BF 0 5 15 MOV DI, 1520 Load 1520
address into
DI
110C 89 05 MOV [DI], AX Store AX
value into DI
110E 47 INC DI
110F 47 INC DI Increment the
DI
1110 89 15 MOV [DI], BX Store BX value
into DI
1112 CC INT 3 Break point

PROGRAM-4: (DIVISION)

EFFECTIVE OPCODES MNEMONICS OPERAND COMMENTS

ADDRESS S
1100 BA 00 00 MOV DX, 0000 Clear DX registers
1103 B8 83 00 MOV AX, 0083 Load the dividend
in AX
1106 B9 00 02 MOV BX, 02 Load the divisor
value in BX
1109 F7 F1 DIV BX Divide the two
data’s
110B BF 20 15 MOV DI, 1520 Load 1520 address
into DI
110E 88 05 MOV [DI], AL Load AL value into
DI
1110 47 INC DI Increment DI
 1111 88 25 MOV [DI], Load AH value into
AH DI
1113 47 INC DI Increment DI
1114 89 15 MOV [DI], Load DX value into
DX DI
1116 CC INT3 Break point

PROGRAM-5: (LARGEST NUMBER IN DATA ARRAY)

EFFECTIV MNEMONI LABL MNEMONIC OPERAND COMMENTS

E C CODES E S S
ADDRESS
0101 B8, 00, 00 MOV AX, 0000 ;Initial value for
comparison
0104 BE, 00, 02 MOV SI, 0200 ;memory address in SI

0107 8B, 0C MOV CX, [SI] ;count in CX

0109 46 BACK INC SI ;increment SI
010A 46 INC SI ;increment SI
010B 3B, 04 CMP AX, [SI] ;compare previous
largest number with
next number
010D 73, 02 JAE GO ;Jump if number in
AX is greater i.e. CF
=0
010F 8B, 04 MOV AX, [SI] ;save next larger
number in AX
0111 E2, F6 GO LOOP BACK ;jump to BACK until
CX become zero
0113 A3, 51, 02 MOV [0251], AX ;store largest
number in memory
0116 CC INT3 ;interrupt program
 PROGRAM-6: (SMALLEST NUMBER IN DATA ARRAY)

EFFECTIV MNEMONI LABE MNEMONIC OPERAND COMMENTS

E CS CODES L S S
ADDRESS
0101 B8,FF,FF MOV AX,FFFF Initial value for
comparison.

0104 BE,00,02 MOV SI,0200 Memory

address in SI.

0107 8B,0C MOV CX,[SI] Count in CX

0109 46 BACK INC SI Increment SI

010A 46 INC SI Increment SI

010B 3B,04 CMP AX,[SI] Compare previous

smallest with
next
number

010D 72,02 JB GO Jump if

number in AX
is smaller
i.e. CF=1
010F 8B,04 MOV AX,[SI] Save next
smaller
0111 E2,F6 GO LOOP BACK Jump to back until
CX
becomes
zero.
0113 A3,51,02 MOV [0251],AX Store smallest
number in
memory

0116 CC INT 3 Interrupt

program.
 8086- ASSEMBLY LANGUAGE DEVELOPMENT TOOLS
To develop an assembly language program we need certain program development tools
.the following section explains the 8086 development tools in details.

ASSEMBLY LANGUAGE DEVELOPMENT TOOLS:

Editor :

 An Editor is a program which allows us to create a file containing the assembly language
statements for the program. Examples of some editors are PC write Wordstar.
 As we type the program the editor stores the ACSII codes for the letters and numbers in
successive RAM locations.
 If any typing mistake is done editor will alert us to correct it.
 If we leave out a program statement an editor will let you move everything down and insert a
line.
 After typing all the program we have to save the program for a hard disk.
 This we call it as source file.
 The next step is to process the source file with an assembler.
 While using TASM or MASM we should give a file name and
extension .ASM.

Ex: Sample. asm

Assembler:

 An Assembler is used to translate the assembly language mnemonics into machine

language( i.e binary codes).
 When you run the assembler it reads the source file of your program from where you have
saved it.
 The assembler generates two files . The first file is the Object file with the extension .OBJ.
 The object file consists of the binary codes for the instructions and information about the
addresses of the instructions.
 After further processing, the contents of the file will be loaded in to memory and run. The
second file is the assembler list file with the extension .LST.

Linker :

 A linker is a program used to connect several object files into one large object file.
 While writing large programs it is better to divide the large program into smaller modules.
 Each module can be individually written, tested and debugged.
 Then all the object modules are linked together to form one, functioning program.
 These object modules can also be kept in library file and linked into other programs as
needed.
 A linker produces a link file which contains the binary codes for all the combined modules.
 The linker also produces a link map file which contains the address information about the
linked files.
 The linkers which come with TASM or MASM assemblers produce link files with
the .EXE extension.
 Locator:

 A locator is a program used to assign the specific addresses of where the segments of object
code are to be loaded into memory.
 A locator program called EXE2BIN comes with the IBM PC Disk Operating System (DOS).
EXE2BIN converts a .EXE file to a .BIN file which has physical addresses.

Debugger:

 A debugger is a program which allows to load your object code program into system
memory, execute the program, and troubleshoot or debug it.
 The debugger allows to look into the contents of registers and memory locations after the
program runs. We can also change the contents of registers and memory locations and rerun
the program.
 Some debuggers allows to stop the program after each instruction so that you can check or
alter memory and register contents. This is called single step debug.
 A debugger also allows to set a breakpoint at any point in the program.
 If we insert a break point, the debugger will run the program up to the instruction where the
breakpoint is put and then stop the execution.

Emulator:

 An emulator is a mixture of hard ware and software.

 It is usually used to test and debug the hardware and software of an external system such
as the prototype of a microprocessor based instrument.