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Unit –III

Analysis and Synthesis of Sequential Logic Circuits

Sequential logic Circuit (SLC)

A sequential logic circuit is a digital circuit in which the output at any point of time depends on
present inputs and past outputs. Sequential circuits include memory elements along with
combinational logic circuits. The memory elements are connected to the combinational logic
circuit as a feedback path. Fig 1 shows the block diagram of a sequential logic circuit.

Fig. 1 Block diagram of sequential logic circuit.

Finite State Machines

Classification of SLC

The sequential circuits can be classified into two categories depending on the timing of their
signals
1. Synchronous sequential logic circuit
2. Asynchronous sequential logic circuit

In case of synchronous sequential circuits, it is assumed that the behavior of the system
synchronized by a clock. The system behavior is determined by the values of present state and
external input signals at discrete instants of time.

In case of asynchronous sequential logic circuits the order in which input signals change affected
network behavior. Further more, these changes are allowed to occur at any instant of time.
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Mealy Model

Fig. _2____shows the clocked synchronous sequential Mealy machine. The output of mealy
machine is the function of present inputs and present state (Flip flop outputs).

Fig _2____ model for mealy machine

Moore Machine

Fig. __3___ shows the block diagram of a Moore machine. The output of Moore machine depends
only op the present state. So the output of Moore machine is a function of its present state

Fig __3___ model for Moore machine

Difference between Moore and Mealy Machine

SNo. Moore machine Mealy machine

The output of this machine is the function of Its output is function of input as well as
1.
the present state only present state present
Input changes may affect the output of the
2. Input changes do not affect the output
circuit
It requires more number of states for It requires less number of states for
3.
implementing same function implementing same function

4 Speed is high Speed is low

5 Design process is very complicate Less complex than Moore design

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ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS

 The behavior of sequential circuit can be determined from the inputs, the output and state of
its flip flops.

 The outputs and next state are both a function of its inputs and the present state.

 The analysis of a sequential circuit consists of obtaining a table or diagram for the time
sequence of inputs, outputs and internal states.

 The analysis of the clocked sequential circuits can be done by following the procedure as
Analysis Procedure
1. Identify type of circuit either Mealy or Moore circuit
2. Derive excitation equation (Boolean expression)
3. Derive next state and output equations
4. Generate state table
5. Generate state diagram

Analysis of Example Sequential Logic Circuit

Figure 7.6 shows a clocked sequential circuit. It has one input variable X, output variable Y and
two clocked JK flin flops. The flip flops are labelled as A and B and their outputs are labelled as
A and A, B and B respectively.

Fig __4_

Step 1 : Type of circuit

The output of given logic circuit y (Fig. __4____) depends on present input and also on present
state (Flip flop outputs) of flip flops, so the given sequential logic circuit is Mealy sequential
machine.

Step 2 : Excitation equations

The excitation equations or Boolean expressions of flip flops A and B are obtained. The equations
will be in the form of present states A and B and external input x. Since there are two JK flip
flops which have output A and B. Therefore the excitation equation (equation formed for flip flop
input)
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For Flip flop – A

J A  x B and K A  xB

For Flip flop – A

J B  xA and K B  x A

Step 3 : Next state equations

The state equations can be derived directly from the logic diagram. Looking at Fig. ____, we can
see that the signal for J input of the flip flop A is generated by the function x B and the signal for
input K by the function xB . Substituting J A  x B and K A  xB into a JK flip flop characteristic
equation given by

Characteristic Equation of JK Flip flop

Qn 1  J Qn  KQn
Substitute the JA and KA in the above equation to obtain the state equation of fkip-flop A

State equation of flip flop A

 
An 1  Bx Qn  xBQn where Qn=A
An 1  Bx A  xB A
Simplify the above equation we get
An 1  AB  Ax  Bx

Similarly we get next state equation for flip-flop B

Bn 1  AB  A x  B x

Output equation y  ABx

Step 4 : State Table

The Table ____ shows the state table for the given sequential logic circuit. It represents the
relationship between input, output, and flipflop states. It consists of three columns: Present state,
next state and output.

Present state: it specifies the state of flip-flop before occurrence of a clock pulse

Next state :it is the state of flip flop after the application of clock

Output: this section gives the value of the output variables during the present state. Both next
state and output section have two columns representing two possible input conditions x=0 and
x=1.
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State Table

Output
Next state
Present state Y
x=0 x=1 x=
x=1
AB AB AB 0
00 00 10 0 0
01 01 00 0 0
10 11 10 0 1
11 01 11 0 0

Step 5 State diagram

State diagram is a graphical representation of a state table. Fig. ____shows the state diagram for
sequential circuit. Here each state is represented by a circle, and transition between states is
indicated by directed lines connecting the circles. The binary number inside each circle identifies
the state represented by the circle. The directed lines are labelled with two binary numbrs separated
by a symbol `I' (slash). The input value that causes the state transition is labelled first and output
value is next.
0/0

Fig__5___ State diagram.

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1,5 STATE REDUCTION

 Any logic design process must consider the problem of minimizing the cost of the final
circuit.

 One way to reduce the cost is by reducing the number of flip flops, i . e . by reducing the
number of states.

 The state reduction technique basically avoids the introduction of redundant equivalent
states. The reduction of redundant states reduces the number of flip flops and logic gates
required, thus reducing the cost of the final circuit.

 Two states are said to be redundant or equivalent, if every possible set of inputs generate
exactly the same outputs and the same next states.

 When two states are equivalent one of them can be removed without altering input output
relationship. Let us consider the state diagram as shown in Fig. 7.8.

 The states are denoted by letter symbols instead of their binary values because instate
reduction technique internal states are important, but input output sequences are
important. The procedure contains two steps.

Step 1: Finding State table for the given state diagram

First the given state diagram is converted into a state table.

Next state output

Present state
x=0 x=1 x=0 x=1
a b c 0 0

b d e 1 0

c c d 0 1
d a d 0 0

e c d 0 1
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Step 2 : Finding equivalent states

It is determined from the state diagram. The equivalent state table is given for the above state
diagram as
The two present states go to the same next state and have the same output for both the input
combinations. We can easily find this from the state table, states c and e are equivalent. This is
because both c and e states go to states c and d outputs of 0 and 1 for x = 0, x = 1 respectively.
Therefore, the state e can be removed and replaced by c. The final reduced table and state
diagram are given in the table ______ and Fig._____. The second row have e state for the input
x = l, it is replaced by c because the states c and e are equivalent.

Reduced state table

Table 7.2
Next state Output

Present state x=0 x=1 x=0 x=1

a b c 0 0
b d c 1 0
c c d 0 1
d 1/0 a d 0 0

Reduced State Diagram

Fig 6
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DESIGN PROCEDURE FOR CLOCKED SEQUENTIAL CIRCUIT

The following steps are followed to design the clocked sequential logic circuit.
1. Obtain the state table from the given circuit information such as a state diagram, a timing
diagram or description.
2. The number of states may be reduced by state reduction technique.
3. Assign binary values to each state in the state table.
4. Determine the number of flip flops required and assign a letter symbol to each flip flop.
5. Choose the flip flop type to be used according to the application.
6. Derive the excitation table from the reduced state table.
7. Derive the expression for flip flop inputs and outputs using k-map simplification (The
present state and inputs are considered for k-map simplification) and draw logic circuit
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using flip flops and gates.

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