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Tutorial Slides

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manjupriya20k
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© © All Rights Reserved
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Tutorials

Numerical 1
Solution
Numerical 2
Solution
Numerical 2 contd.
Solution
Numerical 3
Solution
Solution
What is function OUT of the circuit of Fig.2 as a function of the A, B, and C
inputs?
What is function OUT of the circuit of Fig.2 as a function of the A, B, and C
inputs?

Solution
Consider the circuit of Figure 6.14. Assume the inverter switches ideally
at VDD/2, neglect body effect, channel length modulation and all
parasitic capacitance throughout this problem. a. What is the logic
function performed by this circuit?

What is the logic function performed by this circuit?


Consider the circuit of Figure 6.14. Assume the inverter switches ideally
at VDD/2, neglect body effect, channel length modulation and all
parasitic capacitance throughout this problem. a. What is the logic
function performed by this circuit?

What is the logic function performed by this circuit?

Solution
The circuit is a NAND gate
Consider the circuit of Figure 6.14. Assume the inverter switches ideally
at VDD/2, neglect body effect, channel length modulation and all
parasitic capacitance throughout this problem. a. What is the logic
function performed by this circuit?

Explain why this circuit has non-zero static dissipation.


Consider the circuit of Figure 6.14. Assume the inverter switches ideally
at VDD/2, neglect body effect, channel length modulation and all
parasitic capacitance throughout this problem. a. What is the logic
function performed by this circuit?

Explain why this circuit has non-zero static dissipation.


Solution

Sol: When A=B= VDD, the voltage at node x is VX=VDD-VtN. This causes
static power dissipation at the inverter the pass transistor network is
driving.
Consider the circuit of Figure 6.14. Assume the inverter switches ideally
at VDD/2, neglect body effect, channel length modulation and all
parasitic capacitance throughout this problem. a. What is the logic
function performed by this circuit?

Using only just 1 transistor, design a fix so that there will not be any static power
dissipation. Explain how you chose the size of the transistor
Consider the circuit of Figure 6.14. Assume the inverter switches ideally
at VDD/2, neglect body effect, channel length modulation and all
parasitic capacitance throughout this problem. a. What is the logic
function performed by this circuit?

Using only just 1 transistor, design a fix so that there will not be any static power
dissipation. Explain how you chose the size of the transistor

Solution
Consider the circuit of Figure 6.14. Assume the inverter switches ideally
at VDD/2, neglect body effect, channel length modulation and all
parasitic capacitance throughout this problem. a. What is the logic
function performed by this circuit?

Using only just 1 transistor, design a fix so that there will not be any static power
dissipation. Explain how you chose the size of the transistor

Solution
Consider the circuit of Figure 6.14. Assume the inverter switches ideally
at VDD/2, neglect body effect, channel length modulation and all
parasitic capacitance throughout this problem. a. What is the logic
function performed by this circuit?

d. Implement the same circuit using transmission gates.


Consider the circuit of Figure 6.14. Assume the inverter switches ideally
at VDD/2, neglect body effect, channel length modulation and all
parasitic capacitance throughout this problem. a. What is the logic
function performed by this circuit?

d. Implement the same circuit using transmission gates.

Solution
Consider the circuit of Figure 6.14. Assume the inverter switches ideally
at VDD/2, neglect body effect, channel length modulation and all
parasitic capacitance throughout this problem. a. What is the logic
function performed by this circuit?

Replace the pass-transistor network in Figure 6.14 with a pass transistor


network that computes the following function: x = ABC at the node x.
Assume you have the true and complementary versions of the three
inputs A,B and C
Consider the circuit of Figure 6.14. Assume the inverter switches ideally
at VDD/2, neglect body effect, channel length modulation and all
parasitic capacitance throughout this problem. a. What is the logic
function performed by this circuit?

Replace the pass-transistor network in Figure 6.14 with a pass transistor


network that computes the following function: x = ABC at the node x.
Assume you have the true and complementary versions of the three
inputs A,B and C

Solution
2
4
4) Consider a conventional 4-stage Domino logic circuit as shown in
Figure P4 in which all precharge and evaluate devices are clocked
using a common clock . For this entire problem, assume that the
pulldown network is simply a single NMOS device, so that each
Domino stage consists of a dynamic inverter followed by a static
inverter. Assume that the precharge time, evaluate time, and
propagation delay of the static inverter are all T/2. Assume that the
transitions are ideal (zero rise/fall times).

Figure P4
a) Complete the timing diagram for signals Out1, Out2, Out3 and
Out4, when the IN signal goes high before the rising edge of the
clock  as given below. Assume that the clock period is 10 T time
units.
2
5
4) Consider a conventional 4-stage Domino logic circuit as shown in Figure P4 in which all
precharge and evaluate devices are clocked using a common clock . For this entire problem,
assume that the pulldown network is simply a single NMOS device, so that each Domino stage
consists of a dynamic inverter followed by a static inverter. Assume that the precharge time,
evaluate time, and propagation delay of the static inverter are all T/2. Assume that the transitions
are ideal (zero rise/fall times).

Figure P4

a) Complete the timing diagram for signals Out1, Out2, Out3 and Out4, when the IN signal
goes high before the rising edge of the clock  as given below. Assume that the clock
period is 10 T time units.

Solution
2
6

b) Suppose that there are no evaluate switches at the 3 latter stages.


Assume that the clock
 is initially in the precharge state (=0 with all nodes settled
to the correct precharge states), and the block enters the
evaluate period (=1). Is there a problem during the evaluate
period, or is there a benefit to the overall performance?
Explain.
2
7

b) Suppose that there are no evaluate switches at the 3 latter stages.


Assume that the clock
 is initially in the precharge state (=0 with all nodes settled to
the correct precharge states), and the block enters the evaluate
period (=1). Is there a problem during the evaluate period, or is
there a benefit to the overall performance? Explain.
Solution
There is no problem during the evaluate stage. The precharged
nodes remain charged until a signal propogates through the logic,
activating the pull-down network and discharging the node. In fact,
this topology improves the circuit’s robustness in terms of charge
sharing affecting the output for any generic pull-down network,
and reduces the body effect in the pull-down network.
2
8

c) Assume that the clock  is initially in the evaluate state


(=1), and the block enters the precharge state ( = ). Is
there a problem, or is there any benefit, if the last three
evaluate switches are removed? Explain.
2
9

c) Assume that the clock  is initially in the evaluate state (=1),


and the block enters the precharge state ( = ). Is there a
problem, or is there any benefit, if the last three evaluate
switches are removed? Explain.
Solution
There is a problem during the precharge stage. If all precharged
nodes are discharged during the evaluate stage, when the
precharge FETs simultaneously turn on, the pull-down networks
will initially remain on, creating a short circuit. This continues in
each gate until the previous gate charges, disabling its pull-down
network.
Numerical 1
• For the below circuits, the inverters are realized using static CMOS
logic. Write the Boolean equation for G and H
Numerical 1 (Homework)
• For the below circuits, the inverters are realized using static CMOS
logic. Write the Boolean equation for X, Y
Numerical 2
Numerical 2-Solution
• Sol: A
Numerical 4
Design a 4- bit carry lookahead adder using multiple-output
domino CMOS logic
Numerical 4 Solution
Design a 4- bit carry lookahead adder using multiple-output
domino CMOS logic
Numerical 5
• Consider a conventional 4-stage Domino logic circuit as shown
in Figure in which all precharge and evaluate devices are
clocked using a common clock ɸ. For this entire problem,
assume that the pulldown network is simply a single NMOS
device, so that each Domino stage consists of a dynamic
inverter followed by a static inverter. Assume that the
precharge time, evaluate time, and propagation delay of the
static inverter are all T/2. Assume that the transitions are ideal
(zero rise/fall times).
Numerical 5
a. Complete the timing diagram for signals Out1, Out2, Out3 and Out4, when the IN
signal goes high before the rising edge of the clock f. Assume that the clock period
is 10 T time units.
a. Complete the timing diagram for signals Out1, Out2, Out3 and Out4, when the IN
signal goes high before the rising edge of the clock f. Assume that the clock period
is 10 T time units.
a. Complete the timing diagram for signals Out1, Out2, Out3 and Out4, when the IN
signal goes high before the rising edge of the clock f. Assume that the clock period
is 10 T time units.
Numerical 5
Sol
• 5.88GHz

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