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Lab 6

Lab6

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25 views3 pages

Lab 6

Lab6

Uploaded by

Aditi Nahar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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INTRODUCTION TO DIGITAL SYSTEMS

SYSC2310 (Fall 2021)


Dr. Mostafa Taha

Lab 6: Sequential Logic Circuits


Objectives
• Design a binary counter and a binary sequence detector
Relation to course outcomes
The work in this lab is related to the two following course outcomes:
• Able to design, implement and analyze sequential logic circuits with flip-flops.

Part 1: Graded Pre-Lab Preparation


Under your ‘sysc2310lab/lab6’ folder, create folders ‘Ex1’, ‘Ex2’ to save your work during this
lab. Remember, by the end of the term, you are required to have the files for all the exercises in
every lab. TAs and lab technicians will not be able to recover any deleted file, or any file that
you have overwritten by mistake. Local Windows recycle bin doesn’t work with the network M
drive.
Exercise 1 Pre-lab: Design a Binary Counter
Design, construct and test a 3-bit binary counter that goes through the following sequence of
binary states:
1, 2, 3, 4, 5, then back to 1.

Note that the binary states ‘0’, ‘6’ and ‘7’ are not used. The counter must be self-starting; that is,
if the circuit starts on any of the invalid states (‘0’, ‘6’ or ‘7’), the counter must move on to any
valid state on the next pulse and continue to work correctly. Not specifying any particular next
valid state gives some flexibility in our design, allowing for the use of don’t care conditions and
further reduce the circuit size. However, there is a possibility of instability. The design should
resemble an FSM without inputs or outputs, using D flip-flops. The counter is controlled only
by the clock.

1.1 Design procedure


The following are steps to design such circuit:
1. State diagram,
2. State table,
3. FF-input equations,
4. A complete circuit schematic.
Exercise 2-Pre-lab: Design a Binary Sequence Detector
Design, construct and test a binary sequence detector that can be used to search for a specific
sequence of binary values within a long stream of bits. Search for the binary sequence “1101”.
The sequence detector should be “Overlapping” signatures. For instance, the following input
sequence will generate the corresponding output:

Input: 0 1 1 0 1 1 0 1 0 0 1 0
Output: 0 0 0 0 1 0 0 1 0 0 0 0

Note how one bit can be common between two detected sequences. The design should
resemble a Moore FSM, using D flip-flops. You can use don’t care in case there are unused
states to simplify the combinational circuit.
1.2 Design procedure
Derive the following design data about the system:
1. Complete problem description (similar to the lecture).
2. State diagram,
3. State table,
4. FF-input equations,
5. A complete circuit schematic.

Pre-labs must be submitted on Brightspace before the start of the lab and by the
deadline posted on Brightspace.

Part 2: In the lab

2.1 Experiment 1: Counter


1. In Logisim, please use D flip-flops from the memory library. The default for these flip-flops
is being +ve edge triggered. For help with the D flip-flop, please hover over the input pins
to read its function refer to
(http://www.cburch.com/logisim/docs/2.7/en/html/libs/mem/index.html).

2. Use the clock input from the wiring library. For help with the clock input, please refer to
(http://www.cburch.com/logisim/docs/2.7/en/html/libs/wiring/clock.html).

3. To check operation of the counter, use the 7-seg decoder display designed in previous
labs.
4. Enable logging to ‘Lab6_Ex1_log.txt’, and use the poke tool ( ) to change values of the
input Clk. Notice and record the output 7-seg display.

5. To check operation of the counter during the invalid states, please use the preset/clear
inputs of the D flip-flop to initialize the counter to each of the invalid states (‘0’, ‘6’ and ‘7’).
Then, proceed with the clock to ensure correct transition to ant valid state.

6. Save the circuit as ‘Lab6_Ex1.circ’.


2.2 Experiment 2: Sequence Detector
1. Implement the circuit on Logisim.
2. In Logisim, the circuit has only two inputs: data input (𝑥), and the input clock (clk) and a
single output (𝑦). Use an input clock from the wiring library, and D flip-flops from the
memory library.
3. The flip-flops are +ve edge triggered. You should change the input (𝑥) to a selected
new value following the input sequence above before changing the clock from low to
high (the +ve edge).
4. Enable logging to ‘Lab6_Ex2_log.txt’ and use the poke tool ( ) to change values of
the input (x) and the (clk). Notice and record the output (𝑦) after each clock cycle.
5. Save the circuit as ‘Lab6_Ex2.circ’.

Lab Report and Deliverables:


In the lab:
• You must attend the lab to get its mark, make sure to sign your name before leaving the
lab.
• In order to get full credit, complete all exercises and be prepared to answer questions
asked by the TA during the lab.
• Be ready to show to your TA all circuit files as well as all simulation files.
What to include in the report?
• Review the rubric given on Brightspace.
• Your report should have the following sections.
1- Screenshot of the circuit design on Logisim
2- Logging file that shows the inputs and outputs for the circuit
3- A conclusion summarizing the experiment and the circuits functionality.
Lab report format
• A single pdf file that contains all above.
• Include a text with your name, student ID, lab number and date into your circuits.

Note: Version 1.3, This manual was revised by Dr. Rose Gomar in June 2024.

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